Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
69c18c15 | 53 | |
8aef135c | 54 | #include <asm/acpi.h> |
cb3c8b90 | 55 | #include <asm/desc.h> |
69c18c15 GC |
56 | #include <asm/nmi.h> |
57 | #include <asm/irq.h> | |
07bbc16a | 58 | #include <asm/idle.h> |
e44b7b75 | 59 | #include <asm/trampoline.h> |
69c18c15 GC |
60 | #include <asm/cpu.h> |
61 | #include <asm/numa.h> | |
cb3c8b90 GOC |
62 | #include <asm/pgtable.h> |
63 | #include <asm/tlbflush.h> | |
64 | #include <asm/mtrr.h> | |
7b6aa335 | 65 | #include <asm/apic.h> |
569712b2 | 66 | #include <asm/setup.h> |
bdbcdd48 | 67 | #include <asm/uv/uv.h> |
cb3c8b90 | 68 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 69 | |
1164dd00 | 70 | #include <asm/smpboot_hooks.h> |
b81bb373 | 71 | #include <asm/i8259.h> |
cb3c8b90 | 72 | |
16ecf7a4 | 73 | #ifdef CONFIG_X86_32 |
4cedb334 | 74 | u8 apicid_2_node[MAX_APICID]; |
acbb6734 GOC |
75 | #endif |
76 | ||
a8db8453 GOC |
77 | /* State of each CPU */ |
78 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
79 | ||
cb3c8b90 GOC |
80 | /* Store all idle threads, this can be reused instead of creating |
81 | * a new thread. Also avoids complicated thread destroy functionality | |
82 | * for idle threads. | |
83 | */ | |
84 | #ifdef CONFIG_HOTPLUG_CPU | |
85 | /* | |
86 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
87 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
88 | */ | |
89 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
90 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
91 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
92 | |
93 | /* | |
94 | * We need this for trampoline_base protection from concurrent accesses when | |
95 | * off- and onlining cores wildly. | |
96 | */ | |
97 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
98 | ||
99 | void cpu_hotplug_driver_lock() | |
100 | { | |
101 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
102 | } | |
103 | ||
104 | void cpu_hotplug_driver_unlock() | |
105 | { | |
106 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
107 | } | |
108 | ||
109 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
110 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 111 | #else |
f86c9985 | 112 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
113 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
114 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
115 | #endif | |
f6bc4029 | 116 | |
a355352b GC |
117 | /* Number of siblings per CPU package */ |
118 | int smp_num_siblings = 1; | |
119 | EXPORT_SYMBOL(smp_num_siblings); | |
120 | ||
121 | /* Last level cache ID of each logical CPU */ | |
122 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
123 | ||
a355352b | 124 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 125 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
126 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
127 | ||
128 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 129 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
130 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
131 | ||
132 | /* Per CPU bogomips and other parameters */ | |
133 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
134 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 135 | |
2b6163bf | 136 | atomic_t init_deasserted; |
cb3c8b90 | 137 | |
7cc3959e | 138 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
7cc3959e GOC |
139 | /* which node each logical CPU is on */ |
140 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
141 | EXPORT_SYMBOL(cpu_to_node_map); | |
142 | ||
143 | /* set up a mapping between cpu and node. */ | |
144 | static void map_cpu_to_node(int cpu, int node) | |
145 | { | |
146 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
c032ef60 | 147 | cpumask_set_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
148 | cpu_to_node_map[cpu] = node; |
149 | } | |
150 | ||
151 | /* undo a mapping between cpu and node. */ | |
152 | static void unmap_cpu_to_node(int cpu) | |
153 | { | |
154 | int node; | |
155 | ||
156 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
157 | for (node = 0; node < MAX_NUMNODES; node++) | |
c032ef60 | 158 | cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); |
7cc3959e GOC |
159 | cpu_to_node_map[cpu] = 0; |
160 | } | |
161 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
162 | #define map_cpu_to_node(cpu, node) ({}) | |
163 | #define unmap_cpu_to_node(cpu) ({}) | |
164 | #endif | |
165 | ||
166 | #ifdef CONFIG_X86_32 | |
1b374e4d SS |
167 | static int boot_cpu_logical_apicid; |
168 | ||
7cc3959e GOC |
169 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = |
170 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
171 | ||
a4928cff | 172 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
173 | { |
174 | int cpu = smp_processor_id(); | |
175 | int apicid = logical_smp_processor_id(); | |
3f57a318 | 176 | int node = apic->apicid_to_node(apicid); |
7cc3959e GOC |
177 | |
178 | if (!node_online(node)) | |
179 | node = first_online_node; | |
180 | ||
181 | cpu_2_logical_apicid[cpu] = apicid; | |
182 | map_cpu_to_node(cpu, node); | |
183 | } | |
184 | ||
1481a3dd | 185 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
186 | { |
187 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
188 | unmap_cpu_to_node(cpu); | |
189 | } | |
190 | #else | |
7cc3959e GOC |
191 | #define map_cpu_to_logical_apicid() do {} while (0) |
192 | #endif | |
193 | ||
cb3c8b90 GOC |
194 | /* |
195 | * Report back to the Boot Processor. | |
196 | * Running on AP. | |
197 | */ | |
a4928cff | 198 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
199 | { |
200 | int cpuid, phys_id; | |
201 | unsigned long timeout; | |
202 | ||
203 | /* | |
204 | * If waken up by an INIT in an 82489DX configuration | |
205 | * we may get here before an INIT-deassert IPI reaches | |
206 | * our local APIC. We have to wait for the IPI or we'll | |
207 | * lock up on an APIC access. | |
208 | */ | |
a9659366 IM |
209 | if (apic->wait_for_init_deassert) |
210 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
211 | |
212 | /* | |
213 | * (This works even if the APIC is not enabled.) | |
214 | */ | |
4c9961d5 | 215 | phys_id = read_apic_id(); |
cb3c8b90 | 216 | cpuid = smp_processor_id(); |
c2d1cec1 | 217 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
218 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
219 | phys_id, cpuid); | |
220 | } | |
cfc1b9a6 | 221 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
222 | |
223 | /* | |
224 | * STARTUP IPIs are fragile beasts as they might sometimes | |
225 | * trigger some glue motherboard logic. Complete APIC bus | |
226 | * silence for 1 second, this overestimates the time the | |
227 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
228 | * by a factor of two. This should be enough. | |
229 | */ | |
230 | ||
231 | /* | |
232 | * Waiting 2s total for startup (udelay is not yet working) | |
233 | */ | |
234 | timeout = jiffies + 2*HZ; | |
235 | while (time_before(jiffies, timeout)) { | |
236 | /* | |
237 | * Has the boot CPU finished it's STARTUP sequence? | |
238 | */ | |
c2d1cec1 | 239 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
240 | break; |
241 | cpu_relax(); | |
242 | } | |
243 | ||
244 | if (!time_before(jiffies, timeout)) { | |
245 | panic("%s: CPU%d started up but did not get a callout!\n", | |
246 | __func__, cpuid); | |
247 | } | |
248 | ||
249 | /* | |
250 | * the boot CPU has finished the init stage and is spinning | |
251 | * on callin_map until we finish. We are free to set up this | |
252 | * CPU, first the APIC. (this is probably redundant on most | |
253 | * boards) | |
254 | */ | |
255 | ||
cfc1b9a6 | 256 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
257 | if (apic->smp_callin_clear_local_apic) |
258 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
259 | setup_local_APIC(); |
260 | end_local_APIC_setup(); | |
261 | map_cpu_to_logical_apicid(); | |
262 | ||
9d133e5d SS |
263 | /* |
264 | * Need to setup vector mappings before we enable interrupts. | |
265 | */ | |
36e9e1ea | 266 | setup_vector_irq(smp_processor_id()); |
cb3c8b90 GOC |
267 | /* |
268 | * Get our bogomips. | |
269 | * | |
270 | * Need to enable IRQs because it can take longer and then | |
271 | * the NMI watchdog might kill us. | |
272 | */ | |
273 | local_irq_enable(); | |
274 | calibrate_delay(); | |
275 | local_irq_disable(); | |
cfc1b9a6 | 276 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
277 | |
278 | /* | |
279 | * Save our processor parameters | |
280 | */ | |
281 | smp_store_cpu_info(cpuid); | |
282 | ||
85257024 PZ |
283 | notify_cpu_starting(cpuid); |
284 | ||
cb3c8b90 GOC |
285 | /* |
286 | * Allow the master to continue. | |
287 | */ | |
c2d1cec1 | 288 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
289 | } |
290 | ||
bbc2ff6a GOC |
291 | /* |
292 | * Activate a secondary processor. | |
293 | */ | |
0ca59dd9 | 294 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
295 | { |
296 | /* | |
297 | * Don't put *anything* before cpu_init(), SMP booting is too | |
298 | * fragile that we want to limit the things done here to the | |
299 | * most necessary things. | |
300 | */ | |
fd89a137 JR |
301 | |
302 | #ifdef CONFIG_X86_32 | |
303 | /* | |
304 | * Switch away from the trampoline page-table | |
305 | * | |
306 | * Do this before cpu_init() because it needs to access per-cpu | |
307 | * data which may not be mapped in the trampoline page-table. | |
308 | */ | |
309 | load_cr3(swapper_pg_dir); | |
310 | __flush_tlb_all(); | |
311 | #endif | |
312 | ||
bbc2ff6a GOC |
313 | cpu_init(); |
314 | preempt_disable(); | |
315 | smp_callin(); | |
316 | ||
317 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
318 | barrier(); | |
319 | /* | |
320 | * Check TSC synchronization with the BP: | |
321 | */ | |
322 | check_tsc_sync_target(); | |
323 | ||
324 | if (nmi_watchdog == NMI_IO_APIC) { | |
b81bb373 | 325 | legacy_pic->chip->mask(0); |
bbc2ff6a | 326 | enable_NMI_through_LVT0(); |
b81bb373 | 327 | legacy_pic->chip->unmask(0); |
bbc2ff6a GOC |
328 | } |
329 | ||
4f062896 | 330 | /* This must be done before setting cpu_online_mask */ |
bbc2ff6a GOC |
331 | set_cpu_sibling_map(raw_smp_processor_id()); |
332 | wmb(); | |
333 | ||
334 | /* | |
335 | * We need to hold call_lock, so there is no inconsistency | |
336 | * between the time smp_call_function() determines number of | |
337 | * IPI recipients, and the time when the determination is made | |
338 | * for which cpus receive the IPI. Holding this | |
339 | * lock helps us to not include this cpu in a currently in progress | |
340 | * smp_call_function(). | |
d388e5fd EB |
341 | * |
342 | * We need to hold vector_lock so there the set of online cpus | |
343 | * does not change while we are assigning vectors to cpus. Holding | |
344 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 345 | */ |
0cefa5b9 | 346 | ipi_call_lock(); |
d388e5fd | 347 | lock_vector_lock(); |
c2d1cec1 | 348 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 349 | unlock_vector_lock(); |
0cefa5b9 | 350 | ipi_call_unlock(); |
bbc2ff6a | 351 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 352 | x86_platform.nmi_init(); |
bbc2ff6a | 353 | |
0cefa5b9 MS |
354 | /* enable local interrupts */ |
355 | local_irq_enable(); | |
356 | ||
35f720c5 JP |
357 | /* to prevent fake stack check failure in clock setup */ |
358 | boot_init_stack_canary(); | |
0cefa5b9 | 359 | |
736decac | 360 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
361 | |
362 | wmb(); | |
363 | cpu_idle(); | |
364 | } | |
365 | ||
155dd720 RR |
366 | #ifdef CONFIG_CPUMASK_OFFSTACK |
367 | /* In this case, llc_shared_map is a pointer to a cpumask. */ | |
368 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
369 | const struct cpuinfo_x86 *src) | |
370 | { | |
371 | struct cpumask *llc = dst->llc_shared_map; | |
372 | *dst = *src; | |
373 | dst->llc_shared_map = llc; | |
374 | } | |
375 | #else | |
376 | static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, | |
377 | const struct cpuinfo_x86 *src) | |
378 | { | |
379 | *dst = *src; | |
380 | } | |
381 | #endif /* CONFIG_CPUMASK_OFFSTACK */ | |
382 | ||
1d89a7f0 GOC |
383 | /* |
384 | * The bootstrap kernel entry code has set these up. Save them for | |
385 | * a given CPU | |
386 | */ | |
387 | ||
388 | void __cpuinit smp_store_cpu_info(int id) | |
389 | { | |
390 | struct cpuinfo_x86 *c = &cpu_data(id); | |
391 | ||
155dd720 | 392 | copy_cpuinfo_x86(c, &boot_cpu_data); |
1d89a7f0 GOC |
393 | c->cpu_index = id; |
394 | if (id != 0) | |
395 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
396 | } |
397 | ||
398 | ||
768d9505 GC |
399 | void __cpuinit set_cpu_sibling_map(int cpu) |
400 | { | |
401 | int i; | |
402 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
403 | ||
c2d1cec1 | 404 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
405 | |
406 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
407 | for_each_cpu(i, cpu_sibling_setup_mask) { |
408 | struct cpuinfo_x86 *o = &cpu_data(i); | |
409 | ||
410 | if (c->phys_proc_id == o->phys_proc_id && | |
411 | c->cpu_core_id == o->cpu_core_id) { | |
412 | cpumask_set_cpu(i, cpu_sibling_mask(cpu)); | |
413 | cpumask_set_cpu(cpu, cpu_sibling_mask(i)); | |
414 | cpumask_set_cpu(i, cpu_core_mask(cpu)); | |
415 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
155dd720 RR |
416 | cpumask_set_cpu(i, c->llc_shared_map); |
417 | cpumask_set_cpu(cpu, o->llc_shared_map); | |
768d9505 GC |
418 | } |
419 | } | |
420 | } else { | |
c2d1cec1 | 421 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
422 | } |
423 | ||
155dd720 | 424 | cpumask_set_cpu(cpu, c->llc_shared_map); |
768d9505 GC |
425 | |
426 | if (current_cpu_data.x86_max_cores == 1) { | |
c2d1cec1 | 427 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
428 | c->booted_cores = 1; |
429 | return; | |
430 | } | |
431 | ||
c2d1cec1 | 432 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
433 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
434 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
155dd720 RR |
435 | cpumask_set_cpu(i, c->llc_shared_map); |
436 | cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); | |
768d9505 GC |
437 | } |
438 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
439 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
440 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
441 | /* |
442 | * Does this new cpu bringup a new core? | |
443 | */ | |
c2d1cec1 | 444 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
445 | /* |
446 | * for each core in package, increment | |
447 | * the booted_cores for this new cpu | |
448 | */ | |
c2d1cec1 | 449 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
450 | c->booted_cores++; |
451 | /* | |
452 | * increment the core count for all | |
453 | * the other cpus in this package | |
454 | */ | |
455 | if (i != cpu) | |
456 | cpu_data(i).booted_cores++; | |
457 | } else if (i != cpu && !c->booted_cores) | |
458 | c->booted_cores = cpu_data(i).booted_cores; | |
459 | } | |
460 | } | |
461 | } | |
462 | ||
70708a18 | 463 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 464 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
465 | { |
466 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
467 | /* | |
468 | * For perf, we return last level cache shared map. | |
469 | * And for power savings, we return cpu_core_map | |
470 | */ | |
5a925b42 AH |
471 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
472 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 473 | return cpu_core_mask(cpu); |
70708a18 | 474 | else |
155dd720 | 475 | return c->llc_shared_map; |
030bb203 RR |
476 | } |
477 | ||
a4928cff | 478 | static void impress_friends(void) |
904541e2 GOC |
479 | { |
480 | int cpu; | |
481 | unsigned long bogosum = 0; | |
482 | /* | |
483 | * Allow the user to impress friends. | |
484 | */ | |
cfc1b9a6 | 485 | pr_debug("Before bogomips.\n"); |
904541e2 | 486 | for_each_possible_cpu(cpu) |
c2d1cec1 | 487 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
488 | bogosum += cpu_data(cpu).loops_per_jiffy; |
489 | printk(KERN_INFO | |
490 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 491 | num_online_cpus(), |
904541e2 GOC |
492 | bogosum/(500000/HZ), |
493 | (bogosum/(5000/HZ))%100); | |
494 | ||
cfc1b9a6 | 495 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
496 | } |
497 | ||
569712b2 | 498 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
499 | { |
500 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
501 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
502 | int timeout; | |
503 | u32 status; | |
504 | ||
823b259b | 505 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
506 | |
507 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 508 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
509 | |
510 | /* | |
511 | * Wait for idle. | |
512 | */ | |
513 | status = safe_apic_wait_icr_idle(); | |
514 | if (status) | |
515 | printk(KERN_CONT | |
516 | "a previous APIC delivery may have failed\n"); | |
517 | ||
1b374e4d | 518 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
519 | |
520 | timeout = 0; | |
521 | do { | |
522 | udelay(100); | |
523 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
524 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
525 | ||
526 | switch (status) { | |
527 | case APIC_ICR_RR_VALID: | |
528 | status = apic_read(APIC_RRR); | |
529 | printk(KERN_CONT "%08x\n", status); | |
530 | break; | |
531 | default: | |
532 | printk(KERN_CONT "failed\n"); | |
533 | } | |
534 | } | |
535 | } | |
536 | ||
cb3c8b90 GOC |
537 | /* |
538 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
539 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
540 | * won't ... remember to clear down the APIC, etc later. | |
541 | */ | |
cece3155 | 542 | int __cpuinit |
569712b2 | 543 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
544 | { |
545 | unsigned long send_status, accept_status = 0; | |
546 | int maxlvt; | |
547 | ||
548 | /* Target chip */ | |
cb3c8b90 GOC |
549 | /* Boot on the stack */ |
550 | /* Kick the second */ | |
bdb1a9b6 | 551 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 552 | |
cfc1b9a6 | 553 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
554 | send_status = safe_apic_wait_icr_idle(); |
555 | ||
556 | /* | |
557 | * Give the other CPU some time to accept the IPI. | |
558 | */ | |
559 | udelay(200); | |
569712b2 | 560 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
561 | maxlvt = lapic_get_maxlvt(); |
562 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
563 | apic_write(APIC_ESR, 0); | |
564 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
565 | } | |
cfc1b9a6 | 566 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
567 | |
568 | if (send_status) | |
569 | printk(KERN_ERR "APIC never delivered???\n"); | |
570 | if (accept_status) | |
571 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
572 | ||
573 | return (send_status | accept_status); | |
574 | } | |
cb3c8b90 | 575 | |
cece3155 | 576 | static int __cpuinit |
569712b2 | 577 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
578 | { |
579 | unsigned long send_status, accept_status = 0; | |
580 | int maxlvt, num_starts, j; | |
581 | ||
593f4a78 MR |
582 | maxlvt = lapic_get_maxlvt(); |
583 | ||
cb3c8b90 GOC |
584 | /* |
585 | * Be paranoid about clearing APIC errors. | |
586 | */ | |
587 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
588 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
589 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
590 | apic_read(APIC_ESR); |
591 | } | |
592 | ||
cfc1b9a6 | 593 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
594 | |
595 | /* | |
596 | * Turn INIT on target chip | |
597 | */ | |
cb3c8b90 GOC |
598 | /* |
599 | * Send IPI | |
600 | */ | |
1b374e4d SS |
601 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
602 | phys_apicid); | |
cb3c8b90 | 603 | |
cfc1b9a6 | 604 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
605 | send_status = safe_apic_wait_icr_idle(); |
606 | ||
607 | mdelay(10); | |
608 | ||
cfc1b9a6 | 609 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
610 | |
611 | /* Target chip */ | |
cb3c8b90 | 612 | /* Send IPI */ |
1b374e4d | 613 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 614 | |
cfc1b9a6 | 615 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
616 | send_status = safe_apic_wait_icr_idle(); |
617 | ||
618 | mb(); | |
619 | atomic_set(&init_deasserted, 1); | |
620 | ||
621 | /* | |
622 | * Should we send STARTUP IPIs ? | |
623 | * | |
624 | * Determine this based on the APIC version. | |
625 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
626 | */ | |
627 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
628 | num_starts = 2; | |
629 | else | |
630 | num_starts = 0; | |
631 | ||
632 | /* | |
633 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
634 | * target processor state. | |
635 | */ | |
636 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 637 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
638 | |
639 | /* | |
640 | * Run STARTUP IPI loop. | |
641 | */ | |
cfc1b9a6 | 642 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 643 | |
cb3c8b90 | 644 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 645 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
646 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
647 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 648 | apic_read(APIC_ESR); |
cfc1b9a6 | 649 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
650 | |
651 | /* | |
652 | * STARTUP IPI | |
653 | */ | |
654 | ||
655 | /* Target chip */ | |
cb3c8b90 GOC |
656 | /* Boot on the stack */ |
657 | /* Kick the second */ | |
1b374e4d SS |
658 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
659 | phys_apicid); | |
cb3c8b90 GOC |
660 | |
661 | /* | |
662 | * Give the other CPU some time to accept the IPI. | |
663 | */ | |
664 | udelay(300); | |
665 | ||
cfc1b9a6 | 666 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 667 | |
cfc1b9a6 | 668 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
669 | send_status = safe_apic_wait_icr_idle(); |
670 | ||
671 | /* | |
672 | * Give the other CPU some time to accept the IPI. | |
673 | */ | |
674 | udelay(200); | |
593f4a78 | 675 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 676 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
677 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
678 | if (send_status || accept_status) | |
679 | break; | |
680 | } | |
cfc1b9a6 | 681 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
682 | |
683 | if (send_status) | |
684 | printk(KERN_ERR "APIC never delivered???\n"); | |
685 | if (accept_status) | |
686 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
687 | ||
688 | return (send_status | accept_status); | |
689 | } | |
cb3c8b90 GOC |
690 | |
691 | struct create_idle { | |
692 | struct work_struct work; | |
693 | struct task_struct *idle; | |
694 | struct completion done; | |
695 | int cpu; | |
696 | }; | |
697 | ||
698 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
699 | { | |
700 | struct create_idle *c_idle = | |
701 | container_of(work, struct create_idle, work); | |
702 | ||
703 | c_idle->idle = fork_idle(c_idle->cpu); | |
704 | complete(&c_idle->done); | |
705 | } | |
706 | ||
2eaad1fd MT |
707 | /* reduce the number of lines printed when booting a large cpu count system */ |
708 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
709 | { | |
710 | static int current_node = -1; | |
4adc8b71 | 711 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
712 | |
713 | if (system_state == SYSTEM_BOOTING) { | |
714 | if (node != current_node) { | |
715 | if (current_node > (-1)) | |
716 | pr_cont(" Ok.\n"); | |
717 | current_node = node; | |
718 | pr_info("Booting Node %3d, Processors ", node); | |
719 | } | |
720 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
721 | return; | |
722 | } else | |
723 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
724 | node, cpu, apicid); | |
725 | } | |
726 | ||
cb3c8b90 GOC |
727 | /* |
728 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
729 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
730 | * Returns zero if CPU booted OK, else error code from |
731 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 732 | */ |
ab6fb7c0 | 733 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
734 | { |
735 | unsigned long boot_error = 0; | |
cb3c8b90 | 736 | unsigned long start_ip; |
ab6fb7c0 | 737 | int timeout; |
cb3c8b90 | 738 | struct create_idle c_idle = { |
ab6fb7c0 IM |
739 | .cpu = cpu, |
740 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 741 | }; |
ab6fb7c0 | 742 | |
dc186ad7 | 743 | INIT_WORK_ON_STACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 744 | |
cb3c8b90 GOC |
745 | alternatives_smp_switch(1); |
746 | ||
747 | c_idle.idle = get_idle_for_cpu(cpu); | |
748 | ||
749 | /* | |
750 | * We can't use kernel_thread since we must avoid to | |
751 | * reschedule the child. | |
752 | */ | |
753 | if (c_idle.idle) { | |
754 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
755 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
756 | init_idle(c_idle.idle, cpu); | |
757 | goto do_rest; | |
758 | } | |
759 | ||
d7a7c573 SS |
760 | schedule_work(&c_idle.work); |
761 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
762 | |
763 | if (IS_ERR(c_idle.idle)) { | |
764 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 765 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
766 | return PTR_ERR(c_idle.idle); |
767 | } | |
768 | ||
769 | set_idle_for_cpu(cpu, c_idle.idle); | |
770 | do_rest: | |
cb3c8b90 | 771 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 772 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 773 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 | 774 | irq_ctx_init(cpu); |
fd89a137 | 775 | initial_page_table = __pa(&trampoline_pg_dir); |
cb3c8b90 | 776 | #else |
cb3c8b90 | 777 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 778 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
779 | per_cpu(kernel_stack, cpu) = |
780 | (unsigned long)task_stack_page(c_idle.idle) - | |
781 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 782 | #endif |
a939098a | 783 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 784 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 785 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
786 | |
787 | /* start_ip had better be page-aligned! */ | |
788 | start_ip = setup_trampoline(); | |
789 | ||
2eaad1fd MT |
790 | /* So we see what's up */ |
791 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
792 | |
793 | /* | |
794 | * This grunge runs the startup process for | |
795 | * the targeted processor. | |
796 | */ | |
797 | ||
798 | atomic_set(&init_deasserted, 0); | |
799 | ||
34d05591 | 800 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 801 | |
cfc1b9a6 | 802 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 803 | |
34d05591 JS |
804 | smpboot_setup_warm_reset_vector(start_ip); |
805 | /* | |
806 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
807 | */ |
808 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
809 | apic_write(APIC_ESR, 0); | |
810 | apic_read(APIC_ESR); | |
811 | } | |
34d05591 | 812 | } |
cb3c8b90 | 813 | |
cb3c8b90 | 814 | /* |
1f5bcabf IM |
815 | * Kick the secondary CPU. Use the method in the APIC driver |
816 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 817 | */ |
1f5bcabf IM |
818 | if (apic->wakeup_secondary_cpu) |
819 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
820 | else | |
821 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
822 | |
823 | if (!boot_error) { | |
824 | /* | |
825 | * allow APs to start initializing. | |
826 | */ | |
cfc1b9a6 | 827 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 828 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 829 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
830 | |
831 | /* | |
832 | * Wait 5s total for a response | |
833 | */ | |
834 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 835 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
836 | break; /* It has booted */ |
837 | udelay(100); | |
68f202e4 SS |
838 | /* |
839 | * Allow other tasks to run while we wait for the | |
840 | * AP to come online. This also gives a chance | |
841 | * for the MTRR work(triggered by the AP coming online) | |
842 | * to be completed in the stop machine context. | |
843 | */ | |
844 | schedule(); | |
cb3c8b90 GOC |
845 | } |
846 | ||
2eaad1fd MT |
847 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
848 | pr_debug("CPU%d: has booted.\n", cpu); | |
849 | else { | |
cb3c8b90 GOC |
850 | boot_error = 1; |
851 | if (*((volatile unsigned char *)trampoline_base) | |
852 | == 0xA5) | |
853 | /* trampoline started but...? */ | |
2eaad1fd | 854 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
855 | else |
856 | /* trampoline code not run */ | |
2eaad1fd | 857 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
858 | if (apic->inquire_remote_apic) |
859 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
860 | } |
861 | } | |
1a51e3a0 | 862 | |
cb3c8b90 GOC |
863 | if (boot_error) { |
864 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 865 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
866 | |
867 | /* was set by do_boot_cpu() */ | |
868 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
869 | ||
870 | /* was set by cpu_init() */ | |
871 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
872 | ||
873 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
874 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
875 | } | |
876 | ||
877 | /* mark "stuck" area as not stuck */ | |
878 | *((volatile unsigned long *)trampoline_base) = 0; | |
879 | ||
02421f98 YL |
880 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
881 | /* | |
882 | * Cleanup possible dangling ends... | |
883 | */ | |
884 | smpboot_restore_warm_reset_vector(); | |
885 | } | |
63d38198 | 886 | |
dc186ad7 | 887 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
888 | return boot_error; |
889 | } | |
890 | ||
891 | int __cpuinit native_cpu_up(unsigned int cpu) | |
892 | { | |
a21769a4 | 893 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
894 | unsigned long flags; |
895 | int err; | |
896 | ||
897 | WARN_ON(irqs_disabled()); | |
898 | ||
cfc1b9a6 | 899 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
900 | |
901 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
902 | !physid_isset(apicid, phys_cpu_present_map)) { | |
903 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
904 | return -EINVAL; | |
905 | } | |
906 | ||
907 | /* | |
908 | * Already booted CPU? | |
909 | */ | |
c2d1cec1 | 910 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 911 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
912 | return -ENOSYS; |
913 | } | |
914 | ||
915 | /* | |
916 | * Save current MTRR state in case it was changed since early boot | |
917 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
918 | */ | |
919 | mtrr_save_state(); | |
920 | ||
921 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
922 | ||
cb3c8b90 | 923 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 924 | |
61165d7a | 925 | if (err) { |
cfc1b9a6 | 926 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 927 | return -EIO; |
cb3c8b90 GOC |
928 | } |
929 | ||
930 | /* | |
931 | * Check TSC synchronization with the AP (keep irqs disabled | |
932 | * while doing so): | |
933 | */ | |
934 | local_irq_save(flags); | |
935 | check_tsc_sync_source(cpu); | |
936 | local_irq_restore(flags); | |
937 | ||
7c04e64a | 938 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
939 | cpu_relax(); |
940 | touch_nmi_watchdog(); | |
941 | } | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
8aef135c GOC |
946 | /* |
947 | * Fall back to non SMP mode after errors. | |
948 | * | |
949 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
950 | */ | |
951 | static __init void disable_smp(void) | |
952 | { | |
4f062896 RR |
953 | init_cpu_present(cpumask_of(0)); |
954 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 955 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 956 | |
8aef135c | 957 | if (smp_found_config) |
b6df1b8b | 958 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 959 | else |
b6df1b8b | 960 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c | 961 | map_cpu_to_logical_apicid(); |
c2d1cec1 MT |
962 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
963 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
964 | } |
965 | ||
966 | /* | |
967 | * Various sanity checks. | |
968 | */ | |
969 | static int __init smp_sanity_check(unsigned max_cpus) | |
970 | { | |
ac23d4ee | 971 | preempt_disable(); |
a58f03b0 | 972 | |
1ff2f20d | 973 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
974 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
975 | unsigned int cpu; | |
976 | unsigned nr; | |
977 | ||
978 | printk(KERN_WARNING | |
979 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 980 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
981 | |
982 | nr = 0; | |
983 | for_each_present_cpu(cpu) { | |
984 | if (nr >= 8) | |
c2d1cec1 | 985 | set_cpu_present(cpu, false); |
a58f03b0 YL |
986 | nr++; |
987 | } | |
988 | ||
989 | nr = 0; | |
990 | for_each_possible_cpu(cpu) { | |
991 | if (nr >= 8) | |
c2d1cec1 | 992 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
993 | nr++; |
994 | } | |
995 | ||
996 | nr_cpu_ids = 8; | |
997 | } | |
998 | #endif | |
999 | ||
8aef135c | 1000 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
1001 | printk(KERN_WARNING |
1002 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1003 | hard_smp_processor_id()); | |
1004 | ||
8aef135c GOC |
1005 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1006 | } | |
1007 | ||
1008 | /* | |
1009 | * If we couldn't find an SMP configuration at boot time, | |
1010 | * get out of here now! | |
1011 | */ | |
1012 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1013 | preempt_enable(); |
8aef135c GOC |
1014 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1015 | disable_smp(); | |
1016 | if (APIC_init_uniprocessor()) | |
1017 | printk(KERN_NOTICE "Local APIC not detected." | |
1018 | " Using dummy APIC emulation.\n"); | |
1019 | return -1; | |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * Should not be necessary because the MP table should list the boot | |
1024 | * CPU too, but we do it for the sake of robustness anyway. | |
1025 | */ | |
a27a6210 | 1026 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
1027 | printk(KERN_NOTICE |
1028 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1029 | boot_cpu_physical_apicid); | |
1030 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1031 | } | |
ac23d4ee | 1032 | preempt_enable(); |
8aef135c GOC |
1033 | |
1034 | /* | |
1035 | * If we couldn't find a local APIC, then get out of here now! | |
1036 | */ | |
1037 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1038 | !cpu_has_apic) { | |
103428e5 CG |
1039 | if (!disable_apic) { |
1040 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1041 | boot_cpu_physical_apicid); | |
1042 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 1043 | "(tell your hw vendor)\n"); |
103428e5 | 1044 | } |
8aef135c | 1045 | smpboot_clear_io_apic(); |
65a4e574 | 1046 | arch_disable_smp_support(); |
8aef135c GOC |
1047 | return -1; |
1048 | } | |
1049 | ||
1050 | verify_local_APIC(); | |
1051 | ||
1052 | /* | |
1053 | * If SMP should be disabled, then really disable it! | |
1054 | */ | |
1055 | if (!max_cpus) { | |
73d08e63 | 1056 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1057 | smpboot_clear_io_apic(); |
d54db1ac MR |
1058 | |
1059 | localise_nmi_watchdog(); | |
1060 | ||
e90955c2 | 1061 | connect_bsp_APIC(); |
e90955c2 JB |
1062 | setup_local_APIC(); |
1063 | end_local_APIC_setup(); | |
8aef135c GOC |
1064 | return -1; |
1065 | } | |
1066 | ||
1067 | return 0; | |
1068 | } | |
1069 | ||
1070 | static void __init smp_cpu_index_default(void) | |
1071 | { | |
1072 | int i; | |
1073 | struct cpuinfo_x86 *c; | |
1074 | ||
7c04e64a | 1075 | for_each_possible_cpu(i) { |
8aef135c GOC |
1076 | c = &cpu_data(i); |
1077 | /* mark all to hotplug */ | |
9628937d | 1078 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1079 | } |
1080 | } | |
1081 | ||
1082 | /* | |
1083 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1084 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1085 | */ | |
1086 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1087 | { | |
7ad728f9 RR |
1088 | unsigned int i; |
1089 | ||
deef3250 | 1090 | preempt_disable(); |
8aef135c GOC |
1091 | smp_cpu_index_default(); |
1092 | current_cpu_data = boot_cpu_data; | |
c2d1cec1 | 1093 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
8aef135c GOC |
1094 | mb(); |
1095 | /* | |
1096 | * Setup boot CPU information | |
1097 | */ | |
1098 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1b374e4d | 1099 | #ifdef CONFIG_X86_32 |
8aef135c | 1100 | boot_cpu_logical_apicid = logical_smp_processor_id(); |
1b374e4d | 1101 | #endif |
8aef135c | 1102 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1103 | for_each_possible_cpu(i) { |
79f55997 LZ |
1104 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1105 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
1106 | zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); | |
7ad728f9 | 1107 | } |
8aef135c GOC |
1108 | set_cpu_sibling_map(0); |
1109 | ||
6e1cb38a | 1110 | enable_IR_x2apic(); |
72ce0165 | 1111 | default_setup_apic_routing(); |
6e1cb38a | 1112 | |
8aef135c GOC |
1113 | if (smp_sanity_check(max_cpus) < 0) { |
1114 | printk(KERN_INFO "SMP disabled\n"); | |
1115 | disable_smp(); | |
deef3250 | 1116 | goto out; |
8aef135c GOC |
1117 | } |
1118 | ||
ac23d4ee | 1119 | preempt_disable(); |
4c9961d5 | 1120 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1121 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1122 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1123 | /* Or can we switch back to PIC here? */ |
1124 | } | |
ac23d4ee | 1125 | preempt_enable(); |
8aef135c | 1126 | |
8aef135c | 1127 | connect_bsp_APIC(); |
b5841765 | 1128 | |
8aef135c GOC |
1129 | /* |
1130 | * Switch from PIC to APIC mode. | |
1131 | */ | |
1132 | setup_local_APIC(); | |
1133 | ||
8aef135c GOC |
1134 | /* |
1135 | * Enable IO APIC before setting up error vector | |
1136 | */ | |
1137 | if (!skip_ioapic_setup && nr_ioapics) | |
1138 | enable_IO_APIC(); | |
88d0f550 | 1139 | |
8aef135c GOC |
1140 | end_local_APIC_setup(); |
1141 | ||
1142 | map_cpu_to_logical_apicid(); | |
1143 | ||
d83093b5 IM |
1144 | if (apic->setup_portio_remap) |
1145 | apic->setup_portio_remap(); | |
8aef135c GOC |
1146 | |
1147 | smpboot_setup_io_apic(); | |
1148 | /* | |
1149 | * Set up local APIC timer on boot CPU. | |
1150 | */ | |
1151 | ||
1152 | printk(KERN_INFO "CPU%d: ", 0); | |
1153 | print_cpu_info(&cpu_data(0)); | |
736decac | 1154 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1155 | |
1156 | if (is_uv_system()) | |
1157 | uv_system_init(); | |
d0af9eed SS |
1158 | |
1159 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1160 | out: |
1161 | preempt_enable(); | |
8aef135c | 1162 | } |
d0af9eed SS |
1163 | |
1164 | void arch_enable_nonboot_cpus_begin(void) | |
1165 | { | |
1166 | set_mtrr_aps_delayed_init(); | |
1167 | } | |
1168 | ||
1169 | void arch_enable_nonboot_cpus_end(void) | |
1170 | { | |
1171 | mtrr_aps_init(); | |
1172 | } | |
1173 | ||
a8db8453 GOC |
1174 | /* |
1175 | * Early setup to make printk work. | |
1176 | */ | |
1177 | void __init native_smp_prepare_boot_cpu(void) | |
1178 | { | |
1179 | int me = smp_processor_id(); | |
552be871 | 1180 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1181 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1182 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1183 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1184 | } | |
1185 | ||
83f7eb9c GOC |
1186 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1187 | { | |
cfc1b9a6 | 1188 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1189 | |
1190 | impress_friends(); | |
83f7eb9c GOC |
1191 | #ifdef CONFIG_X86_IO_APIC |
1192 | setup_ioapic_dest(); | |
1193 | #endif | |
1194 | check_nmi_watchdog(); | |
d0af9eed | 1195 | mtrr_aps_init(); |
83f7eb9c GOC |
1196 | } |
1197 | ||
3b11ce7f MT |
1198 | static int __initdata setup_possible_cpus = -1; |
1199 | static int __init _setup_possible_cpus(char *str) | |
1200 | { | |
1201 | get_option(&str, &setup_possible_cpus); | |
1202 | return 0; | |
1203 | } | |
1204 | early_param("possible_cpus", _setup_possible_cpus); | |
1205 | ||
1206 | ||
68a1c3f8 | 1207 | /* |
4f062896 | 1208 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1209 | * are onlined, or offlined. The reason is per-cpu data-structures |
1210 | * are allocated by some modules at init time, and dont expect to | |
1211 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1212 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1213 | * In case when cpu_hotplug is not compiled, then we resort to current |
1214 | * behaviour, which is cpu_possible == cpu_present. | |
1215 | * - Ashok Raj | |
1216 | * | |
1217 | * Three ways to find out the number of additional hotplug CPUs: | |
1218 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1219 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1220 | * - Otherwise don't reserve additional CPUs. |
1221 | * We do this because additional CPUs waste a lot of memory. | |
1222 | * -AK | |
1223 | */ | |
1224 | __init void prefill_possible_map(void) | |
1225 | { | |
cb48bb59 | 1226 | int i, possible; |
68a1c3f8 | 1227 | |
329513a3 YL |
1228 | /* no processor from mptable or madt */ |
1229 | if (!num_processors) | |
1230 | num_processors = 1; | |
1231 | ||
5f2eb550 JB |
1232 | i = setup_max_cpus ?: 1; |
1233 | if (setup_possible_cpus == -1) { | |
1234 | possible = num_processors; | |
1235 | #ifdef CONFIG_HOTPLUG_CPU | |
1236 | if (setup_max_cpus) | |
1237 | possible += disabled_cpus; | |
1238 | #else | |
1239 | if (possible > i) | |
1240 | possible = i; | |
1241 | #endif | |
1242 | } else | |
3b11ce7f MT |
1243 | possible = setup_possible_cpus; |
1244 | ||
730cf272 MT |
1245 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1246 | ||
2b633e3f YL |
1247 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1248 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1249 | printk(KERN_WARNING |
1250 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1251 | possible, nr_cpu_ids); |
1252 | possible = nr_cpu_ids; | |
3b11ce7f | 1253 | } |
68a1c3f8 | 1254 | |
5f2eb550 JB |
1255 | #ifdef CONFIG_HOTPLUG_CPU |
1256 | if (!setup_max_cpus) | |
1257 | #endif | |
1258 | if (possible > i) { | |
1259 | printk(KERN_WARNING | |
1260 | "%d Processors exceeds max_cpus limit of %u\n", | |
1261 | possible, setup_max_cpus); | |
1262 | possible = i; | |
1263 | } | |
1264 | ||
68a1c3f8 GC |
1265 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1266 | possible, max_t(int, possible - num_processors, 0)); | |
1267 | ||
1268 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1269 | set_cpu_possible(i, true); |
5f2eb550 JB |
1270 | for (; i < NR_CPUS; i++) |
1271 | set_cpu_possible(i, false); | |
3461b0af MT |
1272 | |
1273 | nr_cpu_ids = possible; | |
68a1c3f8 | 1274 | } |
69c18c15 | 1275 | |
14adf855 CE |
1276 | #ifdef CONFIG_HOTPLUG_CPU |
1277 | ||
1278 | static void remove_siblinginfo(int cpu) | |
1279 | { | |
1280 | int sibling; | |
1281 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1282 | ||
c2d1cec1 MT |
1283 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1284 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1285 | /*/ |
1286 | * last thread sibling in this cpu core going down | |
1287 | */ | |
c2d1cec1 | 1288 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1289 | cpu_data(sibling).booted_cores--; |
1290 | } | |
1291 | ||
c2d1cec1 MT |
1292 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1293 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1294 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1295 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1296 | c->phys_proc_id = 0; |
1297 | c->cpu_core_id = 0; | |
c2d1cec1 | 1298 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1299 | } |
1300 | ||
69c18c15 GC |
1301 | static void __ref remove_cpu_from_maps(int cpu) |
1302 | { | |
c2d1cec1 MT |
1303 | set_cpu_online(cpu, false); |
1304 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1305 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1306 | /* was set by cpu_init() */ |
c2d1cec1 | 1307 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1308 | numa_remove_cpu(cpu); |
69c18c15 GC |
1309 | } |
1310 | ||
8227dce7 | 1311 | void cpu_disable_common(void) |
69c18c15 GC |
1312 | { |
1313 | int cpu = smp_processor_id(); | |
69c18c15 | 1314 | |
69c18c15 GC |
1315 | remove_siblinginfo(cpu); |
1316 | ||
1317 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1318 | lock_vector_lock(); |
69c18c15 | 1319 | remove_cpu_from_maps(cpu); |
d388e5fd | 1320 | unlock_vector_lock(); |
d7b381bb | 1321 | fixup_irqs(); |
8227dce7 AN |
1322 | } |
1323 | ||
1324 | int native_cpu_disable(void) | |
1325 | { | |
1326 | int cpu = smp_processor_id(); | |
1327 | ||
1328 | /* | |
1329 | * Perhaps use cpufreq to drop frequency, but that could go | |
1330 | * into generic code. | |
1331 | * | |
1332 | * We won't take down the boot processor on i386 due to some | |
1333 | * interrupts only being able to be serviced by the BSP. | |
1334 | * Especially so if we're not using an IOAPIC -zwane | |
1335 | */ | |
1336 | if (cpu == 0) | |
1337 | return -EBUSY; | |
1338 | ||
1339 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1340 | stop_apic_nmi_watchdog(NULL); | |
1341 | clear_local_APIC(); | |
1342 | ||
1343 | cpu_disable_common(); | |
69c18c15 GC |
1344 | return 0; |
1345 | } | |
1346 | ||
93be71b6 | 1347 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1348 | { |
1349 | /* We don't do anything here: idle task is faking death itself. */ | |
1350 | unsigned int i; | |
1351 | ||
1352 | for (i = 0; i < 10; i++) { | |
1353 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1354 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1355 | if (system_state == SYSTEM_RUNNING) |
1356 | pr_info("CPU %u is now offline\n", cpu); | |
1357 | ||
69c18c15 GC |
1358 | if (1 == num_online_cpus()) |
1359 | alternatives_smp_switch(0); | |
1360 | return; | |
1361 | } | |
1362 | msleep(100); | |
1363 | } | |
2eaad1fd | 1364 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1365 | } |
a21f5d88 AN |
1366 | |
1367 | void play_dead_common(void) | |
1368 | { | |
1369 | idle_task_exit(); | |
1370 | reset_lazy_tlbstate(); | |
1371 | irq_ctx_exit(raw_smp_processor_id()); | |
07bbc16a | 1372 | c1e_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1373 | |
1374 | mb(); | |
1375 | /* Ack it */ | |
1376 | __get_cpu_var(cpu_state) = CPU_DEAD; | |
1377 | ||
1378 | /* | |
1379 | * With physical CPU hotplug, we should halt the cpu | |
1380 | */ | |
1381 | local_irq_disable(); | |
1382 | } | |
1383 | ||
1384 | void native_play_dead(void) | |
1385 | { | |
1386 | play_dead_common(); | |
86886e55 | 1387 | tboot_shutdown(TB_SHUTDOWN_WFS); |
a21f5d88 AN |
1388 | wbinvd_halt(); |
1389 | } | |
1390 | ||
69c18c15 | 1391 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1392 | int native_cpu_disable(void) |
69c18c15 GC |
1393 | { |
1394 | return -ENOSYS; | |
1395 | } | |
1396 | ||
93be71b6 | 1397 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1398 | { |
1399 | /* We said "no" in __cpu_disable */ | |
1400 | BUG(); | |
1401 | } | |
a21f5d88 AN |
1402 | |
1403 | void native_play_dead(void) | |
1404 | { | |
1405 | BUG(); | |
1406 | } | |
1407 | ||
68a1c3f8 | 1408 | #endif |