Commit | Line | Data |
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68a1c3f8 GC |
1 | #include <linux/init.h> |
2 | #include <linux/smp.h> | |
a355352b | 3 | #include <linux/module.h> |
70708a18 | 4 | #include <linux/sched.h> |
69c18c15 | 5 | #include <linux/percpu.h> |
91718e8d | 6 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
7 | #include <linux/err.h> |
8 | #include <linux/nmi.h> | |
69c18c15 | 9 | |
8aef135c | 10 | #include <asm/acpi.h> |
cb3c8b90 | 11 | #include <asm/desc.h> |
69c18c15 GC |
12 | #include <asm/nmi.h> |
13 | #include <asm/irq.h> | |
14 | #include <asm/smp.h> | |
15 | #include <asm/cpu.h> | |
16 | #include <asm/numa.h> | |
cb3c8b90 GOC |
17 | #include <asm/pgtable.h> |
18 | #include <asm/tlbflush.h> | |
19 | #include <asm/mtrr.h> | |
20 | #include <asm/nmi.h> | |
bbc2ff6a | 21 | #include <asm/vmi.h> |
cb3c8b90 | 22 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 23 | |
f6bc4029 | 24 | #include <mach_apic.h> |
cb3c8b90 GOC |
25 | #include <mach_wakecpu.h> |
26 | #include <smpboot_hooks.h> | |
27 | ||
acbb6734 GOC |
28 | /* |
29 | * FIXME: For x86_64, those are defined in other files. But moving them here, | |
30 | * would make the setup areas dependent on smp, which is a loss. When we | |
31 | * integrate apic between arches, we can probably do a better job, but | |
32 | * right now, they'll stay here -- glommer | |
33 | */ | |
34 | #ifdef CONFIG_X86_32 | |
35 | /* which logical CPU number maps to which CPU (physical APIC ID) */ | |
36 | u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata = | |
37 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
38 | void *x86_cpu_to_apicid_early_ptr; | |
39 | DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID; | |
40 | EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid); | |
41 | ||
42 | u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata | |
43 | = { [0 ... NR_CPUS-1] = BAD_APICID }; | |
44 | void *x86_bios_cpu_apicid_early_ptr; | |
45 | DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID; | |
46 | EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid); | |
47 | #endif | |
48 | ||
a8db8453 GOC |
49 | /* State of each CPU */ |
50 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
51 | ||
cb3c8b90 GOC |
52 | /* Store all idle threads, this can be reused instead of creating |
53 | * a new thread. Also avoids complicated thread destroy functionality | |
54 | * for idle threads. | |
55 | */ | |
56 | #ifdef CONFIG_HOTPLUG_CPU | |
57 | /* | |
58 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
59 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
60 | */ | |
61 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
62 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
63 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
64 | #else | |
65 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
66 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
67 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
68 | #endif | |
f6bc4029 | 69 | |
a355352b GC |
70 | /* Number of siblings per CPU package */ |
71 | int smp_num_siblings = 1; | |
72 | EXPORT_SYMBOL(smp_num_siblings); | |
73 | ||
74 | /* Last level cache ID of each logical CPU */ | |
75 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
76 | ||
77 | /* bitmap of online cpus */ | |
78 | cpumask_t cpu_online_map __read_mostly; | |
79 | EXPORT_SYMBOL(cpu_online_map); | |
80 | ||
81 | cpumask_t cpu_callin_map; | |
82 | cpumask_t cpu_callout_map; | |
83 | cpumask_t cpu_possible_map; | |
84 | EXPORT_SYMBOL(cpu_possible_map); | |
85 | ||
86 | /* representing HT siblings of each logical CPU */ | |
87 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
89 | ||
90 | /* representing HT and core siblings of each logical CPU */ | |
91 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
93 | ||
94 | /* Per CPU bogomips and other parameters */ | |
95 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
96 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 97 | |
cb3c8b90 GOC |
98 | static atomic_t init_deasserted; |
99 | ||
8aef135c GOC |
100 | static int boot_cpu_logical_apicid; |
101 | ||
91718e8d GC |
102 | /* ready for x86_64, no harm for x86, since it will overwrite after alloc */ |
103 | unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE); | |
104 | ||
768d9505 GC |
105 | /* representing cpus for which sibling maps can be computed */ |
106 | static cpumask_t cpu_sibling_setup_map; | |
107 | ||
1d89a7f0 GOC |
108 | /* Set if we find a B stepping CPU */ |
109 | int __cpuinitdata smp_b_stepping; | |
1d89a7f0 | 110 | |
7cc3959e GOC |
111 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
112 | ||
113 | /* which logical CPUs are on which nodes */ | |
114 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
115 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
116 | EXPORT_SYMBOL(node_to_cpumask_map); | |
117 | /* which node each logical CPU is on */ | |
118 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
119 | EXPORT_SYMBOL(cpu_to_node_map); | |
120 | ||
121 | /* set up a mapping between cpu and node. */ | |
122 | static void map_cpu_to_node(int cpu, int node) | |
123 | { | |
124 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
125 | cpu_set(cpu, node_to_cpumask_map[node]); | |
126 | cpu_to_node_map[cpu] = node; | |
127 | } | |
128 | ||
129 | /* undo a mapping between cpu and node. */ | |
130 | static void unmap_cpu_to_node(int cpu) | |
131 | { | |
132 | int node; | |
133 | ||
134 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
135 | for (node = 0; node < MAX_NUMNODES; node++) | |
136 | cpu_clear(cpu, node_to_cpumask_map[node]); | |
137 | cpu_to_node_map[cpu] = 0; | |
138 | } | |
139 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
140 | #define map_cpu_to_node(cpu, node) ({}) | |
141 | #define unmap_cpu_to_node(cpu) ({}) | |
142 | #endif | |
143 | ||
144 | #ifdef CONFIG_X86_32 | |
145 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = | |
146 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
147 | ||
148 | void map_cpu_to_logical_apicid(void) | |
149 | { | |
150 | int cpu = smp_processor_id(); | |
151 | int apicid = logical_smp_processor_id(); | |
152 | int node = apicid_to_node(apicid); | |
153 | ||
154 | if (!node_online(node)) | |
155 | node = first_online_node; | |
156 | ||
157 | cpu_2_logical_apicid[cpu] = apicid; | |
158 | map_cpu_to_node(cpu, node); | |
159 | } | |
160 | ||
161 | void unmap_cpu_to_logical_apicid(int cpu) | |
162 | { | |
163 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
164 | unmap_cpu_to_node(cpu); | |
165 | } | |
166 | #else | |
167 | #define unmap_cpu_to_logical_apicid(cpu) do {} while (0) | |
168 | #define map_cpu_to_logical_apicid() do {} while (0) | |
169 | #endif | |
170 | ||
cb3c8b90 GOC |
171 | /* |
172 | * Report back to the Boot Processor. | |
173 | * Running on AP. | |
174 | */ | |
175 | void __cpuinit smp_callin(void) | |
176 | { | |
177 | int cpuid, phys_id; | |
178 | unsigned long timeout; | |
179 | ||
180 | /* | |
181 | * If waken up by an INIT in an 82489DX configuration | |
182 | * we may get here before an INIT-deassert IPI reaches | |
183 | * our local APIC. We have to wait for the IPI or we'll | |
184 | * lock up on an APIC access. | |
185 | */ | |
186 | wait_for_init_deassert(&init_deasserted); | |
187 | ||
188 | /* | |
189 | * (This works even if the APIC is not enabled.) | |
190 | */ | |
191 | phys_id = GET_APIC_ID(apic_read(APIC_ID)); | |
192 | cpuid = smp_processor_id(); | |
193 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
194 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, | |
195 | phys_id, cpuid); | |
196 | } | |
197 | Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); | |
198 | ||
199 | /* | |
200 | * STARTUP IPIs are fragile beasts as they might sometimes | |
201 | * trigger some glue motherboard logic. Complete APIC bus | |
202 | * silence for 1 second, this overestimates the time the | |
203 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
204 | * by a factor of two. This should be enough. | |
205 | */ | |
206 | ||
207 | /* | |
208 | * Waiting 2s total for startup (udelay is not yet working) | |
209 | */ | |
210 | timeout = jiffies + 2*HZ; | |
211 | while (time_before(jiffies, timeout)) { | |
212 | /* | |
213 | * Has the boot CPU finished it's STARTUP sequence? | |
214 | */ | |
215 | if (cpu_isset(cpuid, cpu_callout_map)) | |
216 | break; | |
217 | cpu_relax(); | |
218 | } | |
219 | ||
220 | if (!time_before(jiffies, timeout)) { | |
221 | panic("%s: CPU%d started up but did not get a callout!\n", | |
222 | __func__, cpuid); | |
223 | } | |
224 | ||
225 | /* | |
226 | * the boot CPU has finished the init stage and is spinning | |
227 | * on callin_map until we finish. We are free to set up this | |
228 | * CPU, first the APIC. (this is probably redundant on most | |
229 | * boards) | |
230 | */ | |
231 | ||
232 | Dprintk("CALLIN, before setup_local_APIC().\n"); | |
233 | smp_callin_clear_local_apic(); | |
234 | setup_local_APIC(); | |
235 | end_local_APIC_setup(); | |
236 | map_cpu_to_logical_apicid(); | |
237 | ||
238 | /* | |
239 | * Get our bogomips. | |
240 | * | |
241 | * Need to enable IRQs because it can take longer and then | |
242 | * the NMI watchdog might kill us. | |
243 | */ | |
244 | local_irq_enable(); | |
245 | calibrate_delay(); | |
246 | local_irq_disable(); | |
247 | Dprintk("Stack at about %p\n", &cpuid); | |
248 | ||
249 | /* | |
250 | * Save our processor parameters | |
251 | */ | |
252 | smp_store_cpu_info(cpuid); | |
253 | ||
254 | /* | |
255 | * Allow the master to continue. | |
256 | */ | |
257 | cpu_set(cpuid, cpu_callin_map); | |
258 | } | |
259 | ||
bbc2ff6a GOC |
260 | /* |
261 | * Activate a secondary processor. | |
262 | */ | |
263 | void __cpuinit start_secondary(void *unused) | |
264 | { | |
265 | /* | |
266 | * Don't put *anything* before cpu_init(), SMP booting is too | |
267 | * fragile that we want to limit the things done here to the | |
268 | * most necessary things. | |
269 | */ | |
270 | #ifdef CONFIG_VMI | |
271 | vmi_bringup(); | |
272 | #endif | |
273 | cpu_init(); | |
274 | preempt_disable(); | |
275 | smp_callin(); | |
276 | ||
277 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
278 | barrier(); | |
279 | /* | |
280 | * Check TSC synchronization with the BP: | |
281 | */ | |
282 | check_tsc_sync_target(); | |
283 | ||
284 | if (nmi_watchdog == NMI_IO_APIC) { | |
285 | disable_8259A_irq(0); | |
286 | enable_NMI_through_LVT0(); | |
287 | enable_8259A_irq(0); | |
288 | } | |
289 | ||
290 | /* This must be done before setting cpu_online_map */ | |
291 | set_cpu_sibling_map(raw_smp_processor_id()); | |
292 | wmb(); | |
293 | ||
294 | /* | |
295 | * We need to hold call_lock, so there is no inconsistency | |
296 | * between the time smp_call_function() determines number of | |
297 | * IPI recipients, and the time when the determination is made | |
298 | * for which cpus receive the IPI. Holding this | |
299 | * lock helps us to not include this cpu in a currently in progress | |
300 | * smp_call_function(). | |
301 | */ | |
302 | lock_ipi_call_lock(); | |
303 | #ifdef CONFIG_X86_64 | |
304 | spin_lock(&vector_lock); | |
305 | ||
306 | /* Setup the per cpu irq handling data structures */ | |
307 | __setup_vector_irq(smp_processor_id()); | |
308 | /* | |
309 | * Allow the master to continue. | |
310 | */ | |
311 | spin_unlock(&vector_lock); | |
312 | #endif | |
313 | cpu_set(smp_processor_id(), cpu_online_map); | |
314 | unlock_ipi_call_lock(); | |
315 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; | |
316 | ||
317 | setup_secondary_clock(); | |
318 | ||
319 | wmb(); | |
320 | cpu_idle(); | |
321 | } | |
322 | ||
323 | #ifdef CONFIG_X86_32 | |
324 | /* | |
325 | * Everything has been set up for the secondary | |
326 | * CPUs - they just need to reload everything | |
327 | * from the task structure | |
328 | * This function must not return. | |
329 | */ | |
330 | void __devinit initialize_secondary(void) | |
331 | { | |
332 | /* | |
333 | * We don't actually need to load the full TSS, | |
334 | * basically just the stack pointer and the ip. | |
335 | */ | |
336 | ||
337 | asm volatile( | |
338 | "movl %0,%%esp\n\t" | |
339 | "jmp *%1" | |
340 | : | |
341 | :"m" (current->thread.sp), "m" (current->thread.ip)); | |
342 | } | |
343 | #endif | |
cb3c8b90 | 344 | |
1d89a7f0 GOC |
345 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
346 | { | |
347 | #ifdef CONFIG_X86_32 | |
348 | /* | |
349 | * Mask B, Pentium, but not Pentium MMX | |
350 | */ | |
351 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
352 | c->x86 == 5 && | |
353 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
354 | c->x86_model <= 3) | |
355 | /* | |
356 | * Remember we have B step Pentia with bugs | |
357 | */ | |
358 | smp_b_stepping = 1; | |
359 | ||
360 | /* | |
361 | * Certain Athlons might work (for various values of 'work') in SMP | |
362 | * but they are not certified as MP capable. | |
363 | */ | |
364 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
365 | ||
366 | if (num_possible_cpus() == 1) | |
367 | goto valid_k7; | |
368 | ||
369 | /* Athlon 660/661 is valid. */ | |
370 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
371 | (c->x86_mask == 1))) | |
372 | goto valid_k7; | |
373 | ||
374 | /* Duron 670 is valid */ | |
375 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
376 | goto valid_k7; | |
377 | ||
378 | /* | |
379 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
380 | * bit. It's worth noting that the A5 stepping (662) of some | |
381 | * Athlon XP's have the MP bit set. | |
382 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
383 | * more. | |
384 | */ | |
385 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
386 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
387 | (c->x86_model > 7)) | |
388 | if (cpu_has_mp) | |
389 | goto valid_k7; | |
390 | ||
391 | /* If we get here, not a certified SMP capable AMD system. */ | |
392 | add_taint(TAINT_UNSAFE_SMP); | |
393 | } | |
394 | ||
395 | valid_k7: | |
396 | ; | |
397 | #endif | |
398 | } | |
399 | ||
693d4b8a GOC |
400 | void smp_checks(void) |
401 | { | |
402 | if (smp_b_stepping) | |
403 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
404 | "with B stepping processors.\n"); | |
405 | ||
406 | /* | |
407 | * Don't taint if we are running SMP kernel on a single non-MP | |
408 | * approved Athlon | |
409 | */ | |
410 | if (tainted & TAINT_UNSAFE_SMP) { | |
f68e00a3 | 411 | if (num_online_cpus()) |
693d4b8a GOC |
412 | printk(KERN_INFO "WARNING: This combination of AMD" |
413 | "processors is not suitable for SMP.\n"); | |
414 | else | |
415 | tainted &= ~TAINT_UNSAFE_SMP; | |
416 | } | |
417 | } | |
418 | ||
1d89a7f0 GOC |
419 | /* |
420 | * The bootstrap kernel entry code has set these up. Save them for | |
421 | * a given CPU | |
422 | */ | |
423 | ||
424 | void __cpuinit smp_store_cpu_info(int id) | |
425 | { | |
426 | struct cpuinfo_x86 *c = &cpu_data(id); | |
427 | ||
428 | *c = boot_cpu_data; | |
429 | c->cpu_index = id; | |
430 | if (id != 0) | |
431 | identify_secondary_cpu(c); | |
432 | smp_apply_quirks(c); | |
433 | } | |
434 | ||
435 | ||
768d9505 GC |
436 | void __cpuinit set_cpu_sibling_map(int cpu) |
437 | { | |
438 | int i; | |
439 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
440 | ||
441 | cpu_set(cpu, cpu_sibling_setup_map); | |
442 | ||
443 | if (smp_num_siblings > 1) { | |
444 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
445 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && | |
446 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
447 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); | |
448 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
449 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
450 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
451 | cpu_set(i, c->llc_shared_map); | |
452 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
453 | } | |
454 | } | |
455 | } else { | |
456 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); | |
457 | } | |
458 | ||
459 | cpu_set(cpu, c->llc_shared_map); | |
460 | ||
461 | if (current_cpu_data.x86_max_cores == 1) { | |
462 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); | |
463 | c->booted_cores = 1; | |
464 | return; | |
465 | } | |
466 | ||
467 | for_each_cpu_mask(i, cpu_sibling_setup_map) { | |
468 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && | |
469 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
470 | cpu_set(i, c->llc_shared_map); | |
471 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
472 | } | |
473 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
474 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
475 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
476 | /* | |
477 | * Does this new cpu bringup a new core? | |
478 | */ | |
479 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { | |
480 | /* | |
481 | * for each core in package, increment | |
482 | * the booted_cores for this new cpu | |
483 | */ | |
484 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) | |
485 | c->booted_cores++; | |
486 | /* | |
487 | * increment the core count for all | |
488 | * the other cpus in this package | |
489 | */ | |
490 | if (i != cpu) | |
491 | cpu_data(i).booted_cores++; | |
492 | } else if (i != cpu && !c->booted_cores) | |
493 | c->booted_cores = cpu_data(i).booted_cores; | |
494 | } | |
495 | } | |
496 | } | |
497 | ||
70708a18 GC |
498 | /* maps the cpu to the sched domain representing multi-core */ |
499 | cpumask_t cpu_coregroup_map(int cpu) | |
500 | { | |
501 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
502 | /* | |
503 | * For perf, we return last level cache shared map. | |
504 | * And for power savings, we return cpu_core_map | |
505 | */ | |
506 | if (sched_mc_power_savings || sched_smt_power_savings) | |
507 | return per_cpu(cpu_core_map, cpu); | |
508 | else | |
509 | return c->llc_shared_map; | |
510 | } | |
511 | ||
91718e8d GC |
512 | /* |
513 | * Currently trivial. Write the real->protected mode | |
514 | * bootstrap into the page concerned. The caller | |
515 | * has made sure it's suitably aligned. | |
516 | */ | |
517 | ||
518 | unsigned long __cpuinit setup_trampoline(void) | |
519 | { | |
520 | memcpy(trampoline_base, trampoline_data, | |
521 | trampoline_end - trampoline_data); | |
522 | return virt_to_phys(trampoline_base); | |
523 | } | |
524 | ||
525 | #ifdef CONFIG_X86_32 | |
526 | /* | |
527 | * We are called very early to get the low memory for the | |
528 | * SMP bootup trampoline page. | |
529 | */ | |
530 | void __init smp_alloc_memory(void) | |
531 | { | |
532 | trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE); | |
533 | /* | |
534 | * Has to be in very low memory so we can execute | |
535 | * real-mode AP code. | |
536 | */ | |
537 | if (__pa(trampoline_base) >= 0x9F000) | |
538 | BUG(); | |
539 | } | |
540 | #endif | |
70708a18 | 541 | |
904541e2 GOC |
542 | void impress_friends(void) |
543 | { | |
544 | int cpu; | |
545 | unsigned long bogosum = 0; | |
546 | /* | |
547 | * Allow the user to impress friends. | |
548 | */ | |
549 | Dprintk("Before bogomips.\n"); | |
550 | for_each_possible_cpu(cpu) | |
551 | if (cpu_isset(cpu, cpu_callout_map)) | |
552 | bogosum += cpu_data(cpu).loops_per_jiffy; | |
553 | printk(KERN_INFO | |
554 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 555 | num_online_cpus(), |
904541e2 GOC |
556 | bogosum/(500000/HZ), |
557 | (bogosum/(5000/HZ))%100); | |
558 | ||
559 | Dprintk("Before bogocount - setting activated=1.\n"); | |
560 | } | |
561 | ||
cb3c8b90 GOC |
562 | static inline void __inquire_remote_apic(int apicid) |
563 | { | |
564 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
565 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
566 | int timeout; | |
567 | u32 status; | |
568 | ||
569 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
570 | ||
571 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
572 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); | |
573 | ||
574 | /* | |
575 | * Wait for idle. | |
576 | */ | |
577 | status = safe_apic_wait_icr_idle(); | |
578 | if (status) | |
579 | printk(KERN_CONT | |
580 | "a previous APIC delivery may have failed\n"); | |
581 | ||
582 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); | |
583 | apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
584 | ||
585 | timeout = 0; | |
586 | do { | |
587 | udelay(100); | |
588 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
589 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
590 | ||
591 | switch (status) { | |
592 | case APIC_ICR_RR_VALID: | |
593 | status = apic_read(APIC_RRR); | |
594 | printk(KERN_CONT "%08x\n", status); | |
595 | break; | |
596 | default: | |
597 | printk(KERN_CONT "failed\n"); | |
598 | } | |
599 | } | |
600 | } | |
601 | ||
602 | #ifdef WAKE_SECONDARY_VIA_NMI | |
603 | /* | |
604 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
605 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
606 | * won't ... remember to clear down the APIC, etc later. | |
607 | */ | |
608 | static int __devinit | |
609 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) | |
610 | { | |
611 | unsigned long send_status, accept_status = 0; | |
612 | int maxlvt; | |
613 | ||
614 | /* Target chip */ | |
615 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); | |
616 | ||
617 | /* Boot on the stack */ | |
618 | /* Kick the second */ | |
619 | apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); | |
620 | ||
621 | Dprintk("Waiting for send to finish...\n"); | |
622 | send_status = safe_apic_wait_icr_idle(); | |
623 | ||
624 | /* | |
625 | * Give the other CPU some time to accept the IPI. | |
626 | */ | |
627 | udelay(200); | |
628 | /* | |
629 | * Due to the Pentium erratum 3AP. | |
630 | */ | |
631 | maxlvt = lapic_get_maxlvt(); | |
632 | if (maxlvt > 3) { | |
633 | apic_read_around(APIC_SPIV); | |
634 | apic_write(APIC_ESR, 0); | |
635 | } | |
636 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
637 | Dprintk("NMI sent.\n"); | |
638 | ||
639 | if (send_status) | |
640 | printk(KERN_ERR "APIC never delivered???\n"); | |
641 | if (accept_status) | |
642 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
643 | ||
644 | return (send_status | accept_status); | |
645 | } | |
646 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
647 | ||
cb3c8b90 GOC |
648 | #ifdef WAKE_SECONDARY_VIA_INIT |
649 | static int __devinit | |
650 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) | |
651 | { | |
652 | unsigned long send_status, accept_status = 0; | |
653 | int maxlvt, num_starts, j; | |
654 | ||
655 | /* | |
656 | * Be paranoid about clearing APIC errors. | |
657 | */ | |
658 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
659 | apic_read_around(APIC_SPIV); | |
660 | apic_write(APIC_ESR, 0); | |
661 | apic_read(APIC_ESR); | |
662 | } | |
663 | ||
664 | Dprintk("Asserting INIT.\n"); | |
665 | ||
666 | /* | |
667 | * Turn INIT on target chip | |
668 | */ | |
669 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
670 | ||
671 | /* | |
672 | * Send IPI | |
673 | */ | |
674 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | |
675 | | APIC_DM_INIT); | |
676 | ||
677 | Dprintk("Waiting for send to finish...\n"); | |
678 | send_status = safe_apic_wait_icr_idle(); | |
679 | ||
680 | mdelay(10); | |
681 | ||
682 | Dprintk("Deasserting INIT.\n"); | |
683 | ||
684 | /* Target chip */ | |
685 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
686 | ||
687 | /* Send IPI */ | |
688 | apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); | |
689 | ||
690 | Dprintk("Waiting for send to finish...\n"); | |
691 | send_status = safe_apic_wait_icr_idle(); | |
692 | ||
693 | mb(); | |
694 | atomic_set(&init_deasserted, 1); | |
695 | ||
696 | /* | |
697 | * Should we send STARTUP IPIs ? | |
698 | * | |
699 | * Determine this based on the APIC version. | |
700 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
701 | */ | |
702 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
703 | num_starts = 2; | |
704 | else | |
705 | num_starts = 0; | |
706 | ||
707 | /* | |
708 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
709 | * target processor state. | |
710 | */ | |
711 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
712 | #ifdef CONFIG_X86_64 | |
713 | (unsigned long)init_rsp); | |
714 | #else | |
715 | (unsigned long)stack_start.sp); | |
716 | #endif | |
717 | ||
718 | /* | |
719 | * Run STARTUP IPI loop. | |
720 | */ | |
721 | Dprintk("#startup loops: %d.\n", num_starts); | |
722 | ||
723 | maxlvt = lapic_get_maxlvt(); | |
724 | ||
725 | for (j = 1; j <= num_starts; j++) { | |
726 | Dprintk("Sending STARTUP #%d.\n", j); | |
727 | apic_read_around(APIC_SPIV); | |
728 | apic_write(APIC_ESR, 0); | |
729 | apic_read(APIC_ESR); | |
730 | Dprintk("After apic_write.\n"); | |
731 | ||
732 | /* | |
733 | * STARTUP IPI | |
734 | */ | |
735 | ||
736 | /* Target chip */ | |
737 | apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); | |
738 | ||
739 | /* Boot on the stack */ | |
740 | /* Kick the second */ | |
741 | apic_write_around(APIC_ICR, APIC_DM_STARTUP | |
742 | | (start_eip >> 12)); | |
743 | ||
744 | /* | |
745 | * Give the other CPU some time to accept the IPI. | |
746 | */ | |
747 | udelay(300); | |
748 | ||
749 | Dprintk("Startup point 1.\n"); | |
750 | ||
751 | Dprintk("Waiting for send to finish...\n"); | |
752 | send_status = safe_apic_wait_icr_idle(); | |
753 | ||
754 | /* | |
755 | * Give the other CPU some time to accept the IPI. | |
756 | */ | |
757 | udelay(200); | |
758 | /* | |
759 | * Due to the Pentium erratum 3AP. | |
760 | */ | |
761 | if (maxlvt > 3) { | |
762 | apic_read_around(APIC_SPIV); | |
763 | apic_write(APIC_ESR, 0); | |
764 | } | |
765 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
766 | if (send_status || accept_status) | |
767 | break; | |
768 | } | |
769 | Dprintk("After Startup.\n"); | |
770 | ||
771 | if (send_status) | |
772 | printk(KERN_ERR "APIC never delivered???\n"); | |
773 | if (accept_status) | |
774 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
775 | ||
776 | return (send_status | accept_status); | |
777 | } | |
778 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
779 | ||
780 | struct create_idle { | |
781 | struct work_struct work; | |
782 | struct task_struct *idle; | |
783 | struct completion done; | |
784 | int cpu; | |
785 | }; | |
786 | ||
787 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
788 | { | |
789 | struct create_idle *c_idle = | |
790 | container_of(work, struct create_idle, work); | |
791 | ||
792 | c_idle->idle = fork_idle(c_idle->cpu); | |
793 | complete(&c_idle->done); | |
794 | } | |
795 | ||
796 | static int __cpuinit do_boot_cpu(int apicid, int cpu) | |
797 | /* | |
798 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
799 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
800 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
801 | */ | |
802 | { | |
803 | unsigned long boot_error = 0; | |
804 | int timeout; | |
805 | unsigned long start_ip; | |
806 | unsigned short nmi_high = 0, nmi_low = 0; | |
807 | struct create_idle c_idle = { | |
808 | .cpu = cpu, | |
809 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
810 | }; | |
811 | INIT_WORK(&c_idle.work, do_fork_idle); | |
812 | #ifdef CONFIG_X86_64 | |
813 | /* allocate memory for gdts of secondary cpus. Hotplug is considered */ | |
814 | if (!cpu_gdt_descr[cpu].address && | |
815 | !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) { | |
816 | printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu); | |
817 | return -1; | |
818 | } | |
819 | ||
820 | /* Allocate node local memory for AP pdas */ | |
821 | if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) { | |
822 | struct x8664_pda *newpda, *pda; | |
823 | int node = cpu_to_node(cpu); | |
824 | pda = cpu_pda(cpu); | |
825 | newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC, | |
826 | node); | |
827 | if (newpda) { | |
828 | memcpy(newpda, pda, sizeof(struct x8664_pda)); | |
829 | cpu_pda(cpu) = newpda; | |
830 | } else | |
831 | printk(KERN_ERR | |
832 | "Could not allocate node local PDA for CPU %d on node %d\n", | |
833 | cpu, node); | |
834 | } | |
835 | #endif | |
836 | ||
837 | alternatives_smp_switch(1); | |
838 | ||
839 | c_idle.idle = get_idle_for_cpu(cpu); | |
840 | ||
841 | /* | |
842 | * We can't use kernel_thread since we must avoid to | |
843 | * reschedule the child. | |
844 | */ | |
845 | if (c_idle.idle) { | |
846 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
847 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
848 | init_idle(c_idle.idle, cpu); | |
849 | goto do_rest; | |
850 | } | |
851 | ||
852 | if (!keventd_up() || current_is_keventd()) | |
853 | c_idle.work.func(&c_idle.work); | |
854 | else { | |
855 | schedule_work(&c_idle.work); | |
856 | wait_for_completion(&c_idle.done); | |
857 | } | |
858 | ||
859 | if (IS_ERR(c_idle.idle)) { | |
860 | printk("failed fork for CPU %d\n", cpu); | |
861 | return PTR_ERR(c_idle.idle); | |
862 | } | |
863 | ||
864 | set_idle_for_cpu(cpu, c_idle.idle); | |
865 | do_rest: | |
866 | #ifdef CONFIG_X86_32 | |
867 | per_cpu(current_task, cpu) = c_idle.idle; | |
868 | init_gdt(cpu); | |
869 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); | |
870 | c_idle.idle->thread.ip = (unsigned long) start_secondary; | |
871 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
872 | stack_start.sp = (void *) c_idle.idle->thread.sp; | |
873 | irq_ctx_init(cpu); | |
874 | #else | |
875 | cpu_pda(cpu)->pcurrent = c_idle.idle; | |
876 | init_rsp = c_idle.idle->thread.sp; | |
877 | load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread); | |
878 | initial_code = (unsigned long)start_secondary; | |
879 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); | |
880 | #endif | |
881 | ||
882 | /* start_ip had better be page-aligned! */ | |
883 | start_ip = setup_trampoline(); | |
884 | ||
885 | /* So we see what's up */ | |
886 | printk(KERN_INFO "Booting processor %d/%d ip %lx\n", | |
887 | cpu, apicid, start_ip); | |
888 | ||
889 | /* | |
890 | * This grunge runs the startup process for | |
891 | * the targeted processor. | |
892 | */ | |
893 | ||
894 | atomic_set(&init_deasserted, 0); | |
895 | ||
896 | Dprintk("Setting warm reset code and vector.\n"); | |
897 | ||
898 | store_NMI_vector(&nmi_high, &nmi_low); | |
899 | ||
900 | smpboot_setup_warm_reset_vector(start_ip); | |
901 | /* | |
902 | * Be paranoid about clearing APIC errors. | |
903 | */ | |
904 | apic_write(APIC_ESR, 0); | |
905 | apic_read(APIC_ESR); | |
906 | ||
cb3c8b90 GOC |
907 | /* |
908 | * Starting actual IPI sequence... | |
909 | */ | |
910 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
911 | ||
912 | if (!boot_error) { | |
913 | /* | |
914 | * allow APs to start initializing. | |
915 | */ | |
916 | Dprintk("Before Callout %d.\n", cpu); | |
917 | cpu_set(cpu, cpu_callout_map); | |
918 | Dprintk("After Callout %d.\n", cpu); | |
919 | ||
920 | /* | |
921 | * Wait 5s total for a response | |
922 | */ | |
923 | for (timeout = 0; timeout < 50000; timeout++) { | |
924 | if (cpu_isset(cpu, cpu_callin_map)) | |
925 | break; /* It has booted */ | |
926 | udelay(100); | |
927 | } | |
928 | ||
929 | if (cpu_isset(cpu, cpu_callin_map)) { | |
930 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
931 | Dprintk("OK.\n"); | |
932 | printk(KERN_INFO "CPU%d: ", cpu); | |
933 | print_cpu_info(&cpu_data(cpu)); | |
934 | Dprintk("CPU has booted.\n"); | |
935 | } else { | |
936 | boot_error = 1; | |
937 | if (*((volatile unsigned char *)trampoline_base) | |
938 | == 0xA5) | |
939 | /* trampoline started but...? */ | |
940 | printk(KERN_ERR "Stuck ??\n"); | |
941 | else | |
942 | /* trampoline code not run */ | |
943 | printk(KERN_ERR "Not responding.\n"); | |
944 | inquire_remote_apic(apicid); | |
945 | } | |
946 | } | |
947 | ||
948 | if (boot_error) { | |
949 | /* Try to put things back the way they were before ... */ | |
950 | unmap_cpu_to_logical_apicid(cpu); | |
951 | #ifdef CONFIG_X86_64 | |
952 | clear_node_cpumask(cpu); /* was set by numa_add_cpu */ | |
953 | #endif | |
954 | cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ | |
955 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
956 | cpu_clear(cpu, cpu_possible_map); | |
957 | cpu_clear(cpu, cpu_present_map); | |
958 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; | |
959 | } | |
960 | ||
961 | /* mark "stuck" area as not stuck */ | |
962 | *((volatile unsigned long *)trampoline_base) = 0; | |
963 | ||
964 | return boot_error; | |
965 | } | |
966 | ||
967 | int __cpuinit native_cpu_up(unsigned int cpu) | |
968 | { | |
969 | int apicid = cpu_present_to_apicid(cpu); | |
970 | unsigned long flags; | |
971 | int err; | |
972 | ||
973 | WARN_ON(irqs_disabled()); | |
974 | ||
975 | Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu); | |
976 | ||
977 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
978 | !physid_isset(apicid, phys_cpu_present_map)) { | |
979 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
980 | return -EINVAL; | |
981 | } | |
982 | ||
983 | /* | |
984 | * Already booted CPU? | |
985 | */ | |
986 | if (cpu_isset(cpu, cpu_callin_map)) { | |
987 | Dprintk("do_boot_cpu %d Already started\n", cpu); | |
988 | return -ENOSYS; | |
989 | } | |
990 | ||
991 | /* | |
992 | * Save current MTRR state in case it was changed since early boot | |
993 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
994 | */ | |
995 | mtrr_save_state(); | |
996 | ||
997 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
998 | ||
999 | #ifdef CONFIG_X86_32 | |
1000 | /* init low mem mapping */ | |
1001 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS, | |
1002 | min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS)); | |
1003 | flush_tlb_all(); | |
1004 | #endif | |
1005 | ||
1006 | err = do_boot_cpu(apicid, cpu); | |
1007 | if (err < 0) { | |
1008 | Dprintk("do_boot_cpu failed %d\n", err); | |
1009 | return err; | |
1010 | } | |
1011 | ||
1012 | /* | |
1013 | * Check TSC synchronization with the AP (keep irqs disabled | |
1014 | * while doing so): | |
1015 | */ | |
1016 | local_irq_save(flags); | |
1017 | check_tsc_sync_source(cpu); | |
1018 | local_irq_restore(flags); | |
1019 | ||
1020 | while (!cpu_isset(cpu, cpu_online_map)) { | |
1021 | cpu_relax(); | |
1022 | touch_nmi_watchdog(); | |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
8aef135c GOC |
1028 | /* |
1029 | * Fall back to non SMP mode after errors. | |
1030 | * | |
1031 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1032 | */ | |
1033 | static __init void disable_smp(void) | |
1034 | { | |
1035 | cpu_present_map = cpumask_of_cpu(0); | |
1036 | cpu_possible_map = cpumask_of_cpu(0); | |
1037 | #ifdef CONFIG_X86_32 | |
1038 | smpboot_clear_io_apic_irqs(); | |
1039 | #endif | |
1040 | if (smp_found_config) | |
1041 | phys_cpu_present_map = | |
1042 | physid_mask_of_physid(boot_cpu_physical_apicid); | |
1043 | else | |
1044 | phys_cpu_present_map = physid_mask_of_physid(0); | |
1045 | map_cpu_to_logical_apicid(); | |
1046 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
1047 | cpu_set(0, per_cpu(cpu_core_map, 0)); | |
1048 | } | |
1049 | ||
1050 | /* | |
1051 | * Various sanity checks. | |
1052 | */ | |
1053 | static int __init smp_sanity_check(unsigned max_cpus) | |
1054 | { | |
1055 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { | |
1056 | printk(KERN_WARNING "weird, boot CPU (#%d) not listed" | |
1057 | "by the BIOS.\n", hard_smp_processor_id()); | |
1058 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * If we couldn't find an SMP configuration at boot time, | |
1063 | * get out of here now! | |
1064 | */ | |
1065 | if (!smp_found_config && !acpi_lapic) { | |
1066 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | |
1067 | disable_smp(); | |
1068 | if (APIC_init_uniprocessor()) | |
1069 | printk(KERN_NOTICE "Local APIC not detected." | |
1070 | " Using dummy APIC emulation.\n"); | |
1071 | return -1; | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * Should not be necessary because the MP table should list the boot | |
1076 | * CPU too, but we do it for the sake of robustness anyway. | |
1077 | */ | |
1078 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1079 | printk(KERN_NOTICE | |
1080 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1081 | boot_cpu_physical_apicid); | |
1082 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1083 | } | |
1084 | ||
1085 | /* | |
1086 | * If we couldn't find a local APIC, then get out of here now! | |
1087 | */ | |
1088 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1089 | !cpu_has_apic) { | |
1090 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1091 | boot_cpu_physical_apicid); | |
1092 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1093 | "(tell your hw vendor)\n"); | |
1094 | smpboot_clear_io_apic(); | |
1095 | return -1; | |
1096 | } | |
1097 | ||
1098 | verify_local_APIC(); | |
1099 | ||
1100 | /* | |
1101 | * If SMP should be disabled, then really disable it! | |
1102 | */ | |
1103 | if (!max_cpus) { | |
1104 | printk(KERN_INFO "SMP mode deactivated," | |
1105 | "forcing use of dummy APIC emulation.\n"); | |
1106 | smpboot_clear_io_apic(); | |
1107 | #ifdef CONFIG_X86_32 | |
1108 | if (nmi_watchdog == NMI_LOCAL_APIC) { | |
1109 | printk(KERN_INFO "activating minimal APIC for" | |
1110 | "NMI watchdog use.\n"); | |
1111 | connect_bsp_APIC(); | |
1112 | setup_local_APIC(); | |
1113 | end_local_APIC_setup(); | |
1114 | } | |
1115 | #endif | |
1116 | return -1; | |
1117 | } | |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
1122 | static void __init smp_cpu_index_default(void) | |
1123 | { | |
1124 | int i; | |
1125 | struct cpuinfo_x86 *c; | |
1126 | ||
1127 | for_each_cpu_mask(i, cpu_possible_map) { | |
1128 | c = &cpu_data(i); | |
1129 | /* mark all to hotplug */ | |
1130 | c->cpu_index = NR_CPUS; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1136 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1137 | */ | |
1138 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1139 | { | |
1140 | nmi_watchdog_default(); | |
1141 | smp_cpu_index_default(); | |
1142 | current_cpu_data = boot_cpu_data; | |
1143 | cpu_callin_map = cpumask_of_cpu(0); | |
1144 | mb(); | |
1145 | /* | |
1146 | * Setup boot CPU information | |
1147 | */ | |
1148 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1149 | boot_cpu_logical_apicid = logical_smp_processor_id(); | |
1150 | current_thread_info()->cpu = 0; /* needed? */ | |
1151 | set_cpu_sibling_map(0); | |
1152 | ||
1153 | if (smp_sanity_check(max_cpus) < 0) { | |
1154 | printk(KERN_INFO "SMP disabled\n"); | |
1155 | disable_smp(); | |
1156 | return; | |
1157 | } | |
1158 | ||
1159 | if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid) { | |
1160 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", | |
1161 | GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_physical_apicid); | |
1162 | /* Or can we switch back to PIC here? */ | |
1163 | } | |
1164 | ||
1165 | #ifdef CONFIG_X86_32 | |
1166 | connect_bsp_APIC(); | |
1167 | #endif | |
1168 | /* | |
1169 | * Switch from PIC to APIC mode. | |
1170 | */ | |
1171 | setup_local_APIC(); | |
1172 | ||
1173 | #ifdef CONFIG_X86_64 | |
1174 | /* | |
1175 | * Enable IO APIC before setting up error vector | |
1176 | */ | |
1177 | if (!skip_ioapic_setup && nr_ioapics) | |
1178 | enable_IO_APIC(); | |
1179 | #endif | |
1180 | end_local_APIC_setup(); | |
1181 | ||
1182 | map_cpu_to_logical_apicid(); | |
1183 | ||
1184 | setup_portio_remap(); | |
1185 | ||
1186 | smpboot_setup_io_apic(); | |
1187 | /* | |
1188 | * Set up local APIC timer on boot CPU. | |
1189 | */ | |
1190 | ||
1191 | printk(KERN_INFO "CPU%d: ", 0); | |
1192 | print_cpu_info(&cpu_data(0)); | |
1193 | setup_boot_clock(); | |
1194 | } | |
a8db8453 GOC |
1195 | /* |
1196 | * Early setup to make printk work. | |
1197 | */ | |
1198 | void __init native_smp_prepare_boot_cpu(void) | |
1199 | { | |
1200 | int me = smp_processor_id(); | |
1201 | #ifdef CONFIG_X86_32 | |
1202 | init_gdt(me); | |
1203 | switch_to_new_gdt(); | |
1204 | #endif | |
1205 | /* already set me in cpu_online_map in boot_cpu_init() */ | |
1206 | cpu_set(me, cpu_callout_map); | |
1207 | per_cpu(cpu_state, me) = CPU_ONLINE; | |
1208 | } | |
1209 | ||
83f7eb9c GOC |
1210 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1211 | { | |
1212 | /* | |
1213 | * Cleanup possible dangling ends... | |
1214 | */ | |
1215 | smpboot_restore_warm_reset_vector(); | |
1216 | ||
1217 | Dprintk("Boot done.\n"); | |
1218 | ||
1219 | impress_friends(); | |
1220 | smp_checks(); | |
1221 | #ifdef CONFIG_X86_IO_APIC | |
1222 | setup_ioapic_dest(); | |
1223 | #endif | |
1224 | check_nmi_watchdog(); | |
1225 | #ifdef CONFIG_X86_32 | |
1226 | zap_low_mappings(); | |
1227 | #endif | |
1228 | } | |
1229 | ||
68a1c3f8 | 1230 | #ifdef CONFIG_HOTPLUG_CPU |
2cd9fb71 GOC |
1231 | |
1232 | # ifdef CONFIG_X86_32 | |
1233 | void cpu_exit_clear(void) | |
1234 | { | |
1235 | int cpu = raw_smp_processor_id(); | |
1236 | ||
1237 | idle_task_exit(); | |
1238 | ||
1239 | cpu_uninit(); | |
1240 | irq_ctx_exit(cpu); | |
1241 | ||
1242 | cpu_clear(cpu, cpu_callout_map); | |
1243 | cpu_clear(cpu, cpu_callin_map); | |
1244 | ||
1245 | unmap_cpu_to_logical_apicid(cpu); | |
1246 | } | |
1247 | # endif /* CONFIG_X86_32 */ | |
1248 | ||
768d9505 GC |
1249 | void remove_siblinginfo(int cpu) |
1250 | { | |
1251 | int sibling; | |
1252 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1253 | ||
1254 | for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) { | |
1255 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); | |
1256 | /*/ | |
1257 | * last thread sibling in this cpu core going down | |
1258 | */ | |
1259 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) | |
1260 | cpu_data(sibling).booted_cores--; | |
1261 | } | |
1262 | ||
1263 | for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu)) | |
1264 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); | |
1265 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
1266 | cpus_clear(per_cpu(cpu_core_map, cpu)); | |
1267 | c->phys_proc_id = 0; | |
1268 | c->cpu_core_id = 0; | |
1269 | cpu_clear(cpu, cpu_sibling_setup_map); | |
1270 | } | |
68a1c3f8 GC |
1271 | |
1272 | int additional_cpus __initdata = -1; | |
1273 | ||
1274 | static __init int setup_additional_cpus(char *s) | |
1275 | { | |
1276 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; | |
1277 | } | |
1278 | early_param("additional_cpus", setup_additional_cpus); | |
1279 | ||
1280 | /* | |
1281 | * cpu_possible_map should be static, it cannot change as cpu's | |
1282 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1283 | * are allocated by some modules at init time, and dont expect to | |
1284 | * do this dynamically on cpu arrival/departure. | |
1285 | * cpu_present_map on the other hand can change dynamically. | |
1286 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1287 | * behaviour, which is cpu_possible == cpu_present. | |
1288 | * - Ashok Raj | |
1289 | * | |
1290 | * Three ways to find out the number of additional hotplug CPUs: | |
1291 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
1292 | * - The user can overwrite it with additional_cpus=NUM | |
1293 | * - Otherwise don't reserve additional CPUs. | |
1294 | * We do this because additional CPUs waste a lot of memory. | |
1295 | * -AK | |
1296 | */ | |
1297 | __init void prefill_possible_map(void) | |
1298 | { | |
1299 | int i; | |
1300 | int possible; | |
1301 | ||
1302 | if (additional_cpus == -1) { | |
1303 | if (disabled_cpus > 0) | |
1304 | additional_cpus = disabled_cpus; | |
1305 | else | |
1306 | additional_cpus = 0; | |
1307 | } | |
1308 | possible = num_processors + additional_cpus; | |
1309 | if (possible > NR_CPUS) | |
1310 | possible = NR_CPUS; | |
1311 | ||
1312 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1313 | possible, max_t(int, possible - num_processors, 0)); | |
1314 | ||
1315 | for (i = 0; i < possible; i++) | |
1316 | cpu_set(i, cpu_possible_map); | |
1317 | } | |
69c18c15 GC |
1318 | |
1319 | static void __ref remove_cpu_from_maps(int cpu) | |
1320 | { | |
1321 | cpu_clear(cpu, cpu_online_map); | |
1322 | #ifdef CONFIG_X86_64 | |
1323 | cpu_clear(cpu, cpu_callout_map); | |
1324 | cpu_clear(cpu, cpu_callin_map); | |
1325 | /* was set by cpu_init() */ | |
1326 | clear_bit(cpu, (unsigned long *)&cpu_initialized); | |
1327 | clear_node_cpumask(cpu); | |
1328 | #endif | |
1329 | } | |
1330 | ||
1331 | int __cpu_disable(void) | |
1332 | { | |
1333 | int cpu = smp_processor_id(); | |
1334 | ||
1335 | /* | |
1336 | * Perhaps use cpufreq to drop frequency, but that could go | |
1337 | * into generic code. | |
1338 | * | |
1339 | * We won't take down the boot processor on i386 due to some | |
1340 | * interrupts only being able to be serviced by the BSP. | |
1341 | * Especially so if we're not using an IOAPIC -zwane | |
1342 | */ | |
1343 | if (cpu == 0) | |
1344 | return -EBUSY; | |
1345 | ||
1346 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1347 | stop_apic_nmi_watchdog(NULL); | |
1348 | clear_local_APIC(); | |
1349 | ||
1350 | /* | |
1351 | * HACK: | |
1352 | * Allow any queued timer interrupts to get serviced | |
1353 | * This is only a temporary solution until we cleanup | |
1354 | * fixup_irqs as we do for IA64. | |
1355 | */ | |
1356 | local_irq_enable(); | |
1357 | mdelay(1); | |
1358 | ||
1359 | local_irq_disable(); | |
1360 | remove_siblinginfo(cpu); | |
1361 | ||
1362 | /* It's now safe to remove this processor from the online map */ | |
1363 | remove_cpu_from_maps(cpu); | |
1364 | fixup_irqs(cpu_online_map); | |
1365 | return 0; | |
1366 | } | |
1367 | ||
1368 | void __cpu_die(unsigned int cpu) | |
1369 | { | |
1370 | /* We don't do anything here: idle task is faking death itself. */ | |
1371 | unsigned int i; | |
1372 | ||
1373 | for (i = 0; i < 10; i++) { | |
1374 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1375 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1376 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1377 | if (1 == num_online_cpus()) | |
1378 | alternatives_smp_switch(0); | |
1379 | return; | |
1380 | } | |
1381 | msleep(100); | |
1382 | } | |
1383 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1384 | } | |
1385 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1386 | int __cpu_disable(void) | |
1387 | { | |
1388 | return -ENOSYS; | |
1389 | } | |
1390 | ||
1391 | void __cpu_die(unsigned int cpu) | |
1392 | { | |
1393 | /* We said "no" in __cpu_disable */ | |
1394 | BUG(); | |
1395 | } | |
68a1c3f8 GC |
1396 | #endif |
1397 | ||
89b08200 GC |
1398 | /* |
1399 | * If the BIOS enumerates physical processors before logical, | |
1400 | * maxcpus=N at enumeration-time can be used to disable HT. | |
1401 | */ | |
1402 | static int __init parse_maxcpus(char *arg) | |
1403 | { | |
1404 | extern unsigned int maxcpus; | |
1405 | ||
1406 | maxcpus = simple_strtoul(arg, NULL, 0); | |
1407 | return 0; | |
1408 | } | |
1409 | early_param("maxcpus", parse_maxcpus); |