Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> |
569712b2 | 72 | #include <asm/setup.h> |
bdbcdd48 | 73 | #include <asm/uv/uv.h> |
cb3c8b90 | 74 | #include <linux/mc146818rtc.h> |
b81bb373 | 75 | #include <asm/i8259.h> |
48927bbb | 76 | #include <asm/realmode.h> |
646e29a1 | 77 | #include <asm/misc.h> |
48927bbb | 78 | |
a355352b GC |
79 | /* Number of siblings per CPU package */ |
80 | int smp_num_siblings = 1; | |
81 | EXPORT_SYMBOL(smp_num_siblings); | |
82 | ||
83 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 84 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 85 | |
a355352b | 86 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 87 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
89 | ||
90 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
93 | ||
0816b0f0 | 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 95 | |
a355352b | 96 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 97 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 98 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 99 | |
1f12e32f TG |
100 | /* Logical package management. We might want to allocate that dynamically */ |
101 | static int *physical_to_logical_pkg __read_mostly; | |
102 | static unsigned long *physical_package_map __read_mostly;; | |
103 | static unsigned long *logical_package_map __read_mostly; | |
104 | static unsigned int max_physical_pkg_id __read_mostly; | |
105 | unsigned int __max_logical_packages __read_mostly; | |
106 | EXPORT_SYMBOL(__max_logical_packages); | |
107 | ||
f77aa308 TG |
108 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
109 | { | |
110 | unsigned long flags; | |
111 | ||
112 | spin_lock_irqsave(&rtc_lock, flags); | |
113 | CMOS_WRITE(0xa, 0xf); | |
114 | spin_unlock_irqrestore(&rtc_lock, flags); | |
115 | local_flush_tlb(); | |
116 | pr_debug("1.\n"); | |
117 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
118 | start_eip >> 4; | |
119 | pr_debug("2.\n"); | |
120 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
121 | start_eip & 0xf; | |
122 | pr_debug("3.\n"); | |
123 | } | |
124 | ||
125 | static inline void smpboot_restore_warm_reset_vector(void) | |
126 | { | |
127 | unsigned long flags; | |
128 | ||
129 | /* | |
130 | * Install writable page 0 entry to set BIOS data area. | |
131 | */ | |
132 | local_flush_tlb(); | |
133 | ||
134 | /* | |
135 | * Paranoid: Set warm reset code and vector here back | |
136 | * to default values. | |
137 | */ | |
138 | spin_lock_irqsave(&rtc_lock, flags); | |
139 | CMOS_WRITE(0, 0xf); | |
140 | spin_unlock_irqrestore(&rtc_lock, flags); | |
141 | ||
142 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
143 | } | |
144 | ||
cb3c8b90 | 145 | /* |
30106c17 FY |
146 | * Report back to the Boot Processor during boot time or to the caller processor |
147 | * during CPU online. | |
cb3c8b90 | 148 | */ |
148f9bb8 | 149 | static void smp_callin(void) |
cb3c8b90 GOC |
150 | { |
151 | int cpuid, phys_id; | |
cb3c8b90 GOC |
152 | |
153 | /* | |
154 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
155 | * cpu_callout_mask guarantees we don't get here before |
156 | * an INIT_deassert IPI reaches our local APIC, so it is | |
157 | * now safe to touch our local APIC. | |
cb3c8b90 | 158 | */ |
e1c467e6 | 159 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
160 | |
161 | /* | |
162 | * (This works even if the APIC is not enabled.) | |
163 | */ | |
4c9961d5 | 164 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
165 | |
166 | /* | |
167 | * the boot CPU has finished the init stage and is spinning | |
168 | * on callin_map until we finish. We are free to set up this | |
169 | * CPU, first the APIC. (this is probably redundant on most | |
170 | * boards) | |
171 | */ | |
05f7e46d | 172 | apic_ap_setup(); |
cb3c8b90 | 173 | |
b565201c JS |
174 | /* |
175 | * Save our processor parameters. Note: this information | |
176 | * is needed for clock calibration. | |
177 | */ | |
178 | smp_store_cpu_info(cpuid); | |
179 | ||
cb3c8b90 GOC |
180 | /* |
181 | * Get our bogomips. | |
b565201c JS |
182 | * Update loops_per_jiffy in cpu_data. Previous call to |
183 | * smp_store_cpu_info() stored a value that is close but not as | |
184 | * accurate as the value just calculated. | |
cb3c8b90 | 185 | */ |
cb3c8b90 | 186 | calibrate_delay(); |
b565201c | 187 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 188 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 189 | |
5ef428c4 AK |
190 | /* |
191 | * This must be done before setting cpu_online_mask | |
192 | * or calling notify_cpu_starting. | |
193 | */ | |
194 | set_cpu_sibling_map(raw_smp_processor_id()); | |
195 | wmb(); | |
196 | ||
85257024 PZ |
197 | notify_cpu_starting(cpuid); |
198 | ||
cb3c8b90 GOC |
199 | /* |
200 | * Allow the master to continue. | |
201 | */ | |
c2d1cec1 | 202 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
203 | } |
204 | ||
e1c467e6 FY |
205 | static int cpu0_logical_apicid; |
206 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
207 | /* |
208 | * Activate a secondary processor. | |
209 | */ | |
148f9bb8 | 210 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
211 | { |
212 | /* | |
213 | * Don't put *anything* before cpu_init(), SMP booting is too | |
214 | * fragile that we want to limit the things done here to the | |
215 | * most necessary things. | |
216 | */ | |
b40827fa | 217 | cpu_init(); |
df156f90 | 218 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
219 | preempt_disable(); |
220 | smp_callin(); | |
fd89a137 | 221 | |
e1c467e6 FY |
222 | enable_start_cpu0 = 0; |
223 | ||
fd89a137 | 224 | #ifdef CONFIG_X86_32 |
b40827fa | 225 | /* switch away from the initial page table */ |
fd89a137 JR |
226 | load_cr3(swapper_pg_dir); |
227 | __flush_tlb_all(); | |
228 | #endif | |
229 | ||
bbc2ff6a GOC |
230 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
231 | barrier(); | |
232 | /* | |
233 | * Check TSC synchronization with the BP: | |
234 | */ | |
235 | check_tsc_sync_target(); | |
236 | ||
bbc2ff6a | 237 | /* |
5a3f75e3 TG |
238 | * Lock vector_lock and initialize the vectors on this cpu |
239 | * before setting the cpu online. We must set it online with | |
240 | * vector_lock held to prevent a concurrent setup/teardown | |
241 | * from seeing a half valid vector space. | |
bbc2ff6a | 242 | */ |
d388e5fd | 243 | lock_vector_lock(); |
5a3f75e3 | 244 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 245 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 246 | unlock_vector_lock(); |
2a442c9c | 247 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 248 | x86_platform.nmi_init(); |
bbc2ff6a | 249 | |
0cefa5b9 MS |
250 | /* enable local interrupts */ |
251 | local_irq_enable(); | |
252 | ||
35f720c5 JP |
253 | /* to prevent fake stack check failure in clock setup */ |
254 | boot_init_stack_canary(); | |
0cefa5b9 | 255 | |
736decac | 256 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
257 | |
258 | wmb(); | |
fc6d73d6 | 259 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
260 | } |
261 | ||
1f12e32f TG |
262 | int topology_update_package_map(unsigned int apicid, unsigned int cpu) |
263 | { | |
264 | unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits; | |
265 | ||
266 | /* Called from early boot ? */ | |
267 | if (!physical_package_map) | |
268 | return 0; | |
269 | ||
270 | if (pkg >= max_physical_pkg_id) | |
271 | return -EINVAL; | |
272 | ||
273 | /* Set the logical package id */ | |
274 | if (test_and_set_bit(pkg, physical_package_map)) | |
275 | goto found; | |
276 | ||
277 | if (pkg < __max_logical_packages) { | |
278 | set_bit(pkg, logical_package_map); | |
279 | physical_to_logical_pkg[pkg] = pkg; | |
280 | goto found; | |
281 | } | |
282 | new = find_first_zero_bit(logical_package_map, __max_logical_packages); | |
283 | if (new >= __max_logical_packages) { | |
284 | physical_to_logical_pkg[pkg] = -1; | |
285 | pr_warn("APIC(%x) Package %u exceeds logical package map\n", | |
286 | apicid, pkg); | |
287 | return -ENOSPC; | |
288 | } | |
289 | set_bit(new, logical_package_map); | |
290 | pr_info("APIC(%x) Converting physical %u to logical package %u\n", | |
291 | apicid, pkg, new); | |
292 | physical_to_logical_pkg[pkg] = new; | |
293 | ||
294 | found: | |
295 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; | |
296 | return 0; | |
297 | } | |
298 | ||
299 | /** | |
300 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
301 | * | |
302 | * Returns logical package id or -1 if not found | |
303 | */ | |
304 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
305 | { | |
306 | if (phys_pkg >= max_physical_pkg_id) | |
307 | return -1; | |
308 | return physical_to_logical_pkg[phys_pkg]; | |
309 | } | |
310 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
311 | ||
312 | static void __init smp_init_package_map(void) | |
313 | { | |
314 | unsigned int ncpus, cpu; | |
315 | size_t size; | |
316 | ||
317 | /* | |
318 | * Today neither Intel nor AMD support heterogenous systems. That | |
319 | * might change in the future.... | |
320 | */ | |
321 | ncpus = boot_cpu_data.x86_max_cores * smp_num_siblings; | |
322 | __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); | |
323 | ||
324 | /* | |
325 | * Possibly larger than what we need as the number of apic ids per | |
326 | * package can be smaller than the actual used apic ids. | |
327 | */ | |
328 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); | |
329 | size = max_physical_pkg_id * sizeof(unsigned int); | |
330 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); | |
331 | memset(physical_to_logical_pkg, 0xff, size); | |
332 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); | |
333 | physical_package_map = kzalloc(size, GFP_KERNEL); | |
334 | size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long); | |
335 | logical_package_map = kzalloc(size, GFP_KERNEL); | |
336 | ||
337 | pr_info("Max logical packages: %u\n", __max_logical_packages); | |
338 | ||
339 | for_each_present_cpu(cpu) { | |
340 | unsigned int apicid = apic->cpu_present_to_apicid(cpu); | |
341 | ||
342 | if (apicid == BAD_APICID || !apic->apic_id_valid(apicid)) | |
343 | continue; | |
344 | if (!topology_update_package_map(apicid, cpu)) | |
345 | continue; | |
346 | pr_warn("CPU %u APICId %x disabled\n", cpu, apicid); | |
347 | per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID; | |
348 | set_cpu_possible(cpu, false); | |
349 | set_cpu_present(cpu, false); | |
350 | } | |
351 | } | |
352 | ||
30106c17 FY |
353 | void __init smp_store_boot_cpu_info(void) |
354 | { | |
355 | int id = 0; /* CPU 0 */ | |
356 | struct cpuinfo_x86 *c = &cpu_data(id); | |
357 | ||
358 | *c = boot_cpu_data; | |
359 | c->cpu_index = id; | |
1f12e32f | 360 | smp_init_package_map(); |
30106c17 FY |
361 | } |
362 | ||
1d89a7f0 GOC |
363 | /* |
364 | * The bootstrap kernel entry code has set these up. Save them for | |
365 | * a given CPU | |
366 | */ | |
148f9bb8 | 367 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
368 | { |
369 | struct cpuinfo_x86 *c = &cpu_data(id); | |
370 | ||
b3d7336d | 371 | *c = boot_cpu_data; |
1d89a7f0 | 372 | c->cpu_index = id; |
30106c17 FY |
373 | /* |
374 | * During boot time, CPU0 has this setup already. Save the info when | |
375 | * bringing up AP or offlined CPU0. | |
376 | */ | |
377 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
378 | } |
379 | ||
cebf15eb DH |
380 | static bool |
381 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
382 | { | |
383 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
384 | ||
385 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
386 | } | |
387 | ||
148f9bb8 | 388 | static bool |
316ad248 | 389 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 390 | { |
316ad248 PZ |
391 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
392 | ||
cebf15eb | 393 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
394 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
395 | "[node: %d != %d]. Ignoring dependency.\n", | |
396 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
397 | } | |
398 | ||
7d79a7bd | 399 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 400 | do { \ |
7d79a7bd BG |
401 | cpumask_set_cpu((c1), mfunc(c2)); \ |
402 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
403 | } while (0) |
404 | ||
148f9bb8 | 405 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 406 | { |
362f924b | 407 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
408 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
409 | ||
410 | if (c->phys_proc_id == o->phys_proc_id && | |
411 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
412 | c->compute_unit_id == o->compute_unit_id) | |
413 | return topology_sane(c, o, "smt"); | |
414 | ||
415 | } else if (c->phys_proc_id == o->phys_proc_id && | |
416 | c->cpu_core_id == o->cpu_core_id) { | |
417 | return topology_sane(c, o, "smt"); | |
418 | } | |
419 | ||
420 | return false; | |
421 | } | |
422 | ||
148f9bb8 | 423 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
424 | { |
425 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
426 | ||
427 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
428 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
429 | return topology_sane(c, o, "llc"); | |
430 | ||
431 | return false; | |
d4fbe4f0 AH |
432 | } |
433 | ||
cebf15eb DH |
434 | /* |
435 | * Unlike the other levels, we do not enforce keeping a | |
436 | * multicore group inside a NUMA node. If this happens, we will | |
437 | * discard the MC level of the topology later. | |
438 | */ | |
439 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 440 | { |
cebf15eb DH |
441 | if (c->phys_proc_id == o->phys_proc_id) |
442 | return true; | |
316ad248 PZ |
443 | return false; |
444 | } | |
1d89a7f0 | 445 | |
cebf15eb DH |
446 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
447 | #ifdef CONFIG_SCHED_SMT | |
448 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
449 | #endif | |
450 | #ifdef CONFIG_SCHED_MC | |
451 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
452 | #endif | |
453 | { NULL, }, | |
454 | }; | |
455 | /* | |
456 | * set_sched_topology() sets the topology internal to a CPU. The | |
457 | * NUMA topologies are layered on top of it to build the full | |
458 | * system topology. | |
459 | * | |
460 | * If NUMA nodes are observed to occur within a CPU package, this | |
461 | * function should be called. It forces the sched domain code to | |
462 | * only use the SMT level for the CPU portion of the topology. | |
463 | * This essentially falls back to relying on NUMA information | |
464 | * from the SRAT table to describe the entire system topology | |
465 | * (except for hyperthreads). | |
466 | */ | |
467 | static void primarily_use_numa_for_topology(void) | |
468 | { | |
469 | set_sched_topology(numa_inside_package_topology); | |
470 | } | |
471 | ||
148f9bb8 | 472 | void set_cpu_sibling_map(int cpu) |
768d9505 | 473 | { |
316ad248 | 474 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 475 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 476 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
477 | struct cpuinfo_x86 *o; |
478 | int i; | |
768d9505 | 479 | |
c2d1cec1 | 480 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 481 | |
b0bc225d | 482 | if (!has_mp) { |
7d79a7bd | 483 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 484 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 485 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
486 | c->booted_cores = 1; |
487 | return; | |
488 | } | |
489 | ||
c2d1cec1 | 490 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
491 | o = &cpu_data(i); |
492 | ||
493 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 494 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 495 | |
b0bc225d | 496 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 497 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 498 | |
ceb1cbac KB |
499 | } |
500 | ||
501 | /* | |
502 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 503 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
504 | */ |
505 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
506 | o = &cpu_data(i); | |
507 | ||
cebf15eb | 508 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 509 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 510 | |
768d9505 GC |
511 | /* |
512 | * Does this new cpu bringup a new core? | |
513 | */ | |
7d79a7bd BG |
514 | if (cpumask_weight( |
515 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
516 | /* |
517 | * for each core in package, increment | |
518 | * the booted_cores for this new cpu | |
519 | */ | |
7d79a7bd BG |
520 | if (cpumask_first( |
521 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
522 | c->booted_cores++; |
523 | /* | |
524 | * increment the core count for all | |
525 | * the other cpus in this package | |
526 | */ | |
527 | if (i != cpu) | |
528 | cpu_data(i).booted_cores++; | |
529 | } else if (i != cpu && !c->booted_cores) | |
530 | c->booted_cores = cpu_data(i).booted_cores; | |
531 | } | |
728e5653 | 532 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 533 | primarily_use_numa_for_topology(); |
768d9505 GC |
534 | } |
535 | } | |
536 | ||
70708a18 | 537 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 538 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 539 | { |
9f646389 | 540 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
541 | } |
542 | ||
a4928cff | 543 | static void impress_friends(void) |
904541e2 GOC |
544 | { |
545 | int cpu; | |
546 | unsigned long bogosum = 0; | |
547 | /* | |
548 | * Allow the user to impress friends. | |
549 | */ | |
c767a54b | 550 | pr_debug("Before bogomips\n"); |
904541e2 | 551 | for_each_possible_cpu(cpu) |
c2d1cec1 | 552 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 553 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 554 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 555 | num_online_cpus(), |
904541e2 GOC |
556 | bogosum/(500000/HZ), |
557 | (bogosum/(5000/HZ))%100); | |
558 | ||
c767a54b | 559 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
560 | } |
561 | ||
569712b2 | 562 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
563 | { |
564 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 565 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
566 | int timeout; |
567 | u32 status; | |
568 | ||
c767a54b | 569 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
570 | |
571 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 572 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
573 | |
574 | /* | |
575 | * Wait for idle. | |
576 | */ | |
577 | status = safe_apic_wait_icr_idle(); | |
578 | if (status) | |
c767a54b | 579 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 580 | |
1b374e4d | 581 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
582 | |
583 | timeout = 0; | |
584 | do { | |
585 | udelay(100); | |
586 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
587 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
588 | ||
589 | switch (status) { | |
590 | case APIC_ICR_RR_VALID: | |
591 | status = apic_read(APIC_RRR); | |
c767a54b | 592 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
593 | break; |
594 | default: | |
c767a54b | 595 | pr_cont("failed\n"); |
cb3c8b90 GOC |
596 | } |
597 | } | |
598 | } | |
599 | ||
d68921f9 LB |
600 | /* |
601 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
602 | * that there should be a 10ms delay between the BSP asserting INIT | |
603 | * and de-asserting INIT, when starting a remote processor. | |
604 | * But that slows boot and resume on modern processors, which include | |
605 | * many cores and don't require that delay. | |
606 | * | |
607 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 608 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
609 | */ |
610 | #define UDELAY_10MS_DEFAULT 10000 | |
611 | ||
656279a1 | 612 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
613 | |
614 | static int __init cpu_init_udelay(char *str) | |
615 | { | |
616 | get_option(&str, &init_udelay); | |
617 | ||
618 | return 0; | |
619 | } | |
620 | early_param("cpu_init_udelay", cpu_init_udelay); | |
621 | ||
1a744cb3 LB |
622 | static void __init smp_quirk_init_udelay(void) |
623 | { | |
624 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 625 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
626 | return; |
627 | ||
628 | /* if modern processor, use no delay */ | |
629 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 630 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 631 | init_udelay = 0; |
656279a1 LB |
632 | return; |
633 | } | |
f1ccd249 LB |
634 | /* else, use legacy delay */ |
635 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
636 | } |
637 | ||
cb3c8b90 GOC |
638 | /* |
639 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
640 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
641 | * won't ... remember to clear down the APIC, etc later. | |
642 | */ | |
148f9bb8 | 643 | int |
e1c467e6 | 644 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
645 | { |
646 | unsigned long send_status, accept_status = 0; | |
647 | int maxlvt; | |
648 | ||
649 | /* Target chip */ | |
cb3c8b90 GOC |
650 | /* Boot on the stack */ |
651 | /* Kick the second */ | |
e1c467e6 | 652 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 653 | |
cfc1b9a6 | 654 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
655 | send_status = safe_apic_wait_icr_idle(); |
656 | ||
657 | /* | |
658 | * Give the other CPU some time to accept the IPI. | |
659 | */ | |
660 | udelay(200); | |
569712b2 | 661 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
662 | maxlvt = lapic_get_maxlvt(); |
663 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
664 | apic_write(APIC_ESR, 0); | |
665 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
666 | } | |
c767a54b | 667 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
668 | |
669 | if (send_status) | |
c767a54b | 670 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 671 | if (accept_status) |
c767a54b | 672 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
673 | |
674 | return (send_status | accept_status); | |
675 | } | |
cb3c8b90 | 676 | |
148f9bb8 | 677 | static int |
569712b2 | 678 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 679 | { |
f5d6a52f | 680 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
681 | int maxlvt, num_starts, j; |
682 | ||
593f4a78 MR |
683 | maxlvt = lapic_get_maxlvt(); |
684 | ||
cb3c8b90 GOC |
685 | /* |
686 | * Be paranoid about clearing APIC errors. | |
687 | */ | |
688 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
689 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
690 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
691 | apic_read(APIC_ESR); |
692 | } | |
693 | ||
c767a54b | 694 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
695 | |
696 | /* | |
697 | * Turn INIT on target chip | |
698 | */ | |
cb3c8b90 GOC |
699 | /* |
700 | * Send IPI | |
701 | */ | |
1b374e4d SS |
702 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
703 | phys_apicid); | |
cb3c8b90 | 704 | |
cfc1b9a6 | 705 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
706 | send_status = safe_apic_wait_icr_idle(); |
707 | ||
7cb68598 | 708 | udelay(init_udelay); |
cb3c8b90 | 709 | |
c767a54b | 710 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
711 | |
712 | /* Target chip */ | |
cb3c8b90 | 713 | /* Send IPI */ |
1b374e4d | 714 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 715 | |
cfc1b9a6 | 716 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
717 | send_status = safe_apic_wait_icr_idle(); |
718 | ||
719 | mb(); | |
cb3c8b90 GOC |
720 | |
721 | /* | |
722 | * Should we send STARTUP IPIs ? | |
723 | * | |
724 | * Determine this based on the APIC version. | |
725 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
726 | */ | |
727 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
728 | num_starts = 2; | |
729 | else | |
730 | num_starts = 0; | |
731 | ||
cb3c8b90 GOC |
732 | /* |
733 | * Run STARTUP IPI loop. | |
734 | */ | |
c767a54b | 735 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 736 | |
cb3c8b90 | 737 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 738 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
739 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
740 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 741 | apic_read(APIC_ESR); |
c767a54b | 742 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
743 | |
744 | /* | |
745 | * STARTUP IPI | |
746 | */ | |
747 | ||
748 | /* Target chip */ | |
cb3c8b90 GOC |
749 | /* Boot on the stack */ |
750 | /* Kick the second */ | |
1b374e4d SS |
751 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
752 | phys_apicid); | |
cb3c8b90 GOC |
753 | |
754 | /* | |
755 | * Give the other CPU some time to accept the IPI. | |
756 | */ | |
fcafddec LB |
757 | if (init_udelay == 0) |
758 | udelay(10); | |
759 | else | |
a9bcaa02 | 760 | udelay(300); |
cb3c8b90 | 761 | |
c767a54b | 762 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 763 | |
cfc1b9a6 | 764 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
765 | send_status = safe_apic_wait_icr_idle(); |
766 | ||
767 | /* | |
768 | * Give the other CPU some time to accept the IPI. | |
769 | */ | |
fcafddec LB |
770 | if (init_udelay == 0) |
771 | udelay(10); | |
772 | else | |
a9bcaa02 | 773 | udelay(200); |
cb3c8b90 | 774 | |
593f4a78 | 775 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 776 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
777 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
778 | if (send_status || accept_status) | |
779 | break; | |
780 | } | |
c767a54b | 781 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
782 | |
783 | if (send_status) | |
c767a54b | 784 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 785 | if (accept_status) |
c767a54b | 786 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
787 | |
788 | return (send_status | accept_status); | |
789 | } | |
cb3c8b90 | 790 | |
a17bce4d BP |
791 | void smp_announce(void) |
792 | { | |
793 | int num_nodes = num_online_nodes(); | |
794 | ||
795 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
796 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
797 | } | |
798 | ||
2eaad1fd | 799 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 800 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
801 | { |
802 | static int current_node = -1; | |
4adc8b71 | 803 | int node = early_cpu_to_node(cpu); |
a17bce4d | 804 | static int width, node_width; |
646e29a1 BP |
805 | |
806 | if (!width) | |
807 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 808 | |
a17bce4d BP |
809 | if (!node_width) |
810 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
811 | ||
812 | if (cpu == 1) | |
813 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
814 | ||
2eaad1fd MT |
815 | if (system_state == SYSTEM_BOOTING) { |
816 | if (node != current_node) { | |
817 | if (current_node > (-1)) | |
a17bce4d | 818 | pr_cont("\n"); |
2eaad1fd | 819 | current_node = node; |
a17bce4d BP |
820 | |
821 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
822 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 823 | } |
646e29a1 BP |
824 | |
825 | /* Add padding for the BSP */ | |
826 | if (cpu == 1) | |
827 | pr_cont("%*s", width + 1, " "); | |
828 | ||
829 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
830 | ||
2eaad1fd MT |
831 | } else |
832 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
833 | node, cpu, apicid); | |
834 | } | |
835 | ||
e1c467e6 FY |
836 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
837 | { | |
838 | int cpu; | |
839 | ||
840 | cpu = smp_processor_id(); | |
841 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
842 | return NMI_HANDLED; | |
843 | ||
844 | return NMI_DONE; | |
845 | } | |
846 | ||
847 | /* | |
848 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
849 | * | |
850 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
851 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
852 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
853 | * | |
854 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
855 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
856 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
857 | * real platform and request are available. | |
858 | */ | |
148f9bb8 | 859 | static int |
e1c467e6 FY |
860 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
861 | int *cpu0_nmi_registered) | |
862 | { | |
863 | int id; | |
864 | int boot_error; | |
865 | ||
ea7bdc65 JK |
866 | preempt_disable(); |
867 | ||
e1c467e6 FY |
868 | /* |
869 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
870 | */ | |
ea7bdc65 JK |
871 | if (cpu) { |
872 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
873 | goto out; | |
874 | } | |
e1c467e6 FY |
875 | |
876 | /* | |
877 | * Wake up BSP by nmi. | |
878 | * | |
879 | * Register a NMI handler to help wake up CPU0. | |
880 | */ | |
881 | boot_error = register_nmi_handler(NMI_LOCAL, | |
882 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
883 | ||
884 | if (!boot_error) { | |
885 | enable_start_cpu0 = 1; | |
886 | *cpu0_nmi_registered = 1; | |
887 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
888 | id = cpu0_logical_apicid; | |
889 | else | |
890 | id = apicid; | |
891 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
892 | } | |
ea7bdc65 JK |
893 | |
894 | out: | |
895 | preempt_enable(); | |
e1c467e6 FY |
896 | |
897 | return boot_error; | |
898 | } | |
899 | ||
3f85483b BO |
900 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
901 | { | |
902 | /* Just in case we booted with a single CPU. */ | |
903 | alternatives_enable_smp(); | |
904 | ||
905 | per_cpu(current_task, cpu) = idle; | |
906 | ||
907 | #ifdef CONFIG_X86_32 | |
908 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
909 | irq_ctx_init(cpu); | |
910 | per_cpu(cpu_current_top_of_stack, cpu) = | |
911 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
912 | #else | |
913 | clear_tsk_thread_flag(idle, TIF_FORK); | |
914 | initial_gs = per_cpu_offset(cpu); | |
915 | #endif | |
3f85483b BO |
916 | } |
917 | ||
cb3c8b90 GOC |
918 | /* |
919 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
920 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
921 | * Returns zero if CPU booted OK, else error code from |
922 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 923 | */ |
148f9bb8 | 924 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 925 | { |
48927bbb | 926 | volatile u32 *trampoline_status = |
b429dbf6 | 927 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 928 | /* start_ip had better be page-aligned! */ |
f37240f1 | 929 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 930 | |
cb3c8b90 | 931 | unsigned long boot_error = 0; |
e1c467e6 | 932 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 933 | unsigned long timeout; |
cb3c8b90 | 934 | |
7eb43a6d TG |
935 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
936 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
cb3c8b90 | 937 | |
a939098a | 938 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 939 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 940 | stack_start = idle->thread.sp; |
cb3c8b90 | 941 | |
20d5e4a9 ZG |
942 | /* |
943 | * Enable the espfix hack for this CPU | |
944 | */ | |
945 | #ifdef CONFIG_X86_ESPFIX64 | |
946 | init_espfix_ap(cpu); | |
947 | #endif | |
948 | ||
2eaad1fd MT |
949 | /* So we see what's up */ |
950 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
951 | |
952 | /* | |
953 | * This grunge runs the startup process for | |
954 | * the targeted processor. | |
955 | */ | |
956 | ||
34d05591 | 957 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 958 | |
cfc1b9a6 | 959 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 960 | |
34d05591 JS |
961 | smpboot_setup_warm_reset_vector(start_ip); |
962 | /* | |
963 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
964 | */ |
965 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
966 | apic_write(APIC_ESR, 0); | |
967 | apic_read(APIC_ESR); | |
968 | } | |
34d05591 | 969 | } |
cb3c8b90 | 970 | |
ce4b1b16 IM |
971 | /* |
972 | * AP might wait on cpu_callout_mask in cpu_init() with | |
973 | * cpu_initialized_mask set if previous attempt to online | |
974 | * it timed-out. Clear cpu_initialized_mask so that after | |
975 | * INIT/SIPI it could start with a clean state. | |
976 | */ | |
977 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
978 | smp_mb(); | |
979 | ||
cb3c8b90 | 980 | /* |
e1c467e6 FY |
981 | * Wake up a CPU in difference cases: |
982 | * - Use the method in the APIC driver if it's defined | |
983 | * Otherwise, | |
984 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 985 | */ |
1f5bcabf IM |
986 | if (apic->wakeup_secondary_cpu) |
987 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
988 | else | |
e1c467e6 FY |
989 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
990 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
991 | |
992 | if (!boot_error) { | |
993 | /* | |
6e38f1e7 | 994 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 995 | */ |
ce4b1b16 IM |
996 | boot_error = -1; |
997 | timeout = jiffies + 10*HZ; | |
998 | while (time_before(jiffies, timeout)) { | |
999 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1000 | /* | |
1001 | * Tell AP to proceed with initialization | |
1002 | */ | |
1003 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1004 | boot_error = 0; | |
1005 | break; | |
1006 | } | |
ce4b1b16 IM |
1007 | schedule(); |
1008 | } | |
1009 | } | |
cb3c8b90 | 1010 | |
ce4b1b16 | 1011 | if (!boot_error) { |
cb3c8b90 | 1012 | /* |
ce4b1b16 | 1013 | * Wait till AP completes initial initialization |
cb3c8b90 | 1014 | */ |
ce4b1b16 | 1015 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1016 | /* |
1017 | * Allow other tasks to run while we wait for the | |
1018 | * AP to come online. This also gives a chance | |
1019 | * for the MTRR work(triggered by the AP coming online) | |
1020 | * to be completed in the stop machine context. | |
1021 | */ | |
1022 | schedule(); | |
cb3c8b90 | 1023 | } |
cb3c8b90 GOC |
1024 | } |
1025 | ||
1026 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1027 | *trampoline_status = 0; |
cb3c8b90 | 1028 | |
02421f98 YL |
1029 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1030 | /* | |
1031 | * Cleanup possible dangling ends... | |
1032 | */ | |
1033 | smpboot_restore_warm_reset_vector(); | |
1034 | } | |
e1c467e6 FY |
1035 | /* |
1036 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1037 | * to avoid impact of possible long unregister time. | |
1038 | */ | |
1039 | if (cpu0_nmi_registered) | |
1040 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1041 | ||
cb3c8b90 GOC |
1042 | return boot_error; |
1043 | } | |
1044 | ||
148f9bb8 | 1045 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1046 | { |
a21769a4 | 1047 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
1048 | unsigned long flags; |
1049 | int err; | |
1050 | ||
1051 | WARN_ON(irqs_disabled()); | |
1052 | ||
cfc1b9a6 | 1053 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1054 | |
30106c17 | 1055 | if (apicid == BAD_APICID || |
c284b42a | 1056 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1057 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1058 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1059 | return -EINVAL; |
1060 | } | |
1061 | ||
1062 | /* | |
1063 | * Already booted CPU? | |
1064 | */ | |
c2d1cec1 | 1065 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1066 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1067 | return -ENOSYS; |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Save current MTRR state in case it was changed since early boot | |
1072 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1073 | */ | |
1074 | mtrr_save_state(); | |
1075 | ||
2a442c9c PM |
1076 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1077 | err = cpu_check_up_prepare(cpu); | |
1078 | if (err && err != -EBUSY) | |
1079 | return err; | |
cb3c8b90 | 1080 | |
644c1541 VP |
1081 | /* the FPU context is blank, nobody can own it */ |
1082 | __cpu_disable_lazy_restore(cpu); | |
1083 | ||
3f85483b BO |
1084 | common_cpu_up(cpu, tidle); |
1085 | ||
ce0d3c0a TG |
1086 | /* |
1087 | * We have to walk the irq descriptors to setup the vector | |
1088 | * space for the cpu which comes online. Prevent irq | |
1089 | * alloc/free across the bringup. | |
1090 | */ | |
1091 | irq_lock_sparse(); | |
1092 | ||
7eb43a6d | 1093 | err = do_boot_cpu(apicid, cpu, tidle); |
ce0d3c0a | 1094 | |
61165d7a | 1095 | if (err) { |
ce0d3c0a | 1096 | irq_unlock_sparse(); |
feef1e8e | 1097 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 1098 | return -EIO; |
cb3c8b90 GOC |
1099 | } |
1100 | ||
1101 | /* | |
1102 | * Check TSC synchronization with the AP (keep irqs disabled | |
1103 | * while doing so): | |
1104 | */ | |
1105 | local_irq_save(flags); | |
1106 | check_tsc_sync_source(cpu); | |
1107 | local_irq_restore(flags); | |
1108 | ||
7c04e64a | 1109 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1110 | cpu_relax(); |
1111 | touch_nmi_watchdog(); | |
1112 | } | |
1113 | ||
ce0d3c0a TG |
1114 | irq_unlock_sparse(); |
1115 | ||
cb3c8b90 GOC |
1116 | return 0; |
1117 | } | |
1118 | ||
7167d08e HK |
1119 | /** |
1120 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1121 | */ | |
1122 | void arch_disable_smp_support(void) | |
1123 | { | |
1124 | disable_ioapic_support(); | |
1125 | } | |
1126 | ||
8aef135c GOC |
1127 | /* |
1128 | * Fall back to non SMP mode after errors. | |
1129 | * | |
1130 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1131 | */ | |
1132 | static __init void disable_smp(void) | |
1133 | { | |
613c25ef TG |
1134 | pr_info("SMP disabled\n"); |
1135 | ||
ef4c59a4 TG |
1136 | disable_ioapic_support(); |
1137 | ||
4f062896 RR |
1138 | init_cpu_present(cpumask_of(0)); |
1139 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1140 | |
8aef135c | 1141 | if (smp_found_config) |
b6df1b8b | 1142 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1143 | else |
b6df1b8b | 1144 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1145 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1146 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1147 | } |
1148 | ||
613c25ef TG |
1149 | enum { |
1150 | SMP_OK, | |
1151 | SMP_NO_CONFIG, | |
1152 | SMP_NO_APIC, | |
1153 | SMP_FORCE_UP, | |
1154 | }; | |
1155 | ||
8aef135c GOC |
1156 | /* |
1157 | * Various sanity checks. | |
1158 | */ | |
1159 | static int __init smp_sanity_check(unsigned max_cpus) | |
1160 | { | |
ac23d4ee | 1161 | preempt_disable(); |
a58f03b0 | 1162 | |
1ff2f20d | 1163 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1164 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1165 | unsigned int cpu; | |
1166 | unsigned nr; | |
1167 | ||
c767a54b JP |
1168 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1169 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1170 | |
1171 | nr = 0; | |
1172 | for_each_present_cpu(cpu) { | |
1173 | if (nr >= 8) | |
c2d1cec1 | 1174 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1175 | nr++; |
1176 | } | |
1177 | ||
1178 | nr = 0; | |
1179 | for_each_possible_cpu(cpu) { | |
1180 | if (nr >= 8) | |
c2d1cec1 | 1181 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1182 | nr++; |
1183 | } | |
1184 | ||
1185 | nr_cpu_ids = 8; | |
1186 | } | |
1187 | #endif | |
1188 | ||
8aef135c | 1189 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1190 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1191 | hard_smp_processor_id()); |
1192 | ||
8aef135c GOC |
1193 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1194 | } | |
1195 | ||
1196 | /* | |
1197 | * If we couldn't find an SMP configuration at boot time, | |
1198 | * get out of here now! | |
1199 | */ | |
1200 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1201 | preempt_enable(); |
c767a54b | 1202 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1203 | return SMP_NO_CONFIG; |
8aef135c GOC |
1204 | } |
1205 | ||
1206 | /* | |
1207 | * Should not be necessary because the MP table should list the boot | |
1208 | * CPU too, but we do it for the sake of robustness anyway. | |
1209 | */ | |
a27a6210 | 1210 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1211 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1212 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1213 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1214 | } | |
ac23d4ee | 1215 | preempt_enable(); |
8aef135c GOC |
1216 | |
1217 | /* | |
1218 | * If we couldn't find a local APIC, then get out of here now! | |
1219 | */ | |
1220 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1221 | !cpu_has_apic) { | |
103428e5 CG |
1222 | if (!disable_apic) { |
1223 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1224 | boot_cpu_physical_apicid); | |
c767a54b | 1225 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1226 | } |
613c25ef | 1227 | return SMP_NO_APIC; |
8aef135c GOC |
1228 | } |
1229 | ||
8aef135c GOC |
1230 | /* |
1231 | * If SMP should be disabled, then really disable it! | |
1232 | */ | |
1233 | if (!max_cpus) { | |
c767a54b | 1234 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1235 | return SMP_FORCE_UP; |
8aef135c GOC |
1236 | } |
1237 | ||
613c25ef | 1238 | return SMP_OK; |
8aef135c GOC |
1239 | } |
1240 | ||
1241 | static void __init smp_cpu_index_default(void) | |
1242 | { | |
1243 | int i; | |
1244 | struct cpuinfo_x86 *c; | |
1245 | ||
7c04e64a | 1246 | for_each_possible_cpu(i) { |
8aef135c GOC |
1247 | c = &cpu_data(i); |
1248 | /* mark all to hotplug */ | |
9628937d | 1249 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1250 | } |
1251 | } | |
1252 | ||
1253 | /* | |
1254 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1255 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1256 | */ | |
1257 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1258 | { | |
7ad728f9 RR |
1259 | unsigned int i; |
1260 | ||
8aef135c | 1261 | smp_cpu_index_default(); |
792363d2 | 1262 | |
8aef135c GOC |
1263 | /* |
1264 | * Setup boot CPU information | |
1265 | */ | |
30106c17 | 1266 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1267 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1268 | mb(); | |
bd22a2f1 | 1269 | |
8aef135c | 1270 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1271 | for_each_possible_cpu(i) { |
79f55997 LZ |
1272 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1273 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1274 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1275 | } |
8aef135c GOC |
1276 | set_cpu_sibling_map(0); |
1277 | ||
613c25ef TG |
1278 | switch (smp_sanity_check(max_cpus)) { |
1279 | case SMP_NO_CONFIG: | |
8aef135c | 1280 | disable_smp(); |
613c25ef TG |
1281 | if (APIC_init_uniprocessor()) |
1282 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1283 | return; | |
1284 | case SMP_NO_APIC: | |
1285 | disable_smp(); | |
1286 | return; | |
1287 | case SMP_FORCE_UP: | |
1288 | disable_smp(); | |
374aab33 | 1289 | apic_bsp_setup(false); |
250a1ac6 | 1290 | return; |
613c25ef TG |
1291 | case SMP_OK: |
1292 | break; | |
8aef135c GOC |
1293 | } |
1294 | ||
fa47f7e5 SS |
1295 | default_setup_apic_routing(); |
1296 | ||
4c9961d5 | 1297 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1298 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1299 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1300 | /* Or can we switch back to PIC here? */ |
1301 | } | |
1302 | ||
374aab33 | 1303 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1304 | |
c767a54b | 1305 | pr_info("CPU%d: ", 0); |
8aef135c | 1306 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1307 | |
1308 | if (is_uv_system()) | |
1309 | uv_system_init(); | |
d0af9eed SS |
1310 | |
1311 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1312 | |
1313 | smp_quirk_init_udelay(); | |
8aef135c | 1314 | } |
d0af9eed SS |
1315 | |
1316 | void arch_enable_nonboot_cpus_begin(void) | |
1317 | { | |
1318 | set_mtrr_aps_delayed_init(); | |
1319 | } | |
1320 | ||
1321 | void arch_enable_nonboot_cpus_end(void) | |
1322 | { | |
1323 | mtrr_aps_init(); | |
1324 | } | |
1325 | ||
a8db8453 GOC |
1326 | /* |
1327 | * Early setup to make printk work. | |
1328 | */ | |
1329 | void __init native_smp_prepare_boot_cpu(void) | |
1330 | { | |
1331 | int me = smp_processor_id(); | |
552be871 | 1332 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1333 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1334 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1335 | cpu_set_state_online(me); |
a8db8453 GOC |
1336 | } |
1337 | ||
83f7eb9c GOC |
1338 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1339 | { | |
c767a54b | 1340 | pr_debug("Boot done\n"); |
83f7eb9c | 1341 | |
99e8b9ca | 1342 | nmi_selftest(); |
83f7eb9c | 1343 | impress_friends(); |
83f7eb9c | 1344 | setup_ioapic_dest(); |
d0af9eed | 1345 | mtrr_aps_init(); |
83f7eb9c GOC |
1346 | } |
1347 | ||
3b11ce7f MT |
1348 | static int __initdata setup_possible_cpus = -1; |
1349 | static int __init _setup_possible_cpus(char *str) | |
1350 | { | |
1351 | get_option(&str, &setup_possible_cpus); | |
1352 | return 0; | |
1353 | } | |
1354 | early_param("possible_cpus", _setup_possible_cpus); | |
1355 | ||
1356 | ||
68a1c3f8 | 1357 | /* |
4f062896 | 1358 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1359 | * are onlined, or offlined. The reason is per-cpu data-structures |
1360 | * are allocated by some modules at init time, and dont expect to | |
1361 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1362 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1363 | * In case when cpu_hotplug is not compiled, then we resort to current |
1364 | * behaviour, which is cpu_possible == cpu_present. | |
1365 | * - Ashok Raj | |
1366 | * | |
1367 | * Three ways to find out the number of additional hotplug CPUs: | |
1368 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1369 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1370 | * - Otherwise don't reserve additional CPUs. |
1371 | * We do this because additional CPUs waste a lot of memory. | |
1372 | * -AK | |
1373 | */ | |
1374 | __init void prefill_possible_map(void) | |
1375 | { | |
cb48bb59 | 1376 | int i, possible; |
68a1c3f8 | 1377 | |
329513a3 YL |
1378 | /* no processor from mptable or madt */ |
1379 | if (!num_processors) | |
1380 | num_processors = 1; | |
1381 | ||
5f2eb550 JB |
1382 | i = setup_max_cpus ?: 1; |
1383 | if (setup_possible_cpus == -1) { | |
1384 | possible = num_processors; | |
1385 | #ifdef CONFIG_HOTPLUG_CPU | |
1386 | if (setup_max_cpus) | |
1387 | possible += disabled_cpus; | |
1388 | #else | |
1389 | if (possible > i) | |
1390 | possible = i; | |
1391 | #endif | |
1392 | } else | |
3b11ce7f MT |
1393 | possible = setup_possible_cpus; |
1394 | ||
730cf272 MT |
1395 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1396 | ||
2b633e3f YL |
1397 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1398 | if (possible > nr_cpu_ids) { | |
c767a54b | 1399 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1400 | possible, nr_cpu_ids); |
1401 | possible = nr_cpu_ids; | |
3b11ce7f | 1402 | } |
68a1c3f8 | 1403 | |
5f2eb550 JB |
1404 | #ifdef CONFIG_HOTPLUG_CPU |
1405 | if (!setup_max_cpus) | |
1406 | #endif | |
1407 | if (possible > i) { | |
c767a54b | 1408 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1409 | possible, setup_max_cpus); |
1410 | possible = i; | |
1411 | } | |
1412 | ||
c767a54b | 1413 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1414 | possible, max_t(int, possible - num_processors, 0)); |
1415 | ||
1416 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1417 | set_cpu_possible(i, true); |
5f2eb550 JB |
1418 | for (; i < NR_CPUS; i++) |
1419 | set_cpu_possible(i, false); | |
3461b0af MT |
1420 | |
1421 | nr_cpu_ids = possible; | |
68a1c3f8 | 1422 | } |
69c18c15 | 1423 | |
14adf855 CE |
1424 | #ifdef CONFIG_HOTPLUG_CPU |
1425 | ||
1426 | static void remove_siblinginfo(int cpu) | |
1427 | { | |
1428 | int sibling; | |
1429 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1430 | ||
7d79a7bd BG |
1431 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1432 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1433 | /*/ |
1434 | * last thread sibling in this cpu core going down | |
1435 | */ | |
7d79a7bd | 1436 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1437 | cpu_data(sibling).booted_cores--; |
1438 | } | |
1439 | ||
7d79a7bd BG |
1440 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1441 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1442 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1443 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1444 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1445 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1446 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1447 | c->phys_proc_id = 0; |
1448 | c->cpu_core_id = 0; | |
c2d1cec1 | 1449 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1450 | } |
1451 | ||
4daa832d | 1452 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1453 | { |
c2d1cec1 MT |
1454 | set_cpu_online(cpu, false); |
1455 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1456 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1457 | /* was set by cpu_init() */ |
c2d1cec1 | 1458 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1459 | numa_remove_cpu(cpu); |
69c18c15 GC |
1460 | } |
1461 | ||
8227dce7 | 1462 | void cpu_disable_common(void) |
69c18c15 GC |
1463 | { |
1464 | int cpu = smp_processor_id(); | |
69c18c15 | 1465 | |
69c18c15 GC |
1466 | remove_siblinginfo(cpu); |
1467 | ||
1468 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1469 | lock_vector_lock(); |
69c18c15 | 1470 | remove_cpu_from_maps(cpu); |
d388e5fd | 1471 | unlock_vector_lock(); |
d7b381bb | 1472 | fixup_irqs(); |
8227dce7 AN |
1473 | } |
1474 | ||
1475 | int native_cpu_disable(void) | |
1476 | { | |
da6139e4 PB |
1477 | int ret; |
1478 | ||
1479 | ret = check_irq_vectors_for_cpu_disable(); | |
1480 | if (ret) | |
1481 | return ret; | |
1482 | ||
8227dce7 | 1483 | clear_local_APIC(); |
8227dce7 | 1484 | cpu_disable_common(); |
2ed53c0d | 1485 | |
69c18c15 GC |
1486 | return 0; |
1487 | } | |
1488 | ||
2a442c9c | 1489 | int common_cpu_die(unsigned int cpu) |
54279552 | 1490 | { |
2a442c9c | 1491 | int ret = 0; |
54279552 | 1492 | |
69c18c15 | 1493 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1494 | |
2ed53c0d | 1495 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1496 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1497 | if (system_state == SYSTEM_RUNNING) |
1498 | pr_info("CPU %u is now offline\n", cpu); | |
1499 | } else { | |
1500 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1501 | ret = -1; |
69c18c15 | 1502 | } |
2a442c9c PM |
1503 | |
1504 | return ret; | |
1505 | } | |
1506 | ||
1507 | void native_cpu_die(unsigned int cpu) | |
1508 | { | |
1509 | common_cpu_die(cpu); | |
69c18c15 | 1510 | } |
a21f5d88 AN |
1511 | |
1512 | void play_dead_common(void) | |
1513 | { | |
1514 | idle_task_exit(); | |
1515 | reset_lazy_tlbstate(); | |
02c68a02 | 1516 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 | 1517 | |
a21f5d88 | 1518 | /* Ack it */ |
2a442c9c | 1519 | (void)cpu_report_death(); |
a21f5d88 AN |
1520 | |
1521 | /* | |
1522 | * With physical CPU hotplug, we should halt the cpu | |
1523 | */ | |
1524 | local_irq_disable(); | |
1525 | } | |
1526 | ||
e1c467e6 FY |
1527 | static bool wakeup_cpu0(void) |
1528 | { | |
1529 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1530 | return true; | |
1531 | ||
1532 | return false; | |
1533 | } | |
1534 | ||
ea530692 PA |
1535 | /* |
1536 | * We need to flush the caches before going to sleep, lest we have | |
1537 | * dirty data in our caches when we come back up. | |
1538 | */ | |
1539 | static inline void mwait_play_dead(void) | |
1540 | { | |
1541 | unsigned int eax, ebx, ecx, edx; | |
1542 | unsigned int highest_cstate = 0; | |
1543 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1544 | void *mwait_ptr; |
576cfb40 | 1545 | int i; |
ea530692 | 1546 | |
69fb3676 | 1547 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1548 | return; |
840d2830 | 1549 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1550 | return; |
7b543a53 | 1551 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1552 | return; |
1553 | ||
1554 | eax = CPUID_MWAIT_LEAF; | |
1555 | ecx = 0; | |
1556 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1557 | ||
1558 | /* | |
1559 | * eax will be 0 if EDX enumeration is not valid. | |
1560 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1561 | */ | |
1562 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1563 | eax = 0; | |
1564 | } else { | |
1565 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1566 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1567 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1568 | highest_cstate = i; | |
1569 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1570 | } | |
1571 | } | |
1572 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1573 | (highest_subcstate - 1); | |
1574 | } | |
1575 | ||
ce5f6824 PA |
1576 | /* |
1577 | * This should be a memory location in a cache line which is | |
1578 | * unlikely to be touched by other processors. The actual | |
1579 | * content is immaterial as it is not actually modified in any way. | |
1580 | */ | |
1581 | mwait_ptr = ¤t_thread_info()->flags; | |
1582 | ||
a68e5c94 PA |
1583 | wbinvd(); |
1584 | ||
ea530692 | 1585 | while (1) { |
ce5f6824 PA |
1586 | /* |
1587 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1588 | * the Xeon 7400 series. It's not clear it is actually | |
1589 | * needed, but it should be harmless in either case. | |
1590 | * The WBINVD is insufficient due to the spurious-wakeup | |
1591 | * case where we return around the loop. | |
1592 | */ | |
7d590cca | 1593 | mb(); |
ce5f6824 | 1594 | clflush(mwait_ptr); |
7d590cca | 1595 | mb(); |
ce5f6824 | 1596 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1597 | mb(); |
1598 | __mwait(eax, 0); | |
e1c467e6 FY |
1599 | /* |
1600 | * If NMI wants to wake up CPU0, start CPU0. | |
1601 | */ | |
1602 | if (wakeup_cpu0()) | |
1603 | start_cpu0(); | |
ea530692 PA |
1604 | } |
1605 | } | |
1606 | ||
1607 | static inline void hlt_play_dead(void) | |
1608 | { | |
7b543a53 | 1609 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1610 | wbinvd(); |
1611 | ||
ea530692 | 1612 | while (1) { |
ea530692 | 1613 | native_halt(); |
e1c467e6 FY |
1614 | /* |
1615 | * If NMI wants to wake up CPU0, start CPU0. | |
1616 | */ | |
1617 | if (wakeup_cpu0()) | |
1618 | start_cpu0(); | |
ea530692 PA |
1619 | } |
1620 | } | |
1621 | ||
a21f5d88 AN |
1622 | void native_play_dead(void) |
1623 | { | |
1624 | play_dead_common(); | |
86886e55 | 1625 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1626 | |
1627 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1628 | if (cpuidle_play_dead()) |
1629 | hlt_play_dead(); | |
a21f5d88 AN |
1630 | } |
1631 | ||
69c18c15 | 1632 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1633 | int native_cpu_disable(void) |
69c18c15 GC |
1634 | { |
1635 | return -ENOSYS; | |
1636 | } | |
1637 | ||
93be71b6 | 1638 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1639 | { |
1640 | /* We said "no" in __cpu_disable */ | |
1641 | BUG(); | |
1642 | } | |
a21f5d88 AN |
1643 | |
1644 | void native_play_dead(void) | |
1645 | { | |
1646 | BUG(); | |
1647 | } | |
1648 | ||
68a1c3f8 | 1649 | #endif |