Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
4 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> | |
5 | * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> | |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. | |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69c18c15 | 50 | |
8aef135c | 51 | #include <asm/acpi.h> |
cb3c8b90 | 52 | #include <asm/desc.h> |
69c18c15 GC |
53 | #include <asm/nmi.h> |
54 | #include <asm/irq.h> | |
55 | #include <asm/smp.h> | |
e44b7b75 | 56 | #include <asm/trampoline.h> |
69c18c15 GC |
57 | #include <asm/cpu.h> |
58 | #include <asm/numa.h> | |
cb3c8b90 GOC |
59 | #include <asm/pgtable.h> |
60 | #include <asm/tlbflush.h> | |
61 | #include <asm/mtrr.h> | |
bbc2ff6a | 62 | #include <asm/vmi.h> |
34d05591 | 63 | #include <asm/genapic.h> |
cb3c8b90 | 64 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 65 | |
f6bc4029 | 66 | #include <mach_apic.h> |
cb3c8b90 GOC |
67 | #include <mach_wakecpu.h> |
68 | #include <smpboot_hooks.h> | |
69 | ||
16ecf7a4 | 70 | #ifdef CONFIG_X86_32 |
4cedb334 | 71 | u8 apicid_2_node[MAX_APICID]; |
61165d7a | 72 | static int low_mappings; |
acbb6734 GOC |
73 | #endif |
74 | ||
a8db8453 GOC |
75 | /* State of each CPU */ |
76 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
77 | ||
cb3c8b90 GOC |
78 | /* Store all idle threads, this can be reused instead of creating |
79 | * a new thread. Also avoids complicated thread destroy functionality | |
80 | * for idle threads. | |
81 | */ | |
82 | #ifdef CONFIG_HOTPLUG_CPU | |
83 | /* | |
84 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
85 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
86 | */ | |
87 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
88 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
89 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
90 | #else | |
91 | struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; | |
92 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) | |
93 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
94 | #endif | |
f6bc4029 | 95 | |
a355352b GC |
96 | /* Number of siblings per CPU package */ |
97 | int smp_num_siblings = 1; | |
98 | EXPORT_SYMBOL(smp_num_siblings); | |
99 | ||
100 | /* Last level cache ID of each logical CPU */ | |
101 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
102 | ||
103 | /* bitmap of online cpus */ | |
104 | cpumask_t cpu_online_map __read_mostly; | |
105 | EXPORT_SYMBOL(cpu_online_map); | |
106 | ||
107 | cpumask_t cpu_callin_map; | |
108 | cpumask_t cpu_callout_map; | |
109 | cpumask_t cpu_possible_map; | |
110 | EXPORT_SYMBOL(cpu_possible_map); | |
111 | ||
112 | /* representing HT siblings of each logical CPU */ | |
113 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); | |
114 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); | |
115 | ||
116 | /* representing HT and core siblings of each logical CPU */ | |
117 | DEFINE_PER_CPU(cpumask_t, cpu_core_map); | |
118 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); | |
119 | ||
120 | /* Per CPU bogomips and other parameters */ | |
121 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
122 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 123 | |
cb3c8b90 GOC |
124 | static atomic_t init_deasserted; |
125 | ||
8aef135c GOC |
126 | static int boot_cpu_logical_apicid; |
127 | ||
768d9505 GC |
128 | /* representing cpus for which sibling maps can be computed */ |
129 | static cpumask_t cpu_sibling_setup_map; | |
130 | ||
1d89a7f0 GOC |
131 | /* Set if we find a B stepping CPU */ |
132 | int __cpuinitdata smp_b_stepping; | |
1d89a7f0 | 133 | |
7cc3959e GOC |
134 | #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) |
135 | ||
136 | /* which logical CPUs are on which nodes */ | |
137 | cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = | |
138 | { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; | |
139 | EXPORT_SYMBOL(node_to_cpumask_map); | |
140 | /* which node each logical CPU is on */ | |
141 | int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; | |
142 | EXPORT_SYMBOL(cpu_to_node_map); | |
143 | ||
144 | /* set up a mapping between cpu and node. */ | |
145 | static void map_cpu_to_node(int cpu, int node) | |
146 | { | |
147 | printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); | |
148 | cpu_set(cpu, node_to_cpumask_map[node]); | |
149 | cpu_to_node_map[cpu] = node; | |
150 | } | |
151 | ||
152 | /* undo a mapping between cpu and node. */ | |
153 | static void unmap_cpu_to_node(int cpu) | |
154 | { | |
155 | int node; | |
156 | ||
157 | printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); | |
158 | for (node = 0; node < MAX_NUMNODES; node++) | |
159 | cpu_clear(cpu, node_to_cpumask_map[node]); | |
160 | cpu_to_node_map[cpu] = 0; | |
161 | } | |
162 | #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ | |
163 | #define map_cpu_to_node(cpu, node) ({}) | |
164 | #define unmap_cpu_to_node(cpu) ({}) | |
165 | #endif | |
166 | ||
167 | #ifdef CONFIG_X86_32 | |
168 | u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = | |
169 | { [0 ... NR_CPUS-1] = BAD_APICID }; | |
170 | ||
a4928cff | 171 | static void map_cpu_to_logical_apicid(void) |
7cc3959e GOC |
172 | { |
173 | int cpu = smp_processor_id(); | |
174 | int apicid = logical_smp_processor_id(); | |
175 | int node = apicid_to_node(apicid); | |
176 | ||
177 | if (!node_online(node)) | |
178 | node = first_online_node; | |
179 | ||
180 | cpu_2_logical_apicid[cpu] = apicid; | |
181 | map_cpu_to_node(cpu, node); | |
182 | } | |
183 | ||
1481a3dd | 184 | void numa_remove_cpu(int cpu) |
7cc3959e GOC |
185 | { |
186 | cpu_2_logical_apicid[cpu] = BAD_APICID; | |
187 | unmap_cpu_to_node(cpu); | |
188 | } | |
189 | #else | |
7cc3959e GOC |
190 | #define map_cpu_to_logical_apicid() do {} while (0) |
191 | #endif | |
192 | ||
cb3c8b90 GOC |
193 | /* |
194 | * Report back to the Boot Processor. | |
195 | * Running on AP. | |
196 | */ | |
a4928cff | 197 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
198 | { |
199 | int cpuid, phys_id; | |
200 | unsigned long timeout; | |
201 | ||
202 | /* | |
203 | * If waken up by an INIT in an 82489DX configuration | |
204 | * we may get here before an INIT-deassert IPI reaches | |
205 | * our local APIC. We have to wait for the IPI or we'll | |
206 | * lock up on an APIC access. | |
207 | */ | |
208 | wait_for_init_deassert(&init_deasserted); | |
209 | ||
210 | /* | |
211 | * (This works even if the APIC is not enabled.) | |
212 | */ | |
05f2d12c | 213 | phys_id = GET_APIC_ID(read_apic_id()); |
cb3c8b90 GOC |
214 | cpuid = smp_processor_id(); |
215 | if (cpu_isset(cpuid, cpu_callin_map)) { | |
216 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, | |
217 | phys_id, cpuid); | |
218 | } | |
cfc1b9a6 | 219 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
220 | |
221 | /* | |
222 | * STARTUP IPIs are fragile beasts as they might sometimes | |
223 | * trigger some glue motherboard logic. Complete APIC bus | |
224 | * silence for 1 second, this overestimates the time the | |
225 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
226 | * by a factor of two. This should be enough. | |
227 | */ | |
228 | ||
229 | /* | |
230 | * Waiting 2s total for startup (udelay is not yet working) | |
231 | */ | |
232 | timeout = jiffies + 2*HZ; | |
233 | while (time_before(jiffies, timeout)) { | |
234 | /* | |
235 | * Has the boot CPU finished it's STARTUP sequence? | |
236 | */ | |
237 | if (cpu_isset(cpuid, cpu_callout_map)) | |
238 | break; | |
239 | cpu_relax(); | |
240 | } | |
241 | ||
242 | if (!time_before(jiffies, timeout)) { | |
243 | panic("%s: CPU%d started up but did not get a callout!\n", | |
244 | __func__, cpuid); | |
245 | } | |
246 | ||
247 | /* | |
248 | * the boot CPU has finished the init stage and is spinning | |
249 | * on callin_map until we finish. We are free to set up this | |
250 | * CPU, first the APIC. (this is probably redundant on most | |
251 | * boards) | |
252 | */ | |
253 | ||
cfc1b9a6 | 254 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
cb3c8b90 GOC |
255 | smp_callin_clear_local_apic(); |
256 | setup_local_APIC(); | |
257 | end_local_APIC_setup(); | |
258 | map_cpu_to_logical_apicid(); | |
259 | ||
260 | /* | |
261 | * Get our bogomips. | |
262 | * | |
263 | * Need to enable IRQs because it can take longer and then | |
264 | * the NMI watchdog might kill us. | |
265 | */ | |
266 | local_irq_enable(); | |
267 | calibrate_delay(); | |
268 | local_irq_disable(); | |
cfc1b9a6 | 269 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 GOC |
270 | |
271 | /* | |
272 | * Save our processor parameters | |
273 | */ | |
274 | smp_store_cpu_info(cpuid); | |
275 | ||
276 | /* | |
277 | * Allow the master to continue. | |
278 | */ | |
279 | cpu_set(cpuid, cpu_callin_map); | |
280 | } | |
281 | ||
bbc2ff6a GOC |
282 | /* |
283 | * Activate a secondary processor. | |
284 | */ | |
dbe55f47 | 285 | static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
286 | { |
287 | /* | |
288 | * Don't put *anything* before cpu_init(), SMP booting is too | |
289 | * fragile that we want to limit the things done here to the | |
290 | * most necessary things. | |
291 | */ | |
292 | #ifdef CONFIG_VMI | |
293 | vmi_bringup(); | |
294 | #endif | |
295 | cpu_init(); | |
296 | preempt_disable(); | |
297 | smp_callin(); | |
298 | ||
299 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ | |
300 | barrier(); | |
301 | /* | |
302 | * Check TSC synchronization with the BP: | |
303 | */ | |
304 | check_tsc_sync_target(); | |
305 | ||
306 | if (nmi_watchdog == NMI_IO_APIC) { | |
307 | disable_8259A_irq(0); | |
308 | enable_NMI_through_LVT0(); | |
309 | enable_8259A_irq(0); | |
310 | } | |
311 | ||
61165d7a HD |
312 | #ifdef CONFIG_X86_32 |
313 | while (low_mappings) | |
314 | cpu_relax(); | |
315 | __flush_tlb_all(); | |
316 | #endif | |
317 | ||
bbc2ff6a GOC |
318 | /* This must be done before setting cpu_online_map */ |
319 | set_cpu_sibling_map(raw_smp_processor_id()); | |
320 | wmb(); | |
321 | ||
322 | /* | |
323 | * We need to hold call_lock, so there is no inconsistency | |
324 | * between the time smp_call_function() determines number of | |
325 | * IPI recipients, and the time when the determination is made | |
326 | * for which cpus receive the IPI. Holding this | |
327 | * lock helps us to not include this cpu in a currently in progress | |
328 | * smp_call_function(). | |
d388e5fd EB |
329 | * |
330 | * We need to hold vector_lock so there the set of online cpus | |
331 | * does not change while we are assigning vectors to cpus. Holding | |
332 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 333 | */ |
3b16cf87 | 334 | ipi_call_lock_irq(); |
d388e5fd EB |
335 | lock_vector_lock(); |
336 | __setup_vector_irq(smp_processor_id()); | |
bbc2ff6a | 337 | cpu_set(smp_processor_id(), cpu_online_map); |
d388e5fd | 338 | unlock_vector_lock(); |
3b16cf87 | 339 | ipi_call_unlock_irq(); |
bbc2ff6a GOC |
340 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
341 | ||
342 | setup_secondary_clock(); | |
343 | ||
344 | wmb(); | |
345 | cpu_idle(); | |
346 | } | |
347 | ||
1d89a7f0 GOC |
348 | static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) |
349 | { | |
1d89a7f0 GOC |
350 | /* |
351 | * Mask B, Pentium, but not Pentium MMX | |
352 | */ | |
353 | if (c->x86_vendor == X86_VENDOR_INTEL && | |
354 | c->x86 == 5 && | |
355 | c->x86_mask >= 1 && c->x86_mask <= 4 && | |
356 | c->x86_model <= 3) | |
357 | /* | |
358 | * Remember we have B step Pentia with bugs | |
359 | */ | |
360 | smp_b_stepping = 1; | |
361 | ||
362 | /* | |
363 | * Certain Athlons might work (for various values of 'work') in SMP | |
364 | * but they are not certified as MP capable. | |
365 | */ | |
366 | if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { | |
367 | ||
368 | if (num_possible_cpus() == 1) | |
369 | goto valid_k7; | |
370 | ||
371 | /* Athlon 660/661 is valid. */ | |
372 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
373 | (c->x86_mask == 1))) | |
374 | goto valid_k7; | |
375 | ||
376 | /* Duron 670 is valid */ | |
377 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
378 | goto valid_k7; | |
379 | ||
380 | /* | |
381 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
382 | * bit. It's worth noting that the A5 stepping (662) of some | |
383 | * Athlon XP's have the MP bit set. | |
384 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
385 | * more. | |
386 | */ | |
387 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
388 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
389 | (c->x86_model > 7)) | |
390 | if (cpu_has_mp) | |
391 | goto valid_k7; | |
392 | ||
393 | /* If we get here, not a certified SMP capable AMD system. */ | |
394 | add_taint(TAINT_UNSAFE_SMP); | |
395 | } | |
396 | ||
397 | valid_k7: | |
398 | ; | |
1d89a7f0 GOC |
399 | } |
400 | ||
a4928cff | 401 | static void __cpuinit smp_checks(void) |
693d4b8a GOC |
402 | { |
403 | if (smp_b_stepping) | |
404 | printk(KERN_WARNING "WARNING: SMP operation may be unreliable" | |
405 | "with B stepping processors.\n"); | |
406 | ||
407 | /* | |
408 | * Don't taint if we are running SMP kernel on a single non-MP | |
409 | * approved Athlon | |
410 | */ | |
411 | if (tainted & TAINT_UNSAFE_SMP) { | |
f68e00a3 | 412 | if (num_online_cpus()) |
693d4b8a GOC |
413 | printk(KERN_INFO "WARNING: This combination of AMD" |
414 | "processors is not suitable for SMP.\n"); | |
415 | else | |
416 | tainted &= ~TAINT_UNSAFE_SMP; | |
417 | } | |
418 | } | |
419 | ||
1d89a7f0 GOC |
420 | /* |
421 | * The bootstrap kernel entry code has set these up. Save them for | |
422 | * a given CPU | |
423 | */ | |
424 | ||
425 | void __cpuinit smp_store_cpu_info(int id) | |
426 | { | |
427 | struct cpuinfo_x86 *c = &cpu_data(id); | |
428 | ||
429 | *c = boot_cpu_data; | |
430 | c->cpu_index = id; | |
431 | if (id != 0) | |
432 | identify_secondary_cpu(c); | |
433 | smp_apply_quirks(c); | |
434 | } | |
435 | ||
436 | ||
768d9505 GC |
437 | void __cpuinit set_cpu_sibling_map(int cpu) |
438 | { | |
439 | int i; | |
440 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
441 | ||
442 | cpu_set(cpu, cpu_sibling_setup_map); | |
443 | ||
444 | if (smp_num_siblings > 1) { | |
334ef7a7 | 445 | for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { |
768d9505 GC |
446 | if (c->phys_proc_id == cpu_data(i).phys_proc_id && |
447 | c->cpu_core_id == cpu_data(i).cpu_core_id) { | |
448 | cpu_set(i, per_cpu(cpu_sibling_map, cpu)); | |
449 | cpu_set(cpu, per_cpu(cpu_sibling_map, i)); | |
450 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
451 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
452 | cpu_set(i, c->llc_shared_map); | |
453 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
454 | } | |
455 | } | |
456 | } else { | |
457 | cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); | |
458 | } | |
459 | ||
460 | cpu_set(cpu, c->llc_shared_map); | |
461 | ||
462 | if (current_cpu_data.x86_max_cores == 1) { | |
463 | per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); | |
464 | c->booted_cores = 1; | |
465 | return; | |
466 | } | |
467 | ||
334ef7a7 | 468 | for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { |
768d9505 GC |
469 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
470 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
471 | cpu_set(i, c->llc_shared_map); | |
472 | cpu_set(cpu, cpu_data(i).llc_shared_map); | |
473 | } | |
474 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
475 | cpu_set(i, per_cpu(cpu_core_map, cpu)); | |
476 | cpu_set(cpu, per_cpu(cpu_core_map, i)); | |
477 | /* | |
478 | * Does this new cpu bringup a new core? | |
479 | */ | |
480 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { | |
481 | /* | |
482 | * for each core in package, increment | |
483 | * the booted_cores for this new cpu | |
484 | */ | |
485 | if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) | |
486 | c->booted_cores++; | |
487 | /* | |
488 | * increment the core count for all | |
489 | * the other cpus in this package | |
490 | */ | |
491 | if (i != cpu) | |
492 | cpu_data(i).booted_cores++; | |
493 | } else if (i != cpu && !c->booted_cores) | |
494 | c->booted_cores = cpu_data(i).booted_cores; | |
495 | } | |
496 | } | |
497 | } | |
498 | ||
70708a18 GC |
499 | /* maps the cpu to the sched domain representing multi-core */ |
500 | cpumask_t cpu_coregroup_map(int cpu) | |
501 | { | |
502 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
503 | /* | |
504 | * For perf, we return last level cache shared map. | |
505 | * And for power savings, we return cpu_core_map | |
506 | */ | |
507 | if (sched_mc_power_savings || sched_smt_power_savings) | |
508 | return per_cpu(cpu_core_map, cpu); | |
509 | else | |
510 | return c->llc_shared_map; | |
511 | } | |
512 | ||
a4928cff | 513 | static void impress_friends(void) |
904541e2 GOC |
514 | { |
515 | int cpu; | |
516 | unsigned long bogosum = 0; | |
517 | /* | |
518 | * Allow the user to impress friends. | |
519 | */ | |
cfc1b9a6 | 520 | pr_debug("Before bogomips.\n"); |
904541e2 GOC |
521 | for_each_possible_cpu(cpu) |
522 | if (cpu_isset(cpu, cpu_callout_map)) | |
523 | bogosum += cpu_data(cpu).loops_per_jiffy; | |
524 | printk(KERN_INFO | |
525 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 526 | num_online_cpus(), |
904541e2 GOC |
527 | bogosum/(500000/HZ), |
528 | (bogosum/(5000/HZ))%100); | |
529 | ||
cfc1b9a6 | 530 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
531 | } |
532 | ||
cb3c8b90 GOC |
533 | static inline void __inquire_remote_apic(int apicid) |
534 | { | |
535 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
536 | char *names[] = { "ID", "VERSION", "SPIV" }; | |
537 | int timeout; | |
538 | u32 status; | |
539 | ||
540 | printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid); | |
541 | ||
542 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
543 | printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]); | |
544 | ||
545 | /* | |
546 | * Wait for idle. | |
547 | */ | |
548 | status = safe_apic_wait_icr_idle(); | |
549 | if (status) | |
550 | printk(KERN_CONT | |
551 | "a previous APIC delivery may have failed\n"); | |
552 | ||
593f4a78 MR |
553 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid)); |
554 | apic_write(APIC_ICR, APIC_DM_REMRD | regs[i]); | |
cb3c8b90 GOC |
555 | |
556 | timeout = 0; | |
557 | do { | |
558 | udelay(100); | |
559 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
560 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
561 | ||
562 | switch (status) { | |
563 | case APIC_ICR_RR_VALID: | |
564 | status = apic_read(APIC_RRR); | |
565 | printk(KERN_CONT "%08x\n", status); | |
566 | break; | |
567 | default: | |
568 | printk(KERN_CONT "failed\n"); | |
569 | } | |
570 | } | |
571 | } | |
572 | ||
573 | #ifdef WAKE_SECONDARY_VIA_NMI | |
574 | /* | |
575 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
576 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
577 | * won't ... remember to clear down the APIC, etc later. | |
578 | */ | |
579 | static int __devinit | |
580 | wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) | |
581 | { | |
582 | unsigned long send_status, accept_status = 0; | |
583 | int maxlvt; | |
584 | ||
585 | /* Target chip */ | |
593f4a78 | 586 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid)); |
cb3c8b90 GOC |
587 | |
588 | /* Boot on the stack */ | |
589 | /* Kick the second */ | |
593f4a78 | 590 | apic_write(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL); |
cb3c8b90 | 591 | |
cfc1b9a6 | 592 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
593 | send_status = safe_apic_wait_icr_idle(); |
594 | ||
595 | /* | |
596 | * Give the other CPU some time to accept the IPI. | |
597 | */ | |
598 | udelay(200); | |
cb3c8b90 | 599 | maxlvt = lapic_get_maxlvt(); |
593f4a78 | 600 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 601 | apic_write(APIC_ESR, 0); |
cb3c8b90 | 602 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
cfc1b9a6 | 603 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
604 | |
605 | if (send_status) | |
606 | printk(KERN_ERR "APIC never delivered???\n"); | |
607 | if (accept_status) | |
608 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
609 | ||
610 | return (send_status | accept_status); | |
611 | } | |
612 | #endif /* WAKE_SECONDARY_VIA_NMI */ | |
613 | ||
cb3c8b90 GOC |
614 | #ifdef WAKE_SECONDARY_VIA_INIT |
615 | static int __devinit | |
616 | wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) | |
617 | { | |
618 | unsigned long send_status, accept_status = 0; | |
619 | int maxlvt, num_starts, j; | |
620 | ||
34d05591 JS |
621 | if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { |
622 | send_status = uv_wakeup_secondary(phys_apicid, start_eip); | |
623 | atomic_set(&init_deasserted, 1); | |
624 | return send_status; | |
625 | } | |
626 | ||
593f4a78 MR |
627 | maxlvt = lapic_get_maxlvt(); |
628 | ||
cb3c8b90 GOC |
629 | /* |
630 | * Be paranoid about clearing APIC errors. | |
631 | */ | |
632 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
633 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
634 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
635 | apic_read(APIC_ESR); |
636 | } | |
637 | ||
cfc1b9a6 | 638 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
639 | |
640 | /* | |
641 | * Turn INIT on target chip | |
642 | */ | |
593f4a78 | 643 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
cb3c8b90 GOC |
644 | |
645 | /* | |
646 | * Send IPI | |
647 | */ | |
593f4a78 MR |
648 | apic_write(APIC_ICR, |
649 | APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT); | |
cb3c8b90 | 650 | |
cfc1b9a6 | 651 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
652 | send_status = safe_apic_wait_icr_idle(); |
653 | ||
654 | mdelay(10); | |
655 | ||
cfc1b9a6 | 656 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
657 | |
658 | /* Target chip */ | |
593f4a78 | 659 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
cb3c8b90 GOC |
660 | |
661 | /* Send IPI */ | |
593f4a78 | 662 | apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT); |
cb3c8b90 | 663 | |
cfc1b9a6 | 664 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
665 | send_status = safe_apic_wait_icr_idle(); |
666 | ||
667 | mb(); | |
668 | atomic_set(&init_deasserted, 1); | |
669 | ||
670 | /* | |
671 | * Should we send STARTUP IPIs ? | |
672 | * | |
673 | * Determine this based on the APIC version. | |
674 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
675 | */ | |
676 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
677 | num_starts = 2; | |
678 | else | |
679 | num_starts = 0; | |
680 | ||
681 | /* | |
682 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
683 | * target processor state. | |
684 | */ | |
685 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
cb3c8b90 | 686 | (unsigned long)stack_start.sp); |
cb3c8b90 GOC |
687 | |
688 | /* | |
689 | * Run STARTUP IPI loop. | |
690 | */ | |
cfc1b9a6 | 691 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 692 | |
cb3c8b90 | 693 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 694 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
695 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
696 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 697 | apic_read(APIC_ESR); |
cfc1b9a6 | 698 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
699 | |
700 | /* | |
701 | * STARTUP IPI | |
702 | */ | |
703 | ||
704 | /* Target chip */ | |
593f4a78 | 705 | apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid)); |
cb3c8b90 GOC |
706 | |
707 | /* Boot on the stack */ | |
708 | /* Kick the second */ | |
593f4a78 | 709 | apic_write(APIC_ICR, APIC_DM_STARTUP | (start_eip >> 12)); |
cb3c8b90 GOC |
710 | |
711 | /* | |
712 | * Give the other CPU some time to accept the IPI. | |
713 | */ | |
714 | udelay(300); | |
715 | ||
cfc1b9a6 | 716 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 717 | |
cfc1b9a6 | 718 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
719 | send_status = safe_apic_wait_icr_idle(); |
720 | ||
721 | /* | |
722 | * Give the other CPU some time to accept the IPI. | |
723 | */ | |
724 | udelay(200); | |
593f4a78 | 725 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 726 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
727 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
728 | if (send_status || accept_status) | |
729 | break; | |
730 | } | |
cfc1b9a6 | 731 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
732 | |
733 | if (send_status) | |
734 | printk(KERN_ERR "APIC never delivered???\n"); | |
735 | if (accept_status) | |
736 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
737 | ||
738 | return (send_status | accept_status); | |
739 | } | |
740 | #endif /* WAKE_SECONDARY_VIA_INIT */ | |
741 | ||
742 | struct create_idle { | |
743 | struct work_struct work; | |
744 | struct task_struct *idle; | |
745 | struct completion done; | |
746 | int cpu; | |
747 | }; | |
748 | ||
749 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
750 | { | |
751 | struct create_idle *c_idle = | |
752 | container_of(work, struct create_idle, work); | |
753 | ||
754 | c_idle->idle = fork_idle(c_idle->cpu); | |
755 | complete(&c_idle->done); | |
756 | } | |
757 | ||
f307d25e | 758 | #ifdef CONFIG_X86_64 |
3461b0af MT |
759 | /* |
760 | * Allocate node local memory for the AP pda. | |
761 | * | |
762 | * Must be called after the _cpu_pda pointer table is initialized. | |
763 | */ | |
7c33b1e6 | 764 | int __cpuinit get_local_pda(int cpu) |
3461b0af MT |
765 | { |
766 | struct x8664_pda *oldpda, *newpda; | |
767 | unsigned long size = sizeof(struct x8664_pda); | |
768 | int node = cpu_to_node(cpu); | |
769 | ||
770 | if (cpu_pda(cpu) && !cpu_pda(cpu)->in_bootmem) | |
771 | return 0; | |
772 | ||
773 | oldpda = cpu_pda(cpu); | |
774 | newpda = kmalloc_node(size, GFP_ATOMIC, node); | |
775 | if (!newpda) { | |
776 | printk(KERN_ERR "Could not allocate node local PDA " | |
777 | "for CPU %d on node %d\n", cpu, node); | |
778 | ||
779 | if (oldpda) | |
780 | return 0; /* have a usable pda */ | |
781 | else | |
782 | return -1; | |
783 | } | |
784 | ||
785 | if (oldpda) { | |
786 | memcpy(newpda, oldpda, size); | |
787 | if (!after_bootmem) | |
788 | free_bootmem((unsigned long)oldpda, size); | |
789 | } | |
790 | ||
791 | newpda->in_bootmem = 0; | |
792 | cpu_pda(cpu) = newpda; | |
793 | return 0; | |
794 | } | |
f307d25e | 795 | #endif /* CONFIG_X86_64 */ |
3461b0af | 796 | |
cb3c8b90 GOC |
797 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
798 | /* | |
799 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
800 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
801 | * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. | |
802 | */ | |
803 | { | |
804 | unsigned long boot_error = 0; | |
805 | int timeout; | |
806 | unsigned long start_ip; | |
807 | unsigned short nmi_high = 0, nmi_low = 0; | |
808 | struct create_idle c_idle = { | |
809 | .cpu = cpu, | |
810 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
811 | }; | |
812 | INIT_WORK(&c_idle.work, do_fork_idle); | |
cb3c8b90 | 813 | |
a939098a | 814 | #ifdef CONFIG_X86_64 |
cb3c8b90 | 815 | /* Allocate node local memory for AP pdas */ |
3461b0af MT |
816 | if (cpu > 0) { |
817 | boot_error = get_local_pda(cpu); | |
818 | if (boot_error) | |
819 | goto restore_state; | |
820 | /* if can't get pda memory, can't start cpu */ | |
cb3c8b90 GOC |
821 | } |
822 | #endif | |
823 | ||
824 | alternatives_smp_switch(1); | |
825 | ||
826 | c_idle.idle = get_idle_for_cpu(cpu); | |
827 | ||
828 | /* | |
829 | * We can't use kernel_thread since we must avoid to | |
830 | * reschedule the child. | |
831 | */ | |
832 | if (c_idle.idle) { | |
833 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
834 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
835 | init_idle(c_idle.idle, cpu); | |
836 | goto do_rest; | |
837 | } | |
838 | ||
839 | if (!keventd_up() || current_is_keventd()) | |
840 | c_idle.work.func(&c_idle.work); | |
841 | else { | |
842 | schedule_work(&c_idle.work); | |
843 | wait_for_completion(&c_idle.done); | |
844 | } | |
845 | ||
846 | if (IS_ERR(c_idle.idle)) { | |
847 | printk("failed fork for CPU %d\n", cpu); | |
848 | return PTR_ERR(c_idle.idle); | |
849 | } | |
850 | ||
851 | set_idle_for_cpu(cpu, c_idle.idle); | |
852 | do_rest: | |
853 | #ifdef CONFIG_X86_32 | |
854 | per_cpu(current_task, cpu) = c_idle.idle; | |
855 | init_gdt(cpu); | |
cb3c8b90 | 856 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
857 | irq_ctx_init(cpu); |
858 | #else | |
859 | cpu_pda(cpu)->pcurrent = c_idle.idle; | |
cb3c8b90 GOC |
860 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
861 | #endif | |
a939098a | 862 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 863 | initial_code = (unsigned long)start_secondary; |
9cf4f298 | 864 | stack_start.sp = (void *) c_idle.idle->thread.sp; |
cb3c8b90 GOC |
865 | |
866 | /* start_ip had better be page-aligned! */ | |
867 | start_ip = setup_trampoline(); | |
868 | ||
869 | /* So we see what's up */ | |
870 | printk(KERN_INFO "Booting processor %d/%d ip %lx\n", | |
871 | cpu, apicid, start_ip); | |
872 | ||
873 | /* | |
874 | * This grunge runs the startup process for | |
875 | * the targeted processor. | |
876 | */ | |
877 | ||
878 | atomic_set(&init_deasserted, 0); | |
879 | ||
34d05591 | 880 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 881 | |
cfc1b9a6 | 882 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 883 | |
34d05591 JS |
884 | store_NMI_vector(&nmi_high, &nmi_low); |
885 | ||
886 | smpboot_setup_warm_reset_vector(start_ip); | |
887 | /* | |
888 | * Be paranoid about clearing APIC errors. | |
889 | */ | |
890 | apic_write(APIC_ESR, 0); | |
891 | apic_read(APIC_ESR); | |
892 | } | |
cb3c8b90 | 893 | |
cb3c8b90 GOC |
894 | /* |
895 | * Starting actual IPI sequence... | |
896 | */ | |
897 | boot_error = wakeup_secondary_cpu(apicid, start_ip); | |
898 | ||
899 | if (!boot_error) { | |
900 | /* | |
901 | * allow APs to start initializing. | |
902 | */ | |
cfc1b9a6 | 903 | pr_debug("Before Callout %d.\n", cpu); |
cb3c8b90 | 904 | cpu_set(cpu, cpu_callout_map); |
cfc1b9a6 | 905 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
906 | |
907 | /* | |
908 | * Wait 5s total for a response | |
909 | */ | |
910 | for (timeout = 0; timeout < 50000; timeout++) { | |
911 | if (cpu_isset(cpu, cpu_callin_map)) | |
912 | break; /* It has booted */ | |
913 | udelay(100); | |
914 | } | |
915 | ||
916 | if (cpu_isset(cpu, cpu_callin_map)) { | |
917 | /* number CPUs logically, starting from 1 (BSP is 0) */ | |
cfc1b9a6 | 918 | pr_debug("OK.\n"); |
cb3c8b90 GOC |
919 | printk(KERN_INFO "CPU%d: ", cpu); |
920 | print_cpu_info(&cpu_data(cpu)); | |
cfc1b9a6 | 921 | pr_debug("CPU has booted.\n"); |
cb3c8b90 GOC |
922 | } else { |
923 | boot_error = 1; | |
924 | if (*((volatile unsigned char *)trampoline_base) | |
925 | == 0xA5) | |
926 | /* trampoline started but...? */ | |
927 | printk(KERN_ERR "Stuck ??\n"); | |
928 | else | |
929 | /* trampoline code not run */ | |
930 | printk(KERN_ERR "Not responding.\n"); | |
34d05591 JS |
931 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) |
932 | inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
933 | } |
934 | } | |
6f585e01 | 935 | #ifdef CONFIG_X86_64 |
3461b0af | 936 | restore_state: |
6f585e01 | 937 | #endif |
cb3c8b90 GOC |
938 | if (boot_error) { |
939 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 940 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
cb3c8b90 GOC |
941 | cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ |
942 | cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ | |
cb3c8b90 GOC |
943 | cpu_clear(cpu, cpu_present_map); |
944 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; | |
945 | } | |
946 | ||
947 | /* mark "stuck" area as not stuck */ | |
948 | *((volatile unsigned long *)trampoline_base) = 0; | |
949 | ||
63d38198 AK |
950 | /* |
951 | * Cleanup possible dangling ends... | |
952 | */ | |
953 | smpboot_restore_warm_reset_vector(); | |
954 | ||
cb3c8b90 GOC |
955 | return boot_error; |
956 | } | |
957 | ||
958 | int __cpuinit native_cpu_up(unsigned int cpu) | |
959 | { | |
960 | int apicid = cpu_present_to_apicid(cpu); | |
961 | unsigned long flags; | |
962 | int err; | |
963 | ||
964 | WARN_ON(irqs_disabled()); | |
965 | ||
cfc1b9a6 | 966 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
967 | |
968 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
969 | !physid_isset(apicid, phys_cpu_present_map)) { | |
970 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | |
971 | return -EINVAL; | |
972 | } | |
973 | ||
974 | /* | |
975 | * Already booted CPU? | |
976 | */ | |
977 | if (cpu_isset(cpu, cpu_callin_map)) { | |
cfc1b9a6 | 978 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
979 | return -ENOSYS; |
980 | } | |
981 | ||
982 | /* | |
983 | * Save current MTRR state in case it was changed since early boot | |
984 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
985 | */ | |
986 | mtrr_save_state(); | |
987 | ||
988 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
989 | ||
990 | #ifdef CONFIG_X86_32 | |
991 | /* init low mem mapping */ | |
68db065c | 992 | clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, |
61165d7a | 993 | min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); |
cb3c8b90 | 994 | flush_tlb_all(); |
61165d7a | 995 | low_mappings = 1; |
cb3c8b90 | 996 | |
b74548e7 YL |
997 | #ifdef CONFIG_X86_PC |
998 | if (def_to_bigsmp && apicid > 8) { | |
999 | printk(KERN_WARNING | |
1000 | "More than 8 CPUs detected - skipping them.\n" | |
1001 | "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n"); | |
1002 | err = -1; | |
1003 | } else | |
1004 | err = do_boot_cpu(apicid, cpu); | |
1005 | #else | |
cb3c8b90 | 1006 | err = do_boot_cpu(apicid, cpu); |
b74548e7 | 1007 | #endif |
61165d7a HD |
1008 | |
1009 | zap_low_mappings(); | |
1010 | low_mappings = 0; | |
1011 | #else | |
1012 | err = do_boot_cpu(apicid, cpu); | |
1013 | #endif | |
1014 | if (err) { | |
cfc1b9a6 | 1015 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 1016 | return -EIO; |
cb3c8b90 GOC |
1017 | } |
1018 | ||
1019 | /* | |
1020 | * Check TSC synchronization with the AP (keep irqs disabled | |
1021 | * while doing so): | |
1022 | */ | |
1023 | local_irq_save(flags); | |
1024 | check_tsc_sync_source(cpu); | |
1025 | local_irq_restore(flags); | |
1026 | ||
7c04e64a | 1027 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1028 | cpu_relax(); |
1029 | touch_nmi_watchdog(); | |
1030 | } | |
1031 | ||
1032 | return 0; | |
1033 | } | |
1034 | ||
8aef135c GOC |
1035 | /* |
1036 | * Fall back to non SMP mode after errors. | |
1037 | * | |
1038 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1039 | */ | |
1040 | static __init void disable_smp(void) | |
1041 | { | |
1042 | cpu_present_map = cpumask_of_cpu(0); | |
1043 | cpu_possible_map = cpumask_of_cpu(0); | |
8aef135c | 1044 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 1045 | |
8aef135c | 1046 | if (smp_found_config) |
b6df1b8b | 1047 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1048 | else |
b6df1b8b | 1049 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
8aef135c GOC |
1050 | map_cpu_to_logical_apicid(); |
1051 | cpu_set(0, per_cpu(cpu_sibling_map, 0)); | |
1052 | cpu_set(0, per_cpu(cpu_core_map, 0)); | |
1053 | } | |
1054 | ||
1055 | /* | |
1056 | * Various sanity checks. | |
1057 | */ | |
1058 | static int __init smp_sanity_check(unsigned max_cpus) | |
1059 | { | |
ac23d4ee | 1060 | preempt_disable(); |
8aef135c GOC |
1061 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
1062 | printk(KERN_WARNING "weird, boot CPU (#%d) not listed" | |
1063 | "by the BIOS.\n", hard_smp_processor_id()); | |
1064 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1065 | } | |
1066 | ||
1067 | /* | |
1068 | * If we couldn't find an SMP configuration at boot time, | |
1069 | * get out of here now! | |
1070 | */ | |
1071 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1072 | preempt_enable(); |
8aef135c GOC |
1073 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
1074 | disable_smp(); | |
1075 | if (APIC_init_uniprocessor()) | |
1076 | printk(KERN_NOTICE "Local APIC not detected." | |
1077 | " Using dummy APIC emulation.\n"); | |
1078 | return -1; | |
1079 | } | |
1080 | ||
1081 | /* | |
1082 | * Should not be necessary because the MP table should list the boot | |
1083 | * CPU too, but we do it for the sake of robustness anyway. | |
1084 | */ | |
1085 | if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { | |
1086 | printk(KERN_NOTICE | |
1087 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
1088 | boot_cpu_physical_apicid); | |
1089 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
1090 | } | |
ac23d4ee | 1091 | preempt_enable(); |
8aef135c GOC |
1092 | |
1093 | /* | |
1094 | * If we couldn't find a local APIC, then get out of here now! | |
1095 | */ | |
1096 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1097 | !cpu_has_apic) { | |
1098 | printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", | |
1099 | boot_cpu_physical_apicid); | |
1100 | printk(KERN_ERR "... forcing use of dummy APIC emulation." | |
1101 | "(tell your hw vendor)\n"); | |
1102 | smpboot_clear_io_apic(); | |
1103 | return -1; | |
1104 | } | |
1105 | ||
1106 | verify_local_APIC(); | |
1107 | ||
1108 | /* | |
1109 | * If SMP should be disabled, then really disable it! | |
1110 | */ | |
1111 | if (!max_cpus) { | |
73d08e63 | 1112 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 1113 | smpboot_clear_io_apic(); |
d54db1ac MR |
1114 | |
1115 | localise_nmi_watchdog(); | |
1116 | ||
e90955c2 | 1117 | connect_bsp_APIC(); |
e90955c2 JB |
1118 | setup_local_APIC(); |
1119 | end_local_APIC_setup(); | |
8aef135c GOC |
1120 | return -1; |
1121 | } | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | static void __init smp_cpu_index_default(void) | |
1127 | { | |
1128 | int i; | |
1129 | struct cpuinfo_x86 *c; | |
1130 | ||
7c04e64a | 1131 | for_each_possible_cpu(i) { |
8aef135c GOC |
1132 | c = &cpu_data(i); |
1133 | /* mark all to hotplug */ | |
1134 | c->cpu_index = NR_CPUS; | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | /* | |
1139 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1140 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1141 | */ | |
1142 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1143 | { | |
deef3250 | 1144 | preempt_disable(); |
8aef135c GOC |
1145 | smp_cpu_index_default(); |
1146 | current_cpu_data = boot_cpu_data; | |
1147 | cpu_callin_map = cpumask_of_cpu(0); | |
1148 | mb(); | |
1149 | /* | |
1150 | * Setup boot CPU information | |
1151 | */ | |
1152 | smp_store_cpu_info(0); /* Final full version of the data */ | |
1153 | boot_cpu_logical_apicid = logical_smp_processor_id(); | |
1154 | current_thread_info()->cpu = 0; /* needed? */ | |
1155 | set_cpu_sibling_map(0); | |
1156 | ||
1157 | if (smp_sanity_check(max_cpus) < 0) { | |
1158 | printk(KERN_INFO "SMP disabled\n"); | |
1159 | disable_smp(); | |
deef3250 | 1160 | goto out; |
8aef135c GOC |
1161 | } |
1162 | ||
ac23d4ee | 1163 | preempt_disable(); |
05f2d12c | 1164 | if (GET_APIC_ID(read_apic_id()) != boot_cpu_physical_apicid) { |
8aef135c | 1165 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
05f2d12c | 1166 | GET_APIC_ID(read_apic_id()), boot_cpu_physical_apicid); |
8aef135c GOC |
1167 | /* Or can we switch back to PIC here? */ |
1168 | } | |
ac23d4ee | 1169 | preempt_enable(); |
8aef135c | 1170 | |
8aef135c | 1171 | connect_bsp_APIC(); |
b5841765 | 1172 | |
8aef135c GOC |
1173 | /* |
1174 | * Switch from PIC to APIC mode. | |
1175 | */ | |
1176 | setup_local_APIC(); | |
1177 | ||
1178 | #ifdef CONFIG_X86_64 | |
1179 | /* | |
1180 | * Enable IO APIC before setting up error vector | |
1181 | */ | |
1182 | if (!skip_ioapic_setup && nr_ioapics) | |
1183 | enable_IO_APIC(); | |
1184 | #endif | |
1185 | end_local_APIC_setup(); | |
1186 | ||
1187 | map_cpu_to_logical_apicid(); | |
1188 | ||
1189 | setup_portio_remap(); | |
1190 | ||
1191 | smpboot_setup_io_apic(); | |
1192 | /* | |
1193 | * Set up local APIC timer on boot CPU. | |
1194 | */ | |
1195 | ||
1196 | printk(KERN_INFO "CPU%d: ", 0); | |
1197 | print_cpu_info(&cpu_data(0)); | |
1198 | setup_boot_clock(); | |
deef3250 IM |
1199 | out: |
1200 | preempt_enable(); | |
8aef135c | 1201 | } |
a8db8453 GOC |
1202 | /* |
1203 | * Early setup to make printk work. | |
1204 | */ | |
1205 | void __init native_smp_prepare_boot_cpu(void) | |
1206 | { | |
1207 | int me = smp_processor_id(); | |
1208 | #ifdef CONFIG_X86_32 | |
1209 | init_gdt(me); | |
a8db8453 | 1210 | #endif |
a939098a | 1211 | switch_to_new_gdt(); |
a8db8453 GOC |
1212 | /* already set me in cpu_online_map in boot_cpu_init() */ |
1213 | cpu_set(me, cpu_callout_map); | |
1214 | per_cpu(cpu_state, me) = CPU_ONLINE; | |
1215 | } | |
1216 | ||
83f7eb9c GOC |
1217 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1218 | { | |
cfc1b9a6 | 1219 | pr_debug("Boot done.\n"); |
83f7eb9c GOC |
1220 | |
1221 | impress_friends(); | |
1222 | smp_checks(); | |
1223 | #ifdef CONFIG_X86_IO_APIC | |
1224 | setup_ioapic_dest(); | |
1225 | #endif | |
1226 | check_nmi_watchdog(); | |
83f7eb9c GOC |
1227 | } |
1228 | ||
68a1c3f8 | 1229 | #ifdef CONFIG_HOTPLUG_CPU |
2cd9fb71 | 1230 | |
a4928cff | 1231 | static void remove_siblinginfo(int cpu) |
768d9505 GC |
1232 | { |
1233 | int sibling; | |
1234 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1235 | ||
334ef7a7 | 1236 | for_each_cpu_mask_nr(sibling, per_cpu(cpu_core_map, cpu)) { |
768d9505 GC |
1237 | cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); |
1238 | /*/ | |
1239 | * last thread sibling in this cpu core going down | |
1240 | */ | |
1241 | if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) | |
1242 | cpu_data(sibling).booted_cores--; | |
1243 | } | |
1244 | ||
334ef7a7 | 1245 | for_each_cpu_mask_nr(sibling, per_cpu(cpu_sibling_map, cpu)) |
768d9505 GC |
1246 | cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); |
1247 | cpus_clear(per_cpu(cpu_sibling_map, cpu)); | |
1248 | cpus_clear(per_cpu(cpu_core_map, cpu)); | |
1249 | c->phys_proc_id = 0; | |
1250 | c->cpu_core_id = 0; | |
1251 | cpu_clear(cpu, cpu_sibling_setup_map); | |
1252 | } | |
68a1c3f8 | 1253 | |
c5562fae | 1254 | static int additional_cpus __initdata = -1; |
68a1c3f8 GC |
1255 | |
1256 | static __init int setup_additional_cpus(char *s) | |
1257 | { | |
1258 | return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL; | |
1259 | } | |
1260 | early_param("additional_cpus", setup_additional_cpus); | |
1261 | ||
1262 | /* | |
1263 | * cpu_possible_map should be static, it cannot change as cpu's | |
1264 | * are onlined, or offlined. The reason is per-cpu data-structures | |
1265 | * are allocated by some modules at init time, and dont expect to | |
1266 | * do this dynamically on cpu arrival/departure. | |
1267 | * cpu_present_map on the other hand can change dynamically. | |
1268 | * In case when cpu_hotplug is not compiled, then we resort to current | |
1269 | * behaviour, which is cpu_possible == cpu_present. | |
1270 | * - Ashok Raj | |
1271 | * | |
1272 | * Three ways to find out the number of additional hotplug CPUs: | |
1273 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
1274 | * - The user can overwrite it with additional_cpus=NUM | |
1275 | * - Otherwise don't reserve additional CPUs. | |
1276 | * We do this because additional CPUs waste a lot of memory. | |
1277 | * -AK | |
1278 | */ | |
1279 | __init void prefill_possible_map(void) | |
1280 | { | |
1281 | int i; | |
1282 | int possible; | |
1283 | ||
329513a3 YL |
1284 | /* no processor from mptable or madt */ |
1285 | if (!num_processors) | |
1286 | num_processors = 1; | |
1287 | ||
1288 | #ifdef CONFIG_HOTPLUG_CPU | |
68a1c3f8 GC |
1289 | if (additional_cpus == -1) { |
1290 | if (disabled_cpus > 0) | |
1291 | additional_cpus = disabled_cpus; | |
1292 | else | |
1293 | additional_cpus = 0; | |
1294 | } | |
329513a3 YL |
1295 | #else |
1296 | additional_cpus = 0; | |
1297 | #endif | |
68a1c3f8 GC |
1298 | possible = num_processors + additional_cpus; |
1299 | if (possible > NR_CPUS) | |
1300 | possible = NR_CPUS; | |
1301 | ||
1302 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | |
1303 | possible, max_t(int, possible - num_processors, 0)); | |
1304 | ||
1305 | for (i = 0; i < possible; i++) | |
1306 | cpu_set(i, cpu_possible_map); | |
3461b0af MT |
1307 | |
1308 | nr_cpu_ids = possible; | |
68a1c3f8 | 1309 | } |
69c18c15 GC |
1310 | |
1311 | static void __ref remove_cpu_from_maps(int cpu) | |
1312 | { | |
1313 | cpu_clear(cpu, cpu_online_map); | |
69c18c15 GC |
1314 | cpu_clear(cpu, cpu_callout_map); |
1315 | cpu_clear(cpu, cpu_callin_map); | |
1316 | /* was set by cpu_init() */ | |
29cbeb0e | 1317 | cpu_clear(cpu, cpu_initialized); |
23ca4bba | 1318 | numa_remove_cpu(cpu); |
69c18c15 GC |
1319 | } |
1320 | ||
1321 | int __cpu_disable(void) | |
1322 | { | |
1323 | int cpu = smp_processor_id(); | |
1324 | ||
1325 | /* | |
1326 | * Perhaps use cpufreq to drop frequency, but that could go | |
1327 | * into generic code. | |
1328 | * | |
1329 | * We won't take down the boot processor on i386 due to some | |
1330 | * interrupts only being able to be serviced by the BSP. | |
1331 | * Especially so if we're not using an IOAPIC -zwane | |
1332 | */ | |
1333 | if (cpu == 0) | |
1334 | return -EBUSY; | |
1335 | ||
1336 | if (nmi_watchdog == NMI_LOCAL_APIC) | |
1337 | stop_apic_nmi_watchdog(NULL); | |
1338 | clear_local_APIC(); | |
1339 | ||
1340 | /* | |
1341 | * HACK: | |
1342 | * Allow any queued timer interrupts to get serviced | |
1343 | * This is only a temporary solution until we cleanup | |
1344 | * fixup_irqs as we do for IA64. | |
1345 | */ | |
1346 | local_irq_enable(); | |
1347 | mdelay(1); | |
1348 | ||
1349 | local_irq_disable(); | |
1350 | remove_siblinginfo(cpu); | |
1351 | ||
1352 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1353 | lock_vector_lock(); |
69c18c15 | 1354 | remove_cpu_from_maps(cpu); |
d388e5fd | 1355 | unlock_vector_lock(); |
69c18c15 GC |
1356 | fixup_irqs(cpu_online_map); |
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | void __cpu_die(unsigned int cpu) | |
1361 | { | |
1362 | /* We don't do anything here: idle task is faking death itself. */ | |
1363 | unsigned int i; | |
1364 | ||
1365 | for (i = 0; i < 10; i++) { | |
1366 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1367 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
1368 | printk(KERN_INFO "CPU %d is now offline\n", cpu); | |
1369 | if (1 == num_online_cpus()) | |
1370 | alternatives_smp_switch(0); | |
1371 | return; | |
1372 | } | |
1373 | msleep(100); | |
1374 | } | |
1375 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); | |
1376 | } | |
1377 | #else /* ... !CONFIG_HOTPLUG_CPU */ | |
1378 | int __cpu_disable(void) | |
1379 | { | |
1380 | return -ENOSYS; | |
1381 | } | |
1382 | ||
1383 | void __cpu_die(unsigned int cpu) | |
1384 | { | |
1385 | /* We said "no" in __cpu_disable */ | |
1386 | BUG(); | |
1387 | } | |
68a1c3f8 | 1388 | #endif |