Commit | Line | Data |
---|---|---|
c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
a355352b | 46 | #include <linux/module.h> |
70708a18 | 47 | #include <linux/sched.h> |
69c18c15 | 48 | #include <linux/percpu.h> |
91718e8d | 49 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
50 | #include <linux/err.h> |
51 | #include <linux/nmi.h> | |
69575d38 | 52 | #include <linux/tboot.h> |
35f720c5 | 53 | #include <linux/stackprotector.h> |
5a0e3ad6 | 54 | #include <linux/gfp.h> |
1a022e3f | 55 | #include <linux/cpuidle.h> |
69c18c15 | 56 | |
8aef135c | 57 | #include <asm/acpi.h> |
cb3c8b90 | 58 | #include <asm/desc.h> |
69c18c15 GC |
59 | #include <asm/nmi.h> |
60 | #include <asm/irq.h> | |
07bbc16a | 61 | #include <asm/idle.h> |
48927bbb | 62 | #include <asm/realmode.h> |
69c18c15 GC |
63 | #include <asm/cpu.h> |
64 | #include <asm/numa.h> | |
cb3c8b90 GOC |
65 | #include <asm/pgtable.h> |
66 | #include <asm/tlbflush.h> | |
67 | #include <asm/mtrr.h> | |
ea530692 | 68 | #include <asm/mwait.h> |
7b6aa335 | 69 | #include <asm/apic.h> |
7167d08e | 70 | #include <asm/io_apic.h> |
78f7f1e5 | 71 | #include <asm/fpu/internal.h> |
569712b2 | 72 | #include <asm/setup.h> |
bdbcdd48 | 73 | #include <asm/uv/uv.h> |
cb3c8b90 | 74 | #include <linux/mc146818rtc.h> |
b81bb373 | 75 | #include <asm/i8259.h> |
48927bbb | 76 | #include <asm/realmode.h> |
646e29a1 | 77 | #include <asm/misc.h> |
48927bbb | 78 | |
a355352b GC |
79 | /* Number of siblings per CPU package */ |
80 | int smp_num_siblings = 1; | |
81 | EXPORT_SYMBOL(smp_num_siblings); | |
82 | ||
83 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 84 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 85 | |
a355352b | 86 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 87 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
88 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
89 | ||
90 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
93 | ||
0816b0f0 | 94 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 95 | |
a355352b | 96 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 97 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 98 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 99 | |
1f12e32f TG |
100 | /* Logical package management. We might want to allocate that dynamically */ |
101 | static int *physical_to_logical_pkg __read_mostly; | |
102 | static unsigned long *physical_package_map __read_mostly;; | |
103 | static unsigned long *logical_package_map __read_mostly; | |
104 | static unsigned int max_physical_pkg_id __read_mostly; | |
105 | unsigned int __max_logical_packages __read_mostly; | |
106 | EXPORT_SYMBOL(__max_logical_packages); | |
107 | ||
f77aa308 TG |
108 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
109 | { | |
110 | unsigned long flags; | |
111 | ||
112 | spin_lock_irqsave(&rtc_lock, flags); | |
113 | CMOS_WRITE(0xa, 0xf); | |
114 | spin_unlock_irqrestore(&rtc_lock, flags); | |
115 | local_flush_tlb(); | |
116 | pr_debug("1.\n"); | |
117 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = | |
118 | start_eip >> 4; | |
119 | pr_debug("2.\n"); | |
120 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = | |
121 | start_eip & 0xf; | |
122 | pr_debug("3.\n"); | |
123 | } | |
124 | ||
125 | static inline void smpboot_restore_warm_reset_vector(void) | |
126 | { | |
127 | unsigned long flags; | |
128 | ||
129 | /* | |
130 | * Install writable page 0 entry to set BIOS data area. | |
131 | */ | |
132 | local_flush_tlb(); | |
133 | ||
134 | /* | |
135 | * Paranoid: Set warm reset code and vector here back | |
136 | * to default values. | |
137 | */ | |
138 | spin_lock_irqsave(&rtc_lock, flags); | |
139 | CMOS_WRITE(0, 0xf); | |
140 | spin_unlock_irqrestore(&rtc_lock, flags); | |
141 | ||
142 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
143 | } | |
144 | ||
cb3c8b90 | 145 | /* |
30106c17 FY |
146 | * Report back to the Boot Processor during boot time or to the caller processor |
147 | * during CPU online. | |
cb3c8b90 | 148 | */ |
148f9bb8 | 149 | static void smp_callin(void) |
cb3c8b90 GOC |
150 | { |
151 | int cpuid, phys_id; | |
cb3c8b90 GOC |
152 | |
153 | /* | |
154 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
155 | * cpu_callout_mask guarantees we don't get here before |
156 | * an INIT_deassert IPI reaches our local APIC, so it is | |
157 | * now safe to touch our local APIC. | |
cb3c8b90 | 158 | */ |
e1c467e6 | 159 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
160 | |
161 | /* | |
162 | * (This works even if the APIC is not enabled.) | |
163 | */ | |
4c9961d5 | 164 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
165 | |
166 | /* | |
167 | * the boot CPU has finished the init stage and is spinning | |
168 | * on callin_map until we finish. We are free to set up this | |
169 | * CPU, first the APIC. (this is probably redundant on most | |
170 | * boards) | |
171 | */ | |
05f7e46d | 172 | apic_ap_setup(); |
cb3c8b90 | 173 | |
b565201c JS |
174 | /* |
175 | * Save our processor parameters. Note: this information | |
176 | * is needed for clock calibration. | |
177 | */ | |
178 | smp_store_cpu_info(cpuid); | |
179 | ||
cb3c8b90 GOC |
180 | /* |
181 | * Get our bogomips. | |
b565201c JS |
182 | * Update loops_per_jiffy in cpu_data. Previous call to |
183 | * smp_store_cpu_info() stored a value that is close but not as | |
184 | * accurate as the value just calculated. | |
cb3c8b90 | 185 | */ |
cb3c8b90 | 186 | calibrate_delay(); |
b565201c | 187 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 188 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 189 | |
5ef428c4 AK |
190 | /* |
191 | * This must be done before setting cpu_online_mask | |
192 | * or calling notify_cpu_starting. | |
193 | */ | |
194 | set_cpu_sibling_map(raw_smp_processor_id()); | |
195 | wmb(); | |
196 | ||
85257024 PZ |
197 | notify_cpu_starting(cpuid); |
198 | ||
cb3c8b90 GOC |
199 | /* |
200 | * Allow the master to continue. | |
201 | */ | |
c2d1cec1 | 202 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
203 | } |
204 | ||
e1c467e6 FY |
205 | static int cpu0_logical_apicid; |
206 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
207 | /* |
208 | * Activate a secondary processor. | |
209 | */ | |
148f9bb8 | 210 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
211 | { |
212 | /* | |
213 | * Don't put *anything* before cpu_init(), SMP booting is too | |
214 | * fragile that we want to limit the things done here to the | |
215 | * most necessary things. | |
216 | */ | |
b40827fa | 217 | cpu_init(); |
df156f90 | 218 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
219 | preempt_disable(); |
220 | smp_callin(); | |
fd89a137 | 221 | |
e1c467e6 FY |
222 | enable_start_cpu0 = 0; |
223 | ||
fd89a137 | 224 | #ifdef CONFIG_X86_32 |
b40827fa | 225 | /* switch away from the initial page table */ |
fd89a137 JR |
226 | load_cr3(swapper_pg_dir); |
227 | __flush_tlb_all(); | |
228 | #endif | |
229 | ||
bbc2ff6a GOC |
230 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
231 | barrier(); | |
232 | /* | |
233 | * Check TSC synchronization with the BP: | |
234 | */ | |
235 | check_tsc_sync_target(); | |
236 | ||
bbc2ff6a | 237 | /* |
5a3f75e3 TG |
238 | * Lock vector_lock and initialize the vectors on this cpu |
239 | * before setting the cpu online. We must set it online with | |
240 | * vector_lock held to prevent a concurrent setup/teardown | |
241 | * from seeing a half valid vector space. | |
bbc2ff6a | 242 | */ |
d388e5fd | 243 | lock_vector_lock(); |
5a3f75e3 | 244 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 245 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 246 | unlock_vector_lock(); |
2a442c9c | 247 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 248 | x86_platform.nmi_init(); |
bbc2ff6a | 249 | |
0cefa5b9 MS |
250 | /* enable local interrupts */ |
251 | local_irq_enable(); | |
252 | ||
35f720c5 JP |
253 | /* to prevent fake stack check failure in clock setup */ |
254 | boot_init_stack_canary(); | |
0cefa5b9 | 255 | |
736decac | 256 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
257 | |
258 | wmb(); | |
fc6d73d6 | 259 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
260 | } |
261 | ||
1f12e32f TG |
262 | int topology_update_package_map(unsigned int apicid, unsigned int cpu) |
263 | { | |
264 | unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits; | |
265 | ||
266 | /* Called from early boot ? */ | |
267 | if (!physical_package_map) | |
268 | return 0; | |
269 | ||
270 | if (pkg >= max_physical_pkg_id) | |
271 | return -EINVAL; | |
272 | ||
273 | /* Set the logical package id */ | |
274 | if (test_and_set_bit(pkg, physical_package_map)) | |
275 | goto found; | |
276 | ||
1f12e32f TG |
277 | new = find_first_zero_bit(logical_package_map, __max_logical_packages); |
278 | if (new >= __max_logical_packages) { | |
279 | physical_to_logical_pkg[pkg] = -1; | |
280 | pr_warn("APIC(%x) Package %u exceeds logical package map\n", | |
281 | apicid, pkg); | |
282 | return -ENOSPC; | |
283 | } | |
284 | set_bit(new, logical_package_map); | |
285 | pr_info("APIC(%x) Converting physical %u to logical package %u\n", | |
286 | apicid, pkg, new); | |
287 | physical_to_logical_pkg[pkg] = new; | |
288 | ||
289 | found: | |
290 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; | |
291 | return 0; | |
292 | } | |
293 | ||
294 | /** | |
295 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
296 | * | |
297 | * Returns logical package id or -1 if not found | |
298 | */ | |
299 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
300 | { | |
301 | if (phys_pkg >= max_physical_pkg_id) | |
302 | return -1; | |
303 | return physical_to_logical_pkg[phys_pkg]; | |
304 | } | |
305 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
306 | ||
307 | static void __init smp_init_package_map(void) | |
308 | { | |
309 | unsigned int ncpus, cpu; | |
310 | size_t size; | |
311 | ||
312 | /* | |
313 | * Today neither Intel nor AMD support heterogenous systems. That | |
314 | * might change in the future.... | |
63d1e995 PZ |
315 | * |
316 | * While ideally we'd want '* smp_num_siblings' in the below @ncpus | |
317 | * computation, this won't actually work since some Intel BIOSes | |
318 | * report inconsistent HT data when they disable HT. | |
319 | * | |
320 | * In particular, they reduce the APIC-IDs to only include the cores, | |
321 | * but leave the CPUID topology to say there are (2) siblings. | |
322 | * This means we don't know how many threads there will be until | |
323 | * after the APIC enumeration. | |
324 | * | |
325 | * By not including this we'll sometimes over-estimate the number of | |
326 | * logical packages by the amount of !present siblings, but this is | |
327 | * still better than MAX_LOCAL_APIC. | |
1f12e32f | 328 | */ |
63d1e995 | 329 | ncpus = boot_cpu_data.x86_max_cores; |
1f12e32f TG |
330 | __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); |
331 | ||
332 | /* | |
333 | * Possibly larger than what we need as the number of apic ids per | |
334 | * package can be smaller than the actual used apic ids. | |
335 | */ | |
336 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); | |
337 | size = max_physical_pkg_id * sizeof(unsigned int); | |
338 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); | |
339 | memset(physical_to_logical_pkg, 0xff, size); | |
340 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); | |
341 | physical_package_map = kzalloc(size, GFP_KERNEL); | |
342 | size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long); | |
343 | logical_package_map = kzalloc(size, GFP_KERNEL); | |
344 | ||
345 | pr_info("Max logical packages: %u\n", __max_logical_packages); | |
346 | ||
347 | for_each_present_cpu(cpu) { | |
348 | unsigned int apicid = apic->cpu_present_to_apicid(cpu); | |
349 | ||
350 | if (apicid == BAD_APICID || !apic->apic_id_valid(apicid)) | |
351 | continue; | |
352 | if (!topology_update_package_map(apicid, cpu)) | |
353 | continue; | |
354 | pr_warn("CPU %u APICId %x disabled\n", cpu, apicid); | |
355 | per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID; | |
356 | set_cpu_possible(cpu, false); | |
357 | set_cpu_present(cpu, false); | |
358 | } | |
359 | } | |
360 | ||
30106c17 FY |
361 | void __init smp_store_boot_cpu_info(void) |
362 | { | |
363 | int id = 0; /* CPU 0 */ | |
364 | struct cpuinfo_x86 *c = &cpu_data(id); | |
365 | ||
366 | *c = boot_cpu_data; | |
367 | c->cpu_index = id; | |
1f12e32f | 368 | smp_init_package_map(); |
30106c17 FY |
369 | } |
370 | ||
1d89a7f0 GOC |
371 | /* |
372 | * The bootstrap kernel entry code has set these up. Save them for | |
373 | * a given CPU | |
374 | */ | |
148f9bb8 | 375 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
376 | { |
377 | struct cpuinfo_x86 *c = &cpu_data(id); | |
378 | ||
b3d7336d | 379 | *c = boot_cpu_data; |
1d89a7f0 | 380 | c->cpu_index = id; |
30106c17 FY |
381 | /* |
382 | * During boot time, CPU0 has this setup already. Save the info when | |
383 | * bringing up AP or offlined CPU0. | |
384 | */ | |
385 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
386 | } |
387 | ||
cebf15eb DH |
388 | static bool |
389 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
390 | { | |
391 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
392 | ||
393 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
394 | } | |
395 | ||
148f9bb8 | 396 | static bool |
316ad248 | 397 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 398 | { |
316ad248 PZ |
399 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
400 | ||
cebf15eb | 401 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
402 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
403 | "[node: %d != %d]. Ignoring dependency.\n", | |
404 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
405 | } | |
406 | ||
7d79a7bd | 407 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 408 | do { \ |
7d79a7bd BG |
409 | cpumask_set_cpu((c1), mfunc(c2)); \ |
410 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
411 | } while (0) |
412 | ||
148f9bb8 | 413 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 414 | { |
362f924b | 415 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
416 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
417 | ||
418 | if (c->phys_proc_id == o->phys_proc_id && | |
419 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && | |
420 | c->compute_unit_id == o->compute_unit_id) | |
421 | return topology_sane(c, o, "smt"); | |
422 | ||
423 | } else if (c->phys_proc_id == o->phys_proc_id && | |
424 | c->cpu_core_id == o->cpu_core_id) { | |
425 | return topology_sane(c, o, "smt"); | |
426 | } | |
427 | ||
428 | return false; | |
429 | } | |
430 | ||
148f9bb8 | 431 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
432 | { |
433 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
434 | ||
435 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
436 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
437 | return topology_sane(c, o, "llc"); | |
438 | ||
439 | return false; | |
d4fbe4f0 AH |
440 | } |
441 | ||
cebf15eb DH |
442 | /* |
443 | * Unlike the other levels, we do not enforce keeping a | |
444 | * multicore group inside a NUMA node. If this happens, we will | |
445 | * discard the MC level of the topology later. | |
446 | */ | |
447 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 448 | { |
cebf15eb DH |
449 | if (c->phys_proc_id == o->phys_proc_id) |
450 | return true; | |
316ad248 PZ |
451 | return false; |
452 | } | |
1d89a7f0 | 453 | |
cebf15eb DH |
454 | static struct sched_domain_topology_level numa_inside_package_topology[] = { |
455 | #ifdef CONFIG_SCHED_SMT | |
456 | { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, | |
457 | #endif | |
458 | #ifdef CONFIG_SCHED_MC | |
459 | { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, | |
460 | #endif | |
461 | { NULL, }, | |
462 | }; | |
463 | /* | |
464 | * set_sched_topology() sets the topology internal to a CPU. The | |
465 | * NUMA topologies are layered on top of it to build the full | |
466 | * system topology. | |
467 | * | |
468 | * If NUMA nodes are observed to occur within a CPU package, this | |
469 | * function should be called. It forces the sched domain code to | |
470 | * only use the SMT level for the CPU portion of the topology. | |
471 | * This essentially falls back to relying on NUMA information | |
472 | * from the SRAT table to describe the entire system topology | |
473 | * (except for hyperthreads). | |
474 | */ | |
475 | static void primarily_use_numa_for_topology(void) | |
476 | { | |
477 | set_sched_topology(numa_inside_package_topology); | |
478 | } | |
479 | ||
148f9bb8 | 480 | void set_cpu_sibling_map(int cpu) |
768d9505 | 481 | { |
316ad248 | 482 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 483 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 484 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 PZ |
485 | struct cpuinfo_x86 *o; |
486 | int i; | |
768d9505 | 487 | |
c2d1cec1 | 488 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 489 | |
b0bc225d | 490 | if (!has_mp) { |
7d79a7bd | 491 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 492 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 493 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
494 | c->booted_cores = 1; |
495 | return; | |
496 | } | |
497 | ||
c2d1cec1 | 498 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
499 | o = &cpu_data(i); |
500 | ||
501 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 502 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 503 | |
b0bc225d | 504 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 505 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 506 | |
ceb1cbac KB |
507 | } |
508 | ||
509 | /* | |
510 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 511 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
512 | */ |
513 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
514 | o = &cpu_data(i); | |
515 | ||
cebf15eb | 516 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 517 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 518 | |
768d9505 GC |
519 | /* |
520 | * Does this new cpu bringup a new core? | |
521 | */ | |
7d79a7bd BG |
522 | if (cpumask_weight( |
523 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
524 | /* |
525 | * for each core in package, increment | |
526 | * the booted_cores for this new cpu | |
527 | */ | |
7d79a7bd BG |
528 | if (cpumask_first( |
529 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
530 | c->booted_cores++; |
531 | /* | |
532 | * increment the core count for all | |
533 | * the other cpus in this package | |
534 | */ | |
535 | if (i != cpu) | |
536 | cpu_data(i).booted_cores++; | |
537 | } else if (i != cpu && !c->booted_cores) | |
538 | c->booted_cores = cpu_data(i).booted_cores; | |
539 | } | |
728e5653 | 540 | if (match_die(c, o) && !topology_same_node(c, o)) |
cebf15eb | 541 | primarily_use_numa_for_topology(); |
768d9505 GC |
542 | } |
543 | } | |
544 | ||
70708a18 | 545 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 546 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 547 | { |
9f646389 | 548 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
549 | } |
550 | ||
a4928cff | 551 | static void impress_friends(void) |
904541e2 GOC |
552 | { |
553 | int cpu; | |
554 | unsigned long bogosum = 0; | |
555 | /* | |
556 | * Allow the user to impress friends. | |
557 | */ | |
c767a54b | 558 | pr_debug("Before bogomips\n"); |
904541e2 | 559 | for_each_possible_cpu(cpu) |
c2d1cec1 | 560 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 561 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 562 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 563 | num_online_cpus(), |
904541e2 GOC |
564 | bogosum/(500000/HZ), |
565 | (bogosum/(5000/HZ))%100); | |
566 | ||
c767a54b | 567 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
568 | } |
569 | ||
569712b2 | 570 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
571 | { |
572 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 573 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
574 | int timeout; |
575 | u32 status; | |
576 | ||
c767a54b | 577 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
578 | |
579 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 580 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
581 | |
582 | /* | |
583 | * Wait for idle. | |
584 | */ | |
585 | status = safe_apic_wait_icr_idle(); | |
586 | if (status) | |
c767a54b | 587 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 588 | |
1b374e4d | 589 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
590 | |
591 | timeout = 0; | |
592 | do { | |
593 | udelay(100); | |
594 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
595 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
596 | ||
597 | switch (status) { | |
598 | case APIC_ICR_RR_VALID: | |
599 | status = apic_read(APIC_RRR); | |
c767a54b | 600 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
601 | break; |
602 | default: | |
c767a54b | 603 | pr_cont("failed\n"); |
cb3c8b90 GOC |
604 | } |
605 | } | |
606 | } | |
607 | ||
d68921f9 LB |
608 | /* |
609 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
610 | * that there should be a 10ms delay between the BSP asserting INIT | |
611 | * and de-asserting INIT, when starting a remote processor. | |
612 | * But that slows boot and resume on modern processors, which include | |
613 | * many cores and don't require that delay. | |
614 | * | |
615 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 616 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
617 | */ |
618 | #define UDELAY_10MS_DEFAULT 10000 | |
619 | ||
656279a1 | 620 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
621 | |
622 | static int __init cpu_init_udelay(char *str) | |
623 | { | |
624 | get_option(&str, &init_udelay); | |
625 | ||
626 | return 0; | |
627 | } | |
628 | early_param("cpu_init_udelay", cpu_init_udelay); | |
629 | ||
1a744cb3 LB |
630 | static void __init smp_quirk_init_udelay(void) |
631 | { | |
632 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 633 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
634 | return; |
635 | ||
636 | /* if modern processor, use no delay */ | |
637 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 638 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 639 | init_udelay = 0; |
656279a1 LB |
640 | return; |
641 | } | |
f1ccd249 LB |
642 | /* else, use legacy delay */ |
643 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
644 | } |
645 | ||
cb3c8b90 GOC |
646 | /* |
647 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
648 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
649 | * won't ... remember to clear down the APIC, etc later. | |
650 | */ | |
148f9bb8 | 651 | int |
e1c467e6 | 652 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
653 | { |
654 | unsigned long send_status, accept_status = 0; | |
655 | int maxlvt; | |
656 | ||
657 | /* Target chip */ | |
cb3c8b90 GOC |
658 | /* Boot on the stack */ |
659 | /* Kick the second */ | |
e1c467e6 | 660 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 661 | |
cfc1b9a6 | 662 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
663 | send_status = safe_apic_wait_icr_idle(); |
664 | ||
665 | /* | |
666 | * Give the other CPU some time to accept the IPI. | |
667 | */ | |
668 | udelay(200); | |
569712b2 | 669 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
670 | maxlvt = lapic_get_maxlvt(); |
671 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
672 | apic_write(APIC_ESR, 0); | |
673 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
674 | } | |
c767a54b | 675 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
676 | |
677 | if (send_status) | |
c767a54b | 678 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 679 | if (accept_status) |
c767a54b | 680 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
681 | |
682 | return (send_status | accept_status); | |
683 | } | |
cb3c8b90 | 684 | |
148f9bb8 | 685 | static int |
569712b2 | 686 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 687 | { |
f5d6a52f | 688 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
689 | int maxlvt, num_starts, j; |
690 | ||
593f4a78 MR |
691 | maxlvt = lapic_get_maxlvt(); |
692 | ||
cb3c8b90 GOC |
693 | /* |
694 | * Be paranoid about clearing APIC errors. | |
695 | */ | |
696 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
697 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
698 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
699 | apic_read(APIC_ESR); |
700 | } | |
701 | ||
c767a54b | 702 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
703 | |
704 | /* | |
705 | * Turn INIT on target chip | |
706 | */ | |
cb3c8b90 GOC |
707 | /* |
708 | * Send IPI | |
709 | */ | |
1b374e4d SS |
710 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
711 | phys_apicid); | |
cb3c8b90 | 712 | |
cfc1b9a6 | 713 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
714 | send_status = safe_apic_wait_icr_idle(); |
715 | ||
7cb68598 | 716 | udelay(init_udelay); |
cb3c8b90 | 717 | |
c767a54b | 718 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
719 | |
720 | /* Target chip */ | |
cb3c8b90 | 721 | /* Send IPI */ |
1b374e4d | 722 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 723 | |
cfc1b9a6 | 724 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
725 | send_status = safe_apic_wait_icr_idle(); |
726 | ||
727 | mb(); | |
cb3c8b90 GOC |
728 | |
729 | /* | |
730 | * Should we send STARTUP IPIs ? | |
731 | * | |
732 | * Determine this based on the APIC version. | |
733 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
734 | */ | |
735 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
736 | num_starts = 2; | |
737 | else | |
738 | num_starts = 0; | |
739 | ||
cb3c8b90 GOC |
740 | /* |
741 | * Run STARTUP IPI loop. | |
742 | */ | |
c767a54b | 743 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 744 | |
cb3c8b90 | 745 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 746 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
747 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
748 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 749 | apic_read(APIC_ESR); |
c767a54b | 750 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
751 | |
752 | /* | |
753 | * STARTUP IPI | |
754 | */ | |
755 | ||
756 | /* Target chip */ | |
cb3c8b90 GOC |
757 | /* Boot on the stack */ |
758 | /* Kick the second */ | |
1b374e4d SS |
759 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
760 | phys_apicid); | |
cb3c8b90 GOC |
761 | |
762 | /* | |
763 | * Give the other CPU some time to accept the IPI. | |
764 | */ | |
fcafddec LB |
765 | if (init_udelay == 0) |
766 | udelay(10); | |
767 | else | |
a9bcaa02 | 768 | udelay(300); |
cb3c8b90 | 769 | |
c767a54b | 770 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 771 | |
cfc1b9a6 | 772 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
773 | send_status = safe_apic_wait_icr_idle(); |
774 | ||
775 | /* | |
776 | * Give the other CPU some time to accept the IPI. | |
777 | */ | |
fcafddec LB |
778 | if (init_udelay == 0) |
779 | udelay(10); | |
780 | else | |
a9bcaa02 | 781 | udelay(200); |
cb3c8b90 | 782 | |
593f4a78 | 783 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 784 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
785 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
786 | if (send_status || accept_status) | |
787 | break; | |
788 | } | |
c767a54b | 789 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
790 | |
791 | if (send_status) | |
c767a54b | 792 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 793 | if (accept_status) |
c767a54b | 794 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
795 | |
796 | return (send_status | accept_status); | |
797 | } | |
cb3c8b90 | 798 | |
a17bce4d BP |
799 | void smp_announce(void) |
800 | { | |
801 | int num_nodes = num_online_nodes(); | |
802 | ||
803 | printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", | |
804 | num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); | |
805 | } | |
806 | ||
2eaad1fd | 807 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 808 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
809 | { |
810 | static int current_node = -1; | |
4adc8b71 | 811 | int node = early_cpu_to_node(cpu); |
a17bce4d | 812 | static int width, node_width; |
646e29a1 BP |
813 | |
814 | if (!width) | |
815 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 816 | |
a17bce4d BP |
817 | if (!node_width) |
818 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
819 | ||
820 | if (cpu == 1) | |
821 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
822 | ||
2eaad1fd MT |
823 | if (system_state == SYSTEM_BOOTING) { |
824 | if (node != current_node) { | |
825 | if (current_node > (-1)) | |
a17bce4d | 826 | pr_cont("\n"); |
2eaad1fd | 827 | current_node = node; |
a17bce4d BP |
828 | |
829 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
830 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 831 | } |
646e29a1 BP |
832 | |
833 | /* Add padding for the BSP */ | |
834 | if (cpu == 1) | |
835 | pr_cont("%*s", width + 1, " "); | |
836 | ||
837 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
838 | ||
2eaad1fd MT |
839 | } else |
840 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
841 | node, cpu, apicid); | |
842 | } | |
843 | ||
e1c467e6 FY |
844 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
845 | { | |
846 | int cpu; | |
847 | ||
848 | cpu = smp_processor_id(); | |
849 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
850 | return NMI_HANDLED; | |
851 | ||
852 | return NMI_DONE; | |
853 | } | |
854 | ||
855 | /* | |
856 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
857 | * | |
858 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
859 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
860 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
861 | * | |
862 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
863 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
864 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
865 | * real platform and request are available. | |
866 | */ | |
148f9bb8 | 867 | static int |
e1c467e6 FY |
868 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
869 | int *cpu0_nmi_registered) | |
870 | { | |
871 | int id; | |
872 | int boot_error; | |
873 | ||
ea7bdc65 JK |
874 | preempt_disable(); |
875 | ||
e1c467e6 FY |
876 | /* |
877 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
878 | */ | |
ea7bdc65 JK |
879 | if (cpu) { |
880 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
881 | goto out; | |
882 | } | |
e1c467e6 FY |
883 | |
884 | /* | |
885 | * Wake up BSP by nmi. | |
886 | * | |
887 | * Register a NMI handler to help wake up CPU0. | |
888 | */ | |
889 | boot_error = register_nmi_handler(NMI_LOCAL, | |
890 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
891 | ||
892 | if (!boot_error) { | |
893 | enable_start_cpu0 = 1; | |
894 | *cpu0_nmi_registered = 1; | |
895 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
896 | id = cpu0_logical_apicid; | |
897 | else | |
898 | id = apicid; | |
899 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
900 | } | |
ea7bdc65 JK |
901 | |
902 | out: | |
903 | preempt_enable(); | |
e1c467e6 FY |
904 | |
905 | return boot_error; | |
906 | } | |
907 | ||
3f85483b BO |
908 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
909 | { | |
910 | /* Just in case we booted with a single CPU. */ | |
911 | alternatives_enable_smp(); | |
912 | ||
913 | per_cpu(current_task, cpu) = idle; | |
914 | ||
915 | #ifdef CONFIG_X86_32 | |
916 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
917 | irq_ctx_init(cpu); | |
918 | per_cpu(cpu_current_top_of_stack, cpu) = | |
919 | (unsigned long)task_stack_page(idle) + THREAD_SIZE; | |
920 | #else | |
921 | clear_tsk_thread_flag(idle, TIF_FORK); | |
922 | initial_gs = per_cpu_offset(cpu); | |
923 | #endif | |
3f85483b BO |
924 | } |
925 | ||
cb3c8b90 GOC |
926 | /* |
927 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
928 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
929 | * Returns zero if CPU booted OK, else error code from |
930 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 931 | */ |
148f9bb8 | 932 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) |
cb3c8b90 | 933 | { |
48927bbb | 934 | volatile u32 *trampoline_status = |
b429dbf6 | 935 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 936 | /* start_ip had better be page-aligned! */ |
f37240f1 | 937 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 938 | |
cb3c8b90 | 939 | unsigned long boot_error = 0; |
e1c467e6 | 940 | int cpu0_nmi_registered = 0; |
ce4b1b16 | 941 | unsigned long timeout; |
cb3c8b90 | 942 | |
7eb43a6d TG |
943 | idle->thread.sp = (unsigned long) (((struct pt_regs *) |
944 | (THREAD_SIZE + task_stack_page(idle))) - 1); | |
cb3c8b90 | 945 | |
a939098a | 946 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 947 | initial_code = (unsigned long)start_secondary; |
7eb43a6d | 948 | stack_start = idle->thread.sp; |
cb3c8b90 | 949 | |
20d5e4a9 ZG |
950 | /* |
951 | * Enable the espfix hack for this CPU | |
952 | */ | |
953 | #ifdef CONFIG_X86_ESPFIX64 | |
954 | init_espfix_ap(cpu); | |
955 | #endif | |
956 | ||
2eaad1fd MT |
957 | /* So we see what's up */ |
958 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
959 | |
960 | /* | |
961 | * This grunge runs the startup process for | |
962 | * the targeted processor. | |
963 | */ | |
964 | ||
34d05591 | 965 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 966 | |
cfc1b9a6 | 967 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 968 | |
34d05591 JS |
969 | smpboot_setup_warm_reset_vector(start_ip); |
970 | /* | |
971 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
972 | */ |
973 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
974 | apic_write(APIC_ESR, 0); | |
975 | apic_read(APIC_ESR); | |
976 | } | |
34d05591 | 977 | } |
cb3c8b90 | 978 | |
ce4b1b16 IM |
979 | /* |
980 | * AP might wait on cpu_callout_mask in cpu_init() with | |
981 | * cpu_initialized_mask set if previous attempt to online | |
982 | * it timed-out. Clear cpu_initialized_mask so that after | |
983 | * INIT/SIPI it could start with a clean state. | |
984 | */ | |
985 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
986 | smp_mb(); | |
987 | ||
cb3c8b90 | 988 | /* |
e1c467e6 FY |
989 | * Wake up a CPU in difference cases: |
990 | * - Use the method in the APIC driver if it's defined | |
991 | * Otherwise, | |
992 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 993 | */ |
1f5bcabf IM |
994 | if (apic->wakeup_secondary_cpu) |
995 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
996 | else | |
e1c467e6 FY |
997 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
998 | &cpu0_nmi_registered); | |
cb3c8b90 GOC |
999 | |
1000 | if (!boot_error) { | |
1001 | /* | |
6e38f1e7 | 1002 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1003 | */ |
ce4b1b16 IM |
1004 | boot_error = -1; |
1005 | timeout = jiffies + 10*HZ; | |
1006 | while (time_before(jiffies, timeout)) { | |
1007 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1008 | /* | |
1009 | * Tell AP to proceed with initialization | |
1010 | */ | |
1011 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1012 | boot_error = 0; | |
1013 | break; | |
1014 | } | |
ce4b1b16 IM |
1015 | schedule(); |
1016 | } | |
1017 | } | |
cb3c8b90 | 1018 | |
ce4b1b16 | 1019 | if (!boot_error) { |
cb3c8b90 | 1020 | /* |
ce4b1b16 | 1021 | * Wait till AP completes initial initialization |
cb3c8b90 | 1022 | */ |
ce4b1b16 | 1023 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1024 | /* |
1025 | * Allow other tasks to run while we wait for the | |
1026 | * AP to come online. This also gives a chance | |
1027 | * for the MTRR work(triggered by the AP coming online) | |
1028 | * to be completed in the stop machine context. | |
1029 | */ | |
1030 | schedule(); | |
cb3c8b90 | 1031 | } |
cb3c8b90 GOC |
1032 | } |
1033 | ||
1034 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1035 | *trampoline_status = 0; |
cb3c8b90 | 1036 | |
02421f98 YL |
1037 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1038 | /* | |
1039 | * Cleanup possible dangling ends... | |
1040 | */ | |
1041 | smpboot_restore_warm_reset_vector(); | |
1042 | } | |
e1c467e6 FY |
1043 | /* |
1044 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1045 | * to avoid impact of possible long unregister time. | |
1046 | */ | |
1047 | if (cpu0_nmi_registered) | |
1048 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1049 | ||
cb3c8b90 GOC |
1050 | return boot_error; |
1051 | } | |
1052 | ||
148f9bb8 | 1053 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1054 | { |
a21769a4 | 1055 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
1056 | unsigned long flags; |
1057 | int err; | |
1058 | ||
1059 | WARN_ON(irqs_disabled()); | |
1060 | ||
cfc1b9a6 | 1061 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1062 | |
30106c17 | 1063 | if (apicid == BAD_APICID || |
c284b42a | 1064 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1065 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1066 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1067 | return -EINVAL; |
1068 | } | |
1069 | ||
1070 | /* | |
1071 | * Already booted CPU? | |
1072 | */ | |
c2d1cec1 | 1073 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1074 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1075 | return -ENOSYS; |
1076 | } | |
1077 | ||
1078 | /* | |
1079 | * Save current MTRR state in case it was changed since early boot | |
1080 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1081 | */ | |
1082 | mtrr_save_state(); | |
1083 | ||
2a442c9c PM |
1084 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1085 | err = cpu_check_up_prepare(cpu); | |
1086 | if (err && err != -EBUSY) | |
1087 | return err; | |
cb3c8b90 | 1088 | |
644c1541 VP |
1089 | /* the FPU context is blank, nobody can own it */ |
1090 | __cpu_disable_lazy_restore(cpu); | |
1091 | ||
3f85483b BO |
1092 | common_cpu_up(cpu, tidle); |
1093 | ||
ce0d3c0a TG |
1094 | /* |
1095 | * We have to walk the irq descriptors to setup the vector | |
1096 | * space for the cpu which comes online. Prevent irq | |
1097 | * alloc/free across the bringup. | |
1098 | */ | |
1099 | irq_lock_sparse(); | |
1100 | ||
7eb43a6d | 1101 | err = do_boot_cpu(apicid, cpu, tidle); |
ce0d3c0a | 1102 | |
61165d7a | 1103 | if (err) { |
ce0d3c0a | 1104 | irq_unlock_sparse(); |
feef1e8e | 1105 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
61165d7a | 1106 | return -EIO; |
cb3c8b90 GOC |
1107 | } |
1108 | ||
1109 | /* | |
1110 | * Check TSC synchronization with the AP (keep irqs disabled | |
1111 | * while doing so): | |
1112 | */ | |
1113 | local_irq_save(flags); | |
1114 | check_tsc_sync_source(cpu); | |
1115 | local_irq_restore(flags); | |
1116 | ||
7c04e64a | 1117 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1118 | cpu_relax(); |
1119 | touch_nmi_watchdog(); | |
1120 | } | |
1121 | ||
ce0d3c0a TG |
1122 | irq_unlock_sparse(); |
1123 | ||
cb3c8b90 GOC |
1124 | return 0; |
1125 | } | |
1126 | ||
7167d08e HK |
1127 | /** |
1128 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1129 | */ | |
1130 | void arch_disable_smp_support(void) | |
1131 | { | |
1132 | disable_ioapic_support(); | |
1133 | } | |
1134 | ||
8aef135c GOC |
1135 | /* |
1136 | * Fall back to non SMP mode after errors. | |
1137 | * | |
1138 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1139 | */ | |
1140 | static __init void disable_smp(void) | |
1141 | { | |
613c25ef TG |
1142 | pr_info("SMP disabled\n"); |
1143 | ||
ef4c59a4 TG |
1144 | disable_ioapic_support(); |
1145 | ||
4f062896 RR |
1146 | init_cpu_present(cpumask_of(0)); |
1147 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1148 | |
8aef135c | 1149 | if (smp_found_config) |
b6df1b8b | 1150 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1151 | else |
b6df1b8b | 1152 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1153 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1154 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1155 | } |
1156 | ||
613c25ef TG |
1157 | enum { |
1158 | SMP_OK, | |
1159 | SMP_NO_CONFIG, | |
1160 | SMP_NO_APIC, | |
1161 | SMP_FORCE_UP, | |
1162 | }; | |
1163 | ||
8aef135c GOC |
1164 | /* |
1165 | * Various sanity checks. | |
1166 | */ | |
1167 | static int __init smp_sanity_check(unsigned max_cpus) | |
1168 | { | |
ac23d4ee | 1169 | preempt_disable(); |
a58f03b0 | 1170 | |
1ff2f20d | 1171 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1172 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1173 | unsigned int cpu; | |
1174 | unsigned nr; | |
1175 | ||
c767a54b JP |
1176 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1177 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1178 | |
1179 | nr = 0; | |
1180 | for_each_present_cpu(cpu) { | |
1181 | if (nr >= 8) | |
c2d1cec1 | 1182 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1183 | nr++; |
1184 | } | |
1185 | ||
1186 | nr = 0; | |
1187 | for_each_possible_cpu(cpu) { | |
1188 | if (nr >= 8) | |
c2d1cec1 | 1189 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1190 | nr++; |
1191 | } | |
1192 | ||
1193 | nr_cpu_ids = 8; | |
1194 | } | |
1195 | #endif | |
1196 | ||
8aef135c | 1197 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1198 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1199 | hard_smp_processor_id()); |
1200 | ||
8aef135c GOC |
1201 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * If we couldn't find an SMP configuration at boot time, | |
1206 | * get out of here now! | |
1207 | */ | |
1208 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1209 | preempt_enable(); |
c767a54b | 1210 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1211 | return SMP_NO_CONFIG; |
8aef135c GOC |
1212 | } |
1213 | ||
1214 | /* | |
1215 | * Should not be necessary because the MP table should list the boot | |
1216 | * CPU too, but we do it for the sake of robustness anyway. | |
1217 | */ | |
a27a6210 | 1218 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1219 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1220 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1221 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1222 | } | |
ac23d4ee | 1223 | preempt_enable(); |
8aef135c GOC |
1224 | |
1225 | /* | |
1226 | * If we couldn't find a local APIC, then get out of here now! | |
1227 | */ | |
1228 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
1229 | !cpu_has_apic) { | |
103428e5 CG |
1230 | if (!disable_apic) { |
1231 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1232 | boot_cpu_physical_apicid); | |
c767a54b | 1233 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1234 | } |
613c25ef | 1235 | return SMP_NO_APIC; |
8aef135c GOC |
1236 | } |
1237 | ||
8aef135c GOC |
1238 | /* |
1239 | * If SMP should be disabled, then really disable it! | |
1240 | */ | |
1241 | if (!max_cpus) { | |
c767a54b | 1242 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1243 | return SMP_FORCE_UP; |
8aef135c GOC |
1244 | } |
1245 | ||
613c25ef | 1246 | return SMP_OK; |
8aef135c GOC |
1247 | } |
1248 | ||
1249 | static void __init smp_cpu_index_default(void) | |
1250 | { | |
1251 | int i; | |
1252 | struct cpuinfo_x86 *c; | |
1253 | ||
7c04e64a | 1254 | for_each_possible_cpu(i) { |
8aef135c GOC |
1255 | c = &cpu_data(i); |
1256 | /* mark all to hotplug */ | |
9628937d | 1257 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1258 | } |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1263 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1264 | */ | |
1265 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1266 | { | |
7ad728f9 RR |
1267 | unsigned int i; |
1268 | ||
8aef135c | 1269 | smp_cpu_index_default(); |
792363d2 | 1270 | |
8aef135c GOC |
1271 | /* |
1272 | * Setup boot CPU information | |
1273 | */ | |
30106c17 | 1274 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1275 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1276 | mb(); | |
bd22a2f1 | 1277 | |
8aef135c | 1278 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1279 | for_each_possible_cpu(i) { |
79f55997 LZ |
1280 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1281 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1282 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1283 | } |
8aef135c GOC |
1284 | set_cpu_sibling_map(0); |
1285 | ||
613c25ef TG |
1286 | switch (smp_sanity_check(max_cpus)) { |
1287 | case SMP_NO_CONFIG: | |
8aef135c | 1288 | disable_smp(); |
613c25ef TG |
1289 | if (APIC_init_uniprocessor()) |
1290 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1291 | return; | |
1292 | case SMP_NO_APIC: | |
1293 | disable_smp(); | |
1294 | return; | |
1295 | case SMP_FORCE_UP: | |
1296 | disable_smp(); | |
374aab33 | 1297 | apic_bsp_setup(false); |
250a1ac6 | 1298 | return; |
613c25ef TG |
1299 | case SMP_OK: |
1300 | break; | |
8aef135c GOC |
1301 | } |
1302 | ||
fa47f7e5 SS |
1303 | default_setup_apic_routing(); |
1304 | ||
4c9961d5 | 1305 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1306 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1307 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1308 | /* Or can we switch back to PIC here? */ |
1309 | } | |
1310 | ||
374aab33 | 1311 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1312 | |
c767a54b | 1313 | pr_info("CPU%d: ", 0); |
8aef135c | 1314 | print_cpu_info(&cpu_data(0)); |
c4bd1fda MS |
1315 | |
1316 | if (is_uv_system()) | |
1317 | uv_system_init(); | |
d0af9eed SS |
1318 | |
1319 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1320 | |
1321 | smp_quirk_init_udelay(); | |
8aef135c | 1322 | } |
d0af9eed SS |
1323 | |
1324 | void arch_enable_nonboot_cpus_begin(void) | |
1325 | { | |
1326 | set_mtrr_aps_delayed_init(); | |
1327 | } | |
1328 | ||
1329 | void arch_enable_nonboot_cpus_end(void) | |
1330 | { | |
1331 | mtrr_aps_init(); | |
1332 | } | |
1333 | ||
a8db8453 GOC |
1334 | /* |
1335 | * Early setup to make printk work. | |
1336 | */ | |
1337 | void __init native_smp_prepare_boot_cpu(void) | |
1338 | { | |
1339 | int me = smp_processor_id(); | |
552be871 | 1340 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1341 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1342 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1343 | cpu_set_state_online(me); |
a8db8453 GOC |
1344 | } |
1345 | ||
83f7eb9c GOC |
1346 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1347 | { | |
c767a54b | 1348 | pr_debug("Boot done\n"); |
83f7eb9c | 1349 | |
99e8b9ca | 1350 | nmi_selftest(); |
83f7eb9c | 1351 | impress_friends(); |
83f7eb9c | 1352 | setup_ioapic_dest(); |
d0af9eed | 1353 | mtrr_aps_init(); |
83f7eb9c GOC |
1354 | } |
1355 | ||
3b11ce7f MT |
1356 | static int __initdata setup_possible_cpus = -1; |
1357 | static int __init _setup_possible_cpus(char *str) | |
1358 | { | |
1359 | get_option(&str, &setup_possible_cpus); | |
1360 | return 0; | |
1361 | } | |
1362 | early_param("possible_cpus", _setup_possible_cpus); | |
1363 | ||
1364 | ||
68a1c3f8 | 1365 | /* |
4f062896 | 1366 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1367 | * are onlined, or offlined. The reason is per-cpu data-structures |
1368 | * are allocated by some modules at init time, and dont expect to | |
1369 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1370 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1371 | * In case when cpu_hotplug is not compiled, then we resort to current |
1372 | * behaviour, which is cpu_possible == cpu_present. | |
1373 | * - Ashok Raj | |
1374 | * | |
1375 | * Three ways to find out the number of additional hotplug CPUs: | |
1376 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1377 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1378 | * - Otherwise don't reserve additional CPUs. |
1379 | * We do this because additional CPUs waste a lot of memory. | |
1380 | * -AK | |
1381 | */ | |
1382 | __init void prefill_possible_map(void) | |
1383 | { | |
cb48bb59 | 1384 | int i, possible; |
68a1c3f8 | 1385 | |
329513a3 YL |
1386 | /* no processor from mptable or madt */ |
1387 | if (!num_processors) | |
1388 | num_processors = 1; | |
1389 | ||
5f2eb550 JB |
1390 | i = setup_max_cpus ?: 1; |
1391 | if (setup_possible_cpus == -1) { | |
1392 | possible = num_processors; | |
1393 | #ifdef CONFIG_HOTPLUG_CPU | |
1394 | if (setup_max_cpus) | |
1395 | possible += disabled_cpus; | |
1396 | #else | |
1397 | if (possible > i) | |
1398 | possible = i; | |
1399 | #endif | |
1400 | } else | |
3b11ce7f MT |
1401 | possible = setup_possible_cpus; |
1402 | ||
730cf272 MT |
1403 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1404 | ||
2b633e3f YL |
1405 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1406 | if (possible > nr_cpu_ids) { | |
c767a54b | 1407 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1408 | possible, nr_cpu_ids); |
1409 | possible = nr_cpu_ids; | |
3b11ce7f | 1410 | } |
68a1c3f8 | 1411 | |
5f2eb550 JB |
1412 | #ifdef CONFIG_HOTPLUG_CPU |
1413 | if (!setup_max_cpus) | |
1414 | #endif | |
1415 | if (possible > i) { | |
c767a54b | 1416 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1417 | possible, setup_max_cpus); |
1418 | possible = i; | |
1419 | } | |
1420 | ||
c767a54b | 1421 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1422 | possible, max_t(int, possible - num_processors, 0)); |
1423 | ||
1424 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1425 | set_cpu_possible(i, true); |
5f2eb550 JB |
1426 | for (; i < NR_CPUS; i++) |
1427 | set_cpu_possible(i, false); | |
3461b0af MT |
1428 | |
1429 | nr_cpu_ids = possible; | |
68a1c3f8 | 1430 | } |
69c18c15 | 1431 | |
14adf855 CE |
1432 | #ifdef CONFIG_HOTPLUG_CPU |
1433 | ||
1434 | static void remove_siblinginfo(int cpu) | |
1435 | { | |
1436 | int sibling; | |
1437 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1438 | ||
7d79a7bd BG |
1439 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1440 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1441 | /*/ |
1442 | * last thread sibling in this cpu core going down | |
1443 | */ | |
7d79a7bd | 1444 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1445 | cpu_data(sibling).booted_cores--; |
1446 | } | |
1447 | ||
7d79a7bd BG |
1448 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1449 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1450 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1451 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1452 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1453 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1454 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1455 | c->phys_proc_id = 0; |
1456 | c->cpu_core_id = 0; | |
c2d1cec1 | 1457 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1458 | } |
1459 | ||
4daa832d | 1460 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1461 | { |
c2d1cec1 MT |
1462 | set_cpu_online(cpu, false); |
1463 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1464 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1465 | /* was set by cpu_init() */ |
c2d1cec1 | 1466 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1467 | numa_remove_cpu(cpu); |
69c18c15 GC |
1468 | } |
1469 | ||
8227dce7 | 1470 | void cpu_disable_common(void) |
69c18c15 GC |
1471 | { |
1472 | int cpu = smp_processor_id(); | |
69c18c15 | 1473 | |
69c18c15 GC |
1474 | remove_siblinginfo(cpu); |
1475 | ||
1476 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1477 | lock_vector_lock(); |
69c18c15 | 1478 | remove_cpu_from_maps(cpu); |
d388e5fd | 1479 | unlock_vector_lock(); |
d7b381bb | 1480 | fixup_irqs(); |
8227dce7 AN |
1481 | } |
1482 | ||
1483 | int native_cpu_disable(void) | |
1484 | { | |
da6139e4 PB |
1485 | int ret; |
1486 | ||
1487 | ret = check_irq_vectors_for_cpu_disable(); | |
1488 | if (ret) | |
1489 | return ret; | |
1490 | ||
8227dce7 | 1491 | clear_local_APIC(); |
8227dce7 | 1492 | cpu_disable_common(); |
2ed53c0d | 1493 | |
69c18c15 GC |
1494 | return 0; |
1495 | } | |
1496 | ||
2a442c9c | 1497 | int common_cpu_die(unsigned int cpu) |
54279552 | 1498 | { |
2a442c9c | 1499 | int ret = 0; |
54279552 | 1500 | |
69c18c15 | 1501 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1502 | |
2ed53c0d | 1503 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1504 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1505 | if (system_state == SYSTEM_RUNNING) |
1506 | pr_info("CPU %u is now offline\n", cpu); | |
1507 | } else { | |
1508 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1509 | ret = -1; |
69c18c15 | 1510 | } |
2a442c9c PM |
1511 | |
1512 | return ret; | |
1513 | } | |
1514 | ||
1515 | void native_cpu_die(unsigned int cpu) | |
1516 | { | |
1517 | common_cpu_die(cpu); | |
69c18c15 | 1518 | } |
a21f5d88 AN |
1519 | |
1520 | void play_dead_common(void) | |
1521 | { | |
1522 | idle_task_exit(); | |
1523 | reset_lazy_tlbstate(); | |
02c68a02 | 1524 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 | 1525 | |
a21f5d88 | 1526 | /* Ack it */ |
2a442c9c | 1527 | (void)cpu_report_death(); |
a21f5d88 AN |
1528 | |
1529 | /* | |
1530 | * With physical CPU hotplug, we should halt the cpu | |
1531 | */ | |
1532 | local_irq_disable(); | |
1533 | } | |
1534 | ||
e1c467e6 FY |
1535 | static bool wakeup_cpu0(void) |
1536 | { | |
1537 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1538 | return true; | |
1539 | ||
1540 | return false; | |
1541 | } | |
1542 | ||
ea530692 PA |
1543 | /* |
1544 | * We need to flush the caches before going to sleep, lest we have | |
1545 | * dirty data in our caches when we come back up. | |
1546 | */ | |
1547 | static inline void mwait_play_dead(void) | |
1548 | { | |
1549 | unsigned int eax, ebx, ecx, edx; | |
1550 | unsigned int highest_cstate = 0; | |
1551 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1552 | void *mwait_ptr; |
576cfb40 | 1553 | int i; |
ea530692 | 1554 | |
69fb3676 | 1555 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1556 | return; |
840d2830 | 1557 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1558 | return; |
7b543a53 | 1559 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1560 | return; |
1561 | ||
1562 | eax = CPUID_MWAIT_LEAF; | |
1563 | ecx = 0; | |
1564 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1565 | ||
1566 | /* | |
1567 | * eax will be 0 if EDX enumeration is not valid. | |
1568 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1569 | */ | |
1570 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1571 | eax = 0; | |
1572 | } else { | |
1573 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1574 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1575 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1576 | highest_cstate = i; | |
1577 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1578 | } | |
1579 | } | |
1580 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1581 | (highest_subcstate - 1); | |
1582 | } | |
1583 | ||
ce5f6824 PA |
1584 | /* |
1585 | * This should be a memory location in a cache line which is | |
1586 | * unlikely to be touched by other processors. The actual | |
1587 | * content is immaterial as it is not actually modified in any way. | |
1588 | */ | |
1589 | mwait_ptr = ¤t_thread_info()->flags; | |
1590 | ||
a68e5c94 PA |
1591 | wbinvd(); |
1592 | ||
ea530692 | 1593 | while (1) { |
ce5f6824 PA |
1594 | /* |
1595 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1596 | * the Xeon 7400 series. It's not clear it is actually | |
1597 | * needed, but it should be harmless in either case. | |
1598 | * The WBINVD is insufficient due to the spurious-wakeup | |
1599 | * case where we return around the loop. | |
1600 | */ | |
7d590cca | 1601 | mb(); |
ce5f6824 | 1602 | clflush(mwait_ptr); |
7d590cca | 1603 | mb(); |
ce5f6824 | 1604 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1605 | mb(); |
1606 | __mwait(eax, 0); | |
e1c467e6 FY |
1607 | /* |
1608 | * If NMI wants to wake up CPU0, start CPU0. | |
1609 | */ | |
1610 | if (wakeup_cpu0()) | |
1611 | start_cpu0(); | |
ea530692 PA |
1612 | } |
1613 | } | |
1614 | ||
1615 | static inline void hlt_play_dead(void) | |
1616 | { | |
7b543a53 | 1617 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1618 | wbinvd(); |
1619 | ||
ea530692 | 1620 | while (1) { |
ea530692 | 1621 | native_halt(); |
e1c467e6 FY |
1622 | /* |
1623 | * If NMI wants to wake up CPU0, start CPU0. | |
1624 | */ | |
1625 | if (wakeup_cpu0()) | |
1626 | start_cpu0(); | |
ea530692 PA |
1627 | } |
1628 | } | |
1629 | ||
a21f5d88 AN |
1630 | void native_play_dead(void) |
1631 | { | |
1632 | play_dead_common(); | |
86886e55 | 1633 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1634 | |
1635 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1636 | if (cpuidle_play_dead()) |
1637 | hlt_play_dead(); | |
a21f5d88 AN |
1638 | } |
1639 | ||
69c18c15 | 1640 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1641 | int native_cpu_disable(void) |
69c18c15 GC |
1642 | { |
1643 | return -ENOSYS; | |
1644 | } | |
1645 | ||
93be71b6 | 1646 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1647 | { |
1648 | /* We said "no" in __cpu_disable */ | |
1649 | BUG(); | |
1650 | } | |
a21f5d88 AN |
1651 | |
1652 | void native_play_dead(void) | |
1653 | { | |
1654 | BUG(); | |
1655 | } | |
1656 | ||
68a1c3f8 | 1657 | #endif |