Commit | Line | Data |
---|---|---|
4cedb334 GOC |
1 | /* |
2 | * x86 SMP booting functions | |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
a355352b | 44 | #include <linux/module.h> |
70708a18 | 45 | #include <linux/sched.h> |
69c18c15 | 46 | #include <linux/percpu.h> |
91718e8d | 47 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
48 | #include <linux/err.h> |
49 | #include <linux/nmi.h> | |
69575d38 | 50 | #include <linux/tboot.h> |
35f720c5 | 51 | #include <linux/stackprotector.h> |
5a0e3ad6 | 52 | #include <linux/gfp.h> |
1a022e3f | 53 | #include <linux/cpuidle.h> |
69c18c15 | 54 | |
8aef135c | 55 | #include <asm/acpi.h> |
cb3c8b90 | 56 | #include <asm/desc.h> |
69c18c15 GC |
57 | #include <asm/nmi.h> |
58 | #include <asm/irq.h> | |
07bbc16a | 59 | #include <asm/idle.h> |
e44b7b75 | 60 | #include <asm/trampoline.h> |
69c18c15 GC |
61 | #include <asm/cpu.h> |
62 | #include <asm/numa.h> | |
cb3c8b90 GOC |
63 | #include <asm/pgtable.h> |
64 | #include <asm/tlbflush.h> | |
65 | #include <asm/mtrr.h> | |
ea530692 | 66 | #include <asm/mwait.h> |
7b6aa335 | 67 | #include <asm/apic.h> |
7167d08e | 68 | #include <asm/io_apic.h> |
569712b2 | 69 | #include <asm/setup.h> |
bdbcdd48 | 70 | #include <asm/uv/uv.h> |
cb3c8b90 | 71 | #include <linux/mc146818rtc.h> |
68a1c3f8 | 72 | |
1164dd00 | 73 | #include <asm/smpboot_hooks.h> |
b81bb373 | 74 | #include <asm/i8259.h> |
cb3c8b90 | 75 | |
a8db8453 GOC |
76 | /* State of each CPU */ |
77 | DEFINE_PER_CPU(int, cpu_state) = { 0 }; | |
78 | ||
cb3c8b90 GOC |
79 | /* Store all idle threads, this can be reused instead of creating |
80 | * a new thread. Also avoids complicated thread destroy functionality | |
81 | * for idle threads. | |
82 | */ | |
83 | #ifdef CONFIG_HOTPLUG_CPU | |
84 | /* | |
85 | * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is | |
86 | * removed after init for !CONFIG_HOTPLUG_CPU. | |
87 | */ | |
88 | static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); | |
89 | #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) | |
90 | #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) | |
d7c53c9e BP |
91 | |
92 | /* | |
93 | * We need this for trampoline_base protection from concurrent accesses when | |
94 | * off- and onlining cores wildly. | |
95 | */ | |
96 | static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); | |
97 | ||
91d88ce2 | 98 | void cpu_hotplug_driver_lock(void) |
d7c53c9e BP |
99 | { |
100 | mutex_lock(&x86_cpu_hotplug_driver_mutex); | |
101 | } | |
102 | ||
91d88ce2 | 103 | void cpu_hotplug_driver_unlock(void) |
d7c53c9e BP |
104 | { |
105 | mutex_unlock(&x86_cpu_hotplug_driver_mutex); | |
106 | } | |
107 | ||
108 | ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } | |
109 | ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } | |
cb3c8b90 | 110 | #else |
f86c9985 | 111 | static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; |
cb3c8b90 GOC |
112 | #define get_idle_for_cpu(x) (idle_thread_array[(x)]) |
113 | #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) | |
114 | #endif | |
f6bc4029 | 115 | |
a355352b GC |
116 | /* Number of siblings per CPU package */ |
117 | int smp_num_siblings = 1; | |
118 | EXPORT_SYMBOL(smp_num_siblings); | |
119 | ||
120 | /* Last level cache ID of each logical CPU */ | |
121 | DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; | |
122 | ||
a355352b | 123 | /* representing HT siblings of each logical CPU */ |
7ad728f9 | 124 | DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
125 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
126 | ||
127 | /* representing HT and core siblings of each logical CPU */ | |
7ad728f9 | 128 | DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); |
a355352b GC |
129 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
130 | ||
b3d7336d YL |
131 | DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); |
132 | ||
a355352b GC |
133 | /* Per CPU bogomips and other parameters */ |
134 | DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); | |
135 | EXPORT_PER_CPU_SYMBOL(cpu_info); | |
768d9505 | 136 | |
2b6163bf | 137 | atomic_t init_deasserted; |
cb3c8b90 | 138 | |
cb3c8b90 GOC |
139 | /* |
140 | * Report back to the Boot Processor. | |
141 | * Running on AP. | |
142 | */ | |
a4928cff | 143 | static void __cpuinit smp_callin(void) |
cb3c8b90 GOC |
144 | { |
145 | int cpuid, phys_id; | |
146 | unsigned long timeout; | |
147 | ||
148 | /* | |
149 | * If waken up by an INIT in an 82489DX configuration | |
150 | * we may get here before an INIT-deassert IPI reaches | |
151 | * our local APIC. We have to wait for the IPI or we'll | |
152 | * lock up on an APIC access. | |
153 | */ | |
a9659366 IM |
154 | if (apic->wait_for_init_deassert) |
155 | apic->wait_for_init_deassert(&init_deasserted); | |
cb3c8b90 GOC |
156 | |
157 | /* | |
158 | * (This works even if the APIC is not enabled.) | |
159 | */ | |
4c9961d5 | 160 | phys_id = read_apic_id(); |
cb3c8b90 | 161 | cpuid = smp_processor_id(); |
c2d1cec1 | 162 | if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { |
cb3c8b90 GOC |
163 | panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, |
164 | phys_id, cpuid); | |
165 | } | |
cfc1b9a6 | 166 | pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); |
cb3c8b90 GOC |
167 | |
168 | /* | |
169 | * STARTUP IPIs are fragile beasts as they might sometimes | |
170 | * trigger some glue motherboard logic. Complete APIC bus | |
171 | * silence for 1 second, this overestimates the time the | |
172 | * boot CPU is spending to send the up to 2 STARTUP IPIs | |
173 | * by a factor of two. This should be enough. | |
174 | */ | |
175 | ||
176 | /* | |
177 | * Waiting 2s total for startup (udelay is not yet working) | |
178 | */ | |
179 | timeout = jiffies + 2*HZ; | |
180 | while (time_before(jiffies, timeout)) { | |
181 | /* | |
182 | * Has the boot CPU finished it's STARTUP sequence? | |
183 | */ | |
c2d1cec1 | 184 | if (cpumask_test_cpu(cpuid, cpu_callout_mask)) |
cb3c8b90 GOC |
185 | break; |
186 | cpu_relax(); | |
187 | } | |
188 | ||
189 | if (!time_before(jiffies, timeout)) { | |
190 | panic("%s: CPU%d started up but did not get a callout!\n", | |
191 | __func__, cpuid); | |
192 | } | |
193 | ||
194 | /* | |
195 | * the boot CPU has finished the init stage and is spinning | |
196 | * on callin_map until we finish. We are free to set up this | |
197 | * CPU, first the APIC. (this is probably redundant on most | |
198 | * boards) | |
199 | */ | |
200 | ||
cfc1b9a6 | 201 | pr_debug("CALLIN, before setup_local_APIC().\n"); |
333344d9 IM |
202 | if (apic->smp_callin_clear_local_apic) |
203 | apic->smp_callin_clear_local_apic(); | |
cb3c8b90 GOC |
204 | setup_local_APIC(); |
205 | end_local_APIC_setup(); | |
cb3c8b90 | 206 | |
9d133e5d SS |
207 | /* |
208 | * Need to setup vector mappings before we enable interrupts. | |
209 | */ | |
36e9e1ea | 210 | setup_vector_irq(smp_processor_id()); |
b565201c JS |
211 | |
212 | /* | |
213 | * Save our processor parameters. Note: this information | |
214 | * is needed for clock calibration. | |
215 | */ | |
216 | smp_store_cpu_info(cpuid); | |
217 | ||
cb3c8b90 GOC |
218 | /* |
219 | * Get our bogomips. | |
b565201c JS |
220 | * Update loops_per_jiffy in cpu_data. Previous call to |
221 | * smp_store_cpu_info() stored a value that is close but not as | |
222 | * accurate as the value just calculated. | |
cb3c8b90 | 223 | */ |
cb3c8b90 | 224 | calibrate_delay(); |
b565201c | 225 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 226 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 227 | |
5ef428c4 AK |
228 | /* |
229 | * This must be done before setting cpu_online_mask | |
230 | * or calling notify_cpu_starting. | |
231 | */ | |
232 | set_cpu_sibling_map(raw_smp_processor_id()); | |
233 | wmb(); | |
234 | ||
85257024 PZ |
235 | notify_cpu_starting(cpuid); |
236 | ||
cb3c8b90 GOC |
237 | /* |
238 | * Allow the master to continue. | |
239 | */ | |
c2d1cec1 | 240 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
241 | } |
242 | ||
bbc2ff6a GOC |
243 | /* |
244 | * Activate a secondary processor. | |
245 | */ | |
0ca59dd9 | 246 | notrace static void __cpuinit start_secondary(void *unused) |
bbc2ff6a GOC |
247 | { |
248 | /* | |
249 | * Don't put *anything* before cpu_init(), SMP booting is too | |
250 | * fragile that we want to limit the things done here to the | |
251 | * most necessary things. | |
252 | */ | |
b40827fa | 253 | cpu_init(); |
df156f90 | 254 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
255 | preempt_disable(); |
256 | smp_callin(); | |
fd89a137 JR |
257 | |
258 | #ifdef CONFIG_X86_32 | |
b40827fa | 259 | /* switch away from the initial page table */ |
fd89a137 JR |
260 | load_cr3(swapper_pg_dir); |
261 | __flush_tlb_all(); | |
262 | #endif | |
263 | ||
bbc2ff6a GOC |
264 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
265 | barrier(); | |
266 | /* | |
267 | * Check TSC synchronization with the BP: | |
268 | */ | |
269 | check_tsc_sync_target(); | |
270 | ||
bbc2ff6a GOC |
271 | /* |
272 | * We need to hold call_lock, so there is no inconsistency | |
273 | * between the time smp_call_function() determines number of | |
274 | * IPI recipients, and the time when the determination is made | |
275 | * for which cpus receive the IPI. Holding this | |
276 | * lock helps us to not include this cpu in a currently in progress | |
277 | * smp_call_function(). | |
d388e5fd EB |
278 | * |
279 | * We need to hold vector_lock so there the set of online cpus | |
280 | * does not change while we are assigning vectors to cpus. Holding | |
281 | * this lock ensures we don't half assign or remove an irq from a cpu. | |
bbc2ff6a | 282 | */ |
0cefa5b9 | 283 | ipi_call_lock(); |
d388e5fd | 284 | lock_vector_lock(); |
c2d1cec1 | 285 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 286 | unlock_vector_lock(); |
0cefa5b9 | 287 | ipi_call_unlock(); |
bbc2ff6a | 288 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
78c06176 | 289 | x86_platform.nmi_init(); |
bbc2ff6a | 290 | |
0cefa5b9 MS |
291 | /* enable local interrupts */ |
292 | local_irq_enable(); | |
293 | ||
35f720c5 JP |
294 | /* to prevent fake stack check failure in clock setup */ |
295 | boot_init_stack_canary(); | |
0cefa5b9 | 296 | |
736decac | 297 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
298 | |
299 | wmb(); | |
300 | cpu_idle(); | |
301 | } | |
302 | ||
1d89a7f0 GOC |
303 | /* |
304 | * The bootstrap kernel entry code has set these up. Save them for | |
305 | * a given CPU | |
306 | */ | |
307 | ||
308 | void __cpuinit smp_store_cpu_info(int id) | |
309 | { | |
310 | struct cpuinfo_x86 *c = &cpu_data(id); | |
311 | ||
b3d7336d | 312 | *c = boot_cpu_data; |
1d89a7f0 GOC |
313 | c->cpu_index = id; |
314 | if (id != 0) | |
315 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
316 | } |
317 | ||
d4fbe4f0 AH |
318 | static void __cpuinit link_thread_siblings(int cpu1, int cpu2) |
319 | { | |
d4fbe4f0 AH |
320 | cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); |
321 | cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); | |
322 | cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); | |
323 | cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); | |
b3d7336d YL |
324 | cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); |
325 | cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); | |
d4fbe4f0 AH |
326 | } |
327 | ||
1d89a7f0 | 328 | |
768d9505 GC |
329 | void __cpuinit set_cpu_sibling_map(int cpu) |
330 | { | |
331 | int i; | |
332 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
333 | ||
c2d1cec1 | 334 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 GC |
335 | |
336 | if (smp_num_siblings > 1) { | |
c2d1cec1 MT |
337 | for_each_cpu(i, cpu_sibling_setup_mask) { |
338 | struct cpuinfo_x86 *o = &cpu_data(i); | |
339 | ||
d4fbe4f0 AH |
340 | if (cpu_has(c, X86_FEATURE_TOPOEXT)) { |
341 | if (c->phys_proc_id == o->phys_proc_id && | |
d518573d | 342 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && |
d4fbe4f0 AH |
343 | c->compute_unit_id == o->compute_unit_id) |
344 | link_thread_siblings(cpu, i); | |
345 | } else if (c->phys_proc_id == o->phys_proc_id && | |
346 | c->cpu_core_id == o->cpu_core_id) { | |
347 | link_thread_siblings(cpu, i); | |
768d9505 GC |
348 | } |
349 | } | |
350 | } else { | |
c2d1cec1 | 351 | cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); |
768d9505 GC |
352 | } |
353 | ||
b3d7336d | 354 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
768d9505 | 355 | |
7b543a53 | 356 | if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { |
c2d1cec1 | 357 | cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); |
768d9505 GC |
358 | c->booted_cores = 1; |
359 | return; | |
360 | } | |
361 | ||
c2d1cec1 | 362 | for_each_cpu(i, cpu_sibling_setup_mask) { |
768d9505 GC |
363 | if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && |
364 | per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { | |
b3d7336d YL |
365 | cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); |
366 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); | |
768d9505 GC |
367 | } |
368 | if (c->phys_proc_id == cpu_data(i).phys_proc_id) { | |
c2d1cec1 MT |
369 | cpumask_set_cpu(i, cpu_core_mask(cpu)); |
370 | cpumask_set_cpu(cpu, cpu_core_mask(i)); | |
768d9505 GC |
371 | /* |
372 | * Does this new cpu bringup a new core? | |
373 | */ | |
c2d1cec1 | 374 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { |
768d9505 GC |
375 | /* |
376 | * for each core in package, increment | |
377 | * the booted_cores for this new cpu | |
378 | */ | |
c2d1cec1 | 379 | if (cpumask_first(cpu_sibling_mask(i)) == i) |
768d9505 GC |
380 | c->booted_cores++; |
381 | /* | |
382 | * increment the core count for all | |
383 | * the other cpus in this package | |
384 | */ | |
385 | if (i != cpu) | |
386 | cpu_data(i).booted_cores++; | |
387 | } else if (i != cpu && !c->booted_cores) | |
388 | c->booted_cores = cpu_data(i).booted_cores; | |
389 | } | |
390 | } | |
391 | } | |
392 | ||
70708a18 | 393 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 394 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 GC |
395 | { |
396 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
397 | /* | |
398 | * For perf, we return last level cache shared map. | |
399 | * And for power savings, we return cpu_core_map | |
400 | */ | |
5a925b42 AH |
401 | if ((sched_mc_power_savings || sched_smt_power_savings) && |
402 | !(cpu_has(c, X86_FEATURE_AMD_DCM))) | |
c2d1cec1 | 403 | return cpu_core_mask(cpu); |
70708a18 | 404 | else |
b3d7336d | 405 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
406 | } |
407 | ||
a4928cff | 408 | static void impress_friends(void) |
904541e2 GOC |
409 | { |
410 | int cpu; | |
411 | unsigned long bogosum = 0; | |
412 | /* | |
413 | * Allow the user to impress friends. | |
414 | */ | |
cfc1b9a6 | 415 | pr_debug("Before bogomips.\n"); |
904541e2 | 416 | for_each_possible_cpu(cpu) |
c2d1cec1 | 417 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 GOC |
418 | bogosum += cpu_data(cpu).loops_per_jiffy; |
419 | printk(KERN_INFO | |
420 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
f68e00a3 | 421 | num_online_cpus(), |
904541e2 GOC |
422 | bogosum/(500000/HZ), |
423 | (bogosum/(5000/HZ))%100); | |
424 | ||
cfc1b9a6 | 425 | pr_debug("Before bogocount - setting activated=1.\n"); |
904541e2 GOC |
426 | } |
427 | ||
569712b2 | 428 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
429 | { |
430 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 431 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
432 | int timeout; |
433 | u32 status; | |
434 | ||
823b259b | 435 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
436 | |
437 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
823b259b | 438 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
439 | |
440 | /* | |
441 | * Wait for idle. | |
442 | */ | |
443 | status = safe_apic_wait_icr_idle(); | |
444 | if (status) | |
445 | printk(KERN_CONT | |
446 | "a previous APIC delivery may have failed\n"); | |
447 | ||
1b374e4d | 448 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
449 | |
450 | timeout = 0; | |
451 | do { | |
452 | udelay(100); | |
453 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
454 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
455 | ||
456 | switch (status) { | |
457 | case APIC_ICR_RR_VALID: | |
458 | status = apic_read(APIC_RRR); | |
459 | printk(KERN_CONT "%08x\n", status); | |
460 | break; | |
461 | default: | |
462 | printk(KERN_CONT "failed\n"); | |
463 | } | |
464 | } | |
465 | } | |
466 | ||
cb3c8b90 GOC |
467 | /* |
468 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
469 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
470 | * won't ... remember to clear down the APIC, etc later. | |
471 | */ | |
cece3155 | 472 | int __cpuinit |
569712b2 | 473 | wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
474 | { |
475 | unsigned long send_status, accept_status = 0; | |
476 | int maxlvt; | |
477 | ||
478 | /* Target chip */ | |
cb3c8b90 GOC |
479 | /* Boot on the stack */ |
480 | /* Kick the second */ | |
bdb1a9b6 | 481 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); |
cb3c8b90 | 482 | |
cfc1b9a6 | 483 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
484 | send_status = safe_apic_wait_icr_idle(); |
485 | ||
486 | /* | |
487 | * Give the other CPU some time to accept the IPI. | |
488 | */ | |
489 | udelay(200); | |
569712b2 | 490 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { |
59ef48a5 CG |
491 | maxlvt = lapic_get_maxlvt(); |
492 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
493 | apic_write(APIC_ESR, 0); | |
494 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
495 | } | |
cfc1b9a6 | 496 | pr_debug("NMI sent.\n"); |
cb3c8b90 GOC |
497 | |
498 | if (send_status) | |
499 | printk(KERN_ERR "APIC never delivered???\n"); | |
500 | if (accept_status) | |
501 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
502 | ||
503 | return (send_status | accept_status); | |
504 | } | |
cb3c8b90 | 505 | |
cece3155 | 506 | static int __cpuinit |
569712b2 | 507 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 GOC |
508 | { |
509 | unsigned long send_status, accept_status = 0; | |
510 | int maxlvt, num_starts, j; | |
511 | ||
593f4a78 MR |
512 | maxlvt = lapic_get_maxlvt(); |
513 | ||
cb3c8b90 GOC |
514 | /* |
515 | * Be paranoid about clearing APIC errors. | |
516 | */ | |
517 | if (APIC_INTEGRATED(apic_version[phys_apicid])) { | |
593f4a78 MR |
518 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
519 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
520 | apic_read(APIC_ESR); |
521 | } | |
522 | ||
cfc1b9a6 | 523 | pr_debug("Asserting INIT.\n"); |
cb3c8b90 GOC |
524 | |
525 | /* | |
526 | * Turn INIT on target chip | |
527 | */ | |
cb3c8b90 GOC |
528 | /* |
529 | * Send IPI | |
530 | */ | |
1b374e4d SS |
531 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
532 | phys_apicid); | |
cb3c8b90 | 533 | |
cfc1b9a6 | 534 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
535 | send_status = safe_apic_wait_icr_idle(); |
536 | ||
537 | mdelay(10); | |
538 | ||
cfc1b9a6 | 539 | pr_debug("Deasserting INIT.\n"); |
cb3c8b90 GOC |
540 | |
541 | /* Target chip */ | |
cb3c8b90 | 542 | /* Send IPI */ |
1b374e4d | 543 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 544 | |
cfc1b9a6 | 545 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
546 | send_status = safe_apic_wait_icr_idle(); |
547 | ||
548 | mb(); | |
549 | atomic_set(&init_deasserted, 1); | |
550 | ||
551 | /* | |
552 | * Should we send STARTUP IPIs ? | |
553 | * | |
554 | * Determine this based on the APIC version. | |
555 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
556 | */ | |
557 | if (APIC_INTEGRATED(apic_version[phys_apicid])) | |
558 | num_starts = 2; | |
559 | else | |
560 | num_starts = 0; | |
561 | ||
562 | /* | |
563 | * Paravirt / VMI wants a startup IPI hook here to set up the | |
564 | * target processor state. | |
565 | */ | |
566 | startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, | |
11d4c3f9 | 567 | stack_start); |
cb3c8b90 GOC |
568 | |
569 | /* | |
570 | * Run STARTUP IPI loop. | |
571 | */ | |
cfc1b9a6 | 572 | pr_debug("#startup loops: %d.\n", num_starts); |
cb3c8b90 | 573 | |
cb3c8b90 | 574 | for (j = 1; j <= num_starts; j++) { |
cfc1b9a6 | 575 | pr_debug("Sending STARTUP #%d.\n", j); |
593f4a78 MR |
576 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
577 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 578 | apic_read(APIC_ESR); |
cfc1b9a6 | 579 | pr_debug("After apic_write.\n"); |
cb3c8b90 GOC |
580 | |
581 | /* | |
582 | * STARTUP IPI | |
583 | */ | |
584 | ||
585 | /* Target chip */ | |
cb3c8b90 GOC |
586 | /* Boot on the stack */ |
587 | /* Kick the second */ | |
1b374e4d SS |
588 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
589 | phys_apicid); | |
cb3c8b90 GOC |
590 | |
591 | /* | |
592 | * Give the other CPU some time to accept the IPI. | |
593 | */ | |
594 | udelay(300); | |
595 | ||
cfc1b9a6 | 596 | pr_debug("Startup point 1.\n"); |
cb3c8b90 | 597 | |
cfc1b9a6 | 598 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
599 | send_status = safe_apic_wait_icr_idle(); |
600 | ||
601 | /* | |
602 | * Give the other CPU some time to accept the IPI. | |
603 | */ | |
604 | udelay(200); | |
593f4a78 | 605 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 606 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
607 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
608 | if (send_status || accept_status) | |
609 | break; | |
610 | } | |
cfc1b9a6 | 611 | pr_debug("After Startup.\n"); |
cb3c8b90 GOC |
612 | |
613 | if (send_status) | |
614 | printk(KERN_ERR "APIC never delivered???\n"); | |
615 | if (accept_status) | |
616 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | |
617 | ||
618 | return (send_status | accept_status); | |
619 | } | |
cb3c8b90 GOC |
620 | |
621 | struct create_idle { | |
622 | struct work_struct work; | |
623 | struct task_struct *idle; | |
624 | struct completion done; | |
625 | int cpu; | |
626 | }; | |
627 | ||
628 | static void __cpuinit do_fork_idle(struct work_struct *work) | |
629 | { | |
630 | struct create_idle *c_idle = | |
631 | container_of(work, struct create_idle, work); | |
632 | ||
633 | c_idle->idle = fork_idle(c_idle->cpu); | |
634 | complete(&c_idle->done); | |
635 | } | |
636 | ||
2eaad1fd MT |
637 | /* reduce the number of lines printed when booting a large cpu count system */ |
638 | static void __cpuinit announce_cpu(int cpu, int apicid) | |
639 | { | |
640 | static int current_node = -1; | |
4adc8b71 | 641 | int node = early_cpu_to_node(cpu); |
2eaad1fd MT |
642 | |
643 | if (system_state == SYSTEM_BOOTING) { | |
644 | if (node != current_node) { | |
645 | if (current_node > (-1)) | |
646 | pr_cont(" Ok.\n"); | |
647 | current_node = node; | |
648 | pr_info("Booting Node %3d, Processors ", node); | |
649 | } | |
650 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | |
651 | return; | |
652 | } else | |
653 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
654 | node, cpu, apicid); | |
655 | } | |
656 | ||
cb3c8b90 GOC |
657 | /* |
658 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
659 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
660 | * Returns zero if CPU booted OK, else error code from |
661 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 662 | */ |
ab6fb7c0 | 663 | static int __cpuinit do_boot_cpu(int apicid, int cpu) |
cb3c8b90 GOC |
664 | { |
665 | unsigned long boot_error = 0; | |
cb3c8b90 | 666 | unsigned long start_ip; |
ab6fb7c0 | 667 | int timeout; |
cb3c8b90 | 668 | struct create_idle c_idle = { |
ab6fb7c0 IM |
669 | .cpu = cpu, |
670 | .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), | |
cb3c8b90 | 671 | }; |
ab6fb7c0 | 672 | |
ca1cab37 | 673 | INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); |
cb3c8b90 | 674 | |
cb3c8b90 GOC |
675 | alternatives_smp_switch(1); |
676 | ||
677 | c_idle.idle = get_idle_for_cpu(cpu); | |
678 | ||
679 | /* | |
680 | * We can't use kernel_thread since we must avoid to | |
681 | * reschedule the child. | |
682 | */ | |
683 | if (c_idle.idle) { | |
684 | c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) | |
685 | (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); | |
686 | init_idle(c_idle.idle, cpu); | |
687 | goto do_rest; | |
688 | } | |
689 | ||
d7a7c573 SS |
690 | schedule_work(&c_idle.work); |
691 | wait_for_completion(&c_idle.done); | |
cb3c8b90 GOC |
692 | |
693 | if (IS_ERR(c_idle.idle)) { | |
694 | printk("failed fork for CPU %d\n", cpu); | |
dc186ad7 | 695 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
696 | return PTR_ERR(c_idle.idle); |
697 | } | |
698 | ||
699 | set_idle_for_cpu(cpu, c_idle.idle); | |
700 | do_rest: | |
cb3c8b90 | 701 | per_cpu(current_task, cpu) = c_idle.idle; |
c6f5e0ac | 702 | #ifdef CONFIG_X86_32 |
cb3c8b90 | 703 | /* Stack for startup_32 can be just as for start_secondary onwards */ |
cb3c8b90 GOC |
704 | irq_ctx_init(cpu); |
705 | #else | |
cb3c8b90 | 706 | clear_tsk_thread_flag(c_idle.idle, TIF_FORK); |
004aa322 | 707 | initial_gs = per_cpu_offset(cpu); |
9af45651 BG |
708 | per_cpu(kernel_stack, cpu) = |
709 | (unsigned long)task_stack_page(c_idle.idle) - | |
710 | KERNEL_STACK_OFFSET + THREAD_SIZE; | |
cb3c8b90 | 711 | #endif |
a939098a | 712 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); |
3e970473 | 713 | initial_code = (unsigned long)start_secondary; |
11d4c3f9 | 714 | stack_start = c_idle.idle->thread.sp; |
cb3c8b90 GOC |
715 | |
716 | /* start_ip had better be page-aligned! */ | |
4822b7fc | 717 | start_ip = trampoline_address(); |
cb3c8b90 | 718 | |
2eaad1fd MT |
719 | /* So we see what's up */ |
720 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
721 | |
722 | /* | |
723 | * This grunge runs the startup process for | |
724 | * the targeted processor. | |
725 | */ | |
726 | ||
727 | atomic_set(&init_deasserted, 0); | |
728 | ||
34d05591 | 729 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 730 | |
cfc1b9a6 | 731 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 732 | |
34d05591 JS |
733 | smpboot_setup_warm_reset_vector(start_ip); |
734 | /* | |
735 | * Be paranoid about clearing APIC errors. | |
db96b0a0 CG |
736 | */ |
737 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { | |
738 | apic_write(APIC_ESR, 0); | |
739 | apic_read(APIC_ESR); | |
740 | } | |
34d05591 | 741 | } |
cb3c8b90 | 742 | |
cb3c8b90 | 743 | /* |
1f5bcabf IM |
744 | * Kick the secondary CPU. Use the method in the APIC driver |
745 | * if it's defined - or use an INIT boot APIC message otherwise: | |
cb3c8b90 | 746 | */ |
1f5bcabf IM |
747 | if (apic->wakeup_secondary_cpu) |
748 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
749 | else | |
750 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
cb3c8b90 GOC |
751 | |
752 | if (!boot_error) { | |
753 | /* | |
754 | * allow APs to start initializing. | |
755 | */ | |
cfc1b9a6 | 756 | pr_debug("Before Callout %d.\n", cpu); |
c2d1cec1 | 757 | cpumask_set_cpu(cpu, cpu_callout_mask); |
cfc1b9a6 | 758 | pr_debug("After Callout %d.\n", cpu); |
cb3c8b90 GOC |
759 | |
760 | /* | |
761 | * Wait 5s total for a response | |
762 | */ | |
763 | for (timeout = 0; timeout < 50000; timeout++) { | |
c2d1cec1 | 764 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) |
cb3c8b90 GOC |
765 | break; /* It has booted */ |
766 | udelay(100); | |
68f202e4 SS |
767 | /* |
768 | * Allow other tasks to run while we wait for the | |
769 | * AP to come online. This also gives a chance | |
770 | * for the MTRR work(triggered by the AP coming online) | |
771 | * to be completed in the stop machine context. | |
772 | */ | |
773 | schedule(); | |
cb3c8b90 GOC |
774 | } |
775 | ||
21c3fcf3 YL |
776 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
777 | print_cpu_msr(&cpu_data(cpu)); | |
2eaad1fd | 778 | pr_debug("CPU%d: has booted.\n", cpu); |
21c3fcf3 | 779 | } else { |
cb3c8b90 | 780 | boot_error = 1; |
4822b7fc PA |
781 | if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) |
782 | == 0xA5A5A5A5) | |
cb3c8b90 | 783 | /* trampoline started but...? */ |
2eaad1fd | 784 | pr_err("CPU%d: Stuck ??\n", cpu); |
cb3c8b90 GOC |
785 | else |
786 | /* trampoline code not run */ | |
2eaad1fd | 787 | pr_err("CPU%d: Not responding.\n", cpu); |
25dc0049 IM |
788 | if (apic->inquire_remote_apic) |
789 | apic->inquire_remote_apic(apicid); | |
cb3c8b90 GOC |
790 | } |
791 | } | |
1a51e3a0 | 792 | |
cb3c8b90 GOC |
793 | if (boot_error) { |
794 | /* Try to put things back the way they were before ... */ | |
23ca4bba | 795 | numa_remove_cpu(cpu); /* was set by numa_add_cpu */ |
c2d1cec1 MT |
796 | |
797 | /* was set by do_boot_cpu() */ | |
798 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
799 | ||
800 | /* was set by cpu_init() */ | |
801 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
802 | ||
803 | set_cpu_present(cpu, false); | |
cb3c8b90 GOC |
804 | per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; |
805 | } | |
806 | ||
807 | /* mark "stuck" area as not stuck */ | |
4822b7fc | 808 | *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; |
cb3c8b90 | 809 | |
02421f98 YL |
810 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
811 | /* | |
812 | * Cleanup possible dangling ends... | |
813 | */ | |
814 | smpboot_restore_warm_reset_vector(); | |
815 | } | |
63d38198 | 816 | |
dc186ad7 | 817 | destroy_work_on_stack(&c_idle.work); |
cb3c8b90 GOC |
818 | return boot_error; |
819 | } | |
820 | ||
5cdaf183 | 821 | int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 822 | { |
a21769a4 | 823 | int apicid = apic->cpu_present_to_apicid(cpu); |
cb3c8b90 GOC |
824 | unsigned long flags; |
825 | int err; | |
826 | ||
827 | WARN_ON(irqs_disabled()); | |
828 | ||
cfc1b9a6 | 829 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 GOC |
830 | |
831 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | |
c284b42a | 832 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 833 | !apic->apic_id_valid(apicid)) { |
cb3c8b90 GOC |
834 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); |
835 | return -EINVAL; | |
836 | } | |
837 | ||
838 | /* | |
839 | * Already booted CPU? | |
840 | */ | |
c2d1cec1 | 841 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 842 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
843 | return -ENOSYS; |
844 | } | |
845 | ||
846 | /* | |
847 | * Save current MTRR state in case it was changed since early boot | |
848 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
849 | */ | |
850 | mtrr_save_state(); | |
851 | ||
852 | per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; | |
853 | ||
cb3c8b90 | 854 | err = do_boot_cpu(apicid, cpu); |
61165d7a | 855 | if (err) { |
cfc1b9a6 | 856 | pr_debug("do_boot_cpu failed %d\n", err); |
61165d7a | 857 | return -EIO; |
cb3c8b90 GOC |
858 | } |
859 | ||
860 | /* | |
861 | * Check TSC synchronization with the AP (keep irqs disabled | |
862 | * while doing so): | |
863 | */ | |
864 | local_irq_save(flags); | |
865 | check_tsc_sync_source(cpu); | |
866 | local_irq_restore(flags); | |
867 | ||
7c04e64a | 868 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
869 | cpu_relax(); |
870 | touch_nmi_watchdog(); | |
871 | } | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
7167d08e HK |
876 | /** |
877 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
878 | */ | |
879 | void arch_disable_smp_support(void) | |
880 | { | |
881 | disable_ioapic_support(); | |
882 | } | |
883 | ||
8aef135c GOC |
884 | /* |
885 | * Fall back to non SMP mode after errors. | |
886 | * | |
887 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
888 | */ | |
889 | static __init void disable_smp(void) | |
890 | { | |
4f062896 RR |
891 | init_cpu_present(cpumask_of(0)); |
892 | init_cpu_possible(cpumask_of(0)); | |
8aef135c | 893 | smpboot_clear_io_apic_irqs(); |
0f385d1d | 894 | |
8aef135c | 895 | if (smp_found_config) |
b6df1b8b | 896 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 897 | else |
b6df1b8b | 898 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
c2d1cec1 MT |
899 | cpumask_set_cpu(0, cpu_sibling_mask(0)); |
900 | cpumask_set_cpu(0, cpu_core_mask(0)); | |
8aef135c GOC |
901 | } |
902 | ||
903 | /* | |
904 | * Various sanity checks. | |
905 | */ | |
906 | static int __init smp_sanity_check(unsigned max_cpus) | |
907 | { | |
ac23d4ee | 908 | preempt_disable(); |
a58f03b0 | 909 | |
1ff2f20d | 910 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
911 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
912 | unsigned int cpu; | |
913 | unsigned nr; | |
914 | ||
915 | printk(KERN_WARNING | |
916 | "More than 8 CPUs detected - skipping them.\n" | |
26f7ef14 | 917 | "Use CONFIG_X86_BIGSMP.\n"); |
a58f03b0 YL |
918 | |
919 | nr = 0; | |
920 | for_each_present_cpu(cpu) { | |
921 | if (nr >= 8) | |
c2d1cec1 | 922 | set_cpu_present(cpu, false); |
a58f03b0 YL |
923 | nr++; |
924 | } | |
925 | ||
926 | nr = 0; | |
927 | for_each_possible_cpu(cpu) { | |
928 | if (nr >= 8) | |
c2d1cec1 | 929 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
930 | nr++; |
931 | } | |
932 | ||
933 | nr_cpu_ids = 8; | |
934 | } | |
935 | #endif | |
936 | ||
8aef135c | 937 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
55c395b4 MT |
938 | printk(KERN_WARNING |
939 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
940 | hard_smp_processor_id()); | |
941 | ||
8aef135c GOC |
942 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
943 | } | |
944 | ||
945 | /* | |
946 | * If we couldn't find an SMP configuration at boot time, | |
947 | * get out of here now! | |
948 | */ | |
949 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 950 | preempt_enable(); |
8aef135c GOC |
951 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); |
952 | disable_smp(); | |
953 | if (APIC_init_uniprocessor()) | |
954 | printk(KERN_NOTICE "Local APIC not detected." | |
955 | " Using dummy APIC emulation.\n"); | |
956 | return -1; | |
957 | } | |
958 | ||
959 | /* | |
960 | * Should not be necessary because the MP table should list the boot | |
961 | * CPU too, but we do it for the sake of robustness anyway. | |
962 | */ | |
a27a6210 | 963 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
8aef135c GOC |
964 | printk(KERN_NOTICE |
965 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | |
966 | boot_cpu_physical_apicid); | |
967 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | |
968 | } | |
ac23d4ee | 969 | preempt_enable(); |
8aef135c GOC |
970 | |
971 | /* | |
972 | * If we couldn't find a local APIC, then get out of here now! | |
973 | */ | |
974 | if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && | |
975 | !cpu_has_apic) { | |
103428e5 CG |
976 | if (!disable_apic) { |
977 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
978 | boot_cpu_physical_apicid); | |
979 | pr_err("... forcing use of dummy APIC emulation." | |
8aef135c | 980 | "(tell your hw vendor)\n"); |
103428e5 | 981 | } |
8aef135c | 982 | smpboot_clear_io_apic(); |
7167d08e | 983 | disable_ioapic_support(); |
8aef135c GOC |
984 | return -1; |
985 | } | |
986 | ||
987 | verify_local_APIC(); | |
988 | ||
989 | /* | |
990 | * If SMP should be disabled, then really disable it! | |
991 | */ | |
992 | if (!max_cpus) { | |
73d08e63 | 993 | printk(KERN_INFO "SMP mode deactivated.\n"); |
8aef135c | 994 | smpboot_clear_io_apic(); |
d54db1ac | 995 | |
e90955c2 | 996 | connect_bsp_APIC(); |
e90955c2 | 997 | setup_local_APIC(); |
2fb270f3 | 998 | bsp_end_local_APIC_setup(); |
8aef135c GOC |
999 | return -1; |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static void __init smp_cpu_index_default(void) | |
1006 | { | |
1007 | int i; | |
1008 | struct cpuinfo_x86 *c; | |
1009 | ||
7c04e64a | 1010 | for_each_possible_cpu(i) { |
8aef135c GOC |
1011 | c = &cpu_data(i); |
1012 | /* mark all to hotplug */ | |
9628937d | 1013 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1014 | } |
1015 | } | |
1016 | ||
1017 | /* | |
1018 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1019 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1020 | */ | |
1021 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1022 | { | |
7ad728f9 RR |
1023 | unsigned int i; |
1024 | ||
deef3250 | 1025 | preempt_disable(); |
8aef135c | 1026 | smp_cpu_index_default(); |
792363d2 | 1027 | |
8aef135c GOC |
1028 | /* |
1029 | * Setup boot CPU information | |
1030 | */ | |
1031 | smp_store_cpu_info(0); /* Final full version of the data */ | |
792363d2 YL |
1032 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1033 | mb(); | |
bd22a2f1 | 1034 | |
8aef135c | 1035 | current_thread_info()->cpu = 0; /* needed? */ |
7ad728f9 | 1036 | for_each_possible_cpu(i) { |
79f55997 LZ |
1037 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1038 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1039 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1040 | } |
8aef135c GOC |
1041 | set_cpu_sibling_map(0); |
1042 | ||
6e1cb38a | 1043 | |
8aef135c GOC |
1044 | if (smp_sanity_check(max_cpus) < 0) { |
1045 | printk(KERN_INFO "SMP disabled\n"); | |
1046 | disable_smp(); | |
deef3250 | 1047 | goto out; |
8aef135c GOC |
1048 | } |
1049 | ||
fa47f7e5 SS |
1050 | default_setup_apic_routing(); |
1051 | ||
ac23d4ee | 1052 | preempt_disable(); |
4c9961d5 | 1053 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1054 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1055 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1056 | /* Or can we switch back to PIC here? */ |
1057 | } | |
ac23d4ee | 1058 | preempt_enable(); |
8aef135c | 1059 | |
8aef135c | 1060 | connect_bsp_APIC(); |
b5841765 | 1061 | |
8aef135c GOC |
1062 | /* |
1063 | * Switch from PIC to APIC mode. | |
1064 | */ | |
1065 | setup_local_APIC(); | |
1066 | ||
8aef135c GOC |
1067 | /* |
1068 | * Enable IO APIC before setting up error vector | |
1069 | */ | |
1070 | if (!skip_ioapic_setup && nr_ioapics) | |
1071 | enable_IO_APIC(); | |
88d0f550 | 1072 | |
2fb270f3 | 1073 | bsp_end_local_APIC_setup(); |
8aef135c | 1074 | |
d83093b5 IM |
1075 | if (apic->setup_portio_remap) |
1076 | apic->setup_portio_remap(); | |
8aef135c GOC |
1077 | |
1078 | smpboot_setup_io_apic(); | |
1079 | /* | |
1080 | * Set up local APIC timer on boot CPU. | |
1081 | */ | |
1082 | ||
1083 | printk(KERN_INFO "CPU%d: ", 0); | |
1084 | print_cpu_info(&cpu_data(0)); | |
736decac | 1085 | x86_init.timers.setup_percpu_clockev(); |
c4bd1fda MS |
1086 | |
1087 | if (is_uv_system()) | |
1088 | uv_system_init(); | |
d0af9eed SS |
1089 | |
1090 | set_mtrr_aps_delayed_init(); | |
deef3250 IM |
1091 | out: |
1092 | preempt_enable(); | |
8aef135c | 1093 | } |
d0af9eed | 1094 | |
3fb82d56 SS |
1095 | void arch_disable_nonboot_cpus_begin(void) |
1096 | { | |
1097 | /* | |
1098 | * Avoid the smp alternatives switch during the disable_nonboot_cpus(). | |
1099 | * In the suspend path, we will be back in the SMP mode shortly anyways. | |
1100 | */ | |
1101 | skip_smp_alternatives = true; | |
1102 | } | |
1103 | ||
1104 | void arch_disable_nonboot_cpus_end(void) | |
1105 | { | |
1106 | skip_smp_alternatives = false; | |
1107 | } | |
1108 | ||
d0af9eed SS |
1109 | void arch_enable_nonboot_cpus_begin(void) |
1110 | { | |
1111 | set_mtrr_aps_delayed_init(); | |
1112 | } | |
1113 | ||
1114 | void arch_enable_nonboot_cpus_end(void) | |
1115 | { | |
1116 | mtrr_aps_init(); | |
1117 | } | |
1118 | ||
a8db8453 GOC |
1119 | /* |
1120 | * Early setup to make printk work. | |
1121 | */ | |
1122 | void __init native_smp_prepare_boot_cpu(void) | |
1123 | { | |
1124 | int me = smp_processor_id(); | |
552be871 | 1125 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1126 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1127 | cpumask_set_cpu(me, cpu_callout_mask); | |
a8db8453 GOC |
1128 | per_cpu(cpu_state, me) = CPU_ONLINE; |
1129 | } | |
1130 | ||
83f7eb9c GOC |
1131 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1132 | { | |
cfc1b9a6 | 1133 | pr_debug("Boot done.\n"); |
83f7eb9c | 1134 | |
99e8b9ca | 1135 | nmi_selftest(); |
83f7eb9c | 1136 | impress_friends(); |
83f7eb9c GOC |
1137 | #ifdef CONFIG_X86_IO_APIC |
1138 | setup_ioapic_dest(); | |
1139 | #endif | |
d0af9eed | 1140 | mtrr_aps_init(); |
83f7eb9c GOC |
1141 | } |
1142 | ||
3b11ce7f MT |
1143 | static int __initdata setup_possible_cpus = -1; |
1144 | static int __init _setup_possible_cpus(char *str) | |
1145 | { | |
1146 | get_option(&str, &setup_possible_cpus); | |
1147 | return 0; | |
1148 | } | |
1149 | early_param("possible_cpus", _setup_possible_cpus); | |
1150 | ||
1151 | ||
68a1c3f8 | 1152 | /* |
4f062896 | 1153 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1154 | * are onlined, or offlined. The reason is per-cpu data-structures |
1155 | * are allocated by some modules at init time, and dont expect to | |
1156 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1157 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1158 | * In case when cpu_hotplug is not compiled, then we resort to current |
1159 | * behaviour, which is cpu_possible == cpu_present. | |
1160 | * - Ashok Raj | |
1161 | * | |
1162 | * Three ways to find out the number of additional hotplug CPUs: | |
1163 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1164 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1165 | * - Otherwise don't reserve additional CPUs. |
1166 | * We do this because additional CPUs waste a lot of memory. | |
1167 | * -AK | |
1168 | */ | |
1169 | __init void prefill_possible_map(void) | |
1170 | { | |
cb48bb59 | 1171 | int i, possible; |
68a1c3f8 | 1172 | |
329513a3 YL |
1173 | /* no processor from mptable or madt */ |
1174 | if (!num_processors) | |
1175 | num_processors = 1; | |
1176 | ||
5f2eb550 JB |
1177 | i = setup_max_cpus ?: 1; |
1178 | if (setup_possible_cpus == -1) { | |
1179 | possible = num_processors; | |
1180 | #ifdef CONFIG_HOTPLUG_CPU | |
1181 | if (setup_max_cpus) | |
1182 | possible += disabled_cpus; | |
1183 | #else | |
1184 | if (possible > i) | |
1185 | possible = i; | |
1186 | #endif | |
1187 | } else | |
3b11ce7f MT |
1188 | possible = setup_possible_cpus; |
1189 | ||
730cf272 MT |
1190 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1191 | ||
2b633e3f YL |
1192 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1193 | if (possible > nr_cpu_ids) { | |
3b11ce7f MT |
1194 | printk(KERN_WARNING |
1195 | "%d Processors exceeds NR_CPUS limit of %d\n", | |
2b633e3f YL |
1196 | possible, nr_cpu_ids); |
1197 | possible = nr_cpu_ids; | |
3b11ce7f | 1198 | } |
68a1c3f8 | 1199 | |
5f2eb550 JB |
1200 | #ifdef CONFIG_HOTPLUG_CPU |
1201 | if (!setup_max_cpus) | |
1202 | #endif | |
1203 | if (possible > i) { | |
1204 | printk(KERN_WARNING | |
1205 | "%d Processors exceeds max_cpus limit of %u\n", | |
1206 | possible, setup_max_cpus); | |
1207 | possible = i; | |
1208 | } | |
1209 | ||
68a1c3f8 GC |
1210 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", |
1211 | possible, max_t(int, possible - num_processors, 0)); | |
1212 | ||
1213 | for (i = 0; i < possible; i++) | |
c2d1cec1 | 1214 | set_cpu_possible(i, true); |
5f2eb550 JB |
1215 | for (; i < NR_CPUS; i++) |
1216 | set_cpu_possible(i, false); | |
3461b0af MT |
1217 | |
1218 | nr_cpu_ids = possible; | |
68a1c3f8 | 1219 | } |
69c18c15 | 1220 | |
14adf855 CE |
1221 | #ifdef CONFIG_HOTPLUG_CPU |
1222 | ||
1223 | static void remove_siblinginfo(int cpu) | |
1224 | { | |
1225 | int sibling; | |
1226 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1227 | ||
c2d1cec1 MT |
1228 | for_each_cpu(sibling, cpu_core_mask(cpu)) { |
1229 | cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); | |
14adf855 CE |
1230 | /*/ |
1231 | * last thread sibling in this cpu core going down | |
1232 | */ | |
c2d1cec1 | 1233 | if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) |
14adf855 CE |
1234 | cpu_data(sibling).booted_cores--; |
1235 | } | |
1236 | ||
c2d1cec1 MT |
1237 | for_each_cpu(sibling, cpu_sibling_mask(cpu)) |
1238 | cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); | |
1239 | cpumask_clear(cpu_sibling_mask(cpu)); | |
1240 | cpumask_clear(cpu_core_mask(cpu)); | |
14adf855 CE |
1241 | c->phys_proc_id = 0; |
1242 | c->cpu_core_id = 0; | |
c2d1cec1 | 1243 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
14adf855 CE |
1244 | } |
1245 | ||
69c18c15 GC |
1246 | static void __ref remove_cpu_from_maps(int cpu) |
1247 | { | |
c2d1cec1 MT |
1248 | set_cpu_online(cpu, false); |
1249 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1250 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1251 | /* was set by cpu_init() */ |
c2d1cec1 | 1252 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1253 | numa_remove_cpu(cpu); |
69c18c15 GC |
1254 | } |
1255 | ||
8227dce7 | 1256 | void cpu_disable_common(void) |
69c18c15 GC |
1257 | { |
1258 | int cpu = smp_processor_id(); | |
69c18c15 | 1259 | |
69c18c15 GC |
1260 | remove_siblinginfo(cpu); |
1261 | ||
1262 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1263 | lock_vector_lock(); |
69c18c15 | 1264 | remove_cpu_from_maps(cpu); |
d388e5fd | 1265 | unlock_vector_lock(); |
d7b381bb | 1266 | fixup_irqs(); |
8227dce7 AN |
1267 | } |
1268 | ||
1269 | int native_cpu_disable(void) | |
1270 | { | |
1271 | int cpu = smp_processor_id(); | |
1272 | ||
1273 | /* | |
1274 | * Perhaps use cpufreq to drop frequency, but that could go | |
1275 | * into generic code. | |
1276 | * | |
1277 | * We won't take down the boot processor on i386 due to some | |
1278 | * interrupts only being able to be serviced by the BSP. | |
1279 | * Especially so if we're not using an IOAPIC -zwane | |
1280 | */ | |
1281 | if (cpu == 0) | |
1282 | return -EBUSY; | |
1283 | ||
8227dce7 AN |
1284 | clear_local_APIC(); |
1285 | ||
1286 | cpu_disable_common(); | |
69c18c15 GC |
1287 | return 0; |
1288 | } | |
1289 | ||
93be71b6 | 1290 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1291 | { |
1292 | /* We don't do anything here: idle task is faking death itself. */ | |
1293 | unsigned int i; | |
1294 | ||
1295 | for (i = 0; i < 10; i++) { | |
1296 | /* They ack this in play_dead by setting CPU_DEAD */ | |
1297 | if (per_cpu(cpu_state, cpu) == CPU_DEAD) { | |
2eaad1fd MT |
1298 | if (system_state == SYSTEM_RUNNING) |
1299 | pr_info("CPU %u is now offline\n", cpu); | |
1300 | ||
69c18c15 GC |
1301 | if (1 == num_online_cpus()) |
1302 | alternatives_smp_switch(0); | |
1303 | return; | |
1304 | } | |
1305 | msleep(100); | |
1306 | } | |
2eaad1fd | 1307 | pr_err("CPU %u didn't die...\n", cpu); |
69c18c15 | 1308 | } |
a21f5d88 AN |
1309 | |
1310 | void play_dead_common(void) | |
1311 | { | |
1312 | idle_task_exit(); | |
1313 | reset_lazy_tlbstate(); | |
02c68a02 | 1314 | amd_e400_remove_cpu(raw_smp_processor_id()); |
a21f5d88 AN |
1315 | |
1316 | mb(); | |
1317 | /* Ack it */ | |
0a3aee0d | 1318 | __this_cpu_write(cpu_state, CPU_DEAD); |
a21f5d88 AN |
1319 | |
1320 | /* | |
1321 | * With physical CPU hotplug, we should halt the cpu | |
1322 | */ | |
1323 | local_irq_disable(); | |
1324 | } | |
1325 | ||
ea530692 PA |
1326 | /* |
1327 | * We need to flush the caches before going to sleep, lest we have | |
1328 | * dirty data in our caches when we come back up. | |
1329 | */ | |
1330 | static inline void mwait_play_dead(void) | |
1331 | { | |
1332 | unsigned int eax, ebx, ecx, edx; | |
1333 | unsigned int highest_cstate = 0; | |
1334 | unsigned int highest_subcstate = 0; | |
1335 | int i; | |
ce5f6824 | 1336 | void *mwait_ptr; |
93789b32 | 1337 | struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); |
ea530692 | 1338 | |
4f3c125c | 1339 | if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) |
ea530692 | 1340 | return; |
349c004e | 1341 | if (!this_cpu_has(X86_FEATURE_CLFLSH)) |
ce5f6824 | 1342 | return; |
7b543a53 | 1343 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1344 | return; |
1345 | ||
1346 | eax = CPUID_MWAIT_LEAF; | |
1347 | ecx = 0; | |
1348 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1349 | ||
1350 | /* | |
1351 | * eax will be 0 if EDX enumeration is not valid. | |
1352 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1353 | */ | |
1354 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1355 | eax = 0; | |
1356 | } else { | |
1357 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1358 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1359 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1360 | highest_cstate = i; | |
1361 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1362 | } | |
1363 | } | |
1364 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1365 | (highest_subcstate - 1); | |
1366 | } | |
1367 | ||
ce5f6824 PA |
1368 | /* |
1369 | * This should be a memory location in a cache line which is | |
1370 | * unlikely to be touched by other processors. The actual | |
1371 | * content is immaterial as it is not actually modified in any way. | |
1372 | */ | |
1373 | mwait_ptr = ¤t_thread_info()->flags; | |
1374 | ||
a68e5c94 PA |
1375 | wbinvd(); |
1376 | ||
ea530692 | 1377 | while (1) { |
ce5f6824 PA |
1378 | /* |
1379 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1380 | * the Xeon 7400 series. It's not clear it is actually | |
1381 | * needed, but it should be harmless in either case. | |
1382 | * The WBINVD is insufficient due to the spurious-wakeup | |
1383 | * case where we return around the loop. | |
1384 | */ | |
1385 | clflush(mwait_ptr); | |
1386 | __monitor(mwait_ptr, 0, 0); | |
ea530692 PA |
1387 | mb(); |
1388 | __mwait(eax, 0); | |
1389 | } | |
1390 | } | |
1391 | ||
1392 | static inline void hlt_play_dead(void) | |
1393 | { | |
7b543a53 | 1394 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1395 | wbinvd(); |
1396 | ||
ea530692 | 1397 | while (1) { |
ea530692 PA |
1398 | native_halt(); |
1399 | } | |
1400 | } | |
1401 | ||
a21f5d88 AN |
1402 | void native_play_dead(void) |
1403 | { | |
1404 | play_dead_common(); | |
86886e55 | 1405 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1406 | |
1407 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1408 | if (cpuidle_play_dead()) |
1409 | hlt_play_dead(); | |
a21f5d88 AN |
1410 | } |
1411 | ||
69c18c15 | 1412 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1413 | int native_cpu_disable(void) |
69c18c15 GC |
1414 | { |
1415 | return -ENOSYS; | |
1416 | } | |
1417 | ||
93be71b6 | 1418 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1419 | { |
1420 | /* We said "no" in __cpu_disable */ | |
1421 | BUG(); | |
1422 | } | |
a21f5d88 AN |
1423 | |
1424 | void native_play_dead(void) | |
1425 | { | |
1426 | BUG(); | |
1427 | } | |
1428 | ||
68a1c3f8 | 1429 | #endif |