[linux-2.6-block.git] / arch / x86 / kernel / microcode_amd.c

/*
 *  AMD CPU Microcode Update Driver for Linux
 *  Copyright (C) 2008 Advanced Micro Devices Inc.
 *
 *  Author: Peter Oruba <peter.oruba@amd.com>
 *
 *  Based on work by:
 *  Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
 *
 *  This driver allows to upgrade microcode on AMD
 *  family 0x10 and 0x11 processors.
 *
 *  Licensed unter the terms of the GNU General Public
 *  License version 2. See file COPYING for details.
*/

#include <linux/capability.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/miscdevice.h>
#include <linux/spinlock.h>
#include <linux/mm.h>
#include <linux/fs.h>
#include <linux/mutex.h>
#include <linux/cpu.h>
#include <linux/firmware.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>

#include <asm/msr.h>
#include <asm/uaccess.h>
#include <asm/processor.h>
#include <asm/microcode.h>

MODULE_DESCRIPTION("AMD Microcode Update Driver");
MODULE_AUTHOR("Peter Oruba");
MODULE_LICENSE("GPL v2");

#define UCODE_MAGIC                0x00414d44
#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
#define UCODE_UCODE_TYPE           0x00000001

struct equiv_cpu_entry {
	unsigned int installed_cpu;
	unsigned int fixed_errata_mask;
	unsigned int fixed_errata_compare;
	unsigned int equiv_cpu;
};

struct microcode_header_amd {
	unsigned int  data_code;
	unsigned int  patch_id;
	unsigned char mc_patch_data_id[2];
	unsigned char mc_patch_data_len;
	unsigned char init_flag;
	unsigned int  mc_patch_data_checksum;
	unsigned int  nb_dev_id;
	unsigned int  sb_dev_id;
	unsigned char processor_rev_id[2];
	unsigned char nb_rev_id;
	unsigned char sb_rev_id;
	unsigned char bios_api_rev;
	unsigned char reserved1[3];
	unsigned int  match_reg[8];
};

struct microcode_amd {
	struct microcode_header_amd hdr;
	unsigned int mpb[0];
};

#define UCODE_MAX_SIZE          (2048)
#define DEFAULT_UCODE_DATASIZE	(896)
#define MC_HEADER_SIZE		(sizeof(struct microcode_header_amd))
#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
#define DWSIZE			(sizeof(u32))
/* For now we support a fixed ucode total size only */
#define get_totalsize(mc) \
	((((struct microcode_amd *)mc)->hdr.mc_patch_data_len * 28) \
	 + MC_HEADER_SIZE)

/* serialize access to the physical write */
static DEFINE_SPINLOCK(microcode_update_lock);

static struct equiv_cpu_entry *equiv_cpu_table;

static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
{
	struct cpuinfo_x86 *c = &cpu_data(cpu);

	memset(csig, 0, sizeof(*csig));

	if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
		printk(KERN_ERR "microcode: CPU%d not a capable AMD processor\n",
		       cpu);
		return -1;
	}

	asm volatile("movl %1, %%ecx; rdmsr"
		     : "=a" (csig->rev)
		     : "i" (0x0000008B) : "ecx");

	printk(KERN_INFO "microcode: collect_cpu_info_amd : patch_id=0x%x\n",
		csig->rev);

	return 0;
}

static int get_matching_microcode(int cpu, void *mc, int rev)
{
	struct microcode_header_amd *mc_header = mc;
	struct pci_dev *nb_pci_dev, *sb_pci_dev;
	unsigned int current_cpu_id;
	unsigned int equiv_cpu_id = 0x00;
	unsigned int i = 0;

	BUG_ON(equiv_cpu_table == NULL);
	current_cpu_id = cpuid_eax(0x00000001);

	while (equiv_cpu_table[i].installed_cpu != 0) {
		if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
			equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
			break;
		}
		i++;
	}

	if (!equiv_cpu_id) {
		printk(KERN_ERR "microcode: CPU%d cpu_id "
		       "not found in equivalent cpu table \n", cpu);
		return 0;
	}

	if ((mc_header->processor_rev_id[0]) != (equiv_cpu_id & 0xff)) {
		printk(KERN_ERR
			"microcode: CPU%d patch does not match "
			"(patch is %x, cpu extended is %x) \n",
			cpu, mc_header->processor_rev_id[0],
			(equiv_cpu_id & 0xff));
		return 0;
	}

	if ((mc_header->processor_rev_id[1]) != ((equiv_cpu_id >> 16) & 0xff)) {
		printk(KERN_ERR "microcode: CPU%d patch does not match "
			"(patch is %x, cpu base id is %x) \n",
			cpu, mc_header->processor_rev_id[1],
			((equiv_cpu_id >> 16) & 0xff));

		return 0;
	}

	/* ucode may be northbridge specific */
	if (mc_header->nb_dev_id) {
		nb_pci_dev = pci_get_device(PCI_VENDOR_ID_AMD,
					    (mc_header->nb_dev_id & 0xff),
					    NULL);
		if ((!nb_pci_dev) ||
		    (mc_header->nb_rev_id != nb_pci_dev->revision)) {
			printk(KERN_ERR "microcode: CPU%d NB mismatch \n", cpu);
			pci_dev_put(nb_pci_dev);
			return 0;
		}
		pci_dev_put(nb_pci_dev);
	}

	/* ucode may be southbridge specific */
	if (mc_header->sb_dev_id) {
		sb_pci_dev = pci_get_device(PCI_VENDOR_ID_AMD,
					    (mc_header->sb_dev_id & 0xff),
					    NULL);
		if ((!sb_pci_dev) ||
		    (mc_header->sb_rev_id != sb_pci_dev->revision)) {
			printk(KERN_ERR "microcode: CPU%d SB mismatch \n", cpu);
			pci_dev_put(sb_pci_dev);
			return 0;
		}
		pci_dev_put(sb_pci_dev);
	}

	if (mc_header->patch_id <= rev)
		return 0;

	return 1;
}

static void apply_microcode_amd(int cpu)
{
	unsigned long flags;
	unsigned int eax, edx;
	unsigned int rev;
	int cpu_num = raw_smp_processor_id();
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
	struct microcode_amd *mc_amd = uci->mc;
	unsigned long addr;

	/* We should bind the task to the CPU */
	BUG_ON(cpu_num != cpu);

	if (mc_amd == NULL)
		return;

	spin_lock_irqsave(&microcode_update_lock, flags);

	addr = (unsigned long)&mc_amd->hdr.data_code;
	edx = (unsigned int)(((unsigned long)upper_32_bits(addr)));
	eax = (unsigned int)(((unsigned long)lower_32_bits(addr)));

	asm volatile("movl %0, %%ecx; wrmsr" :
		     : "i" (0xc0010020), "a" (eax), "d" (edx) : "ecx");

	/* get patch id after patching */
	asm volatile("movl %1, %%ecx; rdmsr"
		     : "=a" (rev)
		     : "i" (0x0000008B) : "ecx");

	spin_unlock_irqrestore(&microcode_update_lock, flags);

	/* check current patch id and patch's id for match */
	if (rev != mc_amd->hdr.patch_id) {
		printk(KERN_ERR "microcode: CPU%d update from revision "
		       "0x%x to 0x%x failed\n", cpu_num,
		       mc_amd->hdr.patch_id, rev);
		return;
	}

	printk(KERN_INFO "microcode: CPU%d updated from revision "
	       "0x%x to 0x%x \n",
	       cpu_num, uci->cpu_sig.rev, mc_amd->hdr.patch_id);

	uci->cpu_sig.rev = rev;
}

static void * get_next_ucode(u8 *buf, unsigned int size,
			int (*get_ucode_data)(void *, const void *, size_t),
			unsigned int *mc_size)
{
	unsigned int total_size;
#define UCODE_CONTAINER_SECTION_HDR	8
	u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
	void *mc;

	if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
		return NULL;

	if (section_hdr[0] != UCODE_UCODE_TYPE) {
		printk(KERN_ERR "microcode: error! "
		       "Wrong microcode payload type field\n");
		return NULL;
	}

	total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8));

	printk(KERN_INFO "microcode: size %u, total_size %u\n",
		size, total_size);

	if (total_size > size || total_size > UCODE_MAX_SIZE) {
		printk(KERN_ERR "microcode: error! Bad data in microcode data file\n");
		return NULL;
	}

	mc = vmalloc(UCODE_MAX_SIZE);
	if (mc) {
		memset(mc, 0, UCODE_MAX_SIZE);
		if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, total_size)) {
			vfree(mc);
			mc = NULL;
		} else
			*mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
	}
#undef UCODE_CONTAINER_SECTION_HDR
	return mc;
}


static int install_equiv_cpu_table(u8 *buf,
		int (*get_ucode_data)(void *, const void *, size_t))
{
#define UCODE_CONTAINER_HEADER_SIZE	12
	u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE];
	unsigned int *buf_pos = (unsigned int *)container_hdr;
	unsigned long size;

	if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
		return 0;

	size = buf_pos[2];

	if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE || !size) {
		printk(KERN_ERR "microcode: error! "
		       "Wrong microcode equivalnet cpu table\n");
		return 0;
	}

	equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);
	if (!equiv_cpu_table) {
		printk(KERN_ERR "microcode: error, can't allocate memory for equiv CPU table\n");
		return 0;
	}

	buf += UCODE_CONTAINER_HEADER_SIZE;
	if (get_ucode_data(equiv_cpu_table, buf, size)) {
		vfree(equiv_cpu_table);
		return 0;
	}

	return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
#undef UCODE_CONTAINER_HEADER_SIZE
}

static void free_equiv_cpu_table(void)
{
	if (equiv_cpu_table) {
		vfree(equiv_cpu_table);
		equiv_cpu_table = NULL;
	}
}

static int generic_load_microcode(int cpu, void *data, size_t size,
		int (*get_ucode_data)(void *, const void *, size_t))
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	u8 *ucode_ptr = data, *new_mc = NULL, *mc;
	int new_rev = uci->cpu_sig.rev;
	unsigned int leftover;
	unsigned long offset;

	offset = install_equiv_cpu_table(ucode_ptr, get_ucode_data);
	if (!offset) {
		printk(KERN_ERR "microcode: installing equivalent cpu table failed\n");
		return -EINVAL;
	}

	ucode_ptr += offset;
	leftover = size - offset;

	while (leftover) {
		unsigned int uninitialized_var(mc_size);
		struct microcode_header_amd *mc_header;

		mc = get_next_ucode(ucode_ptr, leftover, get_ucode_data, &mc_size);
		if (!mc)
			break;

		mc_header = (struct microcode_header_amd *)mc;
		if (get_matching_microcode(cpu, mc, new_rev)) {
			if (new_mc)
				vfree(new_mc);
			new_rev = mc_header->patch_id;
			new_mc  = mc;
		} else 
			vfree(mc);

		ucode_ptr += mc_size;
		leftover  -= mc_size;
	}

	if (new_mc) {
		if (!leftover) {
			if (uci->mc)
				vfree(uci->mc);
			uci->mc = new_mc;
			pr_debug("microcode: CPU%d found a matching microcode update with"
				" version 0x%x (current=0x%x)\n",
				cpu, new_rev, uci->cpu_sig.rev);
		} else
			vfree(new_mc);
	}

	free_equiv_cpu_table();

	return (int)leftover;
}

static int get_ucode_fw(void *to, const void *from, size_t n)
{
	memcpy(to, from, n);
	return 0;
}

static int request_microcode_fw(int cpu, struct device *device)
{
	const char *fw_name = "amd-ucode/microcode_amd.bin";
	const struct firmware *firmware;
	int ret;

	/* We should bind the task to the CPU */
	BUG_ON(cpu != raw_smp_processor_id());

	ret = request_firmware(&firmware, fw_name, device);
	if (ret) {
		printk(KERN_ERR "microcode: ucode data file %s load failed\n", fw_name);
		return ret;
	}

	ret = generic_load_microcode(cpu, (void*)firmware->data, firmware->size,
			&get_ucode_fw);

	release_firmware(firmware);

	return ret;
}

static int request_microcode_user(int cpu, const void __user *buf, size_t size)
{
	printk(KERN_WARNING "microcode: AMD microcode update via /dev/cpu/microcode"
			"is not supported\n");
	return -1;
}

static void microcode_fini_cpu_amd(int cpu)
{
	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;

	vfree(uci->mc);
	uci->mc = NULL;
}

static struct microcode_ops microcode_amd_ops = {
	.request_microcode_user           = request_microcode_user,
	.request_microcode_fw             = request_microcode_fw,
	.collect_cpu_info                 = collect_cpu_info_amd,
	.apply_microcode                  = apply_microcode_amd,
	.microcode_fini_cpu               = microcode_fini_cpu_amd,
};

struct microcode_ops * __init init_amd_microcode(void)
{
	return &microcode_amd_ops;
}
Commit	Line	Data
80cc9f10 PO	1	/*
	2	* AMD CPU Microcode Update Driver for Linux
	3	* Copyright (C) 2008 Advanced Micro Devices Inc.
	4	*
	5	* Author: Peter Oruba <peter.oruba@amd.com>
	6	*
	7	* Based on work by:
	8	* Tigran Aivazian <tigran@aivazian.fsnet.co.uk>
	9	*
	10	* This driver allows to upgrade microcode on AMD
	11	* family 0x10 and 0x11 processors.
	12	*
	13	* Licensed unter the terms of the GNU General Public
	14	* License version 2. See file COPYING for details.
	15	*/
	16
	17	#include <linux/capability.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/sched.h>
	21	#include <linux/cpumask.h>
	22	#include <linux/module.h>
	23	#include <linux/slab.h>
	24	#include <linux/vmalloc.h>
	25	#include <linux/miscdevice.h>
	26	#include <linux/spinlock.h>
	27	#include <linux/mm.h>
	28	#include <linux/fs.h>
	29	#include <linux/mutex.h>
	30	#include <linux/cpu.h>
	31	#include <linux/firmware.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/pci.h>
	34	#include <linux/pci_ids.h>
	35
	36	#include <asm/msr.h>
	37	#include <asm/uaccess.h>
	38	#include <asm/processor.h>
	39	#include <asm/microcode.h>
	40
	41	MODULE_DESCRIPTION("AMD Microcode Update Driver");
3c52204b	42	MODULE_AUTHOR("Peter Oruba");
5d7b6052	43	MODULE_LICENSE("GPL v2");
80cc9f10 PO	44
	45	#define UCODE_MAGIC 0x00414d44
	46	#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
	47	#define UCODE_UCODE_TYPE 0x00000001
	48
18dbc916 DA	49	struct equiv_cpu_entry {
	50	unsigned int installed_cpu;
	51	unsigned int fixed_errata_mask;
	52	unsigned int fixed_errata_compare;
	53	unsigned int equiv_cpu;
	54	};
	55
	56	struct microcode_header_amd {
	57	unsigned int data_code;
	58	unsigned int patch_id;
	59	unsigned char mc_patch_data_id[2];
	60	unsigned char mc_patch_data_len;
	61	unsigned char init_flag;
	62	unsigned int mc_patch_data_checksum;
	63	unsigned int nb_dev_id;
	64	unsigned int sb_dev_id;
	65	unsigned char processor_rev_id[2];
	66	unsigned char nb_rev_id;
	67	unsigned char sb_rev_id;
	68	unsigned char bios_api_rev;
	69	unsigned char reserved1[3];
	70	unsigned int match_reg[8];
	71	};
	72
	73	struct microcode_amd {
	74	struct microcode_header_amd hdr;
	75	unsigned int mpb[0];
	76	};
	77
80cc9f10	78	#define UCODE_MAX_SIZE (2048)
a0ac87d6 PO	79	#define DEFAULT_UCODE_DATASIZE (896)
	80	#define MC_HEADER_SIZE (sizeof(struct microcode_header_amd))
	81	#define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
80cc9f10 PO	82	#define DWSIZE (sizeof(u32))
	83	/* For now we support a fixed ucode total size only */
	84	#define get_totalsize(mc) \
	85	((((struct microcode_amd )mc)->hdr.mc_patch_data_len 28) \
	86	+ MC_HEADER_SIZE)
	87
80cc9f10 PO	88	/* serialize access to the physical write */
	89	static DEFINE_SPINLOCK(microcode_update_lock);
	90
a0a29b62	91	static struct equiv_cpu_entry *equiv_cpu_table;
80cc9f10	92
d45de409	93	static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
80cc9f10 PO	94	{
80cc9f10 PO	95	struct cpuinfo_x86 *c = &cpu_data(cpu);
80cc9f10	96
d45de409	97	memset(csig, 0, sizeof(*csig));
80cc9f10 PO	98
	99	if (c->x86_vendor != X86_VENDOR_AMD \|\| c->x86 < 0x10) {
	100	printk(KERN_ERR "microcode: CPU%d not a capable AMD processor\n",
	101	cpu);
d45de409	102	return -1;
80cc9f10 PO	103	}
	104
	105	asm volatile("movl %1, %%ecx; rdmsr"
d45de409	106	: "=a" (csig->rev)
80cc9f10 PO	107	: "i" (0x0000008B) : "ecx");
	108
	109	printk(KERN_INFO "microcode: collect_cpu_info_amd : patch_id=0x%x\n",
d45de409 DA	110	csig->rev);
	111
	112	return 0;
80cc9f10 PO	113	}
80cc9f10 PO	114
a0a29b62	115	static int get_matching_microcode(int cpu, void *mc, int rev)
80cc9f10	116	{
80cc9f10	117	struct microcode_header_amd *mc_header = mc;
80cc9f10 PO	118	struct pci_dev nb_pci_dev, sb_pci_dev;
	119	unsigned int current_cpu_id;
	120	unsigned int equiv_cpu_id = 0x00;
	121	unsigned int i = 0;
	122
a0a29b62	123	BUG_ON(equiv_cpu_table == NULL);
80cc9f10 PO	124	current_cpu_id = cpuid_eax(0x00000001);
	125
	126	while (equiv_cpu_table[i].installed_cpu != 0) {
	127	if (current_cpu_id == equiv_cpu_table[i].installed_cpu) {
	128	equiv_cpu_id = equiv_cpu_table[i].equiv_cpu;
	129	break;
	130	}
	131	i++;
	132	}
	133
	134	if (!equiv_cpu_id) {
	135	printk(KERN_ERR "microcode: CPU%d cpu_id "
	136	"not found in equivalent cpu table \n", cpu);
	137	return 0;
	138	}
	139
	140	if ((mc_header->processor_rev_id[0]) != (equiv_cpu_id & 0xff)) {
	141	printk(KERN_ERR
	142	"microcode: CPU%d patch does not match "
	143	"(patch is %x, cpu extended is %x) \n",
	144	cpu, mc_header->processor_rev_id[0],
	145	(equiv_cpu_id & 0xff));
	146	return 0;
	147	}
	148
	149	if ((mc_header->processor_rev_id[1]) != ((equiv_cpu_id >> 16) & 0xff)) {
	150	printk(KERN_ERR "microcode: CPU%d patch does not match "
	151	"(patch is %x, cpu base id is %x) \n",
	152	cpu, mc_header->processor_rev_id[1],
	153	((equiv_cpu_id >> 16) & 0xff));
	154
	155	return 0;
	156	}
	157
	158	/* ucode may be northbridge specific */
	159	if (mc_header->nb_dev_id) {
	160	nb_pci_dev = pci_get_device(PCI_VENDOR_ID_AMD,
	161	(mc_header->nb_dev_id & 0xff),
	162	NULL);
	163	if ((!nb_pci_dev) \|\|
	164	(mc_header->nb_rev_id != nb_pci_dev->revision)) {
	165	printk(KERN_ERR "microcode: CPU%d NB mismatch \n", cpu);
	166	pci_dev_put(nb_pci_dev);
	167	return 0;
	168	}
	169	pci_dev_put(nb_pci_dev);
	170	}
	171
	172	/* ucode may be southbridge specific */
	173	if (mc_header->sb_dev_id) {
	174	sb_pci_dev = pci_get_device(PCI_VENDOR_ID_AMD,
	175	(mc_header->sb_dev_id & 0xff),
	176	NULL);
	177	if ((!sb_pci_dev) \|\|
	178	(mc_header->sb_rev_id != sb_pci_dev->revision)) {
	179	printk(KERN_ERR "microcode: CPU%d SB mismatch \n", cpu);
	180	pci_dev_put(sb_pci_dev);
	181	return 0;
	182	}
	183	pci_dev_put(sb_pci_dev);
	184	}
	185
a0a29b62	186	if (mc_header->patch_id <= rev)
80cc9f10 PO	187	return 0;
80cc9f10 PO	188
80cc9f10 PO	189	return 1;
	190	}
	191
	192	static void apply_microcode_amd(int cpu)
	193	{
	194	unsigned long flags;
	195	unsigned int eax, edx;
	196	unsigned int rev;
	197	int cpu_num = raw_smp_processor_id();
	198	struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
18dbc916	199	struct microcode_amd *mc_amd = uci->mc;
5b792d32	200	unsigned long addr;
80cc9f10 PO	201
	202	/* We should bind the task to the CPU */
	203	BUG_ON(cpu_num != cpu);
	204
18dbc916	205	if (mc_amd == NULL)
80cc9f10 PO	206	return;
	207
	208	spin_lock_irqsave(&microcode_update_lock, flags);
	209
18dbc916	210	addr = (unsigned long)&mc_amd->hdr.data_code;
5b792d32 RD	211	edx = (unsigned int)(((unsigned long)upper_32_bits(addr)));
5b792d32 RD	212	eax = (unsigned int)(((unsigned long)lower_32_bits(addr)));
80cc9f10 PO	213
	214	asm volatile("movl %0, %%ecx; wrmsr" :
	215	: "i" (0xc0010020), "a" (eax), "d" (edx) : "ecx");
	216
	217	/* get patch id after patching */
	218	asm volatile("movl %1, %%ecx; rdmsr"
	219	: "=a" (rev)
	220	: "i" (0x0000008B) : "ecx");
	221
	222	spin_unlock_irqrestore(&microcode_update_lock, flags);
	223
	224	/* check current patch id and patch's id for match */
18dbc916	225	if (rev != mc_amd->hdr.patch_id) {
80cc9f10 PO	226	printk(KERN_ERR "microcode: CPU%d update from revision "
80cc9f10 PO	227	"0x%x to 0x%x failed\n", cpu_num,
18dbc916	228	mc_amd->hdr.patch_id, rev);
80cc9f10 PO	229	return;
	230	}
	231
	232	printk(KERN_INFO "microcode: CPU%d updated from revision "
	233	"0x%x to 0x%x \n",
18dbc916	234	cpu_num, uci->cpu_sig.rev, mc_amd->hdr.patch_id);
80cc9f10	235
d45de409	236	uci->cpu_sig.rev = rev;
80cc9f10 PO	237	}
80cc9f10 PO	238
a0a29b62 DA	239	static void * get_next_ucode(u8 *buf, unsigned int size,
	240	int (get_ucode_data)(void , const void *, size_t),
	241	unsigned int *mc_size)
80cc9f10	242	{
a0a29b62	243	unsigned int total_size;
d4738792 PO	244	#define UCODE_CONTAINER_SECTION_HDR 8
d4738792 PO	245	u8 section_hdr[UCODE_CONTAINER_SECTION_HDR];
a0a29b62	246	void *mc;
80cc9f10	247
d4738792	248	if (get_ucode_data(section_hdr, buf, UCODE_CONTAINER_SECTION_HDR))
a0a29b62	249	return NULL;
80cc9f10	250
d4738792	251	if (section_hdr[0] != UCODE_UCODE_TYPE) {
80cc9f10 PO	252	printk(KERN_ERR "microcode: error! "
80cc9f10 PO	253	"Wrong microcode payload type field\n");
a0a29b62	254	return NULL;
80cc9f10 PO	255	}
80cc9f10 PO	256
d4738792	257	total_size = (unsigned long) (section_hdr[4] + (section_hdr[5] << 8));
80cc9f10	258
a0a29b62 DA	259	printk(KERN_INFO "microcode: size %u, total_size %u\n",
a0a29b62 DA	260	size, total_size);
80cc9f10	261
a0a29b62	262	if (total_size > size \|\| total_size > UCODE_MAX_SIZE) {
80cc9f10	263	printk(KERN_ERR "microcode: error! Bad data in microcode data file\n");
a0a29b62	264	return NULL;
80cc9f10 PO	265	}
80cc9f10 PO	266
a0a29b62 DA	267	mc = vmalloc(UCODE_MAX_SIZE);
	268	if (mc) {
	269	memset(mc, 0, UCODE_MAX_SIZE);
d4738792	270	if (get_ucode_data(mc, buf + UCODE_CONTAINER_SECTION_HDR, total_size)) {
a0a29b62 DA	271	vfree(mc);
	272	mc = NULL;
	273	} else
d4738792	274	*mc_size = total_size + UCODE_CONTAINER_SECTION_HDR;
80cc9f10	275	}
d4738792	276	#undef UCODE_CONTAINER_SECTION_HDR
a0a29b62	277	return mc;
80cc9f10 PO	278	}
80cc9f10 PO	279
a0a29b62 DA	280
	281	static int install_equiv_cpu_table(u8 *buf,
	282	int (get_ucode_data)(void , const void *, size_t))
80cc9f10	283	{
b6cffde1 PO	284	#define UCODE_CONTAINER_HEADER_SIZE 12
	285	u8 *container_hdr[UCODE_CONTAINER_HEADER_SIZE];
	286	unsigned int buf_pos = (unsigned int )container_hdr;
a0a29b62	287	unsigned long size;
80cc9f10	288
b6cffde1	289	if (get_ucode_data(&container_hdr, buf, UCODE_CONTAINER_HEADER_SIZE))
80cc9f10 PO	290	return 0;
80cc9f10 PO	291
a0a29b62	292	size = buf_pos[2];
80cc9f10	293
a0a29b62	294	if (buf_pos[1] != UCODE_EQUIV_CPU_TABLE_TYPE \|\| !size) {
80cc9f10	295	printk(KERN_ERR "microcode: error! "
a0a29b62	296	"Wrong microcode equivalnet cpu table\n");
80cc9f10 PO	297	return 0;
	298	}
	299
	300	equiv_cpu_table = (struct equiv_cpu_entry *) vmalloc(size);
	301	if (!equiv_cpu_table) {
	302	printk(KERN_ERR "microcode: error, can't allocate memory for equiv CPU table\n");
	303	return 0;
	304	}
	305
b6cffde1	306	buf += UCODE_CONTAINER_HEADER_SIZE;
a0a29b62 DA	307	if (get_ucode_data(equiv_cpu_table, buf, size)) {
	308	vfree(equiv_cpu_table);
	309	return 0;
	310	}
80cc9f10	311
b6cffde1 PO	312	return size + UCODE_CONTAINER_HEADER_SIZE; /* add header length */
b6cffde1 PO	313	#undef UCODE_CONTAINER_HEADER_SIZE
80cc9f10 PO	314	}
80cc9f10 PO	315
a0a29b62	316	static void free_equiv_cpu_table(void)
80cc9f10	317	{
a0a29b62 DA	318	if (equiv_cpu_table) {
	319	vfree(equiv_cpu_table);
	320	equiv_cpu_table = NULL;
80cc9f10	321	}
a0a29b62	322	}
80cc9f10	323
a0a29b62 DA	324	static int generic_load_microcode(int cpu, void *data, size_t size,
	325	int (get_ucode_data)(void , const void *, size_t))
	326	{
	327	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	328	u8 ucode_ptr = data, new_mc = NULL, *mc;
	329	int new_rev = uci->cpu_sig.rev;
	330	unsigned int leftover;
	331	unsigned long offset;
80cc9f10	332
a0a29b62	333	offset = install_equiv_cpu_table(ucode_ptr, get_ucode_data);
80cc9f10 PO	334	if (!offset) {
	335	printk(KERN_ERR "microcode: installing equivalent cpu table failed\n");
	336	return -EINVAL;
	337	}
	338
a0a29b62 DA	339	ucode_ptr += offset;
	340	leftover = size - offset;
	341
	342	while (leftover) {
2f9284e4	343	unsigned int uninitialized_var(mc_size);
a0a29b62 DA	344	struct microcode_header_amd *mc_header;
	345
	346	mc = get_next_ucode(ucode_ptr, leftover, get_ucode_data, &mc_size);
	347	if (!mc)
80cc9f10	348	break;
a0a29b62 DA	349
	350	mc_header = (struct microcode_header_amd *)mc;
	351	if (get_matching_microcode(cpu, mc, new_rev)) {
a1c75cc5 IM	352	if (new_mc)
a1c75cc5 IM	353	vfree(new_mc);
a0a29b62 DA	354	new_rev = mc_header->patch_id;
	355	new_mc = mc;
	356	} else
	357	vfree(mc);
	358
	359	ucode_ptr += mc_size;
	360	leftover -= mc_size;
80cc9f10	361	}
a0a29b62 DA	362
	363	if (new_mc) {
	364	if (!leftover) {
18dbc916 DA	365	if (uci->mc)
	366	vfree(uci->mc);
	367	uci->mc = new_mc;
a0a29b62 DA	368	pr_debug("microcode: CPU%d found a matching microcode update with"
a0a29b62 DA	369	" version 0x%x (current=0x%x)\n",
18dbc916	370	cpu, new_rev, uci->cpu_sig.rev);
a0a29b62 DA	371	} else
a0a29b62 DA	372	vfree(new_mc);
80cc9f10	373	}
a0a29b62 DA	374
	375	free_equiv_cpu_table();
	376
	377	return (int)leftover;
	378	}
	379
	380	static int get_ucode_fw(void to, const void from, size_t n)
	381	{
	382	memcpy(to, from, n);
	383	return 0;
	384	}
	385
	386	static int request_microcode_fw(int cpu, struct device *device)
	387	{
	388	const char *fw_name = "amd-ucode/microcode_amd.bin";
	389	const struct firmware *firmware;
	390	int ret;
	391
	392	/* We should bind the task to the CPU */
	393	BUG_ON(cpu != raw_smp_processor_id());
	394
	395	ret = request_firmware(&firmware, fw_name, device);
	396	if (ret) {
	397	printk(KERN_ERR "microcode: ucode data file %s load failed\n", fw_name);
	398	return ret;
	399	}
	400
	401	ret = generic_load_microcode(cpu, (void*)firmware->data, firmware->size,
	402	&get_ucode_fw);
	403
80cc9f10 PO	404	release_firmware(firmware);
80cc9f10 PO	405
a0a29b62 DA	406	return ret;
	407	}
	408
a0a29b62 DA	409	static int request_microcode_user(int cpu, const void __user *buf, size_t size)
a0a29b62 DA	410	{
2f9284e4 DA	411	printk(KERN_WARNING "microcode: AMD microcode update via /dev/cpu/microcode"
	412	"is not supported\n");
	413	return -1;
80cc9f10 PO	414	}
80cc9f10 PO	415
80cc9f10 PO	416	static void microcode_fini_cpu_amd(int cpu)
	417	{
	418	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
	419
18dbc916 DA	420	vfree(uci->mc);
18dbc916 DA	421	uci->mc = NULL;
80cc9f10 PO	422	}
	423
	424	static struct microcode_ops microcode_amd_ops = {
a0a29b62 DA	425	.request_microcode_user = request_microcode_user,
a0a29b62 DA	426	.request_microcode_fw = request_microcode_fw,
80cc9f10 PO	427	.collect_cpu_info = collect_cpu_info_amd,
	428	.apply_microcode = apply_microcode_amd,
	429	.microcode_fini_cpu = microcode_fini_cpu_amd,
	430	};
	431
18dbc916	432	struct microcode_ops * __init init_amd_microcode(void)
80cc9f10	433	{
18dbc916	434	return &microcode_amd_ops;
80cc9f10	435	}