Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
129f6946 | 8 | #include <linux/module.h> |
44210111 | 9 | #include <linux/regset.h> |
f668964e IM |
10 | #include <linux/sched.h> |
11 | ||
12 | #include <asm/sigcontext.h> | |
1da177e4 | 13 | #include <asm/processor.h> |
1da177e4 | 14 | #include <asm/math_emu.h> |
1da177e4 | 15 | #include <asm/uaccess.h> |
f668964e IM |
16 | #include <asm/ptrace.h> |
17 | #include <asm/i387.h> | |
18 | #include <asm/user.h> | |
1da177e4 | 19 | |
44210111 | 20 | #ifdef CONFIG_X86_64 |
f668964e IM |
21 | # include <asm/sigcontext32.h> |
22 | # include <asm/user32.h> | |
44210111 | 23 | #else |
f668964e IM |
24 | # define save_i387_ia32 save_i387 |
25 | # define restore_i387_ia32 restore_i387 | |
26 | # define _fpstate_ia32 _fpstate | |
27 | # define user_i387_ia32_struct user_i387_struct | |
28 | # define user32_fxsr_struct user_fxsr_struct | |
44210111 RM |
29 | #endif |
30 | ||
1da177e4 | 31 | #ifdef CONFIG_MATH_EMULATION |
f668964e | 32 | # define HAVE_HWFP (boot_cpu_data.hard_math) |
1da177e4 | 33 | #else |
f668964e | 34 | # define HAVE_HWFP 1 |
1da177e4 LT |
35 | #endif |
36 | ||
f668964e | 37 | static unsigned int mxcsr_feature_mask __read_mostly = 0xffffffffu; |
61c4628b SS |
38 | unsigned int xstate_size; |
39 | static struct i387_fxsave_struct fx_scratch __cpuinitdata; | |
1da177e4 | 40 | |
61c4628b | 41 | void __cpuinit mxcsr_feature_mask_init(void) |
1da177e4 LT |
42 | { |
43 | unsigned long mask = 0; | |
f668964e | 44 | |
1da177e4 LT |
45 | clts(); |
46 | if (cpu_has_fxsr) { | |
61c4628b SS |
47 | memset(&fx_scratch, 0, sizeof(struct i387_fxsave_struct)); |
48 | asm volatile("fxsave %0" : : "m" (fx_scratch)); | |
49 | mask = fx_scratch.mxcsr_mask; | |
3b095a04 CG |
50 | if (mask == 0) |
51 | mask = 0x0000ffbf; | |
52 | } | |
1da177e4 LT |
53 | mxcsr_feature_mask &= mask; |
54 | stts(); | |
55 | } | |
56 | ||
61c4628b SS |
57 | void __init init_thread_xstate(void) |
58 | { | |
e8a496ac SS |
59 | if (!HAVE_HWFP) { |
60 | xstate_size = sizeof(struct i387_soft_struct); | |
61 | return; | |
62 | } | |
63 | ||
dc1e35c6 SS |
64 | if (cpu_has_xsave) { |
65 | xsave_cntxt_init(); | |
66 | return; | |
67 | } | |
68 | ||
61c4628b SS |
69 | if (cpu_has_fxsr) |
70 | xstate_size = sizeof(struct i387_fxsave_struct); | |
71 | #ifdef CONFIG_X86_32 | |
72 | else | |
73 | xstate_size = sizeof(struct i387_fsave_struct); | |
74 | #endif | |
61c4628b SS |
75 | } |
76 | ||
44210111 RM |
77 | #ifdef CONFIG_X86_64 |
78 | /* | |
79 | * Called at bootup to set up the initial FPU state that is later cloned | |
80 | * into all processes. | |
81 | */ | |
82 | void __cpuinit fpu_init(void) | |
83 | { | |
84 | unsigned long oldcr0 = read_cr0(); | |
f668964e | 85 | |
44210111 RM |
86 | set_in_cr4(X86_CR4_OSFXSR); |
87 | set_in_cr4(X86_CR4_OSXMMEXCPT); | |
88 | ||
f668964e | 89 | write_cr0(oldcr0 & ~(X86_CR0_TS|X86_CR0_EM)); /* clear TS and EM */ |
44210111 | 90 | |
dc1e35c6 SS |
91 | /* |
92 | * Boot processor to setup the FP and extended state context info. | |
93 | */ | |
94 | if (!smp_processor_id()) | |
95 | init_thread_xstate(); | |
96 | xsave_init(); | |
97 | ||
44210111 RM |
98 | mxcsr_feature_mask_init(); |
99 | /* clean state in init */ | |
b359e8a4 SS |
100 | if (cpu_has_xsave) |
101 | current_thread_info()->status = TS_XSAVE; | |
102 | else | |
103 | current_thread_info()->status = 0; | |
44210111 RM |
104 | clear_used_math(); |
105 | } | |
106 | #endif /* CONFIG_X86_64 */ | |
107 | ||
1da177e4 LT |
108 | /* |
109 | * The _current_ task is using the FPU for the first time | |
110 | * so initialize it and set the mxcsr to its default | |
111 | * value at reset if we support XMM instructions and then | |
112 | * remeber the current task has used the FPU. | |
113 | */ | |
aa283f49 | 114 | int init_fpu(struct task_struct *tsk) |
1da177e4 | 115 | { |
44210111 | 116 | if (tsk_used_math(tsk)) { |
e8a496ac | 117 | if (HAVE_HWFP && tsk == current) |
44210111 | 118 | unlazy_fpu(tsk); |
aa283f49 SS |
119 | return 0; |
120 | } | |
121 | ||
122 | /* | |
123 | * Memory allocation at the first usage of the FPU and other state. | |
124 | */ | |
125 | if (!tsk->thread.xstate) { | |
126 | tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep, | |
127 | GFP_KERNEL); | |
128 | if (!tsk->thread.xstate) | |
129 | return -ENOMEM; | |
44210111 RM |
130 | } |
131 | ||
e8a496ac SS |
132 | #ifdef CONFIG_X86_32 |
133 | if (!HAVE_HWFP) { | |
134 | memset(tsk->thread.xstate, 0, xstate_size); | |
135 | finit(); | |
136 | set_stopped_child_used_math(tsk); | |
137 | return 0; | |
138 | } | |
139 | #endif | |
140 | ||
1da177e4 | 141 | if (cpu_has_fxsr) { |
61c4628b SS |
142 | struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave; |
143 | ||
144 | memset(fx, 0, xstate_size); | |
145 | fx->cwd = 0x37f; | |
1da177e4 | 146 | if (cpu_has_xmm) |
61c4628b | 147 | fx->mxcsr = MXCSR_DEFAULT; |
1da177e4 | 148 | } else { |
61c4628b SS |
149 | struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave; |
150 | memset(fp, 0, xstate_size); | |
151 | fp->cwd = 0xffff037fu; | |
152 | fp->swd = 0xffff0000u; | |
153 | fp->twd = 0xffffffffu; | |
154 | fp->fos = 0xffff0000u; | |
1da177e4 | 155 | } |
44210111 RM |
156 | /* |
157 | * Only the device not available exception or ptrace can call init_fpu. | |
158 | */ | |
1da177e4 | 159 | set_stopped_child_used_math(tsk); |
aa283f49 | 160 | return 0; |
1da177e4 LT |
161 | } |
162 | ||
44210111 RM |
163 | int fpregs_active(struct task_struct *target, const struct user_regset *regset) |
164 | { | |
165 | return tsk_used_math(target) ? regset->n : 0; | |
166 | } | |
1da177e4 | 167 | |
44210111 | 168 | int xfpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 169 | { |
44210111 RM |
170 | return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0; |
171 | } | |
1da177e4 | 172 | |
44210111 RM |
173 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
174 | unsigned int pos, unsigned int count, | |
175 | void *kbuf, void __user *ubuf) | |
176 | { | |
aa283f49 SS |
177 | int ret; |
178 | ||
44210111 RM |
179 | if (!cpu_has_fxsr) |
180 | return -ENODEV; | |
181 | ||
aa283f49 SS |
182 | ret = init_fpu(target); |
183 | if (ret) | |
184 | return ret; | |
44210111 RM |
185 | |
186 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
61c4628b | 187 | &target->thread.xstate->fxsave, 0, -1); |
1da177e4 | 188 | } |
44210111 RM |
189 | |
190 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
191 | unsigned int pos, unsigned int count, | |
192 | const void *kbuf, const void __user *ubuf) | |
193 | { | |
194 | int ret; | |
195 | ||
196 | if (!cpu_has_fxsr) | |
197 | return -ENODEV; | |
198 | ||
aa283f49 SS |
199 | ret = init_fpu(target); |
200 | if (ret) | |
201 | return ret; | |
202 | ||
44210111 RM |
203 | set_stopped_child_used_math(target); |
204 | ||
205 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
61c4628b | 206 | &target->thread.xstate->fxsave, 0, -1); |
44210111 RM |
207 | |
208 | /* | |
209 | * mxcsr reserved bits must be masked to zero for security reasons. | |
210 | */ | |
61c4628b | 211 | target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 RM |
212 | |
213 | return ret; | |
214 | } | |
215 | ||
216 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION | |
1da177e4 | 217 | |
1da177e4 LT |
218 | /* |
219 | * FPU tag word conversions. | |
220 | */ | |
221 | ||
3b095a04 | 222 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
223 | { |
224 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 225 | |
1da177e4 | 226 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 227 | tmp = ~twd; |
44210111 | 228 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
229 | /* and move the valid bits to the lower byte. */ |
230 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
231 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
232 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 233 | |
3b095a04 | 234 | return tmp; |
1da177e4 LT |
235 | } |
236 | ||
1da177e4 | 237 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16); |
44210111 RM |
238 | #define FP_EXP_TAG_VALID 0 |
239 | #define FP_EXP_TAG_ZERO 1 | |
240 | #define FP_EXP_TAG_SPECIAL 2 | |
241 | #define FP_EXP_TAG_EMPTY 3 | |
242 | ||
243 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
244 | { | |
245 | struct _fpxreg *st; | |
246 | u32 tos = (fxsave->swd >> 11) & 7; | |
247 | u32 twd = (unsigned long) fxsave->twd; | |
248 | u32 tag; | |
249 | u32 ret = 0xffff0000u; | |
250 | int i; | |
1da177e4 | 251 | |
44210111 | 252 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
253 | if (twd & 0x1) { |
254 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 255 | |
3b095a04 | 256 | switch (st->exponent & 0x7fff) { |
1da177e4 | 257 | case 0x7fff: |
44210111 | 258 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
259 | break; |
260 | case 0x0000: | |
3b095a04 CG |
261 | if (!st->significand[0] && |
262 | !st->significand[1] && | |
263 | !st->significand[2] && | |
44210111 RM |
264 | !st->significand[3]) |
265 | tag = FP_EXP_TAG_ZERO; | |
266 | else | |
267 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
268 | break; |
269 | default: | |
44210111 RM |
270 | if (st->significand[3] & 0x8000) |
271 | tag = FP_EXP_TAG_VALID; | |
272 | else | |
273 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
274 | break; |
275 | } | |
276 | } else { | |
44210111 | 277 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 278 | } |
44210111 | 279 | ret |= tag << (2 * i); |
1da177e4 LT |
280 | } |
281 | return ret; | |
282 | } | |
283 | ||
284 | /* | |
44210111 | 285 | * FXSR floating point environment conversions. |
1da177e4 LT |
286 | */ |
287 | ||
f668964e IM |
288 | static void |
289 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) | |
1da177e4 | 290 | { |
61c4628b | 291 | struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave; |
44210111 RM |
292 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
293 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
294 | int i; | |
1da177e4 | 295 | |
44210111 RM |
296 | env->cwd = fxsave->cwd | 0xffff0000u; |
297 | env->swd = fxsave->swd | 0xffff0000u; | |
298 | env->twd = twd_fxsr_to_i387(fxsave); | |
299 | ||
300 | #ifdef CONFIG_X86_64 | |
301 | env->fip = fxsave->rip; | |
302 | env->foo = fxsave->rdp; | |
303 | if (tsk == current) { | |
304 | /* | |
305 | * should be actually ds/cs at fpu exception time, but | |
306 | * that information is not available in 64bit mode. | |
307 | */ | |
f668964e IM |
308 | asm("mov %%ds, %[fos]" : [fos] "=r" (env->fos)); |
309 | asm("mov %%cs, %[fcs]" : [fcs] "=r" (env->fcs)); | |
1da177e4 | 310 | } else { |
44210111 | 311 | struct pt_regs *regs = task_pt_regs(tsk); |
f668964e | 312 | |
44210111 RM |
313 | env->fos = 0xffff0000 | tsk->thread.ds; |
314 | env->fcs = regs->cs; | |
1da177e4 | 315 | } |
44210111 RM |
316 | #else |
317 | env->fip = fxsave->fip; | |
609b5297 | 318 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
319 | env->foo = fxsave->foo; |
320 | env->fos = fxsave->fos; | |
321 | #endif | |
1da177e4 | 322 | |
44210111 RM |
323 | for (i = 0; i < 8; ++i) |
324 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
325 | } |
326 | ||
44210111 RM |
327 | static void convert_to_fxsr(struct task_struct *tsk, |
328 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 329 | |
1da177e4 | 330 | { |
61c4628b | 331 | struct i387_fxsave_struct *fxsave = &tsk->thread.xstate->fxsave; |
44210111 RM |
332 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
333 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
334 | int i; | |
1da177e4 | 335 | |
44210111 RM |
336 | fxsave->cwd = env->cwd; |
337 | fxsave->swd = env->swd; | |
338 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
339 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
340 | #ifdef CONFIG_X86_64 | |
341 | fxsave->rip = env->fip; | |
342 | fxsave->rdp = env->foo; | |
343 | /* cs and ds ignored */ | |
344 | #else | |
345 | fxsave->fip = env->fip; | |
346 | fxsave->fcs = (env->fcs & 0xffff); | |
347 | fxsave->foo = env->foo; | |
348 | fxsave->fos = env->fos; | |
349 | #endif | |
1da177e4 | 350 | |
44210111 RM |
351 | for (i = 0; i < 8; ++i) |
352 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
353 | } |
354 | ||
44210111 RM |
355 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
356 | unsigned int pos, unsigned int count, | |
357 | void *kbuf, void __user *ubuf) | |
1da177e4 | 358 | { |
44210111 | 359 | struct user_i387_ia32_struct env; |
aa283f49 | 360 | int ret; |
1da177e4 | 361 | |
aa283f49 SS |
362 | ret = init_fpu(target); |
363 | if (ret) | |
364 | return ret; | |
1da177e4 | 365 | |
e8a496ac SS |
366 | if (!HAVE_HWFP) |
367 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); | |
368 | ||
f668964e | 369 | if (!cpu_has_fxsr) { |
44210111 | 370 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
61c4628b SS |
371 | &target->thread.xstate->fsave, 0, |
372 | -1); | |
f668964e | 373 | } |
1da177e4 | 374 | |
44210111 RM |
375 | if (kbuf && pos == 0 && count == sizeof(env)) { |
376 | convert_from_fxsr(kbuf, target); | |
377 | return 0; | |
1da177e4 | 378 | } |
44210111 RM |
379 | |
380 | convert_from_fxsr(&env, target); | |
f668964e | 381 | |
44210111 | 382 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
383 | } |
384 | ||
44210111 RM |
385 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
386 | unsigned int pos, unsigned int count, | |
387 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 388 | { |
44210111 RM |
389 | struct user_i387_ia32_struct env; |
390 | int ret; | |
1da177e4 | 391 | |
aa283f49 SS |
392 | ret = init_fpu(target); |
393 | if (ret) | |
394 | return ret; | |
395 | ||
44210111 RM |
396 | set_stopped_child_used_math(target); |
397 | ||
e8a496ac SS |
398 | if (!HAVE_HWFP) |
399 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); | |
400 | ||
f668964e | 401 | if (!cpu_has_fxsr) { |
44210111 | 402 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
61c4628b | 403 | &target->thread.xstate->fsave, 0, -1); |
f668964e | 404 | } |
44210111 RM |
405 | |
406 | if (pos > 0 || count < sizeof(env)) | |
407 | convert_from_fxsr(&env, target); | |
408 | ||
409 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
410 | if (!ret) | |
411 | convert_to_fxsr(target, &env); | |
412 | ||
413 | return ret; | |
1da177e4 LT |
414 | } |
415 | ||
416 | /* | |
417 | * Signal frame handlers. | |
418 | */ | |
419 | ||
44210111 | 420 | static inline int save_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
421 | { |
422 | struct task_struct *tsk = current; | |
61c4628b | 423 | struct i387_fsave_struct *fp = &tsk->thread.xstate->fsave; |
1da177e4 | 424 | |
3b095a04 | 425 | unlazy_fpu(tsk); |
61c4628b SS |
426 | fp->status = fp->swd; |
427 | if (__copy_to_user(buf, fp, sizeof(struct i387_fsave_struct))) | |
1da177e4 LT |
428 | return -1; |
429 | return 1; | |
430 | } | |
431 | ||
44210111 | 432 | static int save_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
433 | { |
434 | struct task_struct *tsk = current; | |
61c4628b | 435 | struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave; |
44210111 | 436 | struct user_i387_ia32_struct env; |
1da177e4 LT |
437 | int err = 0; |
438 | ||
3b095a04 | 439 | unlazy_fpu(tsk); |
1da177e4 | 440 | |
44210111 RM |
441 | convert_from_fxsr(&env, tsk); |
442 | if (__copy_to_user(buf, &env, sizeof(env))) | |
1da177e4 LT |
443 | return -1; |
444 | ||
61c4628b | 445 | err |= __put_user(fx->swd, &buf->status); |
3b095a04 CG |
446 | err |= __put_user(X86_FXSR_MAGIC, &buf->magic); |
447 | if (err) | |
1da177e4 LT |
448 | return -1; |
449 | ||
61c4628b | 450 | if (__copy_to_user(&buf->_fxsr_env[0], fx, |
3b095a04 | 451 | sizeof(struct i387_fxsave_struct))) |
1da177e4 LT |
452 | return -1; |
453 | return 1; | |
454 | } | |
455 | ||
44210111 | 456 | int save_i387_ia32(struct _fpstate_ia32 __user *buf) |
1da177e4 | 457 | { |
3b095a04 | 458 | if (!used_math()) |
1da177e4 | 459 | return 0; |
f668964e IM |
460 | /* |
461 | * This will cause a "finit" to be triggered by the next | |
1da177e4 LT |
462 | * attempted FPU operation by the 'current' process. |
463 | */ | |
464 | clear_used_math(); | |
465 | ||
f668964e | 466 | if (!HAVE_HWFP) { |
44210111 RM |
467 | return fpregs_soft_get(current, NULL, |
468 | 0, sizeof(struct user_i387_ia32_struct), | |
469 | NULL, buf) ? -1 : 1; | |
1da177e4 | 470 | } |
f668964e IM |
471 | |
472 | if (cpu_has_fxsr) | |
473 | return save_i387_fxsave(buf); | |
474 | else | |
475 | return save_i387_fsave(buf); | |
1da177e4 LT |
476 | } |
477 | ||
44210111 | 478 | static inline int restore_i387_fsave(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
479 | { |
480 | struct task_struct *tsk = current; | |
f668964e | 481 | |
61c4628b | 482 | return __copy_from_user(&tsk->thread.xstate->fsave, buf, |
3b095a04 | 483 | sizeof(struct i387_fsave_struct)); |
1da177e4 LT |
484 | } |
485 | ||
44210111 | 486 | static int restore_i387_fxsave(struct _fpstate_ia32 __user *buf) |
1da177e4 | 487 | { |
1da177e4 | 488 | struct task_struct *tsk = current; |
44210111 | 489 | struct user_i387_ia32_struct env; |
f668964e IM |
490 | int err; |
491 | ||
61c4628b | 492 | err = __copy_from_user(&tsk->thread.xstate->fxsave, &buf->_fxsr_env[0], |
3b095a04 | 493 | sizeof(struct i387_fxsave_struct)); |
1da177e4 | 494 | /* mxcsr reserved bits must be masked to zero for security reasons */ |
61c4628b | 495 | tsk->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 RM |
496 | if (err || __copy_from_user(&env, buf, sizeof(env))) |
497 | return 1; | |
498 | convert_to_fxsr(tsk, &env); | |
f668964e | 499 | |
44210111 | 500 | return 0; |
1da177e4 LT |
501 | } |
502 | ||
44210111 | 503 | int restore_i387_ia32(struct _fpstate_ia32 __user *buf) |
1da177e4 LT |
504 | { |
505 | int err; | |
e8a496ac | 506 | struct task_struct *tsk = current; |
1da177e4 | 507 | |
e8a496ac | 508 | if (HAVE_HWFP) |
fd3c3ed5 SS |
509 | clear_fpu(tsk); |
510 | ||
e8a496ac SS |
511 | if (!used_math()) { |
512 | err = init_fpu(tsk); | |
513 | if (err) | |
514 | return err; | |
515 | } | |
fd3c3ed5 | 516 | |
e8a496ac | 517 | if (HAVE_HWFP) { |
f668964e | 518 | if (cpu_has_fxsr) |
3b095a04 | 519 | err = restore_i387_fxsave(buf); |
f668964e | 520 | else |
3b095a04 | 521 | err = restore_i387_fsave(buf); |
1da177e4 | 522 | } else { |
44210111 RM |
523 | err = fpregs_soft_set(current, NULL, |
524 | 0, sizeof(struct user_i387_ia32_struct), | |
525 | NULL, buf) != 0; | |
1da177e4 LT |
526 | } |
527 | set_used_math(); | |
f668964e | 528 | |
1da177e4 LT |
529 | return err; |
530 | } | |
531 | ||
1da177e4 LT |
532 | /* |
533 | * FPU state for core dumps. | |
60b3b9af RM |
534 | * This is only used for a.out dumps now. |
535 | * It is declared generically using elf_fpregset_t (which is | |
536 | * struct user_i387_struct) but is in fact only used for 32-bit | |
537 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 538 | */ |
3b095a04 | 539 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu) |
1da177e4 | 540 | { |
1da177e4 | 541 | struct task_struct *tsk = current; |
f668964e | 542 | int fpvalid; |
1da177e4 LT |
543 | |
544 | fpvalid = !!used_math(); | |
60b3b9af RM |
545 | if (fpvalid) |
546 | fpvalid = !fpregs_get(tsk, NULL, | |
547 | 0, sizeof(struct user_i387_ia32_struct), | |
548 | fpu, NULL); | |
1da177e4 LT |
549 | |
550 | return fpvalid; | |
551 | } | |
129f6946 | 552 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 553 | |
60b3b9af | 554 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |