Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 | 3 | #include <linux/interrupt.h> |
69c60c88 | 4 | #include <linux/export.h> |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/hpet.h> |
58ac1e76 | 7 | #include <linux/cpu.h> |
9bc9e1d4 | 8 | #include <linux/irq.h> |
5d0cf410 | 9 | |
3d7295eb | 10 | #include <asm/irq_remapping.h> |
4588c1f0 | 11 | #include <asm/hpet.h> |
16f871bc | 12 | #include <asm/time.h> |
6e3cd952 | 13 | #include <asm/mwait.h> |
5d0cf410 | 14 | |
46e5b64f TG |
15 | #undef pr_fmt |
16 | #define pr_fmt(fmt) "hpet: " fmt | |
17 | ||
9e16e493 TG |
18 | enum hpet_mode { |
19 | HPET_MODE_UNUSED, | |
20 | HPET_MODE_LEGACY, | |
21 | HPET_MODE_CLOCKEVT, | |
22 | HPET_MODE_DEVICE, | |
23 | }; | |
24 | ||
e37f0881 | 25 | struct hpet_channel { |
4d5e6833 | 26 | struct clock_event_device evt; |
e37f0881 | 27 | unsigned int num; |
4d5e6833 | 28 | unsigned int cpu; |
2460d587 | 29 | unsigned int irq; |
45e0a415 | 30 | unsigned int in_use; |
9e16e493 | 31 | enum hpet_mode mode; |
e37f0881 | 32 | unsigned int boot_cfg; |
4d5e6833 | 33 | char name[10]; |
e37f0881 TG |
34 | }; |
35 | ||
36 | struct hpet_base { | |
37 | unsigned int nr_channels; | |
4d5e6833 | 38 | unsigned int nr_clockevents; |
e37f0881 TG |
39 | unsigned int boot_cfg; |
40 | struct hpet_channel *channels; | |
41 | }; | |
42 | ||
4588c1f0 | 43 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
5d0cf410 | 44 | |
f1c18071 TG |
45 | #define HPET_MIN_CYCLES 128 |
46 | #define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1)) | |
47 | ||
e9e2cdb4 TG |
48 | /* |
49 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
50 | */ | |
4588c1f0 | 51 | unsigned long hpet_address; |
c8bc6f3c | 52 | u8 hpet_blockid; /* OS timer block num */ |
3d45ac4b | 53 | bool hpet_msi_disable; |
73472a46 | 54 | |
441ccc35 | 55 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_GENERIC_MSI_IRQ) |
4d5e6833 | 56 | static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel); |
8c273f2c | 57 | static struct irq_domain *hpet_domain; |
e951e4af | 58 | #endif |
8c273f2c | 59 | |
4588c1f0 | 60 | static void __iomem *hpet_virt_address; |
45e0a415 | 61 | |
e37f0881 | 62 | static struct hpet_base hpet_base; |
e9e2cdb4 | 63 | |
8c273f2c TG |
64 | static bool hpet_legacy_int_enabled; |
65 | static unsigned long hpet_freq; | |
66 | ||
67 | bool boot_hpet_disable; | |
68 | bool hpet_force_user; | |
69 | static bool hpet_verbose; | |
70 | ||
3535aa12 | 71 | static inline |
4d5e6833 | 72 | struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt) |
3f7787b3 | 73 | { |
4d5e6833 | 74 | return container_of(evt, struct hpet_channel, evt); |
3f7787b3 FW |
75 | } |
76 | ||
5946fa3d | 77 | inline unsigned int hpet_readl(unsigned int a) |
e9e2cdb4 TG |
78 | { |
79 | return readl(hpet_virt_address + a); | |
80 | } | |
81 | ||
5946fa3d | 82 | static inline void hpet_writel(unsigned int d, unsigned int a) |
e9e2cdb4 TG |
83 | { |
84 | writel(d, hpet_virt_address + a); | |
85 | } | |
86 | ||
06a24dec TG |
87 | static inline void hpet_set_mapping(void) |
88 | { | |
4bdc0d67 | 89 | hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE); |
06a24dec TG |
90 | } |
91 | ||
92 | static inline void hpet_clear_mapping(void) | |
93 | { | |
94 | iounmap(hpet_virt_address); | |
95 | hpet_virt_address = NULL; | |
96 | } | |
97 | ||
e9e2cdb4 TG |
98 | /* |
99 | * HPET command line enable / disable | |
100 | */ | |
4588c1f0 | 101 | static int __init hpet_setup(char *str) |
e9e2cdb4 | 102 | { |
b2d6aba9 JB |
103 | while (str) { |
104 | char *next = strchr(str, ','); | |
105 | ||
106 | if (next) | |
107 | *next++ = 0; | |
e9e2cdb4 | 108 | if (!strncmp("disable", str, 7)) |
3d45ac4b | 109 | boot_hpet_disable = true; |
b17530bd | 110 | if (!strncmp("force", str, 5)) |
3d45ac4b | 111 | hpet_force_user = true; |
b98103a5 | 112 | if (!strncmp("verbose", str, 7)) |
3d45ac4b | 113 | hpet_verbose = true; |
b2d6aba9 | 114 | str = next; |
e9e2cdb4 TG |
115 | } |
116 | return 1; | |
117 | } | |
118 | __setup("hpet=", hpet_setup); | |
119 | ||
28769149 TG |
120 | static int __init disable_hpet(char *str) |
121 | { | |
3d45ac4b | 122 | boot_hpet_disable = true; |
28769149 TG |
123 | return 1; |
124 | } | |
125 | __setup("nohpet", disable_hpet); | |
126 | ||
e9e2cdb4 TG |
127 | static inline int is_hpet_capable(void) |
128 | { | |
4588c1f0 | 129 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
130 | } |
131 | ||
e9e2cdb4 | 132 | /** |
3fe50c34 | 133 | * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled |
e9e2cdb4 TG |
134 | */ |
135 | int is_hpet_enabled(void) | |
136 | { | |
137 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
138 | } | |
1bdbdaac | 139 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 | 140 | |
b98103a5 AH |
141 | static void _hpet_print_config(const char *function, int line) |
142 | { | |
0b5c597d IM |
143 | u32 i, id, period, cfg, status, channels, l, h; |
144 | ||
46e5b64f | 145 | pr_info("%s(%d):\n", function, line); |
0b5c597d IM |
146 | |
147 | id = hpet_readl(HPET_ID); | |
148 | period = hpet_readl(HPET_PERIOD); | |
149 | pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period); | |
150 | ||
151 | cfg = hpet_readl(HPET_CFG); | |
152 | status = hpet_readl(HPET_STATUS); | |
153 | pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); | |
154 | ||
b98103a5 AH |
155 | l = hpet_readl(HPET_COUNTER); |
156 | h = hpet_readl(HPET_COUNTER+4); | |
46e5b64f | 157 | pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h); |
b98103a5 | 158 | |
0b5c597d IM |
159 | channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; |
160 | ||
161 | for (i = 0; i < channels; i++) { | |
b98103a5 AH |
162 | l = hpet_readl(HPET_Tn_CFG(i)); |
163 | h = hpet_readl(HPET_Tn_CFG(i)+4); | |
46e5b64f | 164 | pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h); |
0b5c597d | 165 | |
b98103a5 AH |
166 | l = hpet_readl(HPET_Tn_CMP(i)); |
167 | h = hpet_readl(HPET_Tn_CMP(i)+4); | |
46e5b64f | 168 | pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h); |
0b5c597d | 169 | |
b98103a5 AH |
170 | l = hpet_readl(HPET_Tn_ROUTE(i)); |
171 | h = hpet_readl(HPET_Tn_ROUTE(i)+4); | |
46e5b64f | 172 | pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h); |
b98103a5 AH |
173 | } |
174 | } | |
175 | ||
176 | #define hpet_print_config() \ | |
177 | do { \ | |
178 | if (hpet_verbose) \ | |
02f1f217 | 179 | _hpet_print_config(__func__, __LINE__); \ |
b98103a5 AH |
180 | } while (0) |
181 | ||
e9e2cdb4 | 182 | /* |
3fe50c34 | 183 | * When the HPET driver (/dev/hpet) is enabled, we need to reserve |
e9e2cdb4 TG |
184 | * timer 0 and timer 1 in case of RTC emulation. |
185 | */ | |
186 | #ifdef CONFIG_HPET | |
f0ed4e69 | 187 | |
2460d587 | 188 | static void __init hpet_reserve_platform_timers(void) |
e9e2cdb4 | 189 | { |
e9e2cdb4 | 190 | struct hpet_data hd; |
2460d587 | 191 | unsigned int i; |
e9e2cdb4 | 192 | |
4588c1f0 IM |
193 | memset(&hd, 0, sizeof(hd)); |
194 | hd.hd_phys_address = hpet_address; | |
2460d587 TG |
195 | hd.hd_address = hpet_virt_address; |
196 | hd.hd_nirqs = hpet_base.nr_channels; | |
5761d64b | 197 | |
64a76f66 DB |
198 | /* |
199 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
200 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
201 | * don't bother configuring *any* comparator interrupts. | |
202 | */ | |
e9e2cdb4 TG |
203 | hd.hd_irq[0] = HPET_LEGACY_8254; |
204 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
205 | ||
45e0a415 TG |
206 | for (i = 0; i < hpet_base.nr_channels; i++) { |
207 | struct hpet_channel *hc = hpet_base.channels + i; | |
5761d64b | 208 | |
45e0a415 TG |
209 | if (i >= 2) |
210 | hd.hd_irq[i] = hc->irq; | |
26afe5f2 | 211 | |
45e0a415 TG |
212 | switch (hc->mode) { |
213 | case HPET_MODE_UNUSED: | |
214 | case HPET_MODE_DEVICE: | |
215 | hc->mode = HPET_MODE_DEVICE; | |
216 | break; | |
217 | case HPET_MODE_CLOCKEVT: | |
218 | case HPET_MODE_LEGACY: | |
219 | hpet_reserve_timer(&hd, hc->num); | |
220 | break; | |
221 | } | |
222 | } | |
5761d64b | 223 | |
45e0a415 | 224 | hpet_alloc(&hd); |
e9e2cdb4 | 225 | } |
af5a1dad TG |
226 | |
227 | static void __init hpet_select_device_channel(void) | |
228 | { | |
229 | int i; | |
230 | ||
231 | for (i = 0; i < hpet_base.nr_channels; i++) { | |
232 | struct hpet_channel *hc = hpet_base.channels + i; | |
233 | ||
234 | /* Associate the first unused channel to /dev/hpet */ | |
235 | if (hc->mode == HPET_MODE_UNUSED) { | |
236 | hc->mode = HPET_MODE_DEVICE; | |
237 | return; | |
238 | } | |
239 | } | |
240 | } | |
241 | ||
e9e2cdb4 | 242 | #else |
2460d587 | 243 | static inline void hpet_reserve_platform_timers(void) { } |
af5a1dad | 244 | static inline void hpet_select_device_channel(void) {} |
e9e2cdb4 TG |
245 | #endif |
246 | ||
3fe50c34 | 247 | /* Common HPET functions */ |
8d6f0c82 | 248 | static void hpet_stop_counter(void) |
e9e2cdb4 | 249 | { |
3d45ac4b | 250 | u32 cfg = hpet_readl(HPET_CFG); |
0b5c597d | 251 | |
e9e2cdb4 TG |
252 | cfg &= ~HPET_CFG_ENABLE; |
253 | hpet_writel(cfg, HPET_CFG); | |
7a6f9cbb AH |
254 | } |
255 | ||
256 | static void hpet_reset_counter(void) | |
257 | { | |
e9e2cdb4 TG |
258 | hpet_writel(0, HPET_COUNTER); |
259 | hpet_writel(0, HPET_COUNTER + 4); | |
8d6f0c82 AH |
260 | } |
261 | ||
262 | static void hpet_start_counter(void) | |
263 | { | |
5946fa3d | 264 | unsigned int cfg = hpet_readl(HPET_CFG); |
0b5c597d | 265 | |
e9e2cdb4 TG |
266 | cfg |= HPET_CFG_ENABLE; |
267 | hpet_writel(cfg, HPET_CFG); | |
268 | } | |
269 | ||
8d6f0c82 AH |
270 | static void hpet_restart_counter(void) |
271 | { | |
272 | hpet_stop_counter(); | |
7a6f9cbb | 273 | hpet_reset_counter(); |
8d6f0c82 AH |
274 | hpet_start_counter(); |
275 | } | |
276 | ||
59c69f2a VP |
277 | static void hpet_resume_device(void) |
278 | { | |
bfe0c1cc | 279 | force_hpet_resume(); |
59c69f2a VP |
280 | } |
281 | ||
17622339 | 282 | static void hpet_resume_counter(struct clocksource *cs) |
59c69f2a VP |
283 | { |
284 | hpet_resume_device(); | |
8d6f0c82 | 285 | hpet_restart_counter(); |
59c69f2a VP |
286 | } |
287 | ||
610bf2f1 | 288 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 | 289 | { |
5946fa3d | 290 | unsigned int cfg = hpet_readl(HPET_CFG); |
e9e2cdb4 TG |
291 | |
292 | cfg |= HPET_CFG_LEGACY; | |
293 | hpet_writel(cfg, HPET_CFG); | |
3d45ac4b | 294 | hpet_legacy_int_enabled = true; |
e9e2cdb4 TG |
295 | } |
296 | ||
310b5b3e | 297 | static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt) |
e9e2cdb4 | 298 | { |
310b5b3e | 299 | unsigned int channel = clockevent_to_channel(evt)->num; |
5946fa3d | 300 | unsigned int cfg, cmp, now; |
e9e2cdb4 TG |
301 | uint64_t delta; |
302 | ||
c8b5db7d VK |
303 | hpet_stop_counter(); |
304 | delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; | |
305 | delta >>= evt->shift; | |
306 | now = hpet_readl(HPET_COUNTER); | |
307 | cmp = now + (unsigned int)delta; | |
d415c754 | 308 | cfg = hpet_readl(HPET_Tn_CFG(channel)); |
c8b5db7d VK |
309 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL | |
310 | HPET_TN_32BIT; | |
d415c754 IM |
311 | hpet_writel(cfg, HPET_Tn_CFG(channel)); |
312 | hpet_writel(cmp, HPET_Tn_CMP(channel)); | |
c8b5db7d VK |
313 | udelay(1); |
314 | /* | |
315 | * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL | |
316 | * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL | |
317 | * bit is automatically cleared after the first write. | |
318 | * (See AMD-8111 HyperTransport I/O Hub Data Sheet, | |
319 | * Publication # 24674) | |
320 | */ | |
d415c754 | 321 | hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel)); |
c8b5db7d VK |
322 | hpet_start_counter(); |
323 | hpet_print_config(); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
310b5b3e | 328 | static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt) |
c8b5db7d | 329 | { |
310b5b3e | 330 | unsigned int channel = clockevent_to_channel(evt)->num; |
c8b5db7d VK |
331 | unsigned int cfg; |
332 | ||
d415c754 | 333 | cfg = hpet_readl(HPET_Tn_CFG(channel)); |
c8b5db7d VK |
334 | cfg &= ~HPET_TN_PERIODIC; |
335 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
d415c754 | 336 | hpet_writel(cfg, HPET_Tn_CFG(channel)); |
c8b5db7d VK |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
310b5b3e | 341 | static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt) |
c8b5db7d | 342 | { |
310b5b3e | 343 | unsigned int channel = clockevent_to_channel(evt)->num; |
c8b5db7d VK |
344 | unsigned int cfg; |
345 | ||
d415c754 | 346 | cfg = hpet_readl(HPET_Tn_CFG(channel)); |
c8b5db7d | 347 | cfg &= ~HPET_TN_ENABLE; |
d415c754 | 348 | hpet_writel(cfg, HPET_Tn_CFG(channel)); |
c8b5db7d VK |
349 | |
350 | return 0; | |
351 | } | |
352 | ||
310b5b3e | 353 | static int hpet_clkevt_legacy_resume(struct clock_event_device *evt) |
bb68cfe2 TG |
354 | { |
355 | hpet_enable_legacy_int(); | |
c8b5db7d | 356 | hpet_print_config(); |
c8b5db7d | 357 | return 0; |
e9e2cdb4 TG |
358 | } |
359 | ||
310b5b3e TG |
360 | static int |
361 | hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt) | |
e9e2cdb4 | 362 | { |
310b5b3e | 363 | unsigned int channel = clockevent_to_channel(evt)->num; |
f7676254 | 364 | u32 cnt; |
995bd3bb | 365 | s32 res; |
e9e2cdb4 TG |
366 | |
367 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 368 | cnt += (u32) delta; |
853acaf0 | 369 | hpet_writel(cnt, HPET_Tn_CMP(channel)); |
e9e2cdb4 | 370 | |
72d43d9b | 371 | /* |
995bd3bb TG |
372 | * HPETs are a complete disaster. The compare register is |
373 | * based on a equal comparison and neither provides a less | |
374 | * than or equal functionality (which would require to take | |
375 | * the wraparound into account) nor a simple count down event | |
376 | * mode. Further the write to the comparator register is | |
377 | * delayed internally up to two HPET clock cycles in certain | |
f1c18071 TG |
378 | * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even |
379 | * longer delays. We worked around that by reading back the | |
380 | * compare register, but that required another workaround for | |
381 | * ICH9,10 chips where the first readout after write can | |
382 | * return the old stale value. We already had a minimum | |
383 | * programming delta of 5us enforced, but a NMI or SMI hitting | |
995bd3bb TG |
384 | * between the counter readout and the comparator write can |
385 | * move us behind that point easily. Now instead of reading | |
386 | * the compare register back several times, we make the ETIME | |
387 | * decision based on the following: Return ETIME if the | |
f1c18071 | 388 | * counter value after the write is less than HPET_MIN_CYCLES |
995bd3bb | 389 | * away from the event or if the counter is already ahead of |
f1c18071 TG |
390 | * the event. The minimum programming delta for the generic |
391 | * clockevents code is set to 1.5 * HPET_MIN_CYCLES. | |
72d43d9b | 392 | */ |
995bd3bb | 393 | res = (s32)(cnt - hpet_readl(HPET_COUNTER)); |
72d43d9b | 394 | |
f1c18071 | 395 | return res < HPET_MIN_CYCLES ? -ETIME : 0; |
e9e2cdb4 TG |
396 | } |
397 | ||
ea99110d TG |
398 | static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating) |
399 | { | |
400 | struct clock_event_device *evt = &hc->evt; | |
401 | ||
402 | evt->rating = rating; | |
403 | evt->irq = hc->irq; | |
404 | evt->name = hc->name; | |
405 | evt->cpumask = cpumask_of(hc->cpu); | |
406 | evt->set_state_oneshot = hpet_clkevt_set_state_oneshot; | |
407 | evt->set_next_event = hpet_clkevt_set_next_event; | |
408 | evt->set_state_shutdown = hpet_clkevt_set_state_shutdown; | |
409 | ||
410 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
411 | if (hc->boot_cfg & HPET_TN_PERIODIC) { | |
412 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
413 | evt->set_state_periodic = hpet_clkevt_set_state_periodic; | |
414 | } | |
415 | } | |
416 | ||
49adaa60 TG |
417 | static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc) |
418 | { | |
419 | /* | |
420 | * Start HPET with the boot CPU's cpumask and make it global after | |
421 | * the IO_APIC has been initialized. | |
422 | */ | |
423 | hc->cpu = boot_cpu_data.cpu_index; | |
4108d141 | 424 | strscpy(hc->name, "hpet", sizeof(hc->name)); |
49adaa60 TG |
425 | hpet_init_clockevent(hc, 50); |
426 | ||
427 | hc->evt.tick_resume = hpet_clkevt_legacy_resume; | |
428 | ||
429 | /* | |
430 | * Legacy horrors and sins from the past. HPET used periodic mode | |
431 | * unconditionally forever on the legacy channel 0. Removing the | |
432 | * below hack and using the conditional in hpet_init_clockevent() | |
433 | * makes at least Qemu and one hardware machine fail to boot. | |
434 | * There are two issues which cause the boot failure: | |
435 | * | |
436 | * #1 After the timer delivery test in IOAPIC and the IOAPIC setup | |
437 | * the next interrupt is not delivered despite the HPET channel | |
438 | * being programmed correctly. Reprogramming the HPET after | |
439 | * switching to IOAPIC makes it work again. After fixing this, | |
440 | * the next issue surfaces: | |
441 | * | |
442 | * #2 Due to the unconditional periodic mode availability the Local | |
443 | * APIC timer calibration can hijack the global clockevents | |
444 | * event handler without causing damage. Using oneshot at this | |
445 | * stage makes if hang because the HPET does not get | |
446 | * reprogrammed due to the handler hijacking. Duh, stupid me! | |
447 | * | |
448 | * Both issues require major surgery and especially the kick HPET | |
449 | * again after enabling IOAPIC results in really nasty hackery. | |
450 | * This 'assume periodic works' magic has survived since HPET | |
451 | * support got added, so it's questionable whether this should be | |
452 | * fixed. Both Qemu and the failing hardware machine support | |
453 | * periodic mode despite the fact that both don't advertise it in | |
454 | * the configuration register and both need that extra kick after | |
455 | * switching to IOAPIC. Seems to be a feature... | |
456 | */ | |
457 | hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC; | |
458 | hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic; | |
459 | ||
460 | /* Start HPET legacy interrupts */ | |
461 | hpet_enable_legacy_int(); | |
462 | ||
463 | clockevents_config_and_register(&hc->evt, hpet_freq, | |
464 | HPET_MIN_PROG_DELTA, 0x7FFFFFFF); | |
465 | global_clock_event = &hc->evt; | |
466 | pr_debug("Clockevent registered\n"); | |
467 | } | |
c8b5db7d | 468 | |
58ac1e76 | 469 | /* |
470 | * HPET MSI Support | |
471 | */ | |
441ccc35 | 472 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_GENERIC_MSI_IRQ) |
3d7295eb | 473 | static void hpet_msi_unmask(struct irq_data *data) |
58ac1e76 | 474 | { |
4d5e6833 | 475 | struct hpet_channel *hc = irq_data_get_irq_handler_data(data); |
5946fa3d | 476 | unsigned int cfg; |
58ac1e76 | 477 | |
d415c754 | 478 | cfg = hpet_readl(HPET_Tn_CFG(hc->num)); |
6acf5a8c | 479 | cfg |= HPET_TN_ENABLE | HPET_TN_FSB; |
d415c754 | 480 | hpet_writel(cfg, HPET_Tn_CFG(hc->num)); |
58ac1e76 | 481 | } |
482 | ||
3d7295eb | 483 | static void hpet_msi_mask(struct irq_data *data) |
58ac1e76 | 484 | { |
4d5e6833 | 485 | struct hpet_channel *hc = irq_data_get_irq_handler_data(data); |
5946fa3d | 486 | unsigned int cfg; |
58ac1e76 | 487 | |
d415c754 | 488 | cfg = hpet_readl(HPET_Tn_CFG(hc->num)); |
6acf5a8c | 489 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB); |
d415c754 | 490 | hpet_writel(cfg, HPET_Tn_CFG(hc->num)); |
58ac1e76 | 491 | } |
492 | ||
3d7295eb | 493 | static void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg) |
58ac1e76 | 494 | { |
d415c754 IM |
495 | hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num)); |
496 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4); | |
58ac1e76 | 497 | } |
498 | ||
3d7295eb DW |
499 | static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) |
500 | { | |
501 | hpet_msi_write(irq_data_get_irq_handler_data(data), msg); | |
502 | } | |
503 | ||
504 | static struct irq_chip hpet_msi_controller __ro_after_init = { | |
505 | .name = "HPET-MSI", | |
506 | .irq_unmask = hpet_msi_unmask, | |
507 | .irq_mask = hpet_msi_mask, | |
508 | .irq_ack = irq_chip_ack_parent, | |
509 | .irq_set_affinity = msi_domain_set_affinity, | |
510 | .irq_retrigger = irq_chip_retrigger_hierarchy, | |
511 | .irq_write_msi_msg = hpet_msi_write_msg, | |
ff363f48 | 512 | .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, |
3d7295eb DW |
513 | }; |
514 | ||
515 | static int hpet_msi_init(struct irq_domain *domain, | |
516 | struct msi_domain_info *info, unsigned int virq, | |
517 | irq_hw_number_t hwirq, msi_alloc_info_t *arg) | |
518 | { | |
519 | irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); | |
520 | irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL, | |
521 | handle_edge_irq, arg->data, "edge"); | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | static void hpet_msi_free(struct irq_domain *domain, | |
527 | struct msi_domain_info *info, unsigned int virq) | |
528 | { | |
529 | irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); | |
530 | } | |
531 | ||
532 | static struct msi_domain_ops hpet_msi_domain_ops = { | |
533 | .msi_init = hpet_msi_init, | |
534 | .msi_free = hpet_msi_free, | |
535 | }; | |
536 | ||
537 | static struct msi_domain_info hpet_msi_domain_info = { | |
538 | .ops = &hpet_msi_domain_ops, | |
539 | .chip = &hpet_msi_controller, | |
540 | .flags = MSI_FLAG_USE_DEF_DOM_OPS, | |
541 | }; | |
542 | ||
543 | static struct irq_domain *hpet_create_irq_domain(int hpet_id) | |
544 | { | |
545 | struct msi_domain_info *domain_info; | |
546 | struct irq_domain *parent, *d; | |
3d7295eb | 547 | struct fwnode_handle *fn; |
c2a5881c | 548 | struct irq_fwspec fwspec; |
3d7295eb DW |
549 | |
550 | if (x86_vector_domain == NULL) | |
551 | return NULL; | |
552 | ||
553 | domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); | |
554 | if (!domain_info) | |
555 | return NULL; | |
556 | ||
557 | *domain_info = hpet_msi_domain_info; | |
558 | domain_info->data = (void *)(long)hpet_id; | |
559 | ||
3d7295eb DW |
560 | fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, |
561 | hpet_id); | |
562 | if (!fn) { | |
563 | kfree(domain_info); | |
564 | return NULL; | |
565 | } | |
566 | ||
c2a5881c DW |
567 | fwspec.fwnode = fn; |
568 | fwspec.param_count = 1; | |
569 | fwspec.param[0] = hpet_id; | |
570 | ||
c147e1ef | 571 | parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_GENERIC_MSI); |
c2a5881c DW |
572 | if (!parent) { |
573 | irq_domain_free_fwnode(fn); | |
574 | kfree(domain_info); | |
575 | return NULL; | |
576 | } | |
577 | if (parent != x86_vector_domain) | |
578 | hpet_msi_controller.name = "IR-HPET-MSI"; | |
579 | ||
3d7295eb DW |
580 | d = msi_create_irq_domain(fn, domain_info, parent); |
581 | if (!d) { | |
582 | irq_domain_free_fwnode(fn); | |
583 | kfree(domain_info); | |
584 | } | |
585 | return d; | |
586 | } | |
587 | ||
588 | static inline int hpet_dev_id(struct irq_domain *domain) | |
589 | { | |
590 | struct msi_domain_info *info = msi_get_domain_info(domain); | |
591 | ||
592 | return (int)(long)info->data; | |
593 | } | |
594 | ||
595 | static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc, | |
596 | int dev_num) | |
597 | { | |
598 | struct irq_alloc_info info; | |
599 | ||
600 | init_irq_alloc_info(&info, NULL); | |
601 | info.type = X86_IRQ_ALLOC_TYPE_HPET; | |
602 | info.data = hc; | |
603 | info.devid = hpet_dev_id(domain); | |
604 | info.hwirq = dev_num; | |
605 | ||
606 | return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); | |
607 | } | |
608 | ||
310b5b3e | 609 | static int hpet_clkevt_msi_resume(struct clock_event_device *evt) |
c8b5db7d | 610 | { |
4d5e6833 | 611 | struct hpet_channel *hc = clockevent_to_channel(evt); |
d415c754 | 612 | struct irq_data *data = irq_get_irq_data(hc->irq); |
bb68cfe2 | 613 | struct msi_msg msg; |
c8b5db7d | 614 | |
bb68cfe2 TG |
615 | /* Restore the MSI msg and unmask the interrupt */ |
616 | irq_chip_compose_msi_msg(data, &msg); | |
d415c754 | 617 | hpet_msi_write(hc, &msg); |
bb68cfe2 TG |
618 | hpet_msi_unmask(data); |
619 | return 0; | |
26afe5f2 | 620 | } |
621 | ||
310b5b3e | 622 | static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data) |
26afe5f2 | 623 | { |
4d5e6833 | 624 | struct hpet_channel *hc = data; |
d415c754 | 625 | struct clock_event_device *evt = &hc->evt; |
26afe5f2 | 626 | |
3fe50c34 | 627 | if (!evt->event_handler) { |
d415c754 | 628 | pr_info("Spurious interrupt HPET channel %d\n", hc->num); |
26afe5f2 | 629 | return IRQ_HANDLED; |
630 | } | |
631 | ||
3fe50c34 | 632 | evt->event_handler(evt); |
26afe5f2 | 633 | return IRQ_HANDLED; |
634 | } | |
635 | ||
310b5b3e | 636 | static int hpet_setup_msi_irq(struct hpet_channel *hc) |
26afe5f2 | 637 | { |
310b5b3e | 638 | if (request_irq(hc->irq, hpet_msi_interrupt_handler, |
d20d2efb | 639 | IRQF_TIMER | IRQF_NOBALANCING, |
4d5e6833 | 640 | hc->name, hc)) |
26afe5f2 | 641 | return -1; |
642 | ||
4d5e6833 TG |
643 | disable_irq(hc->irq); |
644 | irq_set_affinity(hc->irq, cpumask_of(hc->cpu)); | |
645 | enable_irq(hc->irq); | |
26afe5f2 | 646 | |
4d5e6833 | 647 | pr_debug("%s irq %u for MSI\n", hc->name, hc->irq); |
c81bba49 | 648 | |
26afe5f2 | 649 | return 0; |
650 | } | |
651 | ||
45e0a415 | 652 | /* Invoked from the hotplug callback on @cpu */ |
4d5e6833 | 653 | static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu) |
26afe5f2 | 654 | { |
d415c754 | 655 | struct clock_event_device *evt = &hc->evt; |
26afe5f2 | 656 | |
d415c754 | 657 | hc->cpu = cpu; |
4d5e6833 | 658 | per_cpu(cpu_hpet_channel, cpu) = hc; |
310b5b3e | 659 | hpet_setup_msi_irq(hc); |
26afe5f2 | 660 | |
ea99110d | 661 | hpet_init_clockevent(hc, 110); |
310b5b3e | 662 | evt->tick_resume = hpet_clkevt_msi_resume; |
ab0e08f1 TG |
663 | |
664 | clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA, | |
665 | 0x7FFFFFFF); | |
26afe5f2 | 666 | } |
667 | ||
4d5e6833 | 668 | static struct hpet_channel *hpet_get_unused_clockevent(void) |
6bdec41a TG |
669 | { |
670 | int i; | |
671 | ||
2460d587 | 672 | for (i = 0; i < hpet_base.nr_channels; i++) { |
4d5e6833 | 673 | struct hpet_channel *hc = hpet_base.channels + i; |
6bdec41a | 674 | |
45e0a415 | 675 | if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use) |
6bdec41a | 676 | continue; |
45e0a415 | 677 | hc->in_use = 1; |
d415c754 | 678 | return hc; |
6bdec41a TG |
679 | } |
680 | return NULL; | |
681 | } | |
682 | ||
683 | static int hpet_cpuhp_online(unsigned int cpu) | |
684 | { | |
4d5e6833 | 685 | struct hpet_channel *hc = hpet_get_unused_clockevent(); |
6bdec41a | 686 | |
d415c754 IM |
687 | if (hc) |
688 | init_one_hpet_msi_clockevent(hc, cpu); | |
6bdec41a TG |
689 | return 0; |
690 | } | |
691 | ||
692 | static int hpet_cpuhp_dead(unsigned int cpu) | |
693 | { | |
4d5e6833 | 694 | struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu); |
6bdec41a | 695 | |
d415c754 | 696 | if (!hc) |
6bdec41a | 697 | return 0; |
d415c754 | 698 | free_irq(hc->irq, hc); |
45e0a415 | 699 | hc->in_use = 0; |
4d5e6833 | 700 | per_cpu(cpu_hpet_channel, cpu) = NULL; |
6bdec41a TG |
701 | return 0; |
702 | } | |
703 | ||
4d5e6833 | 704 | static void __init hpet_select_clockevents(void) |
26afe5f2 | 705 | { |
4d5e6833 | 706 | unsigned int i; |
26afe5f2 | 707 | |
4d5e6833 | 708 | hpet_base.nr_clockevents = 0; |
73472a46 | 709 | |
54aa699e | 710 | /* No point if MSI is disabled or CPU has an Always Running APIC Timer */ |
4d5e6833 | 711 | if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT)) |
39fe05e5 | 712 | return; |
26afe5f2 | 713 | |
b98103a5 | 714 | hpet_print_config(); |
26afe5f2 | 715 | |
3cb96f0c JL |
716 | hpet_domain = hpet_create_irq_domain(hpet_blockid); |
717 | if (!hpet_domain) | |
718 | return; | |
719 | ||
4d5e6833 TG |
720 | for (i = 0; i < hpet_base.nr_channels; i++) { |
721 | struct hpet_channel *hc = hpet_base.channels + i; | |
722 | int irq; | |
26afe5f2 | 723 | |
4d5e6833 TG |
724 | if (hc->mode != HPET_MODE_UNUSED) |
725 | continue; | |
26afe5f2 | 726 | |
4d5e6833 TG |
727 | /* Only consider HPET channel with MSI support */ |
728 | if (!(hc->boot_cfg & HPET_TN_FSB_CAP)) | |
26afe5f2 | 729 | continue; |
730 | ||
d415c754 | 731 | sprintf(hc->name, "hpet%d", i); |
cb17b2a6 | 732 | |
d415c754 | 733 | irq = hpet_assign_irq(hpet_domain, hc, hc->num); |
bafac298 | 734 | if (irq <= 0) |
3cb96f0c JL |
735 | continue; |
736 | ||
d415c754 | 737 | hc->irq = irq; |
4d5e6833 TG |
738 | hc->mode = HPET_MODE_CLOCKEVT; |
739 | ||
740 | if (++hpet_base.nr_clockevents == num_possible_cpus()) | |
26afe5f2 | 741 | break; |
742 | } | |
743 | ||
46e5b64f | 744 | pr_info("%d channels of %d reserved for per-cpu timers\n", |
4d5e6833 | 745 | hpet_base.nr_channels, hpet_base.nr_clockevents); |
26afe5f2 | 746 | } |
747 | ||
26afe5f2 | 748 | #else |
749 | ||
4d5e6833 | 750 | static inline void hpet_select_clockevents(void) { } |
5f79f2f2 | 751 | |
48d7f6c7 SAS |
752 | #define hpet_cpuhp_online NULL |
753 | #define hpet_cpuhp_dead NULL | |
26afe5f2 | 754 | |
755 | #endif | |
756 | ||
6bb74df4 | 757 | /* |
758 | * Clock source related code | |
759 | */ | |
f99fd22e WL |
760 | #if defined(CONFIG_SMP) && defined(CONFIG_64BIT) |
761 | /* | |
762 | * Reading the HPET counter is a very slow operation. If a large number of | |
763 | * CPUs are trying to access the HPET counter simultaneously, it can cause | |
dfe36b57 | 764 | * massive delays and slow down system performance dramatically. This may |
f99fd22e WL |
765 | * happen when HPET is the default clock source instead of TSC. For a |
766 | * really large system with hundreds of CPUs, the slowdown may be so | |
dfe36b57 | 767 | * severe, that it can actually crash the system because of a NMI watchdog |
f99fd22e WL |
768 | * soft lockup, for example. |
769 | * | |
770 | * If multiple CPUs are trying to access the HPET counter at the same time, | |
771 | * we don't actually need to read the counter multiple times. Instead, the | |
772 | * other CPUs can use the counter value read by the first CPU in the group. | |
773 | * | |
774 | * This special feature is only enabled on x86-64 systems. It is unlikely | |
775 | * that 32-bit x86 systems will have enough CPUs to require this feature | |
dfe36b57 | 776 | * with its associated locking overhead. We also need 64-bit atomic read. |
f99fd22e | 777 | * |
3fe50c34 | 778 | * The lock and the HPET value are stored together and can be read in a |
f99fd22e WL |
779 | * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t |
780 | * is 32 bits in size. | |
781 | */ | |
782 | union hpet_lock { | |
783 | struct { | |
784 | arch_spinlock_t lock; | |
785 | u32 value; | |
786 | }; | |
787 | u64 lockval; | |
788 | }; | |
789 | ||
790 | static union hpet_lock hpet __cacheline_aligned = { | |
791 | { .lock = __ARCH_SPIN_LOCK_UNLOCKED, }, | |
792 | }; | |
793 | ||
a5a1d1c2 | 794 | static u64 read_hpet(struct clocksource *cs) |
f99fd22e WL |
795 | { |
796 | unsigned long flags; | |
797 | union hpet_lock old, new; | |
798 | ||
799 | BUILD_BUG_ON(sizeof(union hpet_lock) != 8); | |
800 | ||
801 | /* | |
802 | * Read HPET directly if in NMI. | |
803 | */ | |
804 | if (in_nmi()) | |
a5a1d1c2 | 805 | return (u64)hpet_readl(HPET_COUNTER); |
f99fd22e WL |
806 | |
807 | /* | |
808 | * Read the current state of the lock and HPET value atomically. | |
809 | */ | |
810 | old.lockval = READ_ONCE(hpet.lockval); | |
811 | ||
812 | if (arch_spin_is_locked(&old.lock)) | |
813 | goto contended; | |
814 | ||
815 | local_irq_save(flags); | |
816 | if (arch_spin_trylock(&hpet.lock)) { | |
817 | new.value = hpet_readl(HPET_COUNTER); | |
818 | /* | |
819 | * Use WRITE_ONCE() to prevent store tearing. | |
820 | */ | |
821 | WRITE_ONCE(hpet.value, new.value); | |
822 | arch_spin_unlock(&hpet.lock); | |
823 | local_irq_restore(flags); | |
a5a1d1c2 | 824 | return (u64)new.value; |
f99fd22e WL |
825 | } |
826 | local_irq_restore(flags); | |
827 | ||
828 | contended: | |
829 | /* | |
830 | * Contended case | |
831 | * -------------- | |
832 | * Wait until the HPET value change or the lock is free to indicate | |
833 | * its value is up-to-date. | |
834 | * | |
835 | * It is possible that old.value has already contained the latest | |
836 | * HPET value while the lock holder was in the process of releasing | |
837 | * the lock. Checking for lock state change will enable us to return | |
838 | * the value immediately instead of waiting for the next HPET reader | |
839 | * to come along. | |
840 | */ | |
841 | do { | |
842 | cpu_relax(); | |
843 | new.lockval = READ_ONCE(hpet.lockval); | |
844 | } while ((new.value == old.value) && arch_spin_is_locked(&new.lock)); | |
845 | ||
a5a1d1c2 | 846 | return (u64)new.value; |
f99fd22e WL |
847 | } |
848 | #else | |
849 | /* | |
850 | * For UP or 32-bit. | |
851 | */ | |
a5a1d1c2 | 852 | static u64 read_hpet(struct clocksource *cs) |
6bb74df4 | 853 | { |
a5a1d1c2 | 854 | return (u64)hpet_readl(HPET_COUNTER); |
6bb74df4 | 855 | } |
f99fd22e | 856 | #endif |
6bb74df4 | 857 | |
858 | static struct clocksource clocksource_hpet = { | |
859 | .name = "hpet", | |
860 | .rating = 250, | |
861 | .read = read_hpet, | |
862 | .mask = HPET_MASK, | |
6bb74df4 | 863 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
8d6f0c82 | 864 | .resume = hpet_resume_counter, |
6bb74df4 | 865 | }; |
866 | ||
9b0b28de TG |
867 | /* |
868 | * AMD SB700 based systems with spread spectrum enabled use a SMM based | |
869 | * HPET emulation to provide proper frequency setting. | |
870 | * | |
871 | * On such systems the SMM code is initialized with the first HPET register | |
872 | * access and takes some time to complete. During this time the config | |
873 | * register reads 0xffffffff. We check for max 1000 loops whether the | |
874 | * config register reads a non-0xffffffff value to make sure that the | |
875 | * HPET is up and running before we proceed any further. | |
876 | * | |
877 | * A counting loop is safe, as the HPET access takes thousands of CPU cycles. | |
878 | * | |
879 | * On non-SB700 based machines this check is only done once and has no | |
880 | * side effects. | |
881 | */ | |
882 | static bool __init hpet_cfg_working(void) | |
883 | { | |
884 | int i; | |
885 | ||
886 | for (i = 0; i < 1000; i++) { | |
887 | if (hpet_readl(HPET_CFG) != 0xFFFFFFFF) | |
888 | return true; | |
889 | } | |
890 | ||
891 | pr_warn("Config register invalid. Disabling HPET\n"); | |
892 | return false; | |
893 | } | |
894 | ||
3222daf9 TG |
895 | static bool __init hpet_counting(void) |
896 | { | |
897 | u64 start, now, t1; | |
898 | ||
899 | hpet_restart_counter(); | |
900 | ||
901 | t1 = hpet_readl(HPET_COUNTER); | |
902 | start = rdtsc(); | |
903 | ||
904 | /* | |
905 | * We don't know the TSC frequency yet, but waiting for | |
906 | * 200000 TSC cycles is safe: | |
907 | * 4 GHz == 50us | |
908 | * 1 GHz == 200us | |
909 | */ | |
910 | do { | |
44b5be57 TG |
911 | if (t1 != hpet_readl(HPET_COUNTER)) |
912 | return true; | |
3222daf9 TG |
913 | now = rdtsc(); |
914 | } while ((now - start) < 200000UL); | |
915 | ||
44b5be57 TG |
916 | pr_warn("Counter not counting. HPET disabled\n"); |
917 | return false; | |
3222daf9 | 918 | } |
396e2c6f | 919 | |
6e3cd952 TG |
920 | static bool __init mwait_pc10_supported(void) |
921 | { | |
922 | unsigned int eax, ebx, ecx, mwait_substates; | |
923 | ||
924 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
925 | return false; | |
926 | ||
927 | if (!cpu_feature_enabled(X86_FEATURE_MWAIT)) | |
928 | return false; | |
929 | ||
930 | if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) | |
931 | return false; | |
932 | ||
933 | cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates); | |
934 | ||
935 | return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) && | |
936 | (ecx & CPUID5_ECX_INTERRUPT_BREAK) && | |
937 | (mwait_substates & (0xF << 28)); | |
938 | } | |
939 | ||
940 | /* | |
941 | * Check whether the system supports PC10. If so force disable HPET as that | |
942 | * stops counting in PC10. This check is overbroad as it does not take any | |
943 | * of the following into account: | |
944 | * | |
945 | * - ACPI tables | |
946 | * - Enablement of intel_idle | |
947 | * - Command line arguments which limit intel_idle C-state support | |
948 | * | |
949 | * That's perfectly fine. HPET is a piece of hardware designed by committee | |
950 | * and the only reasons why it is still in use on modern systems is the | |
951 | * fact that it is impossible to reliably query TSC and CPU frequency via | |
952 | * CPUID or firmware. | |
953 | * | |
954 | * If HPET is functional it is useful for calibrating TSC, but this can be | |
955 | * done via PMTIMER as well which seems to be the last remaining timer on | |
956 | * X86/INTEL platforms that has not been completely wreckaged by feature | |
957 | * creep. | |
958 | * | |
959 | * In theory HPET support should be removed altogether, but there are older | |
960 | * systems out there which depend on it because TSC and APIC timer are | |
961 | * dysfunctional in deeper C-states. | |
962 | * | |
963 | * It's only 20 years now that hardware people have been asked to provide | |
964 | * reliable and discoverable facilities which can be used for timekeeping | |
965 | * and per CPU timer interrupts. | |
966 | * | |
967 | * The probability that this problem is going to be solved in the | |
54aa699e | 968 | * foreseeable future is close to zero, so the kernel has to be cluttered |
6e3cd952 TG |
969 | * with heuristics to keep up with the ever growing amount of hardware and |
970 | * firmware trainwrecks. Hopefully some day hardware people will understand | |
971 | * that the approach of "This can be fixed in software" is not sustainable. | |
972 | * Hope dies last... | |
973 | */ | |
974 | static bool __init hpet_is_pc10_damaged(void) | |
975 | { | |
976 | unsigned long long pcfg; | |
977 | ||
978 | /* Check whether PC10 substates are supported */ | |
979 | if (!mwait_pc10_supported()) | |
980 | return false; | |
981 | ||
982 | /* Check whether PC10 is enabled in PKG C-state limit */ | |
983 | rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg); | |
984 | if ((pcfg & 0xF) < 8) | |
985 | return false; | |
986 | ||
987 | if (hpet_force_user) { | |
988 | pr_warn("HPET force enabled via command line, but dysfunctional in PC10.\n"); | |
989 | return false; | |
990 | } | |
991 | ||
992 | pr_info("HPET dysfunctional in PC10. Force disabled.\n"); | |
993 | boot_hpet_disable = true; | |
994 | return true; | |
995 | } | |
996 | ||
b02a7f22 PM |
997 | /** |
998 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
999 | */ |
1000 | int __init hpet_enable(void) | |
1001 | { | |
2460d587 | 1002 | u32 hpet_period, cfg, id, irq; |
9b0b28de | 1003 | unsigned int i, channels; |
e37f0881 | 1004 | struct hpet_channel *hc; |
ab0e08f1 | 1005 | u64 freq; |
610bf2f1 VP |
1006 | |
1007 | if (!is_hpet_capable()) | |
1008 | return 0; | |
1009 | ||
6e3cd952 TG |
1010 | if (hpet_is_pc10_damaged()) |
1011 | return 0; | |
1012 | ||
610bf2f1 | 1013 | hpet_set_mapping(); |
2e84f116 AP |
1014 | if (!hpet_virt_address) |
1015 | return 0; | |
610bf2f1 | 1016 | |
9b0b28de TG |
1017 | /* Validate that the config register is working */ |
1018 | if (!hpet_cfg_working()) | |
1019 | goto out_nohpet; | |
1020 | ||
610bf2f1 VP |
1021 | /* |
1022 | * Read the period and check for a sane value: | |
1023 | */ | |
1024 | hpet_period = hpet_readl(HPET_PERIOD); | |
1025 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) | |
1026 | goto out_nohpet; | |
1027 | ||
9b0b28de | 1028 | /* The period is a femtoseconds value. Convert it to a frequency. */ |
ab0e08f1 TG |
1029 | freq = FSEC_PER_SEC; |
1030 | do_div(freq, hpet_period); | |
1031 | hpet_freq = freq; | |
1032 | ||
610bf2f1 VP |
1033 | /* |
1034 | * Read the HPET ID register to retrieve the IRQ routing | |
1035 | * information and the number of channels | |
1036 | */ | |
1037 | id = hpet_readl(HPET_ID); | |
b98103a5 | 1038 | hpet_print_config(); |
610bf2f1 | 1039 | |
9b0b28de TG |
1040 | /* This is the HPET channel number which is zero based */ |
1041 | channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
396e2c6f | 1042 | |
610bf2f1 VP |
1043 | /* |
1044 | * The legacy routing mode needs at least two channels, tick timer | |
1045 | * and the rtc emulation channel. | |
1046 | */ | |
e37f0881 | 1047 | if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2) |
610bf2f1 | 1048 | goto out_nohpet; |
610bf2f1 | 1049 | |
e37f0881 TG |
1050 | hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL); |
1051 | if (!hc) { | |
1052 | pr_warn("Disabling HPET.\n"); | |
1053 | goto out_nohpet; | |
1054 | } | |
1055 | hpet_base.channels = hc; | |
1056 | hpet_base.nr_channels = channels; | |
1057 | ||
1058 | /* Read, store and sanitize the global configuration */ | |
396e2c6f | 1059 | cfg = hpet_readl(HPET_CFG); |
e37f0881 | 1060 | hpet_base.boot_cfg = cfg; |
396e2c6f | 1061 | cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY); |
1b38a3a1 | 1062 | hpet_writel(cfg, HPET_CFG); |
396e2c6f | 1063 | if (cfg) |
46e5b64f | 1064 | pr_warn("Global config: Unknown bits %#x\n", cfg); |
396e2c6f | 1065 | |
e37f0881 TG |
1066 | /* Read, store and sanitize the per channel configuration */ |
1067 | for (i = 0; i < channels; i++, hc++) { | |
1068 | hc->num = i; | |
1069 | ||
396e2c6f | 1070 | cfg = hpet_readl(HPET_Tn_CFG(i)); |
e37f0881 | 1071 | hc->boot_cfg = cfg; |
2460d587 TG |
1072 | irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; |
1073 | hc->irq = irq; | |
e37f0881 | 1074 | |
396e2c6f JB |
1075 | cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB); |
1076 | hpet_writel(cfg, HPET_Tn_CFG(i)); | |
e37f0881 | 1077 | |
396e2c6f JB |
1078 | cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP |
1079 | | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE | |
1080 | | HPET_TN_FSB | HPET_TN_FSB_CAP); | |
1081 | if (cfg) | |
46e5b64f | 1082 | pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg); |
396e2c6f JB |
1083 | } |
1084 | hpet_print_config(); | |
1085 | ||
643d83f0 TG |
1086 | /* |
1087 | * Validate that the counter is counting. This needs to be done | |
1088 | * after sanitizing the config registers to properly deal with | |
1089 | * force enabled HPETs. | |
1090 | */ | |
1091 | if (!hpet_counting()) | |
1092 | goto out_nohpet; | |
1093 | ||
efc8b329 PM |
1094 | if (tsc_clocksource_watchdog_disabled()) |
1095 | clocksource_hpet.flags |= CLOCK_SOURCE_MUST_VERIFY; | |
3222daf9 | 1096 | clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq); |
610bf2f1 | 1097 | |
e9e2cdb4 | 1098 | if (id & HPET_ID_LEGSUP) { |
e44252f4 | 1099 | hpet_legacy_clockevent_register(&hpet_base.channels[0]); |
9e16e493 TG |
1100 | hpet_base.channels[0].mode = HPET_MODE_LEGACY; |
1101 | if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC)) | |
1102 | hpet_base.channels[1].mode = HPET_MODE_LEGACY; | |
e9e2cdb4 TG |
1103 | return 1; |
1104 | } | |
1105 | return 0; | |
5d0cf410 | 1106 | |
e9e2cdb4 | 1107 | out_nohpet: |
e37f0881 TG |
1108 | kfree(hpet_base.channels); |
1109 | hpet_base.channels = NULL; | |
1110 | hpet_base.nr_channels = 0; | |
06a24dec | 1111 | hpet_clear_mapping(); |
bacbe999 | 1112 | hpet_address = 0; |
e9e2cdb4 TG |
1113 | return 0; |
1114 | } | |
1115 | ||
28769149 | 1116 | /* |
9b0b28de TG |
1117 | * The late initialization runs after the PCI quirks have been invoked |
1118 | * which might have detected a system on which the HPET can be enforced. | |
4d5e6833 TG |
1119 | * |
1120 | * Also, the MSI machinery is not working yet when the HPET is initialized | |
1121 | * early. | |
1122 | * | |
1123 | * If the HPET is enabled, then: | |
1124 | * | |
1125 | * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y | |
1126 | * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents | |
1127 | * 3) Setup /dev/hpet if CONFIG_HPET=y | |
1128 | * 4) Register hotplug callbacks when clockevents are available | |
28769149 TG |
1129 | */ |
1130 | static __init int hpet_late_init(void) | |
1131 | { | |
48d7f6c7 | 1132 | int ret; |
26afe5f2 | 1133 | |
59c69f2a VP |
1134 | if (!hpet_address) { |
1135 | if (!force_hpet_address) | |
1136 | return -ENODEV; | |
1137 | ||
1138 | hpet_address = force_hpet_address; | |
1139 | hpet_enable(); | |
59c69f2a VP |
1140 | } |
1141 | ||
39c04b55 JF |
1142 | if (!hpet_virt_address) |
1143 | return -ENODEV; | |
1144 | ||
4d5e6833 TG |
1145 | hpet_select_device_channel(); |
1146 | hpet_select_clockevents(); | |
2460d587 | 1147 | hpet_reserve_platform_timers(); |
b98103a5 | 1148 | hpet_print_config(); |
59c69f2a | 1149 | |
4d5e6833 | 1150 | if (!hpet_base.nr_clockevents) |
39fe05e5 SL |
1151 | return 0; |
1152 | ||
73c1b41e | 1153 | ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online", |
48d7f6c7 SAS |
1154 | hpet_cpuhp_online, NULL); |
1155 | if (ret) | |
1156 | return ret; | |
73c1b41e | 1157 | ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL, |
48d7f6c7 SAS |
1158 | hpet_cpuhp_dead); |
1159 | if (ret) | |
1160 | goto err_cpuhp; | |
28769149 | 1161 | return 0; |
48d7f6c7 SAS |
1162 | |
1163 | err_cpuhp: | |
1164 | cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE); | |
1165 | return ret; | |
28769149 TG |
1166 | } |
1167 | fs_initcall(hpet_late_init); | |
1168 | ||
c86c7fbc OH |
1169 | void hpet_disable(void) |
1170 | { | |
e37f0881 TG |
1171 | unsigned int i; |
1172 | u32 cfg; | |
396e2c6f | 1173 | |
e37f0881 TG |
1174 | if (!is_hpet_capable() || !hpet_virt_address) |
1175 | return; | |
396e2c6f | 1176 | |
e37f0881 TG |
1177 | /* Restore boot configuration with the enable bit cleared */ |
1178 | cfg = hpet_base.boot_cfg; | |
1179 | cfg &= ~HPET_CFG_ENABLE; | |
1180 | hpet_writel(cfg, HPET_CFG); | |
396e2c6f | 1181 | |
e37f0881 TG |
1182 | /* Restore the channel boot configuration */ |
1183 | for (i = 0; i < hpet_base.nr_channels; i++) | |
1184 | hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i)); | |
396e2c6f | 1185 | |
e37f0881 TG |
1186 | /* If the HPET was enabled at boot time, reenable it */ |
1187 | if (hpet_base.boot_cfg & HPET_CFG_ENABLE) | |
1188 | hpet_writel(hpet_base.boot_cfg, HPET_CFG); | |
c86c7fbc OH |
1189 | } |
1190 | ||
e9e2cdb4 TG |
1191 | #ifdef CONFIG_HPET_EMULATE_RTC |
1192 | ||
dfe36b57 IM |
1193 | /* |
1194 | * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET | |
e9e2cdb4 | 1195 | * is enabled, we support RTC interrupt functionality in software. |
dfe36b57 | 1196 | * |
e9e2cdb4 | 1197 | * RTC has 3 kinds of interrupts: |
dfe36b57 IM |
1198 | * |
1199 | * 1) Update Interrupt - generate an interrupt, every second, when the | |
1200 | * RTC clock is updated | |
1201 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
1202 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
1203 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2) | |
1204 | * | |
1205 | * (1) and (2) above are implemented using polling at a frequency of 64 Hz: | |
1206 | * DEFAULT_RTC_INT_FREQ. | |
1207 | * | |
1208 | * The exact frequency is a tradeoff between accuracy and interrupt overhead. | |
1209 | * | |
1210 | * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency, | |
1211 | * if it's higher. | |
e9e2cdb4 TG |
1212 | */ |
1213 | #include <linux/mc146818rtc.h> | |
1214 | #include <linux/rtc.h> | |
1215 | ||
1216 | #define DEFAULT_RTC_INT_FREQ 64 | |
1217 | #define DEFAULT_RTC_SHIFT 6 | |
1218 | #define RTC_NUM_INTS 1 | |
1219 | ||
1220 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 1221 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
1222 | static struct rtc_time hpet_alarm_time; |
1223 | static unsigned long hpet_pie_count; | |
ff08f76d | 1224 | static u32 hpet_t1_cmp; |
5946fa3d JB |
1225 | static u32 hpet_default_delta; |
1226 | static u32 hpet_pie_delta; | |
e9e2cdb4 TG |
1227 | static unsigned long hpet_pie_limit; |
1228 | ||
1bdbdaac BW |
1229 | static rtc_irq_handler irq_handler; |
1230 | ||
ff08f76d | 1231 | /* |
dfe36b57 | 1232 | * Check that the HPET counter c1 is ahead of c2 |
ff08f76d PE |
1233 | */ |
1234 | static inline int hpet_cnt_ahead(u32 c1, u32 c2) | |
1235 | { | |
1236 | return (s32)(c2 - c1) < 0; | |
1237 | } | |
1238 | ||
1bdbdaac BW |
1239 | /* |
1240 | * Registers a IRQ handler. | |
1241 | */ | |
1242 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
1243 | { | |
1244 | if (!is_hpet_enabled()) | |
1245 | return -ENODEV; | |
1246 | if (irq_handler) | |
1247 | return -EBUSY; | |
1248 | ||
1249 | irq_handler = handler; | |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
1254 | ||
1255 | /* | |
1256 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
1257 | * and does cleanup. | |
1258 | */ | |
1259 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
1260 | { | |
1261 | if (!is_hpet_enabled()) | |
1262 | return; | |
1263 | ||
1264 | irq_handler = NULL; | |
1265 | hpet_rtc_flags = 0; | |
1266 | } | |
1267 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
1268 | ||
e9e2cdb4 | 1269 | /* |
d415c754 IM |
1270 | * Channel 1 for RTC emulation. We use one shot mode, as periodic mode |
1271 | * is not supported by all HPET implementations for channel 1. | |
e9e2cdb4 TG |
1272 | * |
1273 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
1274 | */ | |
1275 | int hpet_rtc_timer_init(void) | |
1276 | { | |
5946fa3d JB |
1277 | unsigned int cfg, cnt, delta; |
1278 | unsigned long flags; | |
e9e2cdb4 TG |
1279 | |
1280 | if (!is_hpet_enabled()) | |
1281 | return 0; | |
1282 | ||
1283 | if (!hpet_default_delta) { | |
e44252f4 | 1284 | struct clock_event_device *evt = &hpet_base.channels[0].evt; |
e9e2cdb4 TG |
1285 | uint64_t clc; |
1286 | ||
18e84a2d TG |
1287 | clc = (uint64_t) evt->mult * NSEC_PER_SEC; |
1288 | clc >>= evt->shift + DEFAULT_RTC_SHIFT; | |
5946fa3d | 1289 | hpet_default_delta = clc; |
e9e2cdb4 TG |
1290 | } |
1291 | ||
1292 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1293 | delta = hpet_default_delta; | |
1294 | else | |
1295 | delta = hpet_pie_delta; | |
1296 | ||
1297 | local_irq_save(flags); | |
1298 | ||
1299 | cnt = delta + hpet_readl(HPET_COUNTER); | |
1300 | hpet_writel(cnt, HPET_T1_CMP); | |
1301 | hpet_t1_cmp = cnt; | |
1302 | ||
1303 | cfg = hpet_readl(HPET_T1_CFG); | |
1304 | cfg &= ~HPET_TN_PERIODIC; | |
1305 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
1306 | hpet_writel(cfg, HPET_T1_CFG); | |
1307 | ||
1308 | local_irq_restore(flags); | |
1309 | ||
1310 | return 1; | |
1311 | } | |
1bdbdaac | 1312 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 | 1313 | |
2ded6e6a ML |
1314 | static void hpet_disable_rtc_channel(void) |
1315 | { | |
3d45ac4b | 1316 | u32 cfg = hpet_readl(HPET_T1_CFG); |
0b5c597d | 1317 | |
2ded6e6a ML |
1318 | cfg &= ~HPET_TN_ENABLE; |
1319 | hpet_writel(cfg, HPET_T1_CFG); | |
1320 | } | |
1321 | ||
e9e2cdb4 TG |
1322 | /* |
1323 | * The functions below are called from rtc driver. | |
1324 | * Return 0 if HPET is not being used. | |
1325 | * Otherwise do the necessary changes and return 1. | |
1326 | */ | |
1327 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
1328 | { | |
1329 | if (!is_hpet_enabled()) | |
1330 | return 0; | |
1331 | ||
1332 | hpet_rtc_flags &= ~bit_mask; | |
2ded6e6a ML |
1333 | if (unlikely(!hpet_rtc_flags)) |
1334 | hpet_disable_rtc_channel(); | |
1335 | ||
e9e2cdb4 TG |
1336 | return 1; |
1337 | } | |
1bdbdaac | 1338 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
1339 | |
1340 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
1341 | { | |
1342 | unsigned long oldbits = hpet_rtc_flags; | |
1343 | ||
1344 | if (!is_hpet_enabled()) | |
1345 | return 0; | |
1346 | ||
1347 | hpet_rtc_flags |= bit_mask; | |
1348 | ||
7e2a31da DB |
1349 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
1350 | hpet_prev_update_sec = -1; | |
1351 | ||
e9e2cdb4 TG |
1352 | if (!oldbits) |
1353 | hpet_rtc_timer_init(); | |
1354 | ||
1355 | return 1; | |
1356 | } | |
1bdbdaac | 1357 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 | 1358 | |
0b5c597d | 1359 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec) |
e9e2cdb4 TG |
1360 | { |
1361 | if (!is_hpet_enabled()) | |
1362 | return 0; | |
1363 | ||
1364 | hpet_alarm_time.tm_hour = hrs; | |
1365 | hpet_alarm_time.tm_min = min; | |
1366 | hpet_alarm_time.tm_sec = sec; | |
1367 | ||
1368 | return 1; | |
1369 | } | |
1bdbdaac | 1370 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
1371 | |
1372 | int hpet_set_periodic_freq(unsigned long freq) | |
1373 | { | |
1374 | uint64_t clc; | |
1375 | ||
1376 | if (!is_hpet_enabled()) | |
1377 | return 0; | |
1378 | ||
0b5c597d | 1379 | if (freq <= DEFAULT_RTC_INT_FREQ) { |
e9e2cdb4 | 1380 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; |
0b5c597d | 1381 | } else { |
e44252f4 | 1382 | struct clock_event_device *evt = &hpet_base.channels[0].evt; |
18e84a2d TG |
1383 | |
1384 | clc = (uint64_t) evt->mult * NSEC_PER_SEC; | |
e9e2cdb4 | 1385 | do_div(clc, freq); |
18e84a2d | 1386 | clc >>= evt->shift; |
5946fa3d | 1387 | hpet_pie_delta = clc; |
b4a5e8a1 | 1388 | hpet_pie_limit = 0; |
e9e2cdb4 | 1389 | } |
0b5c597d | 1390 | |
e9e2cdb4 TG |
1391 | return 1; |
1392 | } | |
1bdbdaac | 1393 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1394 | |
1395 | int hpet_rtc_dropped_irq(void) | |
1396 | { | |
1397 | return is_hpet_enabled(); | |
1398 | } | |
1bdbdaac | 1399 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1400 | |
1401 | static void hpet_rtc_timer_reinit(void) | |
1402 | { | |
2ded6e6a | 1403 | unsigned int delta; |
e9e2cdb4 TG |
1404 | int lost_ints = -1; |
1405 | ||
2ded6e6a ML |
1406 | if (unlikely(!hpet_rtc_flags)) |
1407 | hpet_disable_rtc_channel(); | |
e9e2cdb4 TG |
1408 | |
1409 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1410 | delta = hpet_default_delta; | |
1411 | else | |
1412 | delta = hpet_pie_delta; | |
1413 | ||
1414 | /* | |
1415 | * Increment the comparator value until we are ahead of the | |
1416 | * current count. | |
1417 | */ | |
1418 | do { | |
1419 | hpet_t1_cmp += delta; | |
1420 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1421 | lost_ints++; | |
ff08f76d | 1422 | } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER))); |
e9e2cdb4 TG |
1423 | |
1424 | if (lost_ints) { | |
1425 | if (hpet_rtc_flags & RTC_PIE) | |
1426 | hpet_pie_count += lost_ints; | |
1427 | if (printk_ratelimit()) | |
46e5b64f | 1428 | pr_warn("Lost %d RTC interrupts\n", lost_ints); |
e9e2cdb4 TG |
1429 | } |
1430 | } | |
1431 | ||
1432 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1433 | { | |
1434 | struct rtc_time curr_time; | |
1435 | unsigned long rtc_int_flag = 0; | |
1436 | ||
1437 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1438 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 | 1439 | |
0dd8d6cb | 1440 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) { |
120931db | 1441 | if (unlikely(mc146818_get_time(&curr_time, 10) < 0)) { |
0dd8d6cb MJ |
1442 | pr_err_ratelimited("unable to read current time from RTC\n"); |
1443 | return IRQ_HANDLED; | |
1444 | } | |
1445 | } | |
e9e2cdb4 TG |
1446 | |
1447 | if (hpet_rtc_flags & RTC_UIE && | |
1448 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1449 | if (hpet_prev_update_sec >= 0) |
1450 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1451 | hpet_prev_update_sec = curr_time.tm_sec; |
1452 | } | |
1453 | ||
0b5c597d | 1454 | if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) { |
e9e2cdb4 TG |
1455 | rtc_int_flag |= RTC_PF; |
1456 | hpet_pie_count = 0; | |
1457 | } | |
1458 | ||
8ee291f8 | 1459 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1460 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1461 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1462 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
0b5c597d | 1463 | rtc_int_flag |= RTC_AF; |
e9e2cdb4 TG |
1464 | |
1465 | if (rtc_int_flag) { | |
1466 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1467 | if (irq_handler) |
1468 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1469 | } |
1470 | return IRQ_HANDLED; | |
1471 | } | |
1bdbdaac | 1472 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1473 | #endif |