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pxafb: lcsr1 is unused without CONFIG_FB_PXA_OVERLAY
[linux-2.6-block.git] / arch / x86 / kernel / hpet.c
CommitLineData
5d0cf410 1#include <linux/clocksource.h>
e9e2cdb4 2#include <linux/clockchips.h>
4588c1f0
IM		 3#include <linux/interrupt.h>
4#include <linux/sysdev.h>
28769149 5#include <linux/delay.h>
5d0cf410 6#include <linux/errno.h>
7#include <linux/hpet.h>
8#include <linux/init.h>
58ac1e76 9#include <linux/cpu.h>
4588c1f0
IM		 10#include <linux/pm.h>
11#include <linux/io.h>
5d0cf410 12
28769149 13#include <asm/fixmap.h>
06a24dec 14#include <asm/i8253.h>
4588c1f0 15#include <asm/hpet.h>
5d0cf410 16
4588c1f0
IM		 17#define HPET_MASK CLOCKSOURCE_MASK(32)
18#define HPET_SHIFT 22
5d0cf410 19
b10db7f0
PM		 20/* FSEC = 10^-15
21 NSEC = 10^-9 */
4588c1f0 22#define FSEC_PER_NSEC 1000000L
5d0cf410 23
26afe5f2 24#define HPET_DEV_USED_BIT 2
25#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26#define HPET_DEV_VALID 0x8
27#define HPET_DEV_FSB_CAP 0x1000
28#define HPET_DEV_PERI_CAP 0x2000
29
30#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
31
e9e2cdb4
TG		 32/*
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
34 */
4588c1f0 35unsigned long hpet_address;
e951e4af 36#ifdef CONFIG_PCI_MSI
3b71e9e3 37static unsigned long hpet_num_timers;
e951e4af 38#endif
4588c1f0 39static void __iomem *hpet_virt_address;
e9e2cdb4 40
58ac1e76 41struct hpet_dev {
4588c1f0
IM		 42 struct clock_event_device evt;
43 unsigned int num;
44 int cpu;
45 unsigned int irq;
46 unsigned int flags;
47 char name[10];
58ac1e76 48};
49
31c435d7 50unsigned long hpet_readl(unsigned long a)
e9e2cdb4
TG		 51{
52 return readl(hpet_virt_address + a);
53}
54
55static inline void hpet_writel(unsigned long d, unsigned long a)
56{
57 writel(d, hpet_virt_address + a);
58}
59
28769149 60#ifdef CONFIG_X86_64
28769149 61#include <asm/pgtable.h>
2387ce57 62#endif
28769149 63
06a24dec
TG		 64static inline void hpet_set_mapping(void)
65{
66 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
2387ce57
YL		 67#ifdef CONFIG_X86_64
68 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
69#endif
06a24dec
TG		 70}
71
72static inline void hpet_clear_mapping(void)
73{
74 iounmap(hpet_virt_address);
75 hpet_virt_address = NULL;
76}
77
e9e2cdb4
TG		 78/*
79 * HPET command line enable / disable
80 */
81static int boot_hpet_disable;
b17530bd 82int hpet_force_user;
b98103a5 83static int hpet_verbose;
e9e2cdb4 84
4588c1f0 85static int __init hpet_setup(char *str)
e9e2cdb4
TG		 86{
87 if (str) {
88 if (!strncmp("disable", str, 7))
89 boot_hpet_disable = 1;
b17530bd
TG		 90 if (!strncmp("force", str, 5))
91 hpet_force_user = 1;
b98103a5
AH		 92 if (!strncmp("verbose", str, 7))
93 hpet_verbose = 1;
e9e2cdb4
TG		 94 }
95 return 1;
96}
97__setup("hpet=", hpet_setup);
98
28769149
TG		 99static int __init disable_hpet(char *str)
100{
101 boot_hpet_disable = 1;
102 return 1;
103}
104__setup("nohpet", disable_hpet);
105
e9e2cdb4
TG		 106static inline int is_hpet_capable(void)
107{
4588c1f0 108 return !boot_hpet_disable && hpet_address;
e9e2cdb4
TG		 109}
110
111/*
112 * HPET timer interrupt enable / disable
113 */
114static int hpet_legacy_int_enabled;
115
116/**
117 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
118 */
119int is_hpet_enabled(void)
120{
121 return is_hpet_capable() && hpet_legacy_int_enabled;
122}
1bdbdaac 123EXPORT_SYMBOL_GPL(is_hpet_enabled);
e9e2cdb4 124
b98103a5
AH		 125static void _hpet_print_config(const char *function, int line)
126{
127 u32 i, timers, l, h;
128 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
129 l = hpet_readl(HPET_ID);
130 h = hpet_readl(HPET_PERIOD);
131 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
132 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
133 l = hpet_readl(HPET_CFG);
134 h = hpet_readl(HPET_STATUS);
135 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
136 l = hpet_readl(HPET_COUNTER);
137 h = hpet_readl(HPET_COUNTER+4);
138 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
139
140 for (i = 0; i < timers; i++) {
141 l = hpet_readl(HPET_Tn_CFG(i));
142 h = hpet_readl(HPET_Tn_CFG(i)+4);
143 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
144 i, l, h);
145 l = hpet_readl(HPET_Tn_CMP(i));
146 h = hpet_readl(HPET_Tn_CMP(i)+4);
147 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
148 i, l, h);
149 l = hpet_readl(HPET_Tn_ROUTE(i));
150 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
151 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
152 i, l, h);
153 }
154}
155
156#define hpet_print_config() \
157do { \
158 if (hpet_verbose) \
159 _hpet_print_config(__FUNCTION__, __LINE__); \
160} while (0)
161
e9e2cdb4
TG		 162/*
163 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
164 * timer 0 and timer 1 in case of RTC emulation.
165 */
166#ifdef CONFIG_HPET
f0ed4e69 167
5f79f2f2 168static void hpet_reserve_msi_timers(struct hpet_data *hd);
f0ed4e69 169
e9e2cdb4
TG		 170static void hpet_reserve_platform_timers(unsigned long id)
171{
172 struct hpet __iomem *hpet = hpet_virt_address;
37a47db8
BR		 173 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
174 unsigned int nrtimers, i;
e9e2cdb4
TG		 175 struct hpet_data hd;
176
177 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
178
4588c1f0
IM		 179 memset(&hd, 0, sizeof(hd));
180 hd.hd_phys_address = hpet_address;
181 hd.hd_address = hpet;
182 hd.hd_nirqs = nrtimers;
e9e2cdb4
TG		 183 hpet_reserve_timer(&hd, 0);
184
185#ifdef CONFIG_HPET_EMULATE_RTC
186 hpet_reserve_timer(&hd, 1);
187#endif
5761d64b 188
64a76f66
DB		 189 /*
190 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
191 * is wrong for i8259!) not the output IRQ. Many BIOS writers
192 * don't bother configuring *any* comparator interrupts.
193 */
e9e2cdb4
TG		 194 hd.hd_irq[0] = HPET_LEGACY_8254;
195 hd.hd_irq[1] = HPET_LEGACY_RTC;
196
fc3fbc45 197 for (i = 2; i < nrtimers; timer++, i++) {
4588c1f0
IM		 198 hd.hd_irq[i] = (readl(&timer->hpet_config) &
199 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
fc3fbc45 200 }
5761d64b 201
f0ed4e69 202 hpet_reserve_msi_timers(&hd);
26afe5f2 203
e9e2cdb4 204 hpet_alloc(&hd);
5761d64b 205
e9e2cdb4
TG		 206}
207#else
208static void hpet_reserve_platform_timers(unsigned long id) { }
209#endif
210
211/*
212 * Common hpet info
213 */
214static unsigned long hpet_period;
215
610bf2f1 216static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 217 struct clock_event_device *evt);
610bf2f1 218static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4
TG		 219 struct clock_event_device *evt);
220
221/*
222 * The hpet clock event device
223 */
224static struct clock_event_device hpet_clockevent = {
225 .name = "hpet",
226 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
610bf2f1
VP		 227 .set_mode = hpet_legacy_set_mode,
228 .set_next_event = hpet_legacy_next_event,
e9e2cdb4
TG		 229 .shift = 32,
230 .irq = 0,
59c69f2a 231 .rating = 50,
e9e2cdb4
TG		 232};
233
8d6f0c82 234static void hpet_stop_counter(void)
e9e2cdb4
TG		 235{
236 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 237 cfg &= ~HPET_CFG_ENABLE;
238 hpet_writel(cfg, HPET_CFG);
239 hpet_writel(0, HPET_COUNTER);
240 hpet_writel(0, HPET_COUNTER + 4);
8d6f0c82
AH		 241}
242
243static void hpet_start_counter(void)
244{
245 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 246 cfg |= HPET_CFG_ENABLE;
247 hpet_writel(cfg, HPET_CFG);
248}
249
8d6f0c82
AH		 250static void hpet_restart_counter(void)
251{
252 hpet_stop_counter();
253 hpet_start_counter();
254}
255
59c69f2a
VP		 256static void hpet_resume_device(void)
257{
bfe0c1cc 258 force_hpet_resume();
59c69f2a
VP		 259}
260
8d6f0c82 261static void hpet_resume_counter(void)
59c69f2a
VP		 262{
263 hpet_resume_device();
8d6f0c82 264 hpet_restart_counter();
59c69f2a
VP		 265}
266
610bf2f1 267static void hpet_enable_legacy_int(void)
e9e2cdb4
TG		 268{
269 unsigned long cfg = hpet_readl(HPET_CFG);
270
271 cfg |= HPET_CFG_LEGACY;
272 hpet_writel(cfg, HPET_CFG);
273 hpet_legacy_int_enabled = 1;
274}
275
610bf2f1
VP		 276static void hpet_legacy_clockevent_register(void)
277{
610bf2f1
VP		 278 /* Start HPET legacy interrupts */
279 hpet_enable_legacy_int();
280
281 /*
6fd592da
CM		 282 * The mult factor is defined as (include/linux/clockchips.h)
283 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
284 * hpet_period is in units of femtoseconds (per cycle), so
285 * mult/2^shift = cyc/ns = 10^6/hpet_period
286 * mult = (10^6 * 2^shift)/hpet_period
287 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
610bf2f1 288 */
6fd592da
CM		 289 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
290 hpet_period, hpet_clockevent.shift);
610bf2f1
VP		 291 /* Calculate the min / max delta */
292 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
293 &hpet_clockevent);
7cfb0435
TG		 294 /* 5 usec minimum reprogramming delta. */
295 hpet_clockevent.min_delta_ns = 5000;
610bf2f1
VP		 296
297 /*
298 * Start hpet with the boot cpu mask and make it
299 * global after the IO_APIC has been initialized.
300 */
320ab2b0 301 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
610bf2f1
VP		 302 clockevents_register_device(&hpet_clockevent);
303 global_clock_event = &hpet_clockevent;
304 printk(KERN_DEBUG "hpet clockevent registered\n");
305}
306
26afe5f2 307static int hpet_setup_msi_irq(unsigned int irq);
308
b40d575b 309static void hpet_set_mode(enum clock_event_mode mode,
310 struct clock_event_device *evt, int timer)
e9e2cdb4 311{
c23e253e 312 unsigned long cfg;
e9e2cdb4
TG		 313 uint64_t delta;
314
4588c1f0 315 switch (mode) {
e9e2cdb4 316 case CLOCK_EVT_MODE_PERIODIC:
c23e253e 317 hpet_stop_counter();
b40d575b 318 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
319 delta >>= evt->shift;
b40d575b 320 cfg = hpet_readl(HPET_Tn_CFG(timer));
b13e2464 321 /* Make sure we use edge triggered interrupts */
322 cfg &= ~HPET_TN_LEVEL;
e9e2cdb4
TG		 323 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
324 HPET_TN_SETVAL | HPET_TN_32BIT;
b40d575b 325 hpet_writel(cfg, HPET_Tn_CFG(timer));
b40d575b 326 hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
c23e253e 327 hpet_start_counter();
b98103a5 328 hpet_print_config();
e9e2cdb4
TG		 329 break;
330
331 case CLOCK_EVT_MODE_ONESHOT:
b40d575b 332 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 333 cfg &= ~HPET_TN_PERIODIC;
334 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
b40d575b 335 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4
TG		 336 break;
337
338 case CLOCK_EVT_MODE_UNUSED:
339 case CLOCK_EVT_MODE_SHUTDOWN:
b40d575b 340 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4 341 cfg &= ~HPET_TN_ENABLE;
b40d575b 342 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4 343 break;
18de5bc4
TG		 344
345 case CLOCK_EVT_MODE_RESUME:
26afe5f2 346 if (timer == 0) {
347 hpet_enable_legacy_int();
348 } else {
349 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
350 hpet_setup_msi_irq(hdev->irq);
351 disable_irq(hdev->irq);
0de26520 352 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
26afe5f2 353 enable_irq(hdev->irq);
354 }
b98103a5 355 hpet_print_config();
18de5bc4 356 break;
e9e2cdb4
TG		 357 }
358}
359
b40d575b 360static int hpet_next_event(unsigned long delta,
361 struct clock_event_device *evt, int timer)
e9e2cdb4 362{
f7676254 363 u32 cnt;
e9e2cdb4
TG		 364
365 cnt = hpet_readl(HPET_COUNTER);
f7676254 366 cnt += (u32) delta;
b40d575b 367 hpet_writel(cnt, HPET_Tn_CMP(timer));
e9e2cdb4 368
72d43d9b
TG		 369 /*
370 * We need to read back the CMP register to make sure that
371 * what we wrote hit the chip before we compare it to the
372 * counter.
373 */
89d77a1e 374 WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
72d43d9b 375
f7676254 376 return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
e9e2cdb4
TG		 377}
378
b40d575b 379static void hpet_legacy_set_mode(enum clock_event_mode mode,
380 struct clock_event_device *evt)
381{
382 hpet_set_mode(mode, evt, 0);
383}
384
385static int hpet_legacy_next_event(unsigned long delta,
386 struct clock_event_device *evt)
387{
388 return hpet_next_event(delta, evt, 0);
389}
390
58ac1e76 391/*
392 * HPET MSI Support
393 */
26afe5f2 394#ifdef CONFIG_PCI_MSI
5f79f2f2
VP		 395
396static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
397static struct hpet_dev *hpet_devs;
398
58ac1e76 399void hpet_msi_unmask(unsigned int irq)
400{
401 struct hpet_dev *hdev = get_irq_data(irq);
402 unsigned long cfg;
403
404 /* unmask it */
405 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
406 cfg |= HPET_TN_FSB;
407 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
408}
409
410void hpet_msi_mask(unsigned int irq)
411{
412 unsigned long cfg;
413 struct hpet_dev *hdev = get_irq_data(irq);
414
415 /* mask it */
416 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
417 cfg &= ~HPET_TN_FSB;
418 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
419}
420
421void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
422{
423 struct hpet_dev *hdev = get_irq_data(irq);
424
425 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
426 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
427}
428
429void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
430{
431 struct hpet_dev *hdev = get_irq_data(irq);
432
433 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
434 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
435 msg->address_hi = 0;
436}
437
26afe5f2 438static void hpet_msi_set_mode(enum clock_event_mode mode,
439 struct clock_event_device *evt)
440{
441 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
442 hpet_set_mode(mode, evt, hdev->num);
443}
444
445static int hpet_msi_next_event(unsigned long delta,
446 struct clock_event_device *evt)
447{
448 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
449 return hpet_next_event(delta, evt, hdev->num);
450}
451
452static int hpet_setup_msi_irq(unsigned int irq)
453{
454 if (arch_setup_hpet_msi(irq)) {
455 destroy_irq(irq);
456 return -EINVAL;
457 }
458 return 0;
459}
460
461static int hpet_assign_irq(struct hpet_dev *dev)
462{
463 unsigned int irq;
464
465 irq = create_irq();
466 if (!irq)
467 return -EINVAL;
468
469 set_irq_data(irq, dev);
470
471 if (hpet_setup_msi_irq(irq))
472 return -EINVAL;
473
474 dev->irq = irq;
475 return 0;
476}
477
478static irqreturn_t hpet_interrupt_handler(int irq, void *data)
479{
480 struct hpet_dev *dev = (struct hpet_dev *)data;
481 struct clock_event_device *hevt = &dev->evt;
482
483 if (!hevt->event_handler) {
484 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
485 dev->num);
486 return IRQ_HANDLED;
487 }
488
489 hevt->event_handler(hevt);
490 return IRQ_HANDLED;
491}
492
493static int hpet_setup_irq(struct hpet_dev *dev)
494{
495
496 if (request_irq(dev->irq, hpet_interrupt_handler,
5ceb1a04 497 IRQF_DISABLED|IRQF_NOBALANCING, dev->name, dev))
26afe5f2 498 return -1;
499
500 disable_irq(dev->irq);
0de26520 501 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
26afe5f2 502 enable_irq(dev->irq);
503
c81bba49
YL		 504 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
505 dev->name, dev->irq);
506
26afe5f2 507 return 0;
508}
509
510/* This should be called in specific @cpu */
511static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
512{
513 struct clock_event_device *evt = &hdev->evt;
514 uint64_t hpet_freq;
515
516 WARN_ON(cpu != smp_processor_id());
517 if (!(hdev->flags & HPET_DEV_VALID))
518 return;
519
520 if (hpet_setup_msi_irq(hdev->irq))
521 return;
522
523 hdev->cpu = cpu;
524 per_cpu(cpu_hpet_dev, cpu) = hdev;
525 evt->name = hdev->name;
526 hpet_setup_irq(hdev);
527 evt->irq = hdev->irq;
528
529 evt->rating = 110;
530 evt->features = CLOCK_EVT_FEAT_ONESHOT;
531 if (hdev->flags & HPET_DEV_PERI_CAP)
532 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
533
534 evt->set_mode = hpet_msi_set_mode;
535 evt->set_next_event = hpet_msi_next_event;
536 evt->shift = 32;
537
538 /*
539 * The period is a femto seconds value. We need to calculate the
540 * scaled math multiplication factor for nanosecond to hpet tick
541 * conversion.
542 */
543 hpet_freq = 1000000000000000ULL;
544 do_div(hpet_freq, hpet_period);
545 evt->mult = div_sc((unsigned long) hpet_freq,
546 NSEC_PER_SEC, evt->shift);
547 /* Calculate the max delta */
548 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
549 /* 5 usec minimum reprogramming delta. */
550 evt->min_delta_ns = 5000;
551
320ab2b0 552 evt->cpumask = cpumask_of(hdev->cpu);
26afe5f2 553 clockevents_register_device(evt);
554}
555
556#ifdef CONFIG_HPET
557/* Reserve at least one timer for userspace (/dev/hpet) */
558#define RESERVE_TIMERS 1
559#else
560#define RESERVE_TIMERS 0
561#endif
5f79f2f2
VP		 562
563static void hpet_msi_capability_lookup(unsigned int start_timer)
26afe5f2 564{
565 unsigned int id;
566 unsigned int num_timers;
567 unsigned int num_timers_used = 0;
568 int i;
569
570 id = hpet_readl(HPET_ID);
571
572 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
573 num_timers++; /* Value read out starts from 0 */
b98103a5 574 hpet_print_config();
26afe5f2 575
576 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
577 if (!hpet_devs)
578 return;
579
580 hpet_num_timers = num_timers;
581
582 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
583 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
584 unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
585
586 /* Only consider HPET timer with MSI support */
587 if (!(cfg & HPET_TN_FSB_CAP))
588 continue;
589
590 hdev->flags = 0;
591 if (cfg & HPET_TN_PERIODIC_CAP)
592 hdev->flags |= HPET_DEV_PERI_CAP;
593 hdev->num = i;
594
595 sprintf(hdev->name, "hpet%d", i);
596 if (hpet_assign_irq(hdev))
597 continue;
598
599 hdev->flags |= HPET_DEV_FSB_CAP;
600 hdev->flags |= HPET_DEV_VALID;
601 num_timers_used++;
602 if (num_timers_used == num_possible_cpus())
603 break;
604 }
605
606 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
607 num_timers, num_timers_used);
608}
609
5f79f2f2
VP		 610#ifdef CONFIG_HPET
611static void hpet_reserve_msi_timers(struct hpet_data *hd)
612{
613 int i;
614
615 if (!hpet_devs)
616 return;
617
618 for (i = 0; i < hpet_num_timers; i++) {
619 struct hpet_dev *hdev = &hpet_devs[i];
620
621 if (!(hdev->flags & HPET_DEV_VALID))
622 continue;
623
624 hd->hd_irq[hdev->num] = hdev->irq;
625 hpet_reserve_timer(hd, hdev->num);
626 }
627}
628#endif
629
26afe5f2 630static struct hpet_dev *hpet_get_unused_timer(void)
631{
632 int i;
633
634 if (!hpet_devs)
635 return NULL;
636
637 for (i = 0; i < hpet_num_timers; i++) {
638 struct hpet_dev *hdev = &hpet_devs[i];
639
640 if (!(hdev->flags & HPET_DEV_VALID))
641 continue;
642 if (test_and_set_bit(HPET_DEV_USED_BIT,
643 (unsigned long *)&hdev->flags))
644 continue;
645 return hdev;
646 }
647 return NULL;
648}
649
650struct hpet_work_struct {
651 struct delayed_work work;
652 struct completion complete;
653};
654
655static void hpet_work(struct work_struct *w)
656{
657 struct hpet_dev *hdev;
658 int cpu = smp_processor_id();
659 struct hpet_work_struct *hpet_work;
660
661 hpet_work = container_of(w, struct hpet_work_struct, work.work);
662
663 hdev = hpet_get_unused_timer();
664 if (hdev)
665 init_one_hpet_msi_clockevent(hdev, cpu);
666
667 complete(&hpet_work->complete);
668}
669
670static int hpet_cpuhp_notify(struct notifier_block *n,
671 unsigned long action, void *hcpu)
672{
673 unsigned long cpu = (unsigned long)hcpu;
674 struct hpet_work_struct work;
675 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
676
677 switch (action & 0xf) {
678 case CPU_ONLINE:
336f6c32 679 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
26afe5f2 680 init_completion(&work.complete);
681 /* FIXME: add schedule_work_on() */
682 schedule_delayed_work_on(cpu, &work.work, 0);
683 wait_for_completion(&work.complete);
336f6c32 684 destroy_timer_on_stack(&work.work.timer);
26afe5f2 685 break;
686 case CPU_DEAD:
687 if (hdev) {
688 free_irq(hdev->irq, hdev);
689 hdev->flags &= ~HPET_DEV_USED;
690 per_cpu(cpu_hpet_dev, cpu) = NULL;
691 }
692 break;
693 }
694 return NOTIFY_OK;
695}
696#else
697
ba374c9b
SN		 698static int hpet_setup_msi_irq(unsigned int irq)
699{
700 return 0;
701}
5f79f2f2
VP		 702static void hpet_msi_capability_lookup(unsigned int start_timer)
703{
704 return;
705}
706
707#ifdef CONFIG_HPET
708static void hpet_reserve_msi_timers(struct hpet_data *hd)
26afe5f2 709{
710 return;
711}
5f79f2f2 712#endif
26afe5f2 713
714static int hpet_cpuhp_notify(struct notifier_block *n,
715 unsigned long action, void *hcpu)
716{
717 return NOTIFY_OK;
718}
719
720#endif
721
6bb74df4 722/*
723 * Clock source related code
724 */
725static cycle_t read_hpet(void)
726{
727 return (cycle_t)hpet_readl(HPET_COUNTER);
728}
729
28769149
TG		 730#ifdef CONFIG_X86_64
731static cycle_t __vsyscall_fn vread_hpet(void)
732{
733 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
734}
735#endif
736
6bb74df4 737static struct clocksource clocksource_hpet = {
738 .name = "hpet",
739 .rating = 250,
740 .read = read_hpet,
741 .mask = HPET_MASK,
742 .shift = HPET_SHIFT,
743 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
8d6f0c82 744 .resume = hpet_resume_counter,
28769149
TG		 745#ifdef CONFIG_X86_64
746 .vread = vread_hpet,
747#endif
6bb74df4 748};
749
610bf2f1 750static int hpet_clocksource_register(void)
e9e2cdb4 751{
6fd592da 752 u64 start, now;
075bcd1f 753 cycle_t t1;
e9e2cdb4 754
e9e2cdb4 755 /* Start the counter */
8d6f0c82 756 hpet_restart_counter();
e9e2cdb4 757
075bcd1f
TG		 758 /* Verify whether hpet counter works */
759 t1 = read_hpet();
760 rdtscll(start);
761
762 /*
763 * We don't know the TSC frequency yet, but waiting for
764 * 200000 TSC cycles is safe:
765 * 4 GHz == 50us
766 * 1 GHz == 200us
767 */
768 do {
769 rep_nop();
770 rdtscll(now);
771 } while ((now - start) < 200000UL);
772
773 if (t1 == read_hpet()) {
774 printk(KERN_WARNING
775 "HPET counter not counting. HPET disabled\n");
610bf2f1 776 return -ENODEV;
075bcd1f
TG		 777 }
778
6fd592da
CM		 779 /*
780 * The definition of mult is (include/linux/clocksource.h)
781 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
782 * so we first need to convert hpet_period to ns/cyc units:
783 * mult/2^shift = ns/cyc = hpet_period/10^6
784 * mult = (hpet_period * 2^shift)/10^6
785 * mult = (hpet_period << shift)/FSEC_PER_NSEC
6bb74df4 786 */
6fd592da 787 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
6bb74df4 788
789 clocksource_register(&clocksource_hpet);
790
610bf2f1
VP		 791 return 0;
792}
793
b02a7f22
PM		 794/**
795 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
610bf2f1
VP		 796 */
797int __init hpet_enable(void)
798{
799 unsigned long id;
a6825f1c 800 int i;
610bf2f1
VP		 801
802 if (!is_hpet_capable())
803 return 0;
804
805 hpet_set_mapping();
806
807 /*
808 * Read the period and check for a sane value:
809 */
810 hpet_period = hpet_readl(HPET_PERIOD);
a6825f1c
TG		 811
812 /*
813 * AMD SB700 based systems with spread spectrum enabled use a
814 * SMM based HPET emulation to provide proper frequency
815 * setting. The SMM code is initialized with the first HPET
816 * register access and takes some time to complete. During
817 * this time the config register reads 0xffffffff. We check
818 * for max. 1000 loops whether the config register reads a non
819 * 0xffffffff value to make sure that HPET is up and running
820 * before we go further. A counting loop is safe, as the HPET
821 * access takes thousands of CPU cycles. On non SB700 based
822 * machines this check is only done once and has no side
823 * effects.
824 */
825 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
826 if (i == 1000) {
827 printk(KERN_WARNING
828 "HPET config register value = 0xFFFFFFFF. "
829 "Disabling HPET\n");
830 goto out_nohpet;
831 }
832 }
833
610bf2f1
VP		 834 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
835 goto out_nohpet;
836
837 /*
838 * Read the HPET ID register to retrieve the IRQ routing
839 * information and the number of channels
840 */
841 id = hpet_readl(HPET_ID);
b98103a5 842 hpet_print_config();
610bf2f1
VP		 843
844#ifdef CONFIG_HPET_EMULATE_RTC
845 /*
846 * The legacy routing mode needs at least two channels, tick timer
847 * and the rtc emulation channel.
848 */
849 if (!(id & HPET_ID_NUMBER))
850 goto out_nohpet;
851#endif
852
853 if (hpet_clocksource_register())
854 goto out_nohpet;
855
e9e2cdb4 856 if (id & HPET_ID_LEGSUP) {
610bf2f1 857 hpet_legacy_clockevent_register();
26afe5f2 858 hpet_msi_capability_lookup(2);
e9e2cdb4
TG		 859 return 1;
860 }
26afe5f2 861 hpet_msi_capability_lookup(0);
e9e2cdb4 862 return 0;
5d0cf410 863
e9e2cdb4 864out_nohpet:
06a24dec 865 hpet_clear_mapping();
bacbe999 866 hpet_address = 0;
e9e2cdb4
TG		 867 return 0;
868}
869
28769149
TG		 870/*
871 * Needs to be late, as the reserve_timer code calls kalloc !
872 *
873 * Not a problem on i386 as hpet_enable is called from late_time_init,
874 * but on x86_64 it is necessary !
875 */
876static __init int hpet_late_init(void)
877{
26afe5f2 878 int cpu;
879
59c69f2a 880 if (boot_hpet_disable)
28769149
TG		 881 return -ENODEV;
882
59c69f2a
VP		 883 if (!hpet_address) {
884 if (!force_hpet_address)
885 return -ENODEV;
886
887 hpet_address = force_hpet_address;
888 hpet_enable();
59c69f2a
VP		 889 }
890
39c04b55
JF		 891 if (!hpet_virt_address)
892 return -ENODEV;
893
28769149 894 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
b98103a5 895 hpet_print_config();
59c69f2a 896
26afe5f2 897 for_each_online_cpu(cpu) {
898 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
899 }
900
901 /* This notifier should be called after workqueue is ready */
902 hotcpu_notifier(hpet_cpuhp_notify, -20);
903
28769149
TG		 904 return 0;
905}
906fs_initcall(hpet_late_init);
907
c86c7fbc
OH		 908void hpet_disable(void)
909{
910 if (is_hpet_capable()) {
911 unsigned long cfg = hpet_readl(HPET_CFG);
912
913 if (hpet_legacy_int_enabled) {
914 cfg &= ~HPET_CFG_LEGACY;
915 hpet_legacy_int_enabled = 0;
916 }
917 cfg &= ~HPET_CFG_ENABLE;
918 hpet_writel(cfg, HPET_CFG);
919 }
920}
921
e9e2cdb4
TG		 922#ifdef CONFIG_HPET_EMULATE_RTC
923
924/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
925 * is enabled, we support RTC interrupt functionality in software.
926 * RTC has 3 kinds of interrupts:
927 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
928 * is updated
929 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
930 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
931 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
932 * (1) and (2) above are implemented using polling at a frequency of
933 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
934 * overhead. (DEFAULT_RTC_INT_FREQ)
935 * For (3), we use interrupts at 64Hz or user specified periodic
936 * frequency, whichever is higher.
937 */
938#include <linux/mc146818rtc.h>
939#include <linux/rtc.h>
1bdbdaac 940#include <asm/rtc.h>
e9e2cdb4
TG		 941
942#define DEFAULT_RTC_INT_FREQ 64
943#define DEFAULT_RTC_SHIFT 6
944#define RTC_NUM_INTS 1
945
946static unsigned long hpet_rtc_flags;
7e2a31da 947static int hpet_prev_update_sec;
e9e2cdb4
TG		 948static struct rtc_time hpet_alarm_time;
949static unsigned long hpet_pie_count;
ff08f76d 950static u32 hpet_t1_cmp;
e9e2cdb4
TG		 951static unsigned long hpet_default_delta;
952static unsigned long hpet_pie_delta;
953static unsigned long hpet_pie_limit;
954
1bdbdaac
BW		 955static rtc_irq_handler irq_handler;
956
ff08f76d
PE		 957/*
958 * Check that the hpet counter c1 is ahead of the c2
959 */
960static inline int hpet_cnt_ahead(u32 c1, u32 c2)
961{
962 return (s32)(c2 - c1) < 0;
963}
964
1bdbdaac
BW		 965/*
966 * Registers a IRQ handler.
967 */
968int hpet_register_irq_handler(rtc_irq_handler handler)
969{
970 if (!is_hpet_enabled())
971 return -ENODEV;
972 if (irq_handler)
973 return -EBUSY;
974
975 irq_handler = handler;
976
977 return 0;
978}
979EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
980
981/*
982 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
983 * and does cleanup.
984 */
985void hpet_unregister_irq_handler(rtc_irq_handler handler)
986{
987 if (!is_hpet_enabled())
988 return;
989
990 irq_handler = NULL;
991 hpet_rtc_flags = 0;
992}
993EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
994
e9e2cdb4
TG		 995/*
996 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
997 * is not supported by all HPET implementations for timer 1.
998 *
999 * hpet_rtc_timer_init() is called when the rtc is initialized.
1000 */
1001int hpet_rtc_timer_init(void)
1002{
1003 unsigned long cfg, cnt, delta, flags;
1004
1005 if (!is_hpet_enabled())
1006 return 0;
1007
1008 if (!hpet_default_delta) {
1009 uint64_t clc;
1010
1011 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1012 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1013 hpet_default_delta = (unsigned long) clc;
1014 }
1015
1016 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1017 delta = hpet_default_delta;
1018 else
1019 delta = hpet_pie_delta;
1020
1021 local_irq_save(flags);
1022
1023 cnt = delta + hpet_readl(HPET_COUNTER);
1024 hpet_writel(cnt, HPET_T1_CMP);
1025 hpet_t1_cmp = cnt;
1026
1027 cfg = hpet_readl(HPET_T1_CFG);
1028 cfg &= ~HPET_TN_PERIODIC;
1029 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1030 hpet_writel(cfg, HPET_T1_CFG);
1031
1032 local_irq_restore(flags);
1033
1034 return 1;
1035}
1bdbdaac 1036EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
e9e2cdb4
TG		 1037
1038/*
1039 * The functions below are called from rtc driver.
1040 * Return 0 if HPET is not being used.
1041 * Otherwise do the necessary changes and return 1.
1042 */
1043int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1044{
1045 if (!is_hpet_enabled())
1046 return 0;
1047
1048 hpet_rtc_flags &= ~bit_mask;
1049 return 1;
1050}
1bdbdaac 1051EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
e9e2cdb4
TG		 1052
1053int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1054{
1055 unsigned long oldbits = hpet_rtc_flags;
1056
1057 if (!is_hpet_enabled())
1058 return 0;
1059
1060 hpet_rtc_flags |= bit_mask;
1061
7e2a31da
DB		 1062 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1063 hpet_prev_update_sec = -1;
1064
e9e2cdb4
TG		 1065 if (!oldbits)
1066 hpet_rtc_timer_init();
1067
1068 return 1;
1069}
1bdbdaac 1070EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
e9e2cdb4
TG		 1071
1072int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1073 unsigned char sec)
1074{
1075 if (!is_hpet_enabled())
1076 return 0;
1077
1078 hpet_alarm_time.tm_hour = hrs;
1079 hpet_alarm_time.tm_min = min;
1080 hpet_alarm_time.tm_sec = sec;
1081
1082 return 1;
1083}
1bdbdaac 1084EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
e9e2cdb4
TG		 1085
1086int hpet_set_periodic_freq(unsigned long freq)
1087{
1088 uint64_t clc;
1089
1090 if (!is_hpet_enabled())
1091 return 0;
1092
1093 if (freq <= DEFAULT_RTC_INT_FREQ)
1094 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1095 else {
1096 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1097 do_div(clc, freq);
1098 clc >>= hpet_clockevent.shift;
1099 hpet_pie_delta = (unsigned long) clc;
1100 }
1101 return 1;
1102}
1bdbdaac 1103EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
e9e2cdb4
TG		 1104
1105int hpet_rtc_dropped_irq(void)
1106{
1107 return is_hpet_enabled();
1108}
1bdbdaac 1109EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
e9e2cdb4
TG		 1110
1111static void hpet_rtc_timer_reinit(void)
1112{
1113 unsigned long cfg, delta;
1114 int lost_ints = -1;
1115
1116 if (unlikely(!hpet_rtc_flags)) {
1117 cfg = hpet_readl(HPET_T1_CFG);
1118 cfg &= ~HPET_TN_ENABLE;
1119 hpet_writel(cfg, HPET_T1_CFG);
1120 return;
1121 }
1122
1123 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1124 delta = hpet_default_delta;
1125 else
1126 delta = hpet_pie_delta;
1127
1128 /*
1129 * Increment the comparator value until we are ahead of the
1130 * current count.
1131 */
1132 do {
1133 hpet_t1_cmp += delta;
1134 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1135 lost_ints++;
ff08f76d 1136 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
e9e2cdb4
TG		 1137
1138 if (lost_ints) {
1139 if (hpet_rtc_flags & RTC_PIE)
1140 hpet_pie_count += lost_ints;
1141 if (printk_ratelimit())
7e2a31da 1142 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
e9e2cdb4
TG		 1143 lost_ints);
1144 }
1145}
1146
1147irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1148{
1149 struct rtc_time curr_time;
1150 unsigned long rtc_int_flag = 0;
1151
1152 hpet_rtc_timer_reinit();
1bdbdaac 1153 memset(&curr_time, 0, sizeof(struct rtc_time));
e9e2cdb4
TG		 1154
1155 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1bdbdaac 1156 get_rtc_time(&curr_time);
e9e2cdb4
TG		 1157
1158 if (hpet_rtc_flags & RTC_UIE &&
1159 curr_time.tm_sec != hpet_prev_update_sec) {
7e2a31da
DB		 1160 if (hpet_prev_update_sec >= 0)
1161 rtc_int_flag = RTC_UF;
e9e2cdb4
TG		 1162 hpet_prev_update_sec = curr_time.tm_sec;
1163 }
1164
1165 if (hpet_rtc_flags & RTC_PIE &&
1166 ++hpet_pie_count >= hpet_pie_limit) {
1167 rtc_int_flag |= RTC_PF;
1168 hpet_pie_count = 0;
1169 }
1170
8ee291f8 1171 if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4
TG		 1172 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1173 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1174 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1175 rtc_int_flag |= RTC_AF;
1176
1177 if (rtc_int_flag) {
1178 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1bdbdaac
BW		 1179 if (irq_handler)
1180 irq_handler(rtc_int_flag, dev_id);
e9e2cdb4
TG		 1181 }
1182 return IRQ_HANDLED;
1183}
1bdbdaac 1184EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
e9e2cdb4 1185#endif
Linux 6.x block layer and io_uring tree(s)