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x86, amd, uncore: Fix CPU hotplug callback registration
[linux-2.6-block.git] / arch / x86 / kernel / hpet.c
CommitLineData
5d0cf410 1#include <linux/clocksource.h>
e9e2cdb4 2#include <linux/clockchips.h>
4588c1f0 3#include <linux/interrupt.h>
69c60c88 4#include <linux/export.h>
28769149 5#include <linux/delay.h>
5d0cf410 6#include <linux/errno.h>
334955ef 7#include <linux/i8253.h>
5a0e3ad6 8#include <linux/slab.h>
5d0cf410 9#include <linux/hpet.h>
10#include <linux/init.h>
58ac1e76 11#include <linux/cpu.h>
4588c1f0
IM		 12#include <linux/pm.h>
13#include <linux/io.h>
5d0cf410 14
28769149 15#include <asm/fixmap.h>
4588c1f0 16#include <asm/hpet.h>
16f871bc 17#include <asm/time.h>
5d0cf410 18
4588c1f0 19#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410 20
b10db7f0
PM		 21/* FSEC = 10^-15
22 NSEC = 10^-9 */
4588c1f0 23#define FSEC_PER_NSEC 1000000L
5d0cf410 24
26afe5f2 25#define HPET_DEV_USED_BIT 2
26#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
27#define HPET_DEV_VALID 0x8
28#define HPET_DEV_FSB_CAP 0x1000
29#define HPET_DEV_PERI_CAP 0x2000
30
f1c18071
TG		 31#define HPET_MIN_CYCLES 128
32#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
33
e9e2cdb4
TG		 34/*
35 * HPET address is set in acpi/boot.c, when an ACPI entry exists
36 */
4588c1f0 37unsigned long hpet_address;
c8bc6f3c 38u8 hpet_blockid; /* OS timer block num */
73472a46
PV		 39u8 hpet_msi_disable;
40
e951e4af 41#ifdef CONFIG_PCI_MSI
3b71e9e3 42static unsigned long hpet_num_timers;
e951e4af 43#endif
4588c1f0 44static void __iomem *hpet_virt_address;
e9e2cdb4 45
58ac1e76 46struct hpet_dev {
4588c1f0
IM		 47 struct clock_event_device evt;
48 unsigned int num;
49 int cpu;
50 unsigned int irq;
51 unsigned int flags;
52 char name[10];
58ac1e76 53};
54
3f7787b3
FW		 55inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
56{
57 return container_of(evtdev, struct hpet_dev, evt);
58}
59
5946fa3d 60inline unsigned int hpet_readl(unsigned int a)
e9e2cdb4
TG		 61{
62 return readl(hpet_virt_address + a);
63}
64
5946fa3d 65static inline void hpet_writel(unsigned int d, unsigned int a)
e9e2cdb4
TG		 66{
67 writel(d, hpet_virt_address + a);
68}
69
28769149 70#ifdef CONFIG_X86_64
28769149 71#include <asm/pgtable.h>
2387ce57 72#endif
28769149 73
06a24dec
TG		 74static inline void hpet_set_mapping(void)
75{
76 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
2387ce57 77#ifdef CONFIG_X86_64
d319bb79 78 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VVAR_NOCACHE);
2387ce57 79#endif
06a24dec
TG		 80}
81
82static inline void hpet_clear_mapping(void)
83{
84 iounmap(hpet_virt_address);
85 hpet_virt_address = NULL;
86}
87
e9e2cdb4
TG		 88/*
89 * HPET command line enable / disable
90 */
91static int boot_hpet_disable;
b17530bd 92int hpet_force_user;
b98103a5 93static int hpet_verbose;
e9e2cdb4 94
4588c1f0 95static int __init hpet_setup(char *str)
e9e2cdb4 96{
b2d6aba9
JB		 97 while (str) {
98 char *next = strchr(str, ',');
99
100 if (next)
101 *next++ = 0;
e9e2cdb4
TG		 102 if (!strncmp("disable", str, 7))
103 boot_hpet_disable = 1;
b17530bd
TG		 104 if (!strncmp("force", str, 5))
105 hpet_force_user = 1;
b98103a5
AH		 106 if (!strncmp("verbose", str, 7))
107 hpet_verbose = 1;
b2d6aba9 108 str = next;
e9e2cdb4
TG		 109 }
110 return 1;
111}
112__setup("hpet=", hpet_setup);
113
28769149
TG		 114static int __init disable_hpet(char *str)
115{
116 boot_hpet_disable = 1;
117 return 1;
118}
119__setup("nohpet", disable_hpet);
120
e9e2cdb4
TG		 121static inline int is_hpet_capable(void)
122{
4588c1f0 123 return !boot_hpet_disable && hpet_address;
e9e2cdb4
TG		 124}
125
126/*
127 * HPET timer interrupt enable / disable
128 */
129static int hpet_legacy_int_enabled;
130
131/**
132 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
133 */
134int is_hpet_enabled(void)
135{
136 return is_hpet_capable() && hpet_legacy_int_enabled;
137}
1bdbdaac 138EXPORT_SYMBOL_GPL(is_hpet_enabled);
e9e2cdb4 139
b98103a5
AH		 140static void _hpet_print_config(const char *function, int line)
141{
142 u32 i, timers, l, h;
143 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
144 l = hpet_readl(HPET_ID);
145 h = hpet_readl(HPET_PERIOD);
146 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
147 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
148 l = hpet_readl(HPET_CFG);
149 h = hpet_readl(HPET_STATUS);
150 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
151 l = hpet_readl(HPET_COUNTER);
152 h = hpet_readl(HPET_COUNTER+4);
153 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
154
155 for (i = 0; i < timers; i++) {
156 l = hpet_readl(HPET_Tn_CFG(i));
157 h = hpet_readl(HPET_Tn_CFG(i)+4);
158 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
159 i, l, h);
160 l = hpet_readl(HPET_Tn_CMP(i));
161 h = hpet_readl(HPET_Tn_CMP(i)+4);
162 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
163 i, l, h);
164 l = hpet_readl(HPET_Tn_ROUTE(i));
165 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
166 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
167 i, l, h);
168 }
169}
170
171#define hpet_print_config() \
172do { \
173 if (hpet_verbose) \
174 _hpet_print_config(__FUNCTION__, __LINE__); \
175} while (0)
176
e9e2cdb4
TG		 177/*
178 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
179 * timer 0 and timer 1 in case of RTC emulation.
180 */
181#ifdef CONFIG_HPET
f0ed4e69 182
5f79f2f2 183static void hpet_reserve_msi_timers(struct hpet_data *hd);
f0ed4e69 184
5946fa3d 185static void hpet_reserve_platform_timers(unsigned int id)
e9e2cdb4
TG		 186{
187 struct hpet __iomem *hpet = hpet_virt_address;
37a47db8
BR		 188 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
189 unsigned int nrtimers, i;
e9e2cdb4
TG		 190 struct hpet_data hd;
191
192 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
193
4588c1f0
IM		 194 memset(&hd, 0, sizeof(hd));
195 hd.hd_phys_address = hpet_address;
196 hd.hd_address = hpet;
197 hd.hd_nirqs = nrtimers;
e9e2cdb4
TG		 198 hpet_reserve_timer(&hd, 0);
199
200#ifdef CONFIG_HPET_EMULATE_RTC
201 hpet_reserve_timer(&hd, 1);
202#endif
5761d64b 203
64a76f66
DB		 204 /*
205 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
206 * is wrong for i8259!) not the output IRQ. Many BIOS writers
207 * don't bother configuring *any* comparator interrupts.
208 */
e9e2cdb4
TG		 209 hd.hd_irq[0] = HPET_LEGACY_8254;
210 hd.hd_irq[1] = HPET_LEGACY_RTC;
211
fc3fbc45 212 for (i = 2; i < nrtimers; timer++, i++) {
4588c1f0
IM		 213 hd.hd_irq[i] = (readl(&timer->hpet_config) &
214 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
fc3fbc45 215 }
5761d64b 216
f0ed4e69 217 hpet_reserve_msi_timers(&hd);
26afe5f2 218
e9e2cdb4 219 hpet_alloc(&hd);
5761d64b 220
e9e2cdb4
TG		 221}
222#else
5946fa3d 223static void hpet_reserve_platform_timers(unsigned int id) { }
e9e2cdb4
TG		 224#endif
225
226/*
227 * Common hpet info
228 */
ab0e08f1 229static unsigned long hpet_freq;
e9e2cdb4 230
610bf2f1 231static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 232 struct clock_event_device *evt);
610bf2f1 233static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4
TG		 234 struct clock_event_device *evt);
235
236/*
237 * The hpet clock event device
238 */
239static struct clock_event_device hpet_clockevent = {
240 .name = "hpet",
241 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
610bf2f1
VP		 242 .set_mode = hpet_legacy_set_mode,
243 .set_next_event = hpet_legacy_next_event,
e9e2cdb4 244 .irq = 0,
59c69f2a 245 .rating = 50,
e9e2cdb4
TG		 246};
247
8d6f0c82 248static void hpet_stop_counter(void)
e9e2cdb4
TG		 249{
250 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 251 cfg &= ~HPET_CFG_ENABLE;
252 hpet_writel(cfg, HPET_CFG);
7a6f9cbb
AH		 253}
254
255static void hpet_reset_counter(void)
256{
e9e2cdb4
TG		 257 hpet_writel(0, HPET_COUNTER);
258 hpet_writel(0, HPET_COUNTER + 4);
8d6f0c82
AH		 259}
260
261static void hpet_start_counter(void)
262{
5946fa3d 263 unsigned int cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 264 cfg |= HPET_CFG_ENABLE;
265 hpet_writel(cfg, HPET_CFG);
266}
267
8d6f0c82
AH		 268static void hpet_restart_counter(void)
269{
270 hpet_stop_counter();
7a6f9cbb 271 hpet_reset_counter();
8d6f0c82
AH		 272 hpet_start_counter();
273}
274
59c69f2a
VP		 275static void hpet_resume_device(void)
276{
bfe0c1cc 277 force_hpet_resume();
59c69f2a
VP		 278}
279
17622339 280static void hpet_resume_counter(struct clocksource *cs)
59c69f2a
VP		 281{
282 hpet_resume_device();
8d6f0c82 283 hpet_restart_counter();
59c69f2a
VP		 284}
285
610bf2f1 286static void hpet_enable_legacy_int(void)
e9e2cdb4 287{
5946fa3d 288 unsigned int cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 289
290 cfg |= HPET_CFG_LEGACY;
291 hpet_writel(cfg, HPET_CFG);
292 hpet_legacy_int_enabled = 1;
293}
294
610bf2f1
VP		 295static void hpet_legacy_clockevent_register(void)
296{
610bf2f1
VP		 297 /* Start HPET legacy interrupts */
298 hpet_enable_legacy_int();
299
610bf2f1
VP		 300 /*
301 * Start hpet with the boot cpu mask and make it
302 * global after the IO_APIC has been initialized.
303 */
320ab2b0 304 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
ab0e08f1
TG		 305 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
306 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
610bf2f1
VP		 307 global_clock_event = &hpet_clockevent;
308 printk(KERN_DEBUG "hpet clockevent registered\n");
309}
310
26afe5f2 311static int hpet_setup_msi_irq(unsigned int irq);
312
b40d575b 313static void hpet_set_mode(enum clock_event_mode mode,
314 struct clock_event_device *evt, int timer)
e9e2cdb4 315{
5946fa3d 316 unsigned int cfg, cmp, now;
e9e2cdb4
TG		 317 uint64_t delta;
318
4588c1f0 319 switch (mode) {
e9e2cdb4 320 case CLOCK_EVT_MODE_PERIODIC:
c23e253e 321 hpet_stop_counter();
b40d575b 322 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
323 delta >>= evt->shift;
7a6f9cbb 324 now = hpet_readl(HPET_COUNTER);
5946fa3d 325 cmp = now + (unsigned int) delta;
b40d575b 326 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 327 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
328 HPET_TN_SETVAL | HPET_TN_32BIT;
b40d575b 329 hpet_writel(cfg, HPET_Tn_CFG(timer));
7a6f9cbb
AH		 330 hpet_writel(cmp, HPET_Tn_CMP(timer));
331 udelay(1);
332 /*
333 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
334 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
335 * bit is automatically cleared after the first write.
336 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
337 * Publication # 24674)
338 */
5946fa3d 339 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
c23e253e 340 hpet_start_counter();
b98103a5 341 hpet_print_config();
e9e2cdb4
TG		 342 break;
343
344 case CLOCK_EVT_MODE_ONESHOT:
b40d575b 345 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 346 cfg &= ~HPET_TN_PERIODIC;
347 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
b40d575b 348 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4
TG		 349 break;
350
351 case CLOCK_EVT_MODE_UNUSED:
352 case CLOCK_EVT_MODE_SHUTDOWN:
b40d575b 353 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4 354 cfg &= ~HPET_TN_ENABLE;
b40d575b 355 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4 356 break;
18de5bc4
TG		 357
358 case CLOCK_EVT_MODE_RESUME:
26afe5f2 359 if (timer == 0) {
360 hpet_enable_legacy_int();
361 } else {
362 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
363 hpet_setup_msi_irq(hdev->irq);
364 disable_irq(hdev->irq);
0de26520 365 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
26afe5f2 366 enable_irq(hdev->irq);
367 }
b98103a5 368 hpet_print_config();
18de5bc4 369 break;
e9e2cdb4
TG		 370 }
371}
372
b40d575b 373static int hpet_next_event(unsigned long delta,
374 struct clock_event_device *evt, int timer)
e9e2cdb4 375{
f7676254 376 u32 cnt;
995bd3bb 377 s32 res;
e9e2cdb4
TG		 378
379 cnt = hpet_readl(HPET_COUNTER);
f7676254 380 cnt += (u32) delta;
b40d575b 381 hpet_writel(cnt, HPET_Tn_CMP(timer));
e9e2cdb4 382
72d43d9b 383 /*
995bd3bb
TG		 384 * HPETs are a complete disaster. The compare register is
385 * based on a equal comparison and neither provides a less
386 * than or equal functionality (which would require to take
387 * the wraparound into account) nor a simple count down event
388 * mode. Further the write to the comparator register is
389 * delayed internally up to two HPET clock cycles in certain
f1c18071
TG		 390 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
391 * longer delays. We worked around that by reading back the
392 * compare register, but that required another workaround for
393 * ICH9,10 chips where the first readout after write can
394 * return the old stale value. We already had a minimum
395 * programming delta of 5us enforced, but a NMI or SMI hitting
995bd3bb
TG		 396 * between the counter readout and the comparator write can
397 * move us behind that point easily. Now instead of reading
398 * the compare register back several times, we make the ETIME
399 * decision based on the following: Return ETIME if the
f1c18071 400 * counter value after the write is less than HPET_MIN_CYCLES
995bd3bb 401 * away from the event or if the counter is already ahead of
f1c18071
TG		 402 * the event. The minimum programming delta for the generic
403 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
72d43d9b 404 */
995bd3bb 405 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
72d43d9b 406
f1c18071 407 return res < HPET_MIN_CYCLES ? -ETIME : 0;
e9e2cdb4
TG		 408}
409
b40d575b 410static void hpet_legacy_set_mode(enum clock_event_mode mode,
411 struct clock_event_device *evt)
412{
413 hpet_set_mode(mode, evt, 0);
414}
415
416static int hpet_legacy_next_event(unsigned long delta,
417 struct clock_event_device *evt)
418{
419 return hpet_next_event(delta, evt, 0);
420}
421
58ac1e76 422/*
423 * HPET MSI Support
424 */
26afe5f2 425#ifdef CONFIG_PCI_MSI
5f79f2f2
VP		 426
427static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
428static struct hpet_dev *hpet_devs;
429
d0fbca8f 430void hpet_msi_unmask(struct irq_data *data)
58ac1e76 431{
d0fbca8f 432 struct hpet_dev *hdev = data->handler_data;
5946fa3d 433 unsigned int cfg;
58ac1e76 434
435 /* unmask it */
436 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
6acf5a8c 437 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
58ac1e76 438 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
439}
440
d0fbca8f 441void hpet_msi_mask(struct irq_data *data)
58ac1e76 442{
d0fbca8f 443 struct hpet_dev *hdev = data->handler_data;
5946fa3d 444 unsigned int cfg;
58ac1e76 445
446 /* mask it */
447 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
6acf5a8c 448 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
58ac1e76 449 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
450}
451
d0fbca8f 452void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
58ac1e76 453{
58ac1e76 454 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
455 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
456}
457
d0fbca8f 458void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
58ac1e76 459{
58ac1e76 460 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
461 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
462 msg->address_hi = 0;
463}
464
26afe5f2 465static void hpet_msi_set_mode(enum clock_event_mode mode,
466 struct clock_event_device *evt)
467{
468 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
469 hpet_set_mode(mode, evt, hdev->num);
470}
471
472static int hpet_msi_next_event(unsigned long delta,
473 struct clock_event_device *evt)
474{
475 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
476 return hpet_next_event(delta, evt, hdev->num);
477}
478
479static int hpet_setup_msi_irq(unsigned int irq)
480{
71054d88 481 if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
26afe5f2 482 destroy_irq(irq);
483 return -EINVAL;
484 }
485 return 0;
486}
487
488static int hpet_assign_irq(struct hpet_dev *dev)
489{
490 unsigned int irq;
491
02198962 492 irq = create_irq_nr(0, -1);
26afe5f2 493 if (!irq)
494 return -EINVAL;
495
2c778651 496 irq_set_handler_data(irq, dev);
26afe5f2 497
498 if (hpet_setup_msi_irq(irq))
499 return -EINVAL;
500
501 dev->irq = irq;
502 return 0;
503}
504
505static irqreturn_t hpet_interrupt_handler(int irq, void *data)
506{
507 struct hpet_dev *dev = (struct hpet_dev *)data;
508 struct clock_event_device *hevt = &dev->evt;
509
510 if (!hevt->event_handler) {
511 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
512 dev->num);
513 return IRQ_HANDLED;
514 }
515
516 hevt->event_handler(hevt);
517 return IRQ_HANDLED;
518}
519
520static int hpet_setup_irq(struct hpet_dev *dev)
521{
522
523 if (request_irq(dev->irq, hpet_interrupt_handler,
507fa3a3
TG		 524 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
525 dev->name, dev))
26afe5f2 526 return -1;
527
528 disable_irq(dev->irq);
0de26520 529 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
26afe5f2 530 enable_irq(dev->irq);
531
c81bba49
YL		 532 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
533 dev->name, dev->irq);
534
26afe5f2 535 return 0;
536}
537
538/* This should be called in specific @cpu */
539static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
540{
541 struct clock_event_device *evt = &hdev->evt;
26afe5f2 542
543 WARN_ON(cpu != smp_processor_id());
544 if (!(hdev->flags & HPET_DEV_VALID))
545 return;
546
547 if (hpet_setup_msi_irq(hdev->irq))
548 return;
549
550 hdev->cpu = cpu;
551 per_cpu(cpu_hpet_dev, cpu) = hdev;
552 evt->name = hdev->name;
553 hpet_setup_irq(hdev);
554 evt->irq = hdev->irq;
555
556 evt->rating = 110;
557 evt->features = CLOCK_EVT_FEAT_ONESHOT;
558 if (hdev->flags & HPET_DEV_PERI_CAP)
559 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
560
561 evt->set_mode = hpet_msi_set_mode;
562 evt->set_next_event = hpet_msi_next_event;
320ab2b0 563 evt->cpumask = cpumask_of(hdev->cpu);
ab0e08f1
TG		 564
565 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
566 0x7FFFFFFF);
26afe5f2 567}
568
569#ifdef CONFIG_HPET
570/* Reserve at least one timer for userspace (/dev/hpet) */
571#define RESERVE_TIMERS 1
572#else
573#define RESERVE_TIMERS 0
574#endif
5f79f2f2
VP		 575
576static void hpet_msi_capability_lookup(unsigned int start_timer)
26afe5f2 577{
578 unsigned int id;
579 unsigned int num_timers;
580 unsigned int num_timers_used = 0;
581 int i;
582
73472a46
PV		 583 if (hpet_msi_disable)
584 return;
585
39fe05e5
SL		 586 if (boot_cpu_has(X86_FEATURE_ARAT))
587 return;
26afe5f2 588 id = hpet_readl(HPET_ID);
589
590 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
591 num_timers++; /* Value read out starts from 0 */
b98103a5 592 hpet_print_config();
26afe5f2 593
594 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
595 if (!hpet_devs)
596 return;
597
598 hpet_num_timers = num_timers;
599
600 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
601 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
5946fa3d 602 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
26afe5f2 603
604 /* Only consider HPET timer with MSI support */
605 if (!(cfg & HPET_TN_FSB_CAP))
606 continue;
607
608 hdev->flags = 0;
609 if (cfg & HPET_TN_PERIODIC_CAP)
610 hdev->flags |= HPET_DEV_PERI_CAP;
611 hdev->num = i;
612
613 sprintf(hdev->name, "hpet%d", i);
614 if (hpet_assign_irq(hdev))
615 continue;
616
617 hdev->flags |= HPET_DEV_FSB_CAP;
618 hdev->flags |= HPET_DEV_VALID;
619 num_timers_used++;
620 if (num_timers_used == num_possible_cpus())
621 break;
622 }
623
624 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
625 num_timers, num_timers_used);
626}
627
5f79f2f2
VP		 628#ifdef CONFIG_HPET
629static void hpet_reserve_msi_timers(struct hpet_data *hd)
630{
631 int i;
632
633 if (!hpet_devs)
634 return;
635
636 for (i = 0; i < hpet_num_timers; i++) {
637 struct hpet_dev *hdev = &hpet_devs[i];
638
639 if (!(hdev->flags & HPET_DEV_VALID))
640 continue;
641
642 hd->hd_irq[hdev->num] = hdev->irq;
643 hpet_reserve_timer(hd, hdev->num);
644 }
645}
646#endif
647
26afe5f2 648static struct hpet_dev *hpet_get_unused_timer(void)
649{
650 int i;
651
652 if (!hpet_devs)
653 return NULL;
654
655 for (i = 0; i < hpet_num_timers; i++) {
656 struct hpet_dev *hdev = &hpet_devs[i];
657
658 if (!(hdev->flags & HPET_DEV_VALID))
659 continue;
660 if (test_and_set_bit(HPET_DEV_USED_BIT,
661 (unsigned long *)&hdev->flags))
662 continue;
663 return hdev;
664 }
665 return NULL;
666}
667
668struct hpet_work_struct {
669 struct delayed_work work;
670 struct completion complete;
671};
672
673static void hpet_work(struct work_struct *w)
674{
675 struct hpet_dev *hdev;
676 int cpu = smp_processor_id();
677 struct hpet_work_struct *hpet_work;
678
679 hpet_work = container_of(w, struct hpet_work_struct, work.work);
680
681 hdev = hpet_get_unused_timer();
682 if (hdev)
683 init_one_hpet_msi_clockevent(hdev, cpu);
684
685 complete(&hpet_work->complete);
686}
687
688static int hpet_cpuhp_notify(struct notifier_block *n,
689 unsigned long action, void *hcpu)
690{
691 unsigned long cpu = (unsigned long)hcpu;
692 struct hpet_work_struct work;
693 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
694
695 switch (action & 0xf) {
696 case CPU_ONLINE:
ca1cab37 697 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
26afe5f2 698 init_completion(&work.complete);
699 /* FIXME: add schedule_work_on() */
700 schedule_delayed_work_on(cpu, &work.work, 0);
701 wait_for_completion(&work.complete);
336f6c32 702 destroy_timer_on_stack(&work.work.timer);
26afe5f2 703 break;
704 case CPU_DEAD:
705 if (hdev) {
706 free_irq(hdev->irq, hdev);
707 hdev->flags &= ~HPET_DEV_USED;
708 per_cpu(cpu_hpet_dev, cpu) = NULL;
709 }
710 break;
711 }
712 return NOTIFY_OK;
713}
714#else
715
ba374c9b
SN		 716static int hpet_setup_msi_irq(unsigned int irq)
717{
718 return 0;
719}
5f79f2f2
VP		 720static void hpet_msi_capability_lookup(unsigned int start_timer)
721{
722 return;
723}
724
725#ifdef CONFIG_HPET
726static void hpet_reserve_msi_timers(struct hpet_data *hd)
26afe5f2 727{
728 return;
729}
5f79f2f2 730#endif
26afe5f2 731
732static int hpet_cpuhp_notify(struct notifier_block *n,
733 unsigned long action, void *hcpu)
734{
735 return NOTIFY_OK;
736}
737
738#endif
739
6bb74df4 740/*
741 * Clock source related code
742 */
8e19608e 743static cycle_t read_hpet(struct clocksource *cs)
6bb74df4 744{
745 return (cycle_t)hpet_readl(HPET_COUNTER);
746}
747
748static struct clocksource clocksource_hpet = {
749 .name = "hpet",
750 .rating = 250,
751 .read = read_hpet,
752 .mask = HPET_MASK,
6bb74df4 753 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
8d6f0c82 754 .resume = hpet_resume_counter,
28769149 755#ifdef CONFIG_X86_64
98d0ac38 756 .archdata = { .vclock_mode = VCLOCK_HPET },
28769149 757#endif
6bb74df4 758};
759
610bf2f1 760static int hpet_clocksource_register(void)
e9e2cdb4 761{
6fd592da 762 u64 start, now;
075bcd1f 763 cycle_t t1;
e9e2cdb4 764
e9e2cdb4 765 /* Start the counter */
8d6f0c82 766 hpet_restart_counter();
e9e2cdb4 767
075bcd1f 768 /* Verify whether hpet counter works */
8e19608e 769 t1 = hpet_readl(HPET_COUNTER);
075bcd1f
TG		 770 rdtscll(start);
771
772 /*
773 * We don't know the TSC frequency yet, but waiting for
774 * 200000 TSC cycles is safe:
775 * 4 GHz == 50us
776 * 1 GHz == 200us
777 */
778 do {
779 rep_nop();
780 rdtscll(now);
781 } while ((now - start) < 200000UL);
782
8e19608e 783 if (t1 == hpet_readl(HPET_COUNTER)) {
075bcd1f
TG		 784 printk(KERN_WARNING
785 "HPET counter not counting. HPET disabled\n");
610bf2f1 786 return -ENODEV;
075bcd1f
TG		 787 }
788
f12a15be 789 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
610bf2f1
VP		 790 return 0;
791}
792
396e2c6f
JB		 793static u32 *hpet_boot_cfg;
794
b02a7f22
PM		 795/**
796 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
610bf2f1
VP		 797 */
798int __init hpet_enable(void)
799{
396e2c6f 800 u32 hpet_period, cfg, id;
ab0e08f1 801 u64 freq;
396e2c6f 802 unsigned int i, last;
610bf2f1
VP		 803
804 if (!is_hpet_capable())
805 return 0;
806
807 hpet_set_mapping();
808
809 /*
810 * Read the period and check for a sane value:
811 */
812 hpet_period = hpet_readl(HPET_PERIOD);
a6825f1c
TG		 813
814 /*
815 * AMD SB700 based systems with spread spectrum enabled use a
816 * SMM based HPET emulation to provide proper frequency
817 * setting. The SMM code is initialized with the first HPET
818 * register access and takes some time to complete. During
819 * this time the config register reads 0xffffffff. We check
820 * for max. 1000 loops whether the config register reads a non
821 * 0xffffffff value to make sure that HPET is up and running
822 * before we go further. A counting loop is safe, as the HPET
823 * access takes thousands of CPU cycles. On non SB700 based
824 * machines this check is only done once and has no side
825 * effects.
826 */
827 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
828 if (i == 1000) {
829 printk(KERN_WARNING
830 "HPET config register value = 0xFFFFFFFF. "
831 "Disabling HPET\n");
832 goto out_nohpet;
833 }
834 }
835
610bf2f1
VP		 836 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
837 goto out_nohpet;
838
ab0e08f1
TG		 839 /*
840 * The period is a femto seconds value. Convert it to a
841 * frequency.
842 */
843 freq = FSEC_PER_SEC;
844 do_div(freq, hpet_period);
845 hpet_freq = freq;
846
610bf2f1
VP		 847 /*
848 * Read the HPET ID register to retrieve the IRQ routing
849 * information and the number of channels
850 */
851 id = hpet_readl(HPET_ID);
b98103a5 852 hpet_print_config();
610bf2f1 853
396e2c6f
JB		 854 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
855
610bf2f1
VP		 856#ifdef CONFIG_HPET_EMULATE_RTC
857 /*
858 * The legacy routing mode needs at least two channels, tick timer
859 * and the rtc emulation channel.
860 */
396e2c6f 861 if (!last)
610bf2f1
VP		 862 goto out_nohpet;
863#endif
864
396e2c6f
JB		 865 cfg = hpet_readl(HPET_CFG);
866 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
867 GFP_KERNEL);
868 if (hpet_boot_cfg)
869 *hpet_boot_cfg = cfg;
870 else
871 pr_warn("HPET initial state will not be saved\n");
872 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
1b38a3a1 873 hpet_writel(cfg, HPET_CFG);
396e2c6f
JB		 874 if (cfg)
875 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
876 cfg);
877
878 for (i = 0; i <= last; ++i) {
879 cfg = hpet_readl(HPET_Tn_CFG(i));
880 if (hpet_boot_cfg)
881 hpet_boot_cfg[i + 1] = cfg;
882 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
883 hpet_writel(cfg, HPET_Tn_CFG(i));
884 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
885 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
886 | HPET_TN_FSB | HPET_TN_FSB_CAP);
887 if (cfg)
888 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
889 cfg, i);
890 }
891 hpet_print_config();
892
610bf2f1
VP		 893 if (hpet_clocksource_register())
894 goto out_nohpet;
895
e9e2cdb4 896 if (id & HPET_ID_LEGSUP) {
610bf2f1 897 hpet_legacy_clockevent_register();
e9e2cdb4
TG		 898 return 1;
899 }
900 return 0;
5d0cf410 901
e9e2cdb4 902out_nohpet:
06a24dec 903 hpet_clear_mapping();
bacbe999 904 hpet_address = 0;
e9e2cdb4
TG		 905 return 0;
906}
907
28769149
TG		 908/*
909 * Needs to be late, as the reserve_timer code calls kalloc !
910 *
911 * Not a problem on i386 as hpet_enable is called from late_time_init,
912 * but on x86_64 it is necessary !
913 */
914static __init int hpet_late_init(void)
915{
26afe5f2 916 int cpu;
917
59c69f2a 918 if (boot_hpet_disable)
28769149
TG		 919 return -ENODEV;
920
59c69f2a
VP		 921 if (!hpet_address) {
922 if (!force_hpet_address)
923 return -ENODEV;
924
925 hpet_address = force_hpet_address;
926 hpet_enable();
59c69f2a
VP		 927 }
928
39c04b55
JF		 929 if (!hpet_virt_address)
930 return -ENODEV;
931
39fe05e5
SL		 932 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
933 hpet_msi_capability_lookup(2);
934 else
935 hpet_msi_capability_lookup(0);
936
28769149 937 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
b98103a5 938 hpet_print_config();
59c69f2a 939
73472a46
PV		 940 if (hpet_msi_disable)
941 return 0;
942
39fe05e5
SL		 943 if (boot_cpu_has(X86_FEATURE_ARAT))
944 return 0;
945
26afe5f2 946 for_each_online_cpu(cpu) {
947 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
948 }
949
950 /* This notifier should be called after workqueue is ready */
951 hotcpu_notifier(hpet_cpuhp_notify, -20);
952
28769149
TG		 953 return 0;
954}
955fs_initcall(hpet_late_init);
956
c86c7fbc
OH		 957void hpet_disable(void)
958{
ff487808 959 if (is_hpet_capable() && hpet_virt_address) {
396e2c6f 960 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
c86c7fbc 961
396e2c6f
JB		 962 if (hpet_boot_cfg)
963 cfg = *hpet_boot_cfg;
964 else if (hpet_legacy_int_enabled) {
c86c7fbc
OH		 965 cfg &= ~HPET_CFG_LEGACY;
966 hpet_legacy_int_enabled = 0;
967 }
968 cfg &= ~HPET_CFG_ENABLE;
969 hpet_writel(cfg, HPET_CFG);
396e2c6f
JB		 970
971 if (!hpet_boot_cfg)
972 return;
973
974 id = hpet_readl(HPET_ID);
975 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
976
977 for (id = 0; id <= last; ++id)
978 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
979
980 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
981 hpet_writel(*hpet_boot_cfg, HPET_CFG);
c86c7fbc
OH		 982 }
983}
984
e9e2cdb4
TG		 985#ifdef CONFIG_HPET_EMULATE_RTC
986
987/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
988 * is enabled, we support RTC interrupt functionality in software.
989 * RTC has 3 kinds of interrupts:
990 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
991 * is updated
992 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
993 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
994 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
995 * (1) and (2) above are implemented using polling at a frequency of
996 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
997 * overhead. (DEFAULT_RTC_INT_FREQ)
998 * For (3), we use interrupts at 64Hz or user specified periodic
999 * frequency, whichever is higher.
1000 */
1001#include <linux/mc146818rtc.h>
1002#include <linux/rtc.h>
1bdbdaac 1003#include <asm/rtc.h>
e9e2cdb4
TG		 1004
1005#define DEFAULT_RTC_INT_FREQ 64
1006#define DEFAULT_RTC_SHIFT 6
1007#define RTC_NUM_INTS 1
1008
1009static unsigned long hpet_rtc_flags;
7e2a31da 1010static int hpet_prev_update_sec;
e9e2cdb4
TG		 1011static struct rtc_time hpet_alarm_time;
1012static unsigned long hpet_pie_count;
ff08f76d 1013static u32 hpet_t1_cmp;
5946fa3d
JB		 1014static u32 hpet_default_delta;
1015static u32 hpet_pie_delta;
e9e2cdb4
TG		 1016static unsigned long hpet_pie_limit;
1017
1bdbdaac
BW		 1018static rtc_irq_handler irq_handler;
1019
ff08f76d
PE		 1020/*
1021 * Check that the hpet counter c1 is ahead of the c2
1022 */
1023static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1024{
1025 return (s32)(c2 - c1) < 0;
1026}
1027
1bdbdaac
BW		 1028/*
1029 * Registers a IRQ handler.
1030 */
1031int hpet_register_irq_handler(rtc_irq_handler handler)
1032{
1033 if (!is_hpet_enabled())
1034 return -ENODEV;
1035 if (irq_handler)
1036 return -EBUSY;
1037
1038 irq_handler = handler;
1039
1040 return 0;
1041}
1042EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1043
1044/*
1045 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1046 * and does cleanup.
1047 */
1048void hpet_unregister_irq_handler(rtc_irq_handler handler)
1049{
1050 if (!is_hpet_enabled())
1051 return;
1052
1053 irq_handler = NULL;
1054 hpet_rtc_flags = 0;
1055}
1056EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1057
e9e2cdb4
TG		 1058/*
1059 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1060 * is not supported by all HPET implementations for timer 1.
1061 *
1062 * hpet_rtc_timer_init() is called when the rtc is initialized.
1063 */
1064int hpet_rtc_timer_init(void)
1065{
5946fa3d
JB		 1066 unsigned int cfg, cnt, delta;
1067 unsigned long flags;
e9e2cdb4
TG		 1068
1069 if (!is_hpet_enabled())
1070 return 0;
1071
1072 if (!hpet_default_delta) {
1073 uint64_t clc;
1074
1075 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1076 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
5946fa3d 1077 hpet_default_delta = clc;
e9e2cdb4
TG		 1078 }
1079
1080 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1081 delta = hpet_default_delta;
1082 else
1083 delta = hpet_pie_delta;
1084
1085 local_irq_save(flags);
1086
1087 cnt = delta + hpet_readl(HPET_COUNTER);
1088 hpet_writel(cnt, HPET_T1_CMP);
1089 hpet_t1_cmp = cnt;
1090
1091 cfg = hpet_readl(HPET_T1_CFG);
1092 cfg &= ~HPET_TN_PERIODIC;
1093 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1094 hpet_writel(cfg, HPET_T1_CFG);
1095
1096 local_irq_restore(flags);
1097
1098 return 1;
1099}
1bdbdaac 1100EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
e9e2cdb4 1101
2ded6e6a
ML		 1102static void hpet_disable_rtc_channel(void)
1103{
1104 unsigned long cfg;
1105 cfg = hpet_readl(HPET_T1_CFG);
1106 cfg &= ~HPET_TN_ENABLE;
1107 hpet_writel(cfg, HPET_T1_CFG);
1108}
1109
e9e2cdb4
TG		 1110/*
1111 * The functions below are called from rtc driver.
1112 * Return 0 if HPET is not being used.
1113 * Otherwise do the necessary changes and return 1.
1114 */
1115int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1116{
1117 if (!is_hpet_enabled())
1118 return 0;
1119
1120 hpet_rtc_flags &= ~bit_mask;
2ded6e6a
ML		 1121 if (unlikely(!hpet_rtc_flags))
1122 hpet_disable_rtc_channel();
1123
e9e2cdb4
TG		 1124 return 1;
1125}
1bdbdaac 1126EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
e9e2cdb4
TG		 1127
1128int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1129{
1130 unsigned long oldbits = hpet_rtc_flags;
1131
1132 if (!is_hpet_enabled())
1133 return 0;
1134
1135 hpet_rtc_flags |= bit_mask;
1136
7e2a31da
DB		 1137 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1138 hpet_prev_update_sec = -1;
1139
e9e2cdb4
TG		 1140 if (!oldbits)
1141 hpet_rtc_timer_init();
1142
1143 return 1;
1144}
1bdbdaac 1145EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
e9e2cdb4
TG		 1146
1147int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1148 unsigned char sec)
1149{
1150 if (!is_hpet_enabled())
1151 return 0;
1152
1153 hpet_alarm_time.tm_hour = hrs;
1154 hpet_alarm_time.tm_min = min;
1155 hpet_alarm_time.tm_sec = sec;
1156
1157 return 1;
1158}
1bdbdaac 1159EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
e9e2cdb4
TG		 1160
1161int hpet_set_periodic_freq(unsigned long freq)
1162{
1163 uint64_t clc;
1164
1165 if (!is_hpet_enabled())
1166 return 0;
1167
1168 if (freq <= DEFAULT_RTC_INT_FREQ)
1169 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1170 else {
1171 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1172 do_div(clc, freq);
1173 clc >>= hpet_clockevent.shift;
5946fa3d 1174 hpet_pie_delta = clc;
b4a5e8a1 1175 hpet_pie_limit = 0;
e9e2cdb4
TG		 1176 }
1177 return 1;
1178}
1bdbdaac 1179EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
e9e2cdb4
TG		 1180
1181int hpet_rtc_dropped_irq(void)
1182{
1183 return is_hpet_enabled();
1184}
1bdbdaac 1185EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
e9e2cdb4
TG		 1186
1187static void hpet_rtc_timer_reinit(void)
1188{
2ded6e6a 1189 unsigned int delta;
e9e2cdb4
TG		 1190 int lost_ints = -1;
1191
2ded6e6a
ML		 1192 if (unlikely(!hpet_rtc_flags))
1193 hpet_disable_rtc_channel();
e9e2cdb4
TG		 1194
1195 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1196 delta = hpet_default_delta;
1197 else
1198 delta = hpet_pie_delta;
1199
1200 /*
1201 * Increment the comparator value until we are ahead of the
1202 * current count.
1203 */
1204 do {
1205 hpet_t1_cmp += delta;
1206 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1207 lost_ints++;
ff08f76d 1208 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
e9e2cdb4
TG		 1209
1210 if (lost_ints) {
1211 if (hpet_rtc_flags & RTC_PIE)
1212 hpet_pie_count += lost_ints;
1213 if (printk_ratelimit())
7e2a31da 1214 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
e9e2cdb4
TG		 1215 lost_ints);
1216 }
1217}
1218
1219irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1220{
1221 struct rtc_time curr_time;
1222 unsigned long rtc_int_flag = 0;
1223
1224 hpet_rtc_timer_reinit();
1bdbdaac 1225 memset(&curr_time, 0, sizeof(struct rtc_time));
e9e2cdb4
TG		 1226
1227 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1bdbdaac 1228 get_rtc_time(&curr_time);
e9e2cdb4
TG		 1229
1230 if (hpet_rtc_flags & RTC_UIE &&
1231 curr_time.tm_sec != hpet_prev_update_sec) {
7e2a31da
DB		 1232 if (hpet_prev_update_sec >= 0)
1233 rtc_int_flag = RTC_UF;
e9e2cdb4
TG		 1234 hpet_prev_update_sec = curr_time.tm_sec;
1235 }
1236
1237 if (hpet_rtc_flags & RTC_PIE &&
1238 ++hpet_pie_count >= hpet_pie_limit) {
1239 rtc_int_flag |= RTC_PF;
1240 hpet_pie_count = 0;
1241 }
1242
8ee291f8 1243 if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4
TG		 1244 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1245 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1246 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1247 rtc_int_flag |= RTC_AF;
1248
1249 if (rtc_int_flag) {
1250 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1bdbdaac
BW		 1251 if (irq_handler)
1252 irq_handler(rtc_int_flag, dev_id);
e9e2cdb4
TG		 1253 }
1254 return IRQ_HANDLED;
1255}
1bdbdaac 1256EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
e9e2cdb4 1257#endif
Linux 6.x block layer and io_uring tree(s)