[linux-2.6-block.git] / arch / x86 / kernel / hpet.c

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/hpet.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/pm.h>

#include <asm/fixmap.h>
#include <asm/hpet.h>
#include <asm/i8253.h>
#include <asm/io.h>

#define HPET_MASK	CLOCKSOURCE_MASK(32)
#define HPET_SHIFT	22

/* FSEC = 10^-15
   NSEC = 10^-9 */
#define FSEC_PER_NSEC	1000000

/*
 * HPET address is set in acpi/boot.c, when an ACPI entry exists
 */
unsigned long hpet_address;
static void __iomem *hpet_virt_address;

unsigned long hpet_readl(unsigned long a)
{
	return readl(hpet_virt_address + a);
}

static inline void hpet_writel(unsigned long d, unsigned long a)
{
	writel(d, hpet_virt_address + a);
}

#ifdef CONFIG_X86_64

#include <asm/pgtable.h>

static inline void hpet_set_mapping(void)
{
	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
}

static inline void hpet_clear_mapping(void)
{
	hpet_virt_address = NULL;
}

#else

static inline void hpet_set_mapping(void)
{
	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
}

static inline void hpet_clear_mapping(void)
{
	iounmap(hpet_virt_address);
	hpet_virt_address = NULL;
}
#endif

/*
 * HPET command line enable / disable
 */
static int boot_hpet_disable;
int hpet_force_user;

static int __init hpet_setup(char* str)
{
	if (str) {
		if (!strncmp("disable", str, 7))
			boot_hpet_disable = 1;
		if (!strncmp("force", str, 5))
			hpet_force_user = 1;
	}
	return 1;
}
__setup("hpet=", hpet_setup);

static int __init disable_hpet(char *str)
{
	boot_hpet_disable = 1;
	return 1;
}
__setup("nohpet", disable_hpet);

static inline int is_hpet_capable(void)
{
	return (!boot_hpet_disable && hpet_address);
}

/*
 * HPET timer interrupt enable / disable
 */
static int hpet_legacy_int_enabled;

/**
 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 */
int is_hpet_enabled(void)
{
	return is_hpet_capable() && hpet_legacy_int_enabled;
}

/*
 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 * timer 0 and timer 1 in case of RTC emulation.
 */
#ifdef CONFIG_HPET
static void hpet_reserve_platform_timers(unsigned long id)
{
	struct hpet __iomem *hpet = hpet_virt_address;
	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	unsigned int nrtimers, i;
	struct hpet_data hd;

	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;

	memset(&hd, 0, sizeof (hd));
	hd.hd_phys_address = hpet_address;
	hd.hd_address = hpet;
	hd.hd_nirqs = nrtimers;
	hd.hd_flags = HPET_DATA_PLATFORM;
	hpet_reserve_timer(&hd, 0);

#ifdef CONFIG_HPET_EMULATE_RTC
	hpet_reserve_timer(&hd, 1);
#endif
	hd.hd_irq[0] = HPET_LEGACY_8254;
	hd.hd_irq[1] = HPET_LEGACY_RTC;

       for (i = 2; i < nrtimers; timer++, i++)
	       hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
		       Tn_INT_ROUTE_CNF_SHIFT;
	hpet_alloc(&hd);
}
#else
static void hpet_reserve_platform_timers(unsigned long id) { }
#endif

/*
 * Common hpet info
 */
static unsigned long hpet_period;

static void hpet_legacy_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt);
static int hpet_legacy_next_event(unsigned long delta,
			   struct clock_event_device *evt);

/*
 * The hpet clock event device
 */
static struct clock_event_device hpet_clockevent = {
	.name		= "hpet",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= hpet_legacy_set_mode,
	.set_next_event = hpet_legacy_next_event,
	.shift		= 32,
	.irq		= 0,
	.rating		= 50,
};

static void hpet_start_counter(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg &= ~HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
	hpet_writel(0, HPET_COUNTER);
	hpet_writel(0, HPET_COUNTER + 4);
	cfg |= HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
}

static void hpet_resume_device(void)
{
	force_hpet_resume();
}

static void hpet_restart_counter(void)
{
	hpet_resume_device();
	hpet_start_counter();
}

static void hpet_enable_legacy_int(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg |= HPET_CFG_LEGACY;
	hpet_writel(cfg, HPET_CFG);
	hpet_legacy_int_enabled = 1;
}

static void hpet_legacy_clockevent_register(void)
{
	uint64_t hpet_freq;

	/* Start HPET legacy interrupts */
	hpet_enable_legacy_int();

	/*
	 * The period is a femto seconds value. We need to calculate the
	 * scaled math multiplication factor for nanosecond to hpet tick
	 * conversion.
	 */
	hpet_freq = 1000000000000000ULL;
	do_div(hpet_freq, hpet_period);
	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
				      NSEC_PER_SEC, 32);
	/* Calculate the min / max delta */
	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
							   &hpet_clockevent);
	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
							   &hpet_clockevent);

	/*
	 * Start hpet with the boot cpu mask and make it
	 * global after the IO_APIC has been initialized.
	 */
	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
	clockevents_register_device(&hpet_clockevent);
	global_clock_event = &hpet_clockevent;
	printk(KERN_DEBUG "hpet clockevent registered\n");
}

static void hpet_legacy_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	unsigned long cfg, cmp, now;
	uint64_t delta;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
		delta >>= hpet_clockevent.shift;
		now = hpet_readl(HPET_COUNTER);
		cmp = now + (unsigned long) delta;
		cfg = hpet_readl(HPET_T0_CFG);
		cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
		       HPET_TN_SETVAL | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		/*
		 * The first write after writing TN_SETVAL to the
		 * config register sets the counter value, the second
		 * write sets the period.
		 */
		hpet_writel(cmp, HPET_T0_CMP);
		udelay(1);
		hpet_writel((unsigned long) delta, HPET_T0_CMP);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_PERIODIC;
		cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_RESUME:
		hpet_enable_legacy_int();
		break;
	}
}

static int hpet_legacy_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	unsigned long cnt;

	cnt = hpet_readl(HPET_COUNTER);
	cnt += delta;
	hpet_writel(cnt, HPET_T0_CMP);

	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
}

/*
 * Clock source related code
 */
static cycle_t read_hpet(void)
{
	return (cycle_t)hpet_readl(HPET_COUNTER);
}

#ifdef CONFIG_X86_64
static cycle_t __vsyscall_fn vread_hpet(void)
{
	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
}
#endif

static struct clocksource clocksource_hpet = {
	.name		= "hpet",
	.rating		= 250,
	.read		= read_hpet,
	.mask		= HPET_MASK,
	.shift		= HPET_SHIFT,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= hpet_restart_counter,
#ifdef CONFIG_X86_64
	.vread		= vread_hpet,
#endif
};

static int hpet_clocksource_register(void)
{
	u64 tmp, start, now;
	cycle_t t1;

	/* Start the counter */
	hpet_start_counter();

	/* Verify whether hpet counter works */
	t1 = read_hpet();
	rdtscll(start);

	/*
	 * We don't know the TSC frequency yet, but waiting for
	 * 200000 TSC cycles is safe:
	 * 4 GHz == 50us
	 * 1 GHz == 200us
	 */
	do {
		rep_nop();
		rdtscll(now);
	} while ((now - start) < 200000UL);

	if (t1 == read_hpet()) {
		printk(KERN_WARNING
		       "HPET counter not counting. HPET disabled\n");
		return -ENODEV;
	}

	/* Initialize and register HPET clocksource
	 *
	 * hpet period is in femto seconds per cycle
	 * so we need to convert this to ns/cyc units
	 * approximated by mult/2^shift
	 *
	 *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	 *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	 *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	 *  (fsec/cyc << shift)/1000000 = mult
	 *  (hpet_period << shift)/FSEC_PER_NSEC = mult
	 */
	tmp = (u64)hpet_period << HPET_SHIFT;
	do_div(tmp, FSEC_PER_NSEC);
	clocksource_hpet.mult = (u32)tmp;

	clocksource_register(&clocksource_hpet);

	return 0;
}

/*
 * Try to setup the HPET timer
 */
int __init hpet_enable(void)
{
	unsigned long id;

	if (!is_hpet_capable())
		return 0;

	hpet_set_mapping();

	/*
	 * Read the period and check for a sane value:
	 */
	hpet_period = hpet_readl(HPET_PERIOD);
	if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
		goto out_nohpet;

	/*
	 * Read the HPET ID register to retrieve the IRQ routing
	 * information and the number of channels
	 */
	id = hpet_readl(HPET_ID);

#ifdef CONFIG_HPET_EMULATE_RTC
	/*
	 * The legacy routing mode needs at least two channels, tick timer
	 * and the rtc emulation channel.
	 */
	if (!(id & HPET_ID_NUMBER))
		goto out_nohpet;
#endif

	if (hpet_clocksource_register())
		goto out_nohpet;

	if (id & HPET_ID_LEGSUP) {
		hpet_legacy_clockevent_register();
		return 1;
	}
	return 0;

out_nohpet:
	hpet_clear_mapping();
	boot_hpet_disable = 1;
	return 0;
}

/*
 * Needs to be late, as the reserve_timer code calls kalloc !
 *
 * Not a problem on i386 as hpet_enable is called from late_time_init,
 * but on x86_64 it is necessary !
 */
static __init int hpet_late_init(void)
{
	if (boot_hpet_disable)
		return -ENODEV;

	if (!hpet_address) {
		if (!force_hpet_address)
			return -ENODEV;

		hpet_address = force_hpet_address;
		hpet_enable();
		if (!hpet_virt_address)
			return -ENODEV;
	}

	hpet_reserve_platform_timers(hpet_readl(HPET_ID));

	return 0;
}
fs_initcall(hpet_late_init);

void hpet_disable(void)
{
	if (is_hpet_capable()) {
		unsigned long cfg = hpet_readl(HPET_CFG);

		if (hpet_legacy_int_enabled) {
			cfg &= ~HPET_CFG_LEGACY;
			hpet_legacy_int_enabled = 0;
		}
		cfg &= ~HPET_CFG_ENABLE;
		hpet_writel(cfg, HPET_CFG);
	}
}

#ifdef CONFIG_HPET_EMULATE_RTC

/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 * is enabled, we support RTC interrupt functionality in software.
 * RTC has 3 kinds of interrupts:
 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 *    is updated
 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 * (1) and (2) above are implemented using polling at a frequency of
 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 * overhead. (DEFAULT_RTC_INT_FREQ)
 * For (3), we use interrupts at 64Hz or user specified periodic
 * frequency, whichever is higher.
 */
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>

#define DEFAULT_RTC_INT_FREQ	64
#define DEFAULT_RTC_SHIFT	6
#define RTC_NUM_INTS		1

static unsigned long hpet_rtc_flags;
static unsigned long hpet_prev_update_sec;
static struct rtc_time hpet_alarm_time;
static unsigned long hpet_pie_count;
static unsigned long hpet_t1_cmp;
static unsigned long hpet_default_delta;
static unsigned long hpet_pie_delta;
static unsigned long hpet_pie_limit;

/*
 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 * is not supported by all HPET implementations for timer 1.
 *
 * hpet_rtc_timer_init() is called when the rtc is initialized.
 */
int hpet_rtc_timer_init(void)
{
	unsigned long cfg, cnt, delta, flags;

	if (!is_hpet_enabled())
		return 0;

	if (!hpet_default_delta) {
		uint64_t clc;

		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
		hpet_default_delta = (unsigned long) clc;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	local_irq_save(flags);

	cnt = delta + hpet_readl(HPET_COUNTER);
	hpet_writel(cnt, HPET_T1_CMP);
	hpet_t1_cmp = cnt;

	cfg = hpet_readl(HPET_T1_CFG);
	cfg &= ~HPET_TN_PERIODIC;
	cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
	hpet_writel(cfg, HPET_T1_CFG);

	local_irq_restore(flags);

	return 1;
}

/*
 * The functions below are called from rtc driver.
 * Return 0 if HPET is not being used.
 * Otherwise do the necessary changes and return 1.
 */
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags &= ~bit_mask;
	return 1;
}

int hpet_set_rtc_irq_bit(unsigned long bit_mask)
{
	unsigned long oldbits = hpet_rtc_flags;

	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags |= bit_mask;

	if (!oldbits)
		hpet_rtc_timer_init();

	return 1;
}

int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
			unsigned char sec)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_alarm_time.tm_hour = hrs;
	hpet_alarm_time.tm_min = min;
	hpet_alarm_time.tm_sec = sec;

	return 1;
}

int hpet_set_periodic_freq(unsigned long freq)
{
	uint64_t clc;

	if (!is_hpet_enabled())
		return 0;

	if (freq <= DEFAULT_RTC_INT_FREQ)
		hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
	else {
		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		do_div(clc, freq);
		clc >>= hpet_clockevent.shift;
		hpet_pie_delta = (unsigned long) clc;
	}
	return 1;
}

int hpet_rtc_dropped_irq(void)
{
	return is_hpet_enabled();
}

static void hpet_rtc_timer_reinit(void)
{
	unsigned long cfg, delta;
	int lost_ints = -1;

	if (unlikely(!hpet_rtc_flags)) {
		cfg = hpet_readl(HPET_T1_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T1_CFG);
		return;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	/*
	 * Increment the comparator value until we are ahead of the
	 * current count.
	 */
	do {
		hpet_t1_cmp += delta;
		hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
		lost_ints++;
	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);

	if (lost_ints) {
		if (hpet_rtc_flags & RTC_PIE)
			hpet_pie_count += lost_ints;
		if (printk_ratelimit())
			printk(KERN_WARNING "rtc: lost %d interrupts\n",
				lost_ints);
	}
}

irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
{
	struct rtc_time curr_time;
	unsigned long rtc_int_flag = 0;

	hpet_rtc_timer_reinit();

	if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
		rtc_get_rtc_time(&curr_time);

	if (hpet_rtc_flags & RTC_UIE &&
	    curr_time.tm_sec != hpet_prev_update_sec) {
		rtc_int_flag = RTC_UF;
		hpet_prev_update_sec = curr_time.tm_sec;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    ++hpet_pie_count >= hpet_pie_limit) {
		rtc_int_flag |= RTC_PF;
		hpet_pie_count = 0;
	}

	if (hpet_rtc_flags & RTC_AIE &&
	    (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	    (curr_time.tm_min == hpet_alarm_time.tm_min) &&
	    (curr_time.tm_hour == hpet_alarm_time.tm_hour))
			rtc_int_flag |= RTC_AF;

	if (rtc_int_flag) {
		rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
		rtc_interrupt(rtc_int_flag, dev_id);
	}
	return IRQ_HANDLED;
}
#endif
Commit	Line	Data
5d0cf410	1	#include <linux/clocksource.h>
e9e2cdb4	2	#include <linux/clockchips.h>
28769149	3	#include <linux/delay.h>
5d0cf410	4	#include <linux/errno.h>
	5	#include <linux/hpet.h>
	6	#include <linux/init.h>
399afa4f ML	7	#include <linux/sysdev.h>
399afa4f ML	8	#include <linux/pm.h>
5d0cf410	9
28769149	10	#include <asm/fixmap.h>
5d0cf410	11	#include <asm/hpet.h>
06a24dec	12	#include <asm/i8253.h>
5d0cf410	13	#include <asm/io.h>
5d0cf410	14
7f9f303a	15	#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410	16	#define HPET_SHIFT 22
5d0cf410	17
b10db7f0 PM	18	/* FSEC = 10^-15
b10db7f0 PM	19	NSEC = 10^-9 */
5d0cf410	20	#define FSEC_PER_NSEC 1000000
5d0cf410	21
e9e2cdb4 TG	22	/*
	23	* HPET address is set in acpi/boot.c, when an ACPI entry exists
	24	*/
	25	unsigned long hpet_address;
06a24dec	26	static void __iomem *hpet_virt_address;
e9e2cdb4	27
31c435d7	28	unsigned long hpet_readl(unsigned long a)
e9e2cdb4 TG	29	{
	30	return readl(hpet_virt_address + a);
	31	}
	32
	33	static inline void hpet_writel(unsigned long d, unsigned long a)
	34	{
	35	writel(d, hpet_virt_address + a);
	36	}
	37
28769149 TG	38	#ifdef CONFIG_X86_64
	39
	40	#include <asm/pgtable.h>
	41
	42	static inline void hpet_set_mapping(void)
	43	{
	44	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	45	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	46	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
	47	}
	48
	49	static inline void hpet_clear_mapping(void)
	50	{
	51	hpet_virt_address = NULL;
	52	}
	53
	54	#else
	55
06a24dec TG	56	static inline void hpet_set_mapping(void)
	57	{
	58	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
	59	}
	60
	61	static inline void hpet_clear_mapping(void)
	62	{
	63	iounmap(hpet_virt_address);
	64	hpet_virt_address = NULL;
	65	}
28769149	66	#endif
06a24dec	67
e9e2cdb4 TG	68	/*
	69	* HPET command line enable / disable
	70	*/
	71	static int boot_hpet_disable;
b17530bd	72	int hpet_force_user;
e9e2cdb4 TG	73
	74	static int __init hpet_setup(char* str)
	75	{
	76	if (str) {
	77	if (!strncmp("disable", str, 7))
	78	boot_hpet_disable = 1;
b17530bd TG	79	if (!strncmp("force", str, 5))
b17530bd TG	80	hpet_force_user = 1;
e9e2cdb4 TG	81	}
	82	return 1;
	83	}
	84	__setup("hpet=", hpet_setup);
	85
28769149 TG	86	static int __init disable_hpet(char *str)
	87	{
	88	boot_hpet_disable = 1;
	89	return 1;
	90	}
	91	__setup("nohpet", disable_hpet);
	92
e9e2cdb4 TG	93	static inline int is_hpet_capable(void)
	94	{
	95	return (!boot_hpet_disable && hpet_address);
	96	}
	97
	98	/*
	99	* HPET timer interrupt enable / disable
	100	*/
	101	static int hpet_legacy_int_enabled;
	102
	103	/**
	104	* is_hpet_enabled - check whether the hpet timer interrupt is enabled
	105	*/
	106	int is_hpet_enabled(void)
	107	{
	108	return is_hpet_capable() && hpet_legacy_int_enabled;
	109	}
	110
	111	/*
	112	* When the hpet driver (/dev/hpet) is enabled, we need to reserve
	113	* timer 0 and timer 1 in case of RTC emulation.
	114	*/
	115	#ifdef CONFIG_HPET
	116	static void hpet_reserve_platform_timers(unsigned long id)
	117	{
	118	struct hpet __iomem *hpet = hpet_virt_address;
37a47db8 BR	119	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
37a47db8 BR	120	unsigned int nrtimers, i;
e9e2cdb4 TG	121	struct hpet_data hd;
	122
	123	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
	124
	125	memset(&hd, 0, sizeof (hd));
	126	hd.hd_phys_address = hpet_address;
06a24dec	127	hd.hd_address = hpet;
e9e2cdb4 TG	128	hd.hd_nirqs = nrtimers;
	129	hd.hd_flags = HPET_DATA_PLATFORM;
	130	hpet_reserve_timer(&hd, 0);
	131
	132	#ifdef CONFIG_HPET_EMULATE_RTC
	133	hpet_reserve_timer(&hd, 1);
	134	#endif
e9e2cdb4 TG	135	hd.hd_irq[0] = HPET_LEGACY_8254;
	136	hd.hd_irq[1] = HPET_LEGACY_RTC;
	137
37a47db8 BR	138	for (i = 2; i < nrtimers; timer++, i++)
	139	hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
	140	Tn_INT_ROUTE_CNF_SHIFT;
e9e2cdb4	141	hpet_alloc(&hd);
e9e2cdb4 TG	142	}
	143	#else
	144	static void hpet_reserve_platform_timers(unsigned long id) { }
	145	#endif
	146
	147	/*
	148	* Common hpet info
	149	*/
	150	static unsigned long hpet_period;
	151
610bf2f1	152	static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4	153	struct clock_event_device *evt);
610bf2f1	154	static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4 TG	155	struct clock_event_device *evt);
	156
	157	/*
	158	* The hpet clock event device
	159	*/
	160	static struct clock_event_device hpet_clockevent = {
	161	.name = "hpet",
	162	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
610bf2f1 VP	163	.set_mode = hpet_legacy_set_mode,
610bf2f1 VP	164	.set_next_event = hpet_legacy_next_event,
e9e2cdb4 TG	165	.shift = 32,
e9e2cdb4 TG	166	.irq = 0,
59c69f2a	167	.rating = 50,
e9e2cdb4 TG	168	};
	169
	170	static void hpet_start_counter(void)
	171	{
	172	unsigned long cfg = hpet_readl(HPET_CFG);
	173
	174	cfg &= ~HPET_CFG_ENABLE;
	175	hpet_writel(cfg, HPET_CFG);
	176	hpet_writel(0, HPET_COUNTER);
	177	hpet_writel(0, HPET_COUNTER + 4);
	178	cfg \|= HPET_CFG_ENABLE;
	179	hpet_writel(cfg, HPET_CFG);
	180	}
	181
59c69f2a VP	182	static void hpet_resume_device(void)
59c69f2a VP	183	{
bfe0c1cc	184	force_hpet_resume();
59c69f2a VP	185	}
	186
	187	static void hpet_restart_counter(void)
	188	{
	189	hpet_resume_device();
	190	hpet_start_counter();
	191	}
	192
610bf2f1	193	static void hpet_enable_legacy_int(void)
e9e2cdb4 TG	194	{
	195	unsigned long cfg = hpet_readl(HPET_CFG);
	196
	197	cfg \|= HPET_CFG_LEGACY;
	198	hpet_writel(cfg, HPET_CFG);
	199	hpet_legacy_int_enabled = 1;
	200	}
	201
610bf2f1 VP	202	static void hpet_legacy_clockevent_register(void)
	203	{
	204	uint64_t hpet_freq;
	205
	206	/* Start HPET legacy interrupts */
	207	hpet_enable_legacy_int();
	208
	209	/*
	210	* The period is a femto seconds value. We need to calculate the
	211	* scaled math multiplication factor for nanosecond to hpet tick
	212	* conversion.
	213	*/
	214	hpet_freq = 1000000000000000ULL;
	215	do_div(hpet_freq, hpet_period);
	216	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
	217	NSEC_PER_SEC, 32);
	218	/* Calculate the min / max delta */
	219	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
	220	&hpet_clockevent);
	221	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
	222	&hpet_clockevent);
	223
	224	/*
	225	* Start hpet with the boot cpu mask and make it
	226	* global after the IO_APIC has been initialized.
	227	*/
	228	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
	229	clockevents_register_device(&hpet_clockevent);
	230	global_clock_event = &hpet_clockevent;
	231	printk(KERN_DEBUG "hpet clockevent registered\n");
	232	}
	233
	234	static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 TG	235	struct clock_event_device *evt)
	236	{
	237	unsigned long cfg, cmp, now;
	238	uint64_t delta;
	239
	240	switch(mode) {
	241	case CLOCK_EVT_MODE_PERIODIC:
	242	delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
	243	delta >>= hpet_clockevent.shift;
	244	now = hpet_readl(HPET_COUNTER);
	245	cmp = now + (unsigned long) delta;
	246	cfg = hpet_readl(HPET_T0_CFG);
	247	cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
	248	HPET_TN_SETVAL \| HPET_TN_32BIT;
	249	hpet_writel(cfg, HPET_T0_CFG);
	250	/*
	251	* The first write after writing TN_SETVAL to the
	252	* config register sets the counter value, the second
	253	* write sets the period.
	254	*/
	255	hpet_writel(cmp, HPET_T0_CMP);
	256	udelay(1);
	257	hpet_writel((unsigned long) delta, HPET_T0_CMP);
	258	break;
	259
	260	case CLOCK_EVT_MODE_ONESHOT:
	261	cfg = hpet_readl(HPET_T0_CFG);
	262	cfg &= ~HPET_TN_PERIODIC;
	263	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
	264	hpet_writel(cfg, HPET_T0_CFG);
	265	break;
	266
	267	case CLOCK_EVT_MODE_UNUSED:
	268	case CLOCK_EVT_MODE_SHUTDOWN:
	269	cfg = hpet_readl(HPET_T0_CFG);
	270	cfg &= ~HPET_TN_ENABLE;
	271	hpet_writel(cfg, HPET_T0_CFG);
	272	break;
18de5bc4 TG	273
18de5bc4 TG	274	case CLOCK_EVT_MODE_RESUME:
610bf2f1	275	hpet_enable_legacy_int();
18de5bc4	276	break;
e9e2cdb4 TG	277	}
	278	}
	279
610bf2f1	280	static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4 TG	281	struct clock_event_device *evt)
	282	{
	283	unsigned long cnt;
	284
	285	cnt = hpet_readl(HPET_COUNTER);
	286	cnt += delta;
	287	hpet_writel(cnt, HPET_T0_CMP);
	288
c7f6d15f	289	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
e9e2cdb4 TG	290	}
e9e2cdb4 TG	291
6bb74df4	292	/*
	293	* Clock source related code
	294	*/
	295	static cycle_t read_hpet(void)
	296	{
	297	return (cycle_t)hpet_readl(HPET_COUNTER);
	298	}
	299
28769149 TG	300	#ifdef CONFIG_X86_64
	301	static cycle_t __vsyscall_fn vread_hpet(void)
	302	{
	303	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
	304	}
	305	#endif
	306
6bb74df4	307	static struct clocksource clocksource_hpet = {
	308	.name = "hpet",
	309	.rating = 250,
	310	.read = read_hpet,
	311	.mask = HPET_MASK,
	312	.shift = HPET_SHIFT,
	313	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
59c69f2a	314	.resume = hpet_restart_counter,
28769149 TG	315	#ifdef CONFIG_X86_64
	316	.vread = vread_hpet,
	317	#endif
6bb74df4	318	};
6bb74df4	319
610bf2f1	320	static int hpet_clocksource_register(void)
e9e2cdb4	321	{
075bcd1f TG	322	u64 tmp, start, now;
075bcd1f TG	323	cycle_t t1;
e9e2cdb4	324
e9e2cdb4 TG	325	/* Start the counter */
	326	hpet_start_counter();
	327
075bcd1f TG	328	/* Verify whether hpet counter works */
	329	t1 = read_hpet();
	330	rdtscll(start);
	331
	332	/*
	333	* We don't know the TSC frequency yet, but waiting for
	334	* 200000 TSC cycles is safe:
	335	* 4 GHz == 50us
	336	* 1 GHz == 200us
	337	*/
	338	do {
	339	rep_nop();
	340	rdtscll(now);
	341	} while ((now - start) < 200000UL);
	342
	343	if (t1 == read_hpet()) {
	344	printk(KERN_WARNING
	345	"HPET counter not counting. HPET disabled\n");
610bf2f1	346	return -ENODEV;
075bcd1f TG	347	}
075bcd1f TG	348
6bb74df4	349	/* Initialize and register HPET clocksource
	350	*
	351	* hpet period is in femto seconds per cycle
	352	* so we need to convert this to ns/cyc units
27b46d76	353	* approximated by mult/2^shift
6bb74df4	354	*
	355	* fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	356	* fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	357	* fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	358	* (fsec/cyc << shift)/1000000 = mult
	359	* (hpet_period << shift)/FSEC_PER_NSEC = mult
	360	*/
	361	tmp = (u64)hpet_period << HPET_SHIFT;
	362	do_div(tmp, FSEC_PER_NSEC);
	363	clocksource_hpet.mult = (u32)tmp;
	364
	365	clocksource_register(&clocksource_hpet);
	366
610bf2f1 VP	367	return 0;
	368	}
	369
	370	/*
	371	* Try to setup the HPET timer
	372	*/
	373	int __init hpet_enable(void)
	374	{
	375	unsigned long id;
	376
	377	if (!is_hpet_capable())
	378	return 0;
	379
	380	hpet_set_mapping();
	381
	382	/*
	383	* Read the period and check for a sane value:
	384	*/
	385	hpet_period = hpet_readl(HPET_PERIOD);
	386	if (hpet_period < HPET_MIN_PERIOD \|\| hpet_period > HPET_MAX_PERIOD)
	387	goto out_nohpet;
	388
	389	/*
	390	* Read the HPET ID register to retrieve the IRQ routing
	391	* information and the number of channels
	392	*/
	393	id = hpet_readl(HPET_ID);
	394
	395	#ifdef CONFIG_HPET_EMULATE_RTC
	396	/*
	397	* The legacy routing mode needs at least two channels, tick timer
	398	* and the rtc emulation channel.
	399	*/
	400	if (!(id & HPET_ID_NUMBER))
	401	goto out_nohpet;
	402	#endif
	403
	404	if (hpet_clocksource_register())
	405	goto out_nohpet;
	406
e9e2cdb4	407	if (id & HPET_ID_LEGSUP) {
610bf2f1	408	hpet_legacy_clockevent_register();
e9e2cdb4 TG	409	return 1;
	410	}
	411	return 0;
5d0cf410	412
e9e2cdb4	413	out_nohpet:
06a24dec	414	hpet_clear_mapping();
399afa4f	415	boot_hpet_disable = 1;
e9e2cdb4 TG	416	return 0;
	417	}
	418
28769149 TG	419	/*
	420	* Needs to be late, as the reserve_timer code calls kalloc !
	421	*
	422	* Not a problem on i386 as hpet_enable is called from late_time_init,
	423	* but on x86_64 it is necessary !
	424	*/
	425	static __init int hpet_late_init(void)
	426	{
59c69f2a	427	if (boot_hpet_disable)
28769149 TG	428	return -ENODEV;
28769149 TG	429
59c69f2a VP	430	if (!hpet_address) {
	431	if (!force_hpet_address)
	432	return -ENODEV;
	433
	434	hpet_address = force_hpet_address;
	435	hpet_enable();
	436	if (!hpet_virt_address)
	437	return -ENODEV;
	438	}
	439
28769149	440	hpet_reserve_platform_timers(hpet_readl(HPET_ID));
59c69f2a	441
28769149 TG	442	return 0;
	443	}
	444	fs_initcall(hpet_late_init);
	445
c86c7fbc OH	446	void hpet_disable(void)
	447	{
	448	if (is_hpet_capable()) {
	449	unsigned long cfg = hpet_readl(HPET_CFG);
	450
	451	if (hpet_legacy_int_enabled) {
	452	cfg &= ~HPET_CFG_LEGACY;
	453	hpet_legacy_int_enabled = 0;
	454	}
	455	cfg &= ~HPET_CFG_ENABLE;
	456	hpet_writel(cfg, HPET_CFG);
	457	}
	458	}
	459
e9e2cdb4 TG	460	#ifdef CONFIG_HPET_EMULATE_RTC
	461
	462	/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
	463	* is enabled, we support RTC interrupt functionality in software.
	464	* RTC has 3 kinds of interrupts:
	465	* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
	466	* is updated
	467	* 2) Alarm Interrupt - generate an interrupt at a specific time of day
	468	* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
	469	* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
	470	* (1) and (2) above are implemented using polling at a frequency of
	471	* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
	472	* overhead. (DEFAULT_RTC_INT_FREQ)
	473	* For (3), we use interrupts at 64Hz or user specified periodic
	474	* frequency, whichever is higher.
	475	*/
	476	#include <linux/mc146818rtc.h>
	477	#include <linux/rtc.h>
	478
	479	#define DEFAULT_RTC_INT_FREQ 64
	480	#define DEFAULT_RTC_SHIFT 6
	481	#define RTC_NUM_INTS 1
	482
	483	static unsigned long hpet_rtc_flags;
	484	static unsigned long hpet_prev_update_sec;
	485	static struct rtc_time hpet_alarm_time;
	486	static unsigned long hpet_pie_count;
	487	static unsigned long hpet_t1_cmp;
	488	static unsigned long hpet_default_delta;
	489	static unsigned long hpet_pie_delta;
	490	static unsigned long hpet_pie_limit;
	491
	492	/*
	493	* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
	494	* is not supported by all HPET implementations for timer 1.
	495	*
	496	* hpet_rtc_timer_init() is called when the rtc is initialized.
	497	*/
	498	int hpet_rtc_timer_init(void)
	499	{
	500	unsigned long cfg, cnt, delta, flags;
	501
	502	if (!is_hpet_enabled())
	503	return 0;
	504
	505	if (!hpet_default_delta) {
	506	uint64_t clc;
	507
	508	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
	509	clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
	510	hpet_default_delta = (unsigned long) clc;
	511	}
	512
	513	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
	514	delta = hpet_default_delta;
	515	else
	516	delta = hpet_pie_delta;
	517
	518	local_irq_save(flags);
	519
	520	cnt = delta + hpet_readl(HPET_COUNTER);
	521	hpet_writel(cnt, HPET_T1_CMP);
	522	hpet_t1_cmp = cnt;
	523
524	cfg = hpet_readl(HPET_T1_CFG);
525	cfg &= ~HPET_TN_PERIODIC;
526	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
527	hpet_writel(cfg, HPET_T1_CFG);
528
529	local_irq_restore(flags);
530
531	return 1;
532	}
533
534	/*
535	* The functions below are called from rtc driver.
536	* Return 0 if HPET is not being used.
537	* Otherwise do the necessary changes and return 1.
538	*/
539	int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
540	{
541	if (!is_hpet_enabled())
542	return 0;
543
544	hpet_rtc_flags &= ~bit_mask;
545	return 1;
546	}
547
548	int hpet_set_rtc_irq_bit(unsigned long bit_mask)
549	{
550	unsigned long oldbits = hpet_rtc_flags;
551
552	if (!is_hpet_enabled())
553	return 0;
554
555	hpet_rtc_flags \|= bit_mask;
556
557	if (!oldbits)
558	hpet_rtc_timer_init();
559
560	return 1;
561	}
562
563	int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
564	unsigned char sec)
565	{
566	if (!is_hpet_enabled())
567	return 0;
568
569	hpet_alarm_time.tm_hour = hrs;
570	hpet_alarm_time.tm_min = min;
571	hpet_alarm_time.tm_sec = sec;
572
573	return 1;
574	}
575
576	int hpet_set_periodic_freq(unsigned long freq)
577	{
578	uint64_t clc;
579
580	if (!is_hpet_enabled())
581	return 0;
582
583	if (freq <= DEFAULT_RTC_INT_FREQ)
584	hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
585	else {
586	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
587	do_div(clc, freq);
588	clc >>= hpet_clockevent.shift;
589	hpet_pie_delta = (unsigned long) clc;
590	}
591	return 1;
592	}
593
594	int hpet_rtc_dropped_irq(void)
595	{
596	return is_hpet_enabled();
597	}
598
599	static void hpet_rtc_timer_reinit(void)
600	{
601	unsigned long cfg, delta;
602	int lost_ints = -1;
603
604	if (unlikely(!hpet_rtc_flags)) {
605	cfg = hpet_readl(HPET_T1_CFG);
606	cfg &= ~HPET_TN_ENABLE;
607	hpet_writel(cfg, HPET_T1_CFG);
608	return;
609	}
610
611	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
612	delta = hpet_default_delta;
613	else
614	delta = hpet_pie_delta;
615
616	/*
617	* Increment the comparator value until we are ahead of the
618	* current count.
619	*/
620	do {
621	hpet_t1_cmp += delta;
622	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
623	lost_ints++;
624	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
625
626	if (lost_ints) {
627	if (hpet_rtc_flags & RTC_PIE)
628	hpet_pie_count += lost_ints;
629	if (printk_ratelimit())
630	printk(KERN_WARNING "rtc: lost %d interrupts\n",
631	lost_ints);
632	}
633	}
634
635	irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
636	{
637	struct rtc_time curr_time;
638	unsigned long rtc_int_flag = 0;
639
640	hpet_rtc_timer_reinit();
641
642	if (hpet_rtc_flags & (RTC_UIE \| RTC_AIE))
643	rtc_get_rtc_time(&curr_time);
644
645	if (hpet_rtc_flags & RTC_UIE &&
646	curr_time.tm_sec != hpet_prev_update_sec) {
647	rtc_int_flag = RTC_UF;
648	hpet_prev_update_sec = curr_time.tm_sec;
649	}
650
651	if (hpet_rtc_flags & RTC_PIE &&
652	++hpet_pie_count >= hpet_pie_limit) {
653	rtc_int_flag \|= RTC_PF;
654	hpet_pie_count = 0;
655	}
656
8ee291f8	657	if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4 TG	658	(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	659	(curr_time.tm_min == hpet_alarm_time.tm_min) &&
	660	(curr_time.tm_hour == hpet_alarm_time.tm_hour))
	661	rtc_int_flag \|= RTC_AF;
	662
	663	if (rtc_int_flag) {
	664	rtc_int_flag \|= (RTC_IRQF \| (RTC_NUM_INTS << 8));
	665	rtc_interrupt(rtc_int_flag, dev_id);
	666	}
	667	return IRQ_HANDLED;
	668	}
	669	#endif