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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/fyu/linux-2.6
[linux-2.6-block.git] / arch / x86 / kernel / hpet.c
CommitLineData
5d0cf410 1#include <linux/clocksource.h>
e9e2cdb4 2#include <linux/clockchips.h>
4588c1f0
IM		 3#include <linux/interrupt.h>
4#include <linux/sysdev.h>
28769149 5#include <linux/delay.h>
5d0cf410 6#include <linux/errno.h>
7#include <linux/hpet.h>
8#include <linux/init.h>
58ac1e76 9#include <linux/cpu.h>
4588c1f0
IM		 10#include <linux/pm.h>
11#include <linux/io.h>
5d0cf410 12
28769149 13#include <asm/fixmap.h>
06a24dec 14#include <asm/i8253.h>
4588c1f0 15#include <asm/hpet.h>
5d0cf410 16
4588c1f0
IM		 17#define HPET_MASK CLOCKSOURCE_MASK(32)
18#define HPET_SHIFT 22
5d0cf410 19
b10db7f0
PM		 20/* FSEC = 10^-15
21 NSEC = 10^-9 */
4588c1f0 22#define FSEC_PER_NSEC 1000000L
5d0cf410 23
26afe5f2 24#define HPET_DEV_USED_BIT 2
25#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
26#define HPET_DEV_VALID 0x8
27#define HPET_DEV_FSB_CAP 0x1000
28#define HPET_DEV_PERI_CAP 0x2000
29
30#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
31
e9e2cdb4
TG		 32/*
33 * HPET address is set in acpi/boot.c, when an ACPI entry exists
34 */
4588c1f0 35unsigned long hpet_address;
e951e4af 36#ifdef CONFIG_PCI_MSI
3b71e9e3 37static unsigned long hpet_num_timers;
e951e4af 38#endif
4588c1f0 39static void __iomem *hpet_virt_address;
e9e2cdb4 40
58ac1e76 41struct hpet_dev {
4588c1f0
IM		 42 struct clock_event_device evt;
43 unsigned int num;
44 int cpu;
45 unsigned int irq;
46 unsigned int flags;
47 char name[10];
58ac1e76 48};
49
31c435d7 50unsigned long hpet_readl(unsigned long a)
e9e2cdb4
TG		 51{
52 return readl(hpet_virt_address + a);
53}
54
55static inline void hpet_writel(unsigned long d, unsigned long a)
56{
57 writel(d, hpet_virt_address + a);
58}
59
28769149 60#ifdef CONFIG_X86_64
28769149 61#include <asm/pgtable.h>
2387ce57 62#endif
28769149 63
06a24dec
TG		 64static inline void hpet_set_mapping(void)
65{
66 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
2387ce57
YL		 67#ifdef CONFIG_X86_64
68 __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
69#endif
06a24dec
TG		 70}
71
72static inline void hpet_clear_mapping(void)
73{
74 iounmap(hpet_virt_address);
75 hpet_virt_address = NULL;
76}
77
e9e2cdb4
TG		 78/*
79 * HPET command line enable / disable
80 */
81static int boot_hpet_disable;
b17530bd 82int hpet_force_user;
b98103a5 83static int hpet_verbose;
e9e2cdb4 84
4588c1f0 85static int __init hpet_setup(char *str)
e9e2cdb4
TG		 86{
87 if (str) {
88 if (!strncmp("disable", str, 7))
89 boot_hpet_disable = 1;
b17530bd
TG		 90 if (!strncmp("force", str, 5))
91 hpet_force_user = 1;
b98103a5
AH		 92 if (!strncmp("verbose", str, 7))
93 hpet_verbose = 1;
e9e2cdb4
TG		 94 }
95 return 1;
96}
97__setup("hpet=", hpet_setup);
98
28769149
TG		 99static int __init disable_hpet(char *str)
100{
101 boot_hpet_disable = 1;
102 return 1;
103}
104__setup("nohpet", disable_hpet);
105
e9e2cdb4
TG		 106static inline int is_hpet_capable(void)
107{
4588c1f0 108 return !boot_hpet_disable && hpet_address;
e9e2cdb4
TG		 109}
110
111/*
112 * HPET timer interrupt enable / disable
113 */
114static int hpet_legacy_int_enabled;
115
116/**
117 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
118 */
119int is_hpet_enabled(void)
120{
121 return is_hpet_capable() && hpet_legacy_int_enabled;
122}
1bdbdaac 123EXPORT_SYMBOL_GPL(is_hpet_enabled);
e9e2cdb4 124
b98103a5
AH		 125static void _hpet_print_config(const char *function, int line)
126{
127 u32 i, timers, l, h;
128 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
129 l = hpet_readl(HPET_ID);
130 h = hpet_readl(HPET_PERIOD);
131 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
132 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
133 l = hpet_readl(HPET_CFG);
134 h = hpet_readl(HPET_STATUS);
135 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
136 l = hpet_readl(HPET_COUNTER);
137 h = hpet_readl(HPET_COUNTER+4);
138 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
139
140 for (i = 0; i < timers; i++) {
141 l = hpet_readl(HPET_Tn_CFG(i));
142 h = hpet_readl(HPET_Tn_CFG(i)+4);
143 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
144 i, l, h);
145 l = hpet_readl(HPET_Tn_CMP(i));
146 h = hpet_readl(HPET_Tn_CMP(i)+4);
147 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
148 i, l, h);
149 l = hpet_readl(HPET_Tn_ROUTE(i));
150 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
151 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
152 i, l, h);
153 }
154}
155
156#define hpet_print_config() \
157do { \
158 if (hpet_verbose) \
159 _hpet_print_config(__FUNCTION__, __LINE__); \
160} while (0)
161
e9e2cdb4
TG		 162/*
163 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
164 * timer 0 and timer 1 in case of RTC emulation.
165 */
166#ifdef CONFIG_HPET
f0ed4e69 167
5f79f2f2 168static void hpet_reserve_msi_timers(struct hpet_data *hd);
f0ed4e69 169
e9e2cdb4
TG		 170static void hpet_reserve_platform_timers(unsigned long id)
171{
172 struct hpet __iomem *hpet = hpet_virt_address;
37a47db8
BR		 173 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
174 unsigned int nrtimers, i;
e9e2cdb4
TG		 175 struct hpet_data hd;
176
177 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
178
4588c1f0
IM		 179 memset(&hd, 0, sizeof(hd));
180 hd.hd_phys_address = hpet_address;
181 hd.hd_address = hpet;
182 hd.hd_nirqs = nrtimers;
e9e2cdb4
TG		 183 hpet_reserve_timer(&hd, 0);
184
185#ifdef CONFIG_HPET_EMULATE_RTC
186 hpet_reserve_timer(&hd, 1);
187#endif
5761d64b 188
64a76f66
DB		 189 /*
190 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
191 * is wrong for i8259!) not the output IRQ. Many BIOS writers
192 * don't bother configuring *any* comparator interrupts.
193 */
e9e2cdb4
TG		 194 hd.hd_irq[0] = HPET_LEGACY_8254;
195 hd.hd_irq[1] = HPET_LEGACY_RTC;
196
fc3fbc45 197 for (i = 2; i < nrtimers; timer++, i++) {
4588c1f0
IM		 198 hd.hd_irq[i] = (readl(&timer->hpet_config) &
199 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
fc3fbc45 200 }
5761d64b 201
f0ed4e69 202 hpet_reserve_msi_timers(&hd);
26afe5f2 203
e9e2cdb4 204 hpet_alloc(&hd);
5761d64b 205
e9e2cdb4
TG		 206}
207#else
208static void hpet_reserve_platform_timers(unsigned long id) { }
209#endif
210
211/*
212 * Common hpet info
213 */
214static unsigned long hpet_period;
215
610bf2f1 216static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 217 struct clock_event_device *evt);
610bf2f1 218static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4
TG		 219 struct clock_event_device *evt);
220
221/*
222 * The hpet clock event device
223 */
224static struct clock_event_device hpet_clockevent = {
225 .name = "hpet",
226 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
610bf2f1
VP		 227 .set_mode = hpet_legacy_set_mode,
228 .set_next_event = hpet_legacy_next_event,
e9e2cdb4
TG		 229 .shift = 32,
230 .irq = 0,
59c69f2a 231 .rating = 50,
e9e2cdb4
TG		 232};
233
8d6f0c82 234static void hpet_stop_counter(void)
e9e2cdb4
TG		 235{
236 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 237 cfg &= ~HPET_CFG_ENABLE;
238 hpet_writel(cfg, HPET_CFG);
7a6f9cbb
AH		 239}
240
241static void hpet_reset_counter(void)
242{
e9e2cdb4
TG		 243 hpet_writel(0, HPET_COUNTER);
244 hpet_writel(0, HPET_COUNTER + 4);
8d6f0c82
AH		 245}
246
247static void hpet_start_counter(void)
248{
249 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 250 cfg |= HPET_CFG_ENABLE;
251 hpet_writel(cfg, HPET_CFG);
252}
253
8d6f0c82
AH		 254static void hpet_restart_counter(void)
255{
256 hpet_stop_counter();
7a6f9cbb 257 hpet_reset_counter();
8d6f0c82
AH		 258 hpet_start_counter();
259}
260
59c69f2a
VP		 261static void hpet_resume_device(void)
262{
bfe0c1cc 263 force_hpet_resume();
59c69f2a
VP		 264}
265
8d6f0c82 266static void hpet_resume_counter(void)
59c69f2a
VP		 267{
268 hpet_resume_device();
8d6f0c82 269 hpet_restart_counter();
59c69f2a
VP		 270}
271
610bf2f1 272static void hpet_enable_legacy_int(void)
e9e2cdb4
TG		 273{
274 unsigned long cfg = hpet_readl(HPET_CFG);
275
276 cfg |= HPET_CFG_LEGACY;
277 hpet_writel(cfg, HPET_CFG);
278 hpet_legacy_int_enabled = 1;
279}
280
610bf2f1
VP		 281static void hpet_legacy_clockevent_register(void)
282{
610bf2f1
VP		 283 /* Start HPET legacy interrupts */
284 hpet_enable_legacy_int();
285
286 /*
6fd592da
CM		 287 * The mult factor is defined as (include/linux/clockchips.h)
288 * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
289 * hpet_period is in units of femtoseconds (per cycle), so
290 * mult/2^shift = cyc/ns = 10^6/hpet_period
291 * mult = (10^6 * 2^shift)/hpet_period
292 * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
610bf2f1 293 */
6fd592da
CM		 294 hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
295 hpet_period, hpet_clockevent.shift);
610bf2f1
VP		 296 /* Calculate the min / max delta */
297 hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
298 &hpet_clockevent);
7cfb0435
TG		 299 /* 5 usec minimum reprogramming delta. */
300 hpet_clockevent.min_delta_ns = 5000;
610bf2f1
VP		 301
302 /*
303 * Start hpet with the boot cpu mask and make it
304 * global after the IO_APIC has been initialized.
305 */
320ab2b0 306 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
610bf2f1
VP		 307 clockevents_register_device(&hpet_clockevent);
308 global_clock_event = &hpet_clockevent;
309 printk(KERN_DEBUG "hpet clockevent registered\n");
310}
311
26afe5f2 312static int hpet_setup_msi_irq(unsigned int irq);
313
b40d575b 314static void hpet_set_mode(enum clock_event_mode mode,
315 struct clock_event_device *evt, int timer)
e9e2cdb4 316{
7a6f9cbb 317 unsigned long cfg, cmp, now;
e9e2cdb4
TG		 318 uint64_t delta;
319
4588c1f0 320 switch (mode) {
e9e2cdb4 321 case CLOCK_EVT_MODE_PERIODIC:
c23e253e 322 hpet_stop_counter();
b40d575b 323 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
324 delta >>= evt->shift;
7a6f9cbb
AH		 325 now = hpet_readl(HPET_COUNTER);
326 cmp = now + (unsigned long) delta;
b40d575b 327 cfg = hpet_readl(HPET_Tn_CFG(timer));
b13e2464 328 /* Make sure we use edge triggered interrupts */
329 cfg &= ~HPET_TN_LEVEL;
e9e2cdb4
TG		 330 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
331 HPET_TN_SETVAL | HPET_TN_32BIT;
b40d575b 332 hpet_writel(cfg, HPET_Tn_CFG(timer));
7a6f9cbb
AH		 333 hpet_writel(cmp, HPET_Tn_CMP(timer));
334 udelay(1);
335 /*
336 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
337 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
338 * bit is automatically cleared after the first write.
339 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
340 * Publication # 24674)
341 */
b40d575b 342 hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
c23e253e 343 hpet_start_counter();
b98103a5 344 hpet_print_config();
e9e2cdb4
TG		 345 break;
346
347 case CLOCK_EVT_MODE_ONESHOT:
b40d575b 348 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 349 cfg &= ~HPET_TN_PERIODIC;
350 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
b40d575b 351 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4
TG		 352 break;
353
354 case CLOCK_EVT_MODE_UNUSED:
355 case CLOCK_EVT_MODE_SHUTDOWN:
b40d575b 356 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4 357 cfg &= ~HPET_TN_ENABLE;
b40d575b 358 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4 359 break;
18de5bc4
TG		 360
361 case CLOCK_EVT_MODE_RESUME:
26afe5f2 362 if (timer == 0) {
363 hpet_enable_legacy_int();
364 } else {
365 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
366 hpet_setup_msi_irq(hdev->irq);
367 disable_irq(hdev->irq);
0de26520 368 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
26afe5f2 369 enable_irq(hdev->irq);
370 }
b98103a5 371 hpet_print_config();
18de5bc4 372 break;
e9e2cdb4
TG		 373 }
374}
375
b40d575b 376static int hpet_next_event(unsigned long delta,
377 struct clock_event_device *evt, int timer)
e9e2cdb4 378{
f7676254 379 u32 cnt;
e9e2cdb4
TG		 380
381 cnt = hpet_readl(HPET_COUNTER);
f7676254 382 cnt += (u32) delta;
b40d575b 383 hpet_writel(cnt, HPET_Tn_CMP(timer));
e9e2cdb4 384
72d43d9b
TG		 385 /*
386 * We need to read back the CMP register to make sure that
387 * what we wrote hit the chip before we compare it to the
388 * counter.
389 */
89d77a1e 390 WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
72d43d9b 391
f7676254 392 return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
e9e2cdb4
TG		 393}
394
b40d575b 395static void hpet_legacy_set_mode(enum clock_event_mode mode,
396 struct clock_event_device *evt)
397{
398 hpet_set_mode(mode, evt, 0);
399}
400
401static int hpet_legacy_next_event(unsigned long delta,
402 struct clock_event_device *evt)
403{
404 return hpet_next_event(delta, evt, 0);
405}
406
58ac1e76 407/*
408 * HPET MSI Support
409 */
26afe5f2 410#ifdef CONFIG_PCI_MSI
5f79f2f2
VP		 411
412static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
413static struct hpet_dev *hpet_devs;
414
58ac1e76 415void hpet_msi_unmask(unsigned int irq)
416{
417 struct hpet_dev *hdev = get_irq_data(irq);
418 unsigned long cfg;
419
420 /* unmask it */
421 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
422 cfg |= HPET_TN_FSB;
423 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
424}
425
426void hpet_msi_mask(unsigned int irq)
427{
428 unsigned long cfg;
429 struct hpet_dev *hdev = get_irq_data(irq);
430
431 /* mask it */
432 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
433 cfg &= ~HPET_TN_FSB;
434 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
435}
436
437void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
438{
439 struct hpet_dev *hdev = get_irq_data(irq);
440
441 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
442 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
443}
444
445void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
446{
447 struct hpet_dev *hdev = get_irq_data(irq);
448
449 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
450 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
451 msg->address_hi = 0;
452}
453
26afe5f2 454static void hpet_msi_set_mode(enum clock_event_mode mode,
455 struct clock_event_device *evt)
456{
457 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
458 hpet_set_mode(mode, evt, hdev->num);
459}
460
461static int hpet_msi_next_event(unsigned long delta,
462 struct clock_event_device *evt)
463{
464 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
465 return hpet_next_event(delta, evt, hdev->num);
466}
467
468static int hpet_setup_msi_irq(unsigned int irq)
469{
470 if (arch_setup_hpet_msi(irq)) {
471 destroy_irq(irq);
472 return -EINVAL;
473 }
474 return 0;
475}
476
477static int hpet_assign_irq(struct hpet_dev *dev)
478{
479 unsigned int irq;
480
481 irq = create_irq();
482 if (!irq)
483 return -EINVAL;
484
485 set_irq_data(irq, dev);
486
487 if (hpet_setup_msi_irq(irq))
488 return -EINVAL;
489
490 dev->irq = irq;
491 return 0;
492}
493
494static irqreturn_t hpet_interrupt_handler(int irq, void *data)
495{
496 struct hpet_dev *dev = (struct hpet_dev *)data;
497 struct clock_event_device *hevt = &dev->evt;
498
499 if (!hevt->event_handler) {
500 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
501 dev->num);
502 return IRQ_HANDLED;
503 }
504
505 hevt->event_handler(hevt);
506 return IRQ_HANDLED;
507}
508
509static int hpet_setup_irq(struct hpet_dev *dev)
510{
511
512 if (request_irq(dev->irq, hpet_interrupt_handler,
507fa3a3
TG		 513 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
514 dev->name, dev))
26afe5f2 515 return -1;
516
517 disable_irq(dev->irq);
0de26520 518 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
26afe5f2 519 enable_irq(dev->irq);
520
c81bba49
YL		 521 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
522 dev->name, dev->irq);
523
26afe5f2 524 return 0;
525}
526
527/* This should be called in specific @cpu */
528static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
529{
530 struct clock_event_device *evt = &hdev->evt;
531 uint64_t hpet_freq;
532
533 WARN_ON(cpu != smp_processor_id());
534 if (!(hdev->flags & HPET_DEV_VALID))
535 return;
536
537 if (hpet_setup_msi_irq(hdev->irq))
538 return;
539
540 hdev->cpu = cpu;
541 per_cpu(cpu_hpet_dev, cpu) = hdev;
542 evt->name = hdev->name;
543 hpet_setup_irq(hdev);
544 evt->irq = hdev->irq;
545
546 evt->rating = 110;
547 evt->features = CLOCK_EVT_FEAT_ONESHOT;
548 if (hdev->flags & HPET_DEV_PERI_CAP)
549 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
550
551 evt->set_mode = hpet_msi_set_mode;
552 evt->set_next_event = hpet_msi_next_event;
553 evt->shift = 32;
554
555 /*
556 * The period is a femto seconds value. We need to calculate the
557 * scaled math multiplication factor for nanosecond to hpet tick
558 * conversion.
559 */
560 hpet_freq = 1000000000000000ULL;
561 do_div(hpet_freq, hpet_period);
562 evt->mult = div_sc((unsigned long) hpet_freq,
563 NSEC_PER_SEC, evt->shift);
564 /* Calculate the max delta */
565 evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
566 /* 5 usec minimum reprogramming delta. */
567 evt->min_delta_ns = 5000;
568
320ab2b0 569 evt->cpumask = cpumask_of(hdev->cpu);
26afe5f2 570 clockevents_register_device(evt);
571}
572
573#ifdef CONFIG_HPET
574/* Reserve at least one timer for userspace (/dev/hpet) */
575#define RESERVE_TIMERS 1
576#else
577#define RESERVE_TIMERS 0
578#endif
5f79f2f2
VP		 579
580static void hpet_msi_capability_lookup(unsigned int start_timer)
26afe5f2 581{
582 unsigned int id;
583 unsigned int num_timers;
584 unsigned int num_timers_used = 0;
585 int i;
586
587 id = hpet_readl(HPET_ID);
588
589 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
590 num_timers++; /* Value read out starts from 0 */
b98103a5 591 hpet_print_config();
26afe5f2 592
593 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
594 if (!hpet_devs)
595 return;
596
597 hpet_num_timers = num_timers;
598
599 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
600 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
601 unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
602
603 /* Only consider HPET timer with MSI support */
604 if (!(cfg & HPET_TN_FSB_CAP))
605 continue;
606
607 hdev->flags = 0;
608 if (cfg & HPET_TN_PERIODIC_CAP)
609 hdev->flags |= HPET_DEV_PERI_CAP;
610 hdev->num = i;
611
612 sprintf(hdev->name, "hpet%d", i);
613 if (hpet_assign_irq(hdev))
614 continue;
615
616 hdev->flags |= HPET_DEV_FSB_CAP;
617 hdev->flags |= HPET_DEV_VALID;
618 num_timers_used++;
619 if (num_timers_used == num_possible_cpus())
620 break;
621 }
622
623 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
624 num_timers, num_timers_used);
625}
626
5f79f2f2
VP		 627#ifdef CONFIG_HPET
628static void hpet_reserve_msi_timers(struct hpet_data *hd)
629{
630 int i;
631
632 if (!hpet_devs)
633 return;
634
635 for (i = 0; i < hpet_num_timers; i++) {
636 struct hpet_dev *hdev = &hpet_devs[i];
637
638 if (!(hdev->flags & HPET_DEV_VALID))
639 continue;
640
641 hd->hd_irq[hdev->num] = hdev->irq;
642 hpet_reserve_timer(hd, hdev->num);
643 }
644}
645#endif
646
26afe5f2 647static struct hpet_dev *hpet_get_unused_timer(void)
648{
649 int i;
650
651 if (!hpet_devs)
652 return NULL;
653
654 for (i = 0; i < hpet_num_timers; i++) {
655 struct hpet_dev *hdev = &hpet_devs[i];
656
657 if (!(hdev->flags & HPET_DEV_VALID))
658 continue;
659 if (test_and_set_bit(HPET_DEV_USED_BIT,
660 (unsigned long *)&hdev->flags))
661 continue;
662 return hdev;
663 }
664 return NULL;
665}
666
667struct hpet_work_struct {
668 struct delayed_work work;
669 struct completion complete;
670};
671
672static void hpet_work(struct work_struct *w)
673{
674 struct hpet_dev *hdev;
675 int cpu = smp_processor_id();
676 struct hpet_work_struct *hpet_work;
677
678 hpet_work = container_of(w, struct hpet_work_struct, work.work);
679
680 hdev = hpet_get_unused_timer();
681 if (hdev)
682 init_one_hpet_msi_clockevent(hdev, cpu);
683
684 complete(&hpet_work->complete);
685}
686
687static int hpet_cpuhp_notify(struct notifier_block *n,
688 unsigned long action, void *hcpu)
689{
690 unsigned long cpu = (unsigned long)hcpu;
691 struct hpet_work_struct work;
692 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
693
694 switch (action & 0xf) {
695 case CPU_ONLINE:
336f6c32 696 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
26afe5f2 697 init_completion(&work.complete);
698 /* FIXME: add schedule_work_on() */
699 schedule_delayed_work_on(cpu, &work.work, 0);
700 wait_for_completion(&work.complete);
336f6c32 701 destroy_timer_on_stack(&work.work.timer);
26afe5f2 702 break;
703 case CPU_DEAD:
704 if (hdev) {
705 free_irq(hdev->irq, hdev);
706 hdev->flags &= ~HPET_DEV_USED;
707 per_cpu(cpu_hpet_dev, cpu) = NULL;
708 }
709 break;
710 }
711 return NOTIFY_OK;
712}
713#else
714
ba374c9b
SN		 715static int hpet_setup_msi_irq(unsigned int irq)
716{
717 return 0;
718}
5f79f2f2
VP		 719static void hpet_msi_capability_lookup(unsigned int start_timer)
720{
721 return;
722}
723
724#ifdef CONFIG_HPET
725static void hpet_reserve_msi_timers(struct hpet_data *hd)
26afe5f2 726{
727 return;
728}
5f79f2f2 729#endif
26afe5f2 730
731static int hpet_cpuhp_notify(struct notifier_block *n,
732 unsigned long action, void *hcpu)
733{
734 return NOTIFY_OK;
735}
736
737#endif
738
6bb74df4 739/*
740 * Clock source related code
741 */
8e19608e 742static cycle_t read_hpet(struct clocksource *cs)
6bb74df4 743{
744 return (cycle_t)hpet_readl(HPET_COUNTER);
745}
746
28769149
TG		 747#ifdef CONFIG_X86_64
748static cycle_t __vsyscall_fn vread_hpet(void)
749{
750 return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
751}
752#endif
753
6bb74df4 754static struct clocksource clocksource_hpet = {
755 .name = "hpet",
756 .rating = 250,
757 .read = read_hpet,
758 .mask = HPET_MASK,
759 .shift = HPET_SHIFT,
760 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
8d6f0c82 761 .resume = hpet_resume_counter,
28769149
TG		 762#ifdef CONFIG_X86_64
763 .vread = vread_hpet,
764#endif
6bb74df4 765};
766
610bf2f1 767static int hpet_clocksource_register(void)
e9e2cdb4 768{
6fd592da 769 u64 start, now;
075bcd1f 770 cycle_t t1;
e9e2cdb4 771
e9e2cdb4 772 /* Start the counter */
8d6f0c82 773 hpet_restart_counter();
e9e2cdb4 774
075bcd1f 775 /* Verify whether hpet counter works */
8e19608e 776 t1 = hpet_readl(HPET_COUNTER);
075bcd1f
TG		 777 rdtscll(start);
778
779 /*
780 * We don't know the TSC frequency yet, but waiting for
781 * 200000 TSC cycles is safe:
782 * 4 GHz == 50us
783 * 1 GHz == 200us
784 */
785 do {
786 rep_nop();
787 rdtscll(now);
788 } while ((now - start) < 200000UL);
789
8e19608e 790 if (t1 == hpet_readl(HPET_COUNTER)) {
075bcd1f
TG		 791 printk(KERN_WARNING
792 "HPET counter not counting. HPET disabled\n");
610bf2f1 793 return -ENODEV;
075bcd1f
TG		 794 }
795
6fd592da
CM		 796 /*
797 * The definition of mult is (include/linux/clocksource.h)
798 * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
799 * so we first need to convert hpet_period to ns/cyc units:
800 * mult/2^shift = ns/cyc = hpet_period/10^6
801 * mult = (hpet_period * 2^shift)/10^6
802 * mult = (hpet_period << shift)/FSEC_PER_NSEC
6bb74df4 803 */
6fd592da 804 clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
6bb74df4 805
806 clocksource_register(&clocksource_hpet);
807
610bf2f1
VP		 808 return 0;
809}
810
b02a7f22
PM		 811/**
812 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
610bf2f1
VP		 813 */
814int __init hpet_enable(void)
815{
816 unsigned long id;
a6825f1c 817 int i;
610bf2f1
VP		 818
819 if (!is_hpet_capable())
820 return 0;
821
822 hpet_set_mapping();
823
824 /*
825 * Read the period and check for a sane value:
826 */
827 hpet_period = hpet_readl(HPET_PERIOD);
a6825f1c
TG		 828
829 /*
830 * AMD SB700 based systems with spread spectrum enabled use a
831 * SMM based HPET emulation to provide proper frequency
832 * setting. The SMM code is initialized with the first HPET
833 * register access and takes some time to complete. During
834 * this time the config register reads 0xffffffff. We check
835 * for max. 1000 loops whether the config register reads a non
836 * 0xffffffff value to make sure that HPET is up and running
837 * before we go further. A counting loop is safe, as the HPET
838 * access takes thousands of CPU cycles. On non SB700 based
839 * machines this check is only done once and has no side
840 * effects.
841 */
842 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
843 if (i == 1000) {
844 printk(KERN_WARNING
845 "HPET config register value = 0xFFFFFFFF. "
846 "Disabling HPET\n");
847 goto out_nohpet;
848 }
849 }
850
610bf2f1
VP		 851 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
852 goto out_nohpet;
853
854 /*
855 * Read the HPET ID register to retrieve the IRQ routing
856 * information and the number of channels
857 */
858 id = hpet_readl(HPET_ID);
b98103a5 859 hpet_print_config();
610bf2f1
VP		 860
861#ifdef CONFIG_HPET_EMULATE_RTC
862 /*
863 * The legacy routing mode needs at least two channels, tick timer
864 * and the rtc emulation channel.
865 */
866 if (!(id & HPET_ID_NUMBER))
867 goto out_nohpet;
868#endif
869
870 if (hpet_clocksource_register())
871 goto out_nohpet;
872
e9e2cdb4 873 if (id & HPET_ID_LEGSUP) {
610bf2f1 874 hpet_legacy_clockevent_register();
26afe5f2 875 hpet_msi_capability_lookup(2);
e9e2cdb4
TG		 876 return 1;
877 }
26afe5f2 878 hpet_msi_capability_lookup(0);
e9e2cdb4 879 return 0;
5d0cf410 880
e9e2cdb4 881out_nohpet:
06a24dec 882 hpet_clear_mapping();
bacbe999 883 hpet_address = 0;
e9e2cdb4
TG		 884 return 0;
885}
886
28769149
TG		 887/*
888 * Needs to be late, as the reserve_timer code calls kalloc !
889 *
890 * Not a problem on i386 as hpet_enable is called from late_time_init,
891 * but on x86_64 it is necessary !
892 */
893static __init int hpet_late_init(void)
894{
26afe5f2 895 int cpu;
896
59c69f2a 897 if (boot_hpet_disable)
28769149
TG		 898 return -ENODEV;
899
59c69f2a
VP		 900 if (!hpet_address) {
901 if (!force_hpet_address)
902 return -ENODEV;
903
904 hpet_address = force_hpet_address;
905 hpet_enable();
59c69f2a
VP		 906 }
907
39c04b55
JF		 908 if (!hpet_virt_address)
909 return -ENODEV;
910
28769149 911 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
b98103a5 912 hpet_print_config();
59c69f2a 913
26afe5f2 914 for_each_online_cpu(cpu) {
915 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
916 }
917
918 /* This notifier should be called after workqueue is ready */
919 hotcpu_notifier(hpet_cpuhp_notify, -20);
920
28769149
TG		 921 return 0;
922}
923fs_initcall(hpet_late_init);
924
c86c7fbc
OH		 925void hpet_disable(void)
926{
927 if (is_hpet_capable()) {
928 unsigned long cfg = hpet_readl(HPET_CFG);
929
930 if (hpet_legacy_int_enabled) {
931 cfg &= ~HPET_CFG_LEGACY;
932 hpet_legacy_int_enabled = 0;
933 }
934 cfg &= ~HPET_CFG_ENABLE;
935 hpet_writel(cfg, HPET_CFG);
936 }
937}
938
e9e2cdb4
TG		 939#ifdef CONFIG_HPET_EMULATE_RTC
940
941/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
942 * is enabled, we support RTC interrupt functionality in software.
943 * RTC has 3 kinds of interrupts:
944 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
945 * is updated
946 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
947 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
948 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
949 * (1) and (2) above are implemented using polling at a frequency of
950 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
951 * overhead. (DEFAULT_RTC_INT_FREQ)
952 * For (3), we use interrupts at 64Hz or user specified periodic
953 * frequency, whichever is higher.
954 */
955#include <linux/mc146818rtc.h>
956#include <linux/rtc.h>
1bdbdaac 957#include <asm/rtc.h>
e9e2cdb4
TG		 958
959#define DEFAULT_RTC_INT_FREQ 64
960#define DEFAULT_RTC_SHIFT 6
961#define RTC_NUM_INTS 1
962
963static unsigned long hpet_rtc_flags;
7e2a31da 964static int hpet_prev_update_sec;
e9e2cdb4
TG		 965static struct rtc_time hpet_alarm_time;
966static unsigned long hpet_pie_count;
ff08f76d 967static u32 hpet_t1_cmp;
e9e2cdb4
TG		 968static unsigned long hpet_default_delta;
969static unsigned long hpet_pie_delta;
970static unsigned long hpet_pie_limit;
971
1bdbdaac
BW		 972static rtc_irq_handler irq_handler;
973
ff08f76d
PE		 974/*
975 * Check that the hpet counter c1 is ahead of the c2
976 */
977static inline int hpet_cnt_ahead(u32 c1, u32 c2)
978{
979 return (s32)(c2 - c1) < 0;
980}
981
1bdbdaac
BW		 982/*
983 * Registers a IRQ handler.
984 */
985int hpet_register_irq_handler(rtc_irq_handler handler)
986{
987 if (!is_hpet_enabled())
988 return -ENODEV;
989 if (irq_handler)
990 return -EBUSY;
991
992 irq_handler = handler;
993
994 return 0;
995}
996EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
997
998/*
999 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1000 * and does cleanup.
1001 */
1002void hpet_unregister_irq_handler(rtc_irq_handler handler)
1003{
1004 if (!is_hpet_enabled())
1005 return;
1006
1007 irq_handler = NULL;
1008 hpet_rtc_flags = 0;
1009}
1010EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1011
e9e2cdb4
TG		 1012/*
1013 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1014 * is not supported by all HPET implementations for timer 1.
1015 *
1016 * hpet_rtc_timer_init() is called when the rtc is initialized.
1017 */
1018int hpet_rtc_timer_init(void)
1019{
1020 unsigned long cfg, cnt, delta, flags;
1021
1022 if (!is_hpet_enabled())
1023 return 0;
1024
1025 if (!hpet_default_delta) {
1026 uint64_t clc;
1027
1028 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1029 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1030 hpet_default_delta = (unsigned long) clc;
1031 }
1032
1033 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1034 delta = hpet_default_delta;
1035 else
1036 delta = hpet_pie_delta;
1037
1038 local_irq_save(flags);
1039
1040 cnt = delta + hpet_readl(HPET_COUNTER);
1041 hpet_writel(cnt, HPET_T1_CMP);
1042 hpet_t1_cmp = cnt;
1043
1044 cfg = hpet_readl(HPET_T1_CFG);
1045 cfg &= ~HPET_TN_PERIODIC;
1046 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1047 hpet_writel(cfg, HPET_T1_CFG);
1048
1049 local_irq_restore(flags);
1050
1051 return 1;
1052}
1bdbdaac 1053EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
e9e2cdb4
TG		 1054
1055/*
1056 * The functions below are called from rtc driver.
1057 * Return 0 if HPET is not being used.
1058 * Otherwise do the necessary changes and return 1.
1059 */
1060int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1061{
1062 if (!is_hpet_enabled())
1063 return 0;
1064
1065 hpet_rtc_flags &= ~bit_mask;
1066 return 1;
1067}
1bdbdaac 1068EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
e9e2cdb4
TG		 1069
1070int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1071{
1072 unsigned long oldbits = hpet_rtc_flags;
1073
1074 if (!is_hpet_enabled())
1075 return 0;
1076
1077 hpet_rtc_flags |= bit_mask;
1078
7e2a31da
DB		 1079 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1080 hpet_prev_update_sec = -1;
1081
e9e2cdb4
TG		 1082 if (!oldbits)
1083 hpet_rtc_timer_init();
1084
1085 return 1;
1086}
1bdbdaac 1087EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
e9e2cdb4
TG		 1088
1089int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1090 unsigned char sec)
1091{
1092 if (!is_hpet_enabled())
1093 return 0;
1094
1095 hpet_alarm_time.tm_hour = hrs;
1096 hpet_alarm_time.tm_min = min;
1097 hpet_alarm_time.tm_sec = sec;
1098
1099 return 1;
1100}
1bdbdaac 1101EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
e9e2cdb4
TG		 1102
1103int hpet_set_periodic_freq(unsigned long freq)
1104{
1105 uint64_t clc;
1106
1107 if (!is_hpet_enabled())
1108 return 0;
1109
1110 if (freq <= DEFAULT_RTC_INT_FREQ)
1111 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1112 else {
1113 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1114 do_div(clc, freq);
1115 clc >>= hpet_clockevent.shift;
1116 hpet_pie_delta = (unsigned long) clc;
1117 }
1118 return 1;
1119}
1bdbdaac 1120EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
e9e2cdb4
TG		 1121
1122int hpet_rtc_dropped_irq(void)
1123{
1124 return is_hpet_enabled();
1125}
1bdbdaac 1126EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
e9e2cdb4
TG		 1127
1128static void hpet_rtc_timer_reinit(void)
1129{
1130 unsigned long cfg, delta;
1131 int lost_ints = -1;
1132
1133 if (unlikely(!hpet_rtc_flags)) {
1134 cfg = hpet_readl(HPET_T1_CFG);
1135 cfg &= ~HPET_TN_ENABLE;
1136 hpet_writel(cfg, HPET_T1_CFG);
1137 return;
1138 }
1139
1140 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1141 delta = hpet_default_delta;
1142 else
1143 delta = hpet_pie_delta;
1144
1145 /*
1146 * Increment the comparator value until we are ahead of the
1147 * current count.
1148 */
1149 do {
1150 hpet_t1_cmp += delta;
1151 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1152 lost_ints++;
ff08f76d 1153 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
e9e2cdb4
TG		 1154
1155 if (lost_ints) {
1156 if (hpet_rtc_flags & RTC_PIE)
1157 hpet_pie_count += lost_ints;
1158 if (printk_ratelimit())
7e2a31da 1159 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
e9e2cdb4
TG		 1160 lost_ints);
1161 }
1162}
1163
1164irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1165{
1166 struct rtc_time curr_time;
1167 unsigned long rtc_int_flag = 0;
1168
1169 hpet_rtc_timer_reinit();
1bdbdaac 1170 memset(&curr_time, 0, sizeof(struct rtc_time));
e9e2cdb4
TG		 1171
1172 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1bdbdaac 1173 get_rtc_time(&curr_time);
e9e2cdb4
TG		 1174
1175 if (hpet_rtc_flags & RTC_UIE &&
1176 curr_time.tm_sec != hpet_prev_update_sec) {
7e2a31da
DB		 1177 if (hpet_prev_update_sec >= 0)
1178 rtc_int_flag = RTC_UF;
e9e2cdb4
TG		 1179 hpet_prev_update_sec = curr_time.tm_sec;
1180 }
1181
1182 if (hpet_rtc_flags & RTC_PIE &&
1183 ++hpet_pie_count >= hpet_pie_limit) {
1184 rtc_int_flag |= RTC_PF;
1185 hpet_pie_count = 0;
1186 }
1187
8ee291f8 1188 if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4
TG		 1189 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1190 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1191 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1192 rtc_int_flag |= RTC_AF;
1193
1194 if (rtc_int_flag) {
1195 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1bdbdaac
BW		 1196 if (irq_handler)
1197 irq_handler(rtc_int_flag, dev_id);
e9e2cdb4
TG		 1198 }
1199 return IRQ_HANDLED;
1200}
1bdbdaac 1201EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
e9e2cdb4 1202#endif
Linux 6.x block layer and io_uring tree(s)