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irq_remapping/amd: Enhance AMD IR driver to support hierarchical irqdomains
[linux-2.6-block.git] / arch / x86 / kernel / hpet.c
CommitLineData
5d0cf410 1#include <linux/clocksource.h>
e9e2cdb4 2#include <linux/clockchips.h>
4588c1f0 3#include <linux/interrupt.h>
69c60c88 4#include <linux/export.h>
28769149 5#include <linux/delay.h>
5d0cf410 6#include <linux/errno.h>
334955ef 7#include <linux/i8253.h>
5a0e3ad6 8#include <linux/slab.h>
5d0cf410 9#include <linux/hpet.h>
10#include <linux/init.h>
58ac1e76 11#include <linux/cpu.h>
4588c1f0
IM		 12#include <linux/pm.h>
13#include <linux/io.h>
bd8eb63f 14#include <linux/irqdomain.h>
5d0cf410 15
28769149 16#include <asm/fixmap.h>
4588c1f0 17#include <asm/hpet.h>
16f871bc 18#include <asm/time.h>
5d0cf410 19
4588c1f0 20#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410 21
b10db7f0
PM		 22/* FSEC = 10^-15
23 NSEC = 10^-9 */
4588c1f0 24#define FSEC_PER_NSEC 1000000L
5d0cf410 25
26afe5f2 26#define HPET_DEV_USED_BIT 2
27#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
28#define HPET_DEV_VALID 0x8
29#define HPET_DEV_FSB_CAP 0x1000
30#define HPET_DEV_PERI_CAP 0x2000
31
f1c18071
TG		 32#define HPET_MIN_CYCLES 128
33#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
34
e9e2cdb4
TG		 35/*
36 * HPET address is set in acpi/boot.c, when an ACPI entry exists
37 */
4588c1f0 38unsigned long hpet_address;
c8bc6f3c 39u8 hpet_blockid; /* OS timer block num */
73472a46
PV		 40u8 hpet_msi_disable;
41
e951e4af 42#ifdef CONFIG_PCI_MSI
3b71e9e3 43static unsigned long hpet_num_timers;
e951e4af 44#endif
4588c1f0 45static void __iomem *hpet_virt_address;
e9e2cdb4 46
58ac1e76 47struct hpet_dev {
4588c1f0
IM		 48 struct clock_event_device evt;
49 unsigned int num;
50 int cpu;
51 unsigned int irq;
52 unsigned int flags;
53 char name[10];
58ac1e76 54};
55
3f7787b3
FW		 56inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
57{
58 return container_of(evtdev, struct hpet_dev, evt);
59}
60
5946fa3d 61inline unsigned int hpet_readl(unsigned int a)
e9e2cdb4
TG		 62{
63 return readl(hpet_virt_address + a);
64}
65
5946fa3d 66static inline void hpet_writel(unsigned int d, unsigned int a)
e9e2cdb4
TG		 67{
68 writel(d, hpet_virt_address + a);
69}
70
28769149 71#ifdef CONFIG_X86_64
28769149 72#include <asm/pgtable.h>
2387ce57 73#endif
28769149 74
06a24dec
TG		 75static inline void hpet_set_mapping(void)
76{
77 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
78}
79
80static inline void hpet_clear_mapping(void)
81{
82 iounmap(hpet_virt_address);
83 hpet_virt_address = NULL;
84}
85
e9e2cdb4
TG		 86/*
87 * HPET command line enable / disable
88 */
f10f383d 89int boot_hpet_disable;
b17530bd 90int hpet_force_user;
b98103a5 91static int hpet_verbose;
e9e2cdb4 92
4588c1f0 93static int __init hpet_setup(char *str)
e9e2cdb4 94{
b2d6aba9
JB		 95 while (str) {
96 char *next = strchr(str, ',');
97
98 if (next)
99 *next++ = 0;
e9e2cdb4
TG		 100 if (!strncmp("disable", str, 7))
101 boot_hpet_disable = 1;
b17530bd
TG		 102 if (!strncmp("force", str, 5))
103 hpet_force_user = 1;
b98103a5
AH		 104 if (!strncmp("verbose", str, 7))
105 hpet_verbose = 1;
b2d6aba9 106 str = next;
e9e2cdb4
TG		 107 }
108 return 1;
109}
110__setup("hpet=", hpet_setup);
111
28769149
TG		 112static int __init disable_hpet(char *str)
113{
114 boot_hpet_disable = 1;
115 return 1;
116}
117__setup("nohpet", disable_hpet);
118
e9e2cdb4
TG		 119static inline int is_hpet_capable(void)
120{
4588c1f0 121 return !boot_hpet_disable && hpet_address;
e9e2cdb4
TG		 122}
123
124/*
125 * HPET timer interrupt enable / disable
126 */
127static int hpet_legacy_int_enabled;
128
129/**
130 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
131 */
132int is_hpet_enabled(void)
133{
134 return is_hpet_capable() && hpet_legacy_int_enabled;
135}
1bdbdaac 136EXPORT_SYMBOL_GPL(is_hpet_enabled);
e9e2cdb4 137
b98103a5
AH		 138static void _hpet_print_config(const char *function, int line)
139{
140 u32 i, timers, l, h;
141 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
142 l = hpet_readl(HPET_ID);
143 h = hpet_readl(HPET_PERIOD);
144 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
145 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
146 l = hpet_readl(HPET_CFG);
147 h = hpet_readl(HPET_STATUS);
148 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
149 l = hpet_readl(HPET_COUNTER);
150 h = hpet_readl(HPET_COUNTER+4);
151 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
152
153 for (i = 0; i < timers; i++) {
154 l = hpet_readl(HPET_Tn_CFG(i));
155 h = hpet_readl(HPET_Tn_CFG(i)+4);
156 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
157 i, l, h);
158 l = hpet_readl(HPET_Tn_CMP(i));
159 h = hpet_readl(HPET_Tn_CMP(i)+4);
160 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
161 i, l, h);
162 l = hpet_readl(HPET_Tn_ROUTE(i));
163 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
164 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
165 i, l, h);
166 }
167}
168
169#define hpet_print_config() \
170do { \
171 if (hpet_verbose) \
02f1f217 172 _hpet_print_config(__func__, __LINE__); \
b98103a5
AH		 173} while (0)
174
e9e2cdb4
TG		 175/*
176 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
177 * timer 0 and timer 1 in case of RTC emulation.
178 */
179#ifdef CONFIG_HPET
f0ed4e69 180
5f79f2f2 181static void hpet_reserve_msi_timers(struct hpet_data *hd);
f0ed4e69 182
5946fa3d 183static void hpet_reserve_platform_timers(unsigned int id)
e9e2cdb4
TG		 184{
185 struct hpet __iomem *hpet = hpet_virt_address;
37a47db8
BR		 186 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
187 unsigned int nrtimers, i;
e9e2cdb4
TG		 188 struct hpet_data hd;
189
190 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
191
4588c1f0
IM		 192 memset(&hd, 0, sizeof(hd));
193 hd.hd_phys_address = hpet_address;
194 hd.hd_address = hpet;
195 hd.hd_nirqs = nrtimers;
e9e2cdb4
TG		 196 hpet_reserve_timer(&hd, 0);
197
198#ifdef CONFIG_HPET_EMULATE_RTC
199 hpet_reserve_timer(&hd, 1);
200#endif
5761d64b 201
64a76f66
DB		 202 /*
203 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
204 * is wrong for i8259!) not the output IRQ. Many BIOS writers
205 * don't bother configuring *any* comparator interrupts.
206 */
e9e2cdb4
TG		 207 hd.hd_irq[0] = HPET_LEGACY_8254;
208 hd.hd_irq[1] = HPET_LEGACY_RTC;
209
fc3fbc45 210 for (i = 2; i < nrtimers; timer++, i++) {
4588c1f0
IM		 211 hd.hd_irq[i] = (readl(&timer->hpet_config) &
212 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
fc3fbc45 213 }
5761d64b 214
f0ed4e69 215 hpet_reserve_msi_timers(&hd);
26afe5f2 216
e9e2cdb4 217 hpet_alloc(&hd);
5761d64b 218
e9e2cdb4
TG		 219}
220#else
5946fa3d 221static void hpet_reserve_platform_timers(unsigned int id) { }
e9e2cdb4
TG		 222#endif
223
224/*
225 * Common hpet info
226 */
ab0e08f1 227static unsigned long hpet_freq;
e9e2cdb4 228
610bf2f1 229static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 230 struct clock_event_device *evt);
610bf2f1 231static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4
TG		 232 struct clock_event_device *evt);
233
234/*
235 * The hpet clock event device
236 */
237static struct clock_event_device hpet_clockevent = {
238 .name = "hpet",
239 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
610bf2f1
VP		 240 .set_mode = hpet_legacy_set_mode,
241 .set_next_event = hpet_legacy_next_event,
e9e2cdb4 242 .irq = 0,
59c69f2a 243 .rating = 50,
e9e2cdb4
TG		 244};
245
8d6f0c82 246static void hpet_stop_counter(void)
e9e2cdb4
TG		 247{
248 unsigned long cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 249 cfg &= ~HPET_CFG_ENABLE;
250 hpet_writel(cfg, HPET_CFG);
7a6f9cbb
AH		 251}
252
253static void hpet_reset_counter(void)
254{
e9e2cdb4
TG		 255 hpet_writel(0, HPET_COUNTER);
256 hpet_writel(0, HPET_COUNTER + 4);
8d6f0c82
AH		 257}
258
259static void hpet_start_counter(void)
260{
5946fa3d 261 unsigned int cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 262 cfg |= HPET_CFG_ENABLE;
263 hpet_writel(cfg, HPET_CFG);
264}
265
8d6f0c82
AH		 266static void hpet_restart_counter(void)
267{
268 hpet_stop_counter();
7a6f9cbb 269 hpet_reset_counter();
8d6f0c82
AH		 270 hpet_start_counter();
271}
272
59c69f2a
VP		 273static void hpet_resume_device(void)
274{
bfe0c1cc 275 force_hpet_resume();
59c69f2a
VP		 276}
277
17622339 278static void hpet_resume_counter(struct clocksource *cs)
59c69f2a
VP		 279{
280 hpet_resume_device();
8d6f0c82 281 hpet_restart_counter();
59c69f2a
VP		 282}
283
610bf2f1 284static void hpet_enable_legacy_int(void)
e9e2cdb4 285{
5946fa3d 286 unsigned int cfg = hpet_readl(HPET_CFG);
e9e2cdb4
TG		 287
288 cfg |= HPET_CFG_LEGACY;
289 hpet_writel(cfg, HPET_CFG);
290 hpet_legacy_int_enabled = 1;
291}
292
610bf2f1
VP		 293static void hpet_legacy_clockevent_register(void)
294{
610bf2f1
VP		 295 /* Start HPET legacy interrupts */
296 hpet_enable_legacy_int();
297
610bf2f1
VP		 298 /*
299 * Start hpet with the boot cpu mask and make it
300 * global after the IO_APIC has been initialized.
301 */
320ab2b0 302 hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
ab0e08f1
TG		 303 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
304 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
610bf2f1
VP		 305 global_clock_event = &hpet_clockevent;
306 printk(KERN_DEBUG "hpet clockevent registered\n");
307}
308
26afe5f2 309static int hpet_setup_msi_irq(unsigned int irq);
310
b40d575b 311static void hpet_set_mode(enum clock_event_mode mode,
312 struct clock_event_device *evt, int timer)
e9e2cdb4 313{
5946fa3d 314 unsigned int cfg, cmp, now;
e9e2cdb4
TG		 315 uint64_t delta;
316
4588c1f0 317 switch (mode) {
e9e2cdb4 318 case CLOCK_EVT_MODE_PERIODIC:
c23e253e 319 hpet_stop_counter();
b40d575b 320 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
321 delta >>= evt->shift;
7a6f9cbb 322 now = hpet_readl(HPET_COUNTER);
5946fa3d 323 cmp = now + (unsigned int) delta;
b40d575b 324 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 325 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
326 HPET_TN_SETVAL | HPET_TN_32BIT;
b40d575b 327 hpet_writel(cfg, HPET_Tn_CFG(timer));
7a6f9cbb
AH		 328 hpet_writel(cmp, HPET_Tn_CMP(timer));
329 udelay(1);
330 /*
331 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
332 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
333 * bit is automatically cleared after the first write.
334 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
335 * Publication # 24674)
336 */
5946fa3d 337 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
c23e253e 338 hpet_start_counter();
b98103a5 339 hpet_print_config();
e9e2cdb4
TG		 340 break;
341
342 case CLOCK_EVT_MODE_ONESHOT:
b40d575b 343 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4
TG		 344 cfg &= ~HPET_TN_PERIODIC;
345 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
b40d575b 346 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4
TG		 347 break;
348
349 case CLOCK_EVT_MODE_UNUSED:
350 case CLOCK_EVT_MODE_SHUTDOWN:
b40d575b 351 cfg = hpet_readl(HPET_Tn_CFG(timer));
e9e2cdb4 352 cfg &= ~HPET_TN_ENABLE;
b40d575b 353 hpet_writel(cfg, HPET_Tn_CFG(timer));
e9e2cdb4 354 break;
18de5bc4
TG		 355
356 case CLOCK_EVT_MODE_RESUME:
26afe5f2 357 if (timer == 0) {
358 hpet_enable_legacy_int();
359 } else {
360 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
361 hpet_setup_msi_irq(hdev->irq);
362 disable_irq(hdev->irq);
0de26520 363 irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
26afe5f2 364 enable_irq(hdev->irq);
365 }
b98103a5 366 hpet_print_config();
18de5bc4 367 break;
e9e2cdb4
TG		 368 }
369}
370
b40d575b 371static int hpet_next_event(unsigned long delta,
372 struct clock_event_device *evt, int timer)
e9e2cdb4 373{
f7676254 374 u32 cnt;
995bd3bb 375 s32 res;
e9e2cdb4
TG		 376
377 cnt = hpet_readl(HPET_COUNTER);
f7676254 378 cnt += (u32) delta;
b40d575b 379 hpet_writel(cnt, HPET_Tn_CMP(timer));
e9e2cdb4 380
72d43d9b 381 /*
995bd3bb
TG		 382 * HPETs are a complete disaster. The compare register is
383 * based on a equal comparison and neither provides a less
384 * than or equal functionality (which would require to take
385 * the wraparound into account) nor a simple count down event
386 * mode. Further the write to the comparator register is
387 * delayed internally up to two HPET clock cycles in certain
f1c18071
TG		 388 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
389 * longer delays. We worked around that by reading back the
390 * compare register, but that required another workaround for
391 * ICH9,10 chips where the first readout after write can
392 * return the old stale value. We already had a minimum
393 * programming delta of 5us enforced, but a NMI or SMI hitting
995bd3bb
TG		 394 * between the counter readout and the comparator write can
395 * move us behind that point easily. Now instead of reading
396 * the compare register back several times, we make the ETIME
397 * decision based on the following: Return ETIME if the
f1c18071 398 * counter value after the write is less than HPET_MIN_CYCLES
995bd3bb 399 * away from the event or if the counter is already ahead of
f1c18071
TG		 400 * the event. The minimum programming delta for the generic
401 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
72d43d9b 402 */
995bd3bb 403 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
72d43d9b 404
f1c18071 405 return res < HPET_MIN_CYCLES ? -ETIME : 0;
e9e2cdb4
TG		 406}
407
b40d575b 408static void hpet_legacy_set_mode(enum clock_event_mode mode,
409 struct clock_event_device *evt)
410{
411 hpet_set_mode(mode, evt, 0);
412}
413
414static int hpet_legacy_next_event(unsigned long delta,
415 struct clock_event_device *evt)
416{
417 return hpet_next_event(delta, evt, 0);
418}
419
58ac1e76 420/*
421 * HPET MSI Support
422 */
26afe5f2 423#ifdef CONFIG_PCI_MSI
5f79f2f2
VP		 424
425static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
426static struct hpet_dev *hpet_devs;
427
d0fbca8f 428void hpet_msi_unmask(struct irq_data *data)
58ac1e76 429{
d0fbca8f 430 struct hpet_dev *hdev = data->handler_data;
5946fa3d 431 unsigned int cfg;
58ac1e76 432
433 /* unmask it */
434 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
6acf5a8c 435 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
58ac1e76 436 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
437}
438
d0fbca8f 439void hpet_msi_mask(struct irq_data *data)
58ac1e76 440{
d0fbca8f 441 struct hpet_dev *hdev = data->handler_data;
5946fa3d 442 unsigned int cfg;
58ac1e76 443
444 /* mask it */
445 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
6acf5a8c 446 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
58ac1e76 447 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
448}
449
d0fbca8f 450void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
58ac1e76 451{
58ac1e76 452 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
453 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
454}
455
d0fbca8f 456void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
58ac1e76 457{
58ac1e76 458 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
459 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
460 msg->address_hi = 0;
461}
462
26afe5f2 463static void hpet_msi_set_mode(enum clock_event_mode mode,
464 struct clock_event_device *evt)
465{
466 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
467 hpet_set_mode(mode, evt, hdev->num);
468}
469
470static int hpet_msi_next_event(unsigned long delta,
471 struct clock_event_device *evt)
472{
473 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
474 return hpet_next_event(delta, evt, hdev->num);
475}
476
477static int hpet_setup_msi_irq(unsigned int irq)
478{
71054d88 479 if (x86_msi.setup_hpet_msi(irq, hpet_blockid)) {
bd8eb63f 480 irq_domain_free_irqs(irq, 1);
26afe5f2 481 return -EINVAL;
482 }
483 return 0;
484}
485
486static int hpet_assign_irq(struct hpet_dev *dev)
487{
bd8eb63f 488 int irq;
26afe5f2 489
bd8eb63f
JL		 490 irq = irq_domain_alloc_irqs(NULL, 1, NUMA_NO_NODE, NULL);
491 if (irq <= 0)
26afe5f2 492 return -EINVAL;
493
2c778651 494 irq_set_handler_data(irq, dev);
26afe5f2 495
496 if (hpet_setup_msi_irq(irq))
497 return -EINVAL;
498
499 dev->irq = irq;
500 return 0;
501}
502
503static irqreturn_t hpet_interrupt_handler(int irq, void *data)
504{
505 struct hpet_dev *dev = (struct hpet_dev *)data;
506 struct clock_event_device *hevt = &dev->evt;
507
508 if (!hevt->event_handler) {
509 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
510 dev->num);
511 return IRQ_HANDLED;
512 }
513
514 hevt->event_handler(hevt);
515 return IRQ_HANDLED;
516}
517
518static int hpet_setup_irq(struct hpet_dev *dev)
519{
520
521 if (request_irq(dev->irq, hpet_interrupt_handler,
d20d2efb 522 IRQF_TIMER | IRQF_NOBALANCING,
507fa3a3 523 dev->name, dev))
26afe5f2 524 return -1;
525
526 disable_irq(dev->irq);
0de26520 527 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
26afe5f2 528 enable_irq(dev->irq);
529
c81bba49
YL		 530 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
531 dev->name, dev->irq);
532
26afe5f2 533 return 0;
534}
535
536/* This should be called in specific @cpu */
537static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
538{
539 struct clock_event_device *evt = &hdev->evt;
26afe5f2 540
541 WARN_ON(cpu != smp_processor_id());
542 if (!(hdev->flags & HPET_DEV_VALID))
543 return;
544
545 if (hpet_setup_msi_irq(hdev->irq))
546 return;
547
548 hdev->cpu = cpu;
549 per_cpu(cpu_hpet_dev, cpu) = hdev;
550 evt->name = hdev->name;
551 hpet_setup_irq(hdev);
552 evt->irq = hdev->irq;
553
554 evt->rating = 110;
555 evt->features = CLOCK_EVT_FEAT_ONESHOT;
556 if (hdev->flags & HPET_DEV_PERI_CAP)
557 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
558
559 evt->set_mode = hpet_msi_set_mode;
560 evt->set_next_event = hpet_msi_next_event;
320ab2b0 561 evt->cpumask = cpumask_of(hdev->cpu);
ab0e08f1
TG		 562
563 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
564 0x7FFFFFFF);
26afe5f2 565}
566
567#ifdef CONFIG_HPET
568/* Reserve at least one timer for userspace (/dev/hpet) */
569#define RESERVE_TIMERS 1
570#else
571#define RESERVE_TIMERS 0
572#endif
5f79f2f2
VP		 573
574static void hpet_msi_capability_lookup(unsigned int start_timer)
26afe5f2 575{
576 unsigned int id;
577 unsigned int num_timers;
578 unsigned int num_timers_used = 0;
579 int i;
580
73472a46
PV		 581 if (hpet_msi_disable)
582 return;
583
39fe05e5
SL		 584 if (boot_cpu_has(X86_FEATURE_ARAT))
585 return;
26afe5f2 586 id = hpet_readl(HPET_ID);
587
588 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
589 num_timers++; /* Value read out starts from 0 */
b98103a5 590 hpet_print_config();
26afe5f2 591
592 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
593 if (!hpet_devs)
594 return;
595
596 hpet_num_timers = num_timers;
597
598 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
599 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
5946fa3d 600 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
26afe5f2 601
602 /* Only consider HPET timer with MSI support */
603 if (!(cfg & HPET_TN_FSB_CAP))
604 continue;
605
606 hdev->flags = 0;
607 if (cfg & HPET_TN_PERIODIC_CAP)
608 hdev->flags |= HPET_DEV_PERI_CAP;
609 hdev->num = i;
610
611 sprintf(hdev->name, "hpet%d", i);
612 if (hpet_assign_irq(hdev))
613 continue;
614
615 hdev->flags |= HPET_DEV_FSB_CAP;
616 hdev->flags |= HPET_DEV_VALID;
617 num_timers_used++;
618 if (num_timers_used == num_possible_cpus())
619 break;
620 }
621
622 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
623 num_timers, num_timers_used);
624}
625
5f79f2f2
VP		 626#ifdef CONFIG_HPET
627static void hpet_reserve_msi_timers(struct hpet_data *hd)
628{
629 int i;
630
631 if (!hpet_devs)
632 return;
633
634 for (i = 0; i < hpet_num_timers; i++) {
635 struct hpet_dev *hdev = &hpet_devs[i];
636
637 if (!(hdev->flags & HPET_DEV_VALID))
638 continue;
639
640 hd->hd_irq[hdev->num] = hdev->irq;
641 hpet_reserve_timer(hd, hdev->num);
642 }
643}
644#endif
645
26afe5f2 646static struct hpet_dev *hpet_get_unused_timer(void)
647{
648 int i;
649
650 if (!hpet_devs)
651 return NULL;
652
653 for (i = 0; i < hpet_num_timers; i++) {
654 struct hpet_dev *hdev = &hpet_devs[i];
655
656 if (!(hdev->flags & HPET_DEV_VALID))
657 continue;
658 if (test_and_set_bit(HPET_DEV_USED_BIT,
659 (unsigned long *)&hdev->flags))
660 continue;
661 return hdev;
662 }
663 return NULL;
664}
665
666struct hpet_work_struct {
667 struct delayed_work work;
668 struct completion complete;
669};
670
671static void hpet_work(struct work_struct *w)
672{
673 struct hpet_dev *hdev;
674 int cpu = smp_processor_id();
675 struct hpet_work_struct *hpet_work;
676
677 hpet_work = container_of(w, struct hpet_work_struct, work.work);
678
679 hdev = hpet_get_unused_timer();
680 if (hdev)
681 init_one_hpet_msi_clockevent(hdev, cpu);
682
683 complete(&hpet_work->complete);
684}
685
686static int hpet_cpuhp_notify(struct notifier_block *n,
687 unsigned long action, void *hcpu)
688{
689 unsigned long cpu = (unsigned long)hcpu;
690 struct hpet_work_struct work;
691 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
692
693 switch (action & 0xf) {
694 case CPU_ONLINE:
ca1cab37 695 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
26afe5f2 696 init_completion(&work.complete);
697 /* FIXME: add schedule_work_on() */
698 schedule_delayed_work_on(cpu, &work.work, 0);
699 wait_for_completion(&work.complete);
b712c8da 700 destroy_delayed_work_on_stack(&work.work);
26afe5f2 701 break;
702 case CPU_DEAD:
703 if (hdev) {
704 free_irq(hdev->irq, hdev);
705 hdev->flags &= ~HPET_DEV_USED;
706 per_cpu(cpu_hpet_dev, cpu) = NULL;
707 }
708 break;
709 }
710 return NOTIFY_OK;
711}
712#else
713
ba374c9b
SN		 714static int hpet_setup_msi_irq(unsigned int irq)
715{
716 return 0;
717}
5f79f2f2
VP		 718static void hpet_msi_capability_lookup(unsigned int start_timer)
719{
720 return;
721}
722
723#ifdef CONFIG_HPET
724static void hpet_reserve_msi_timers(struct hpet_data *hd)
26afe5f2 725{
726 return;
727}
5f79f2f2 728#endif
26afe5f2 729
730static int hpet_cpuhp_notify(struct notifier_block *n,
731 unsigned long action, void *hcpu)
732{
733 return NOTIFY_OK;
734}
735
736#endif
737
6bb74df4 738/*
739 * Clock source related code
740 */
8e19608e 741static cycle_t read_hpet(struct clocksource *cs)
6bb74df4 742{
743 return (cycle_t)hpet_readl(HPET_COUNTER);
744}
745
746static struct clocksource clocksource_hpet = {
747 .name = "hpet",
748 .rating = 250,
749 .read = read_hpet,
750 .mask = HPET_MASK,
6bb74df4 751 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
8d6f0c82 752 .resume = hpet_resume_counter,
98d0ac38 753 .archdata = { .vclock_mode = VCLOCK_HPET },
6bb74df4 754};
755
610bf2f1 756static int hpet_clocksource_register(void)
e9e2cdb4 757{
6fd592da 758 u64 start, now;
075bcd1f 759 cycle_t t1;
e9e2cdb4 760
e9e2cdb4 761 /* Start the counter */
8d6f0c82 762 hpet_restart_counter();
e9e2cdb4 763
075bcd1f 764 /* Verify whether hpet counter works */
8e19608e 765 t1 = hpet_readl(HPET_COUNTER);
075bcd1f
TG		 766 rdtscll(start);
767
768 /*
769 * We don't know the TSC frequency yet, but waiting for
770 * 200000 TSC cycles is safe:
771 * 4 GHz == 50us
772 * 1 GHz == 200us
773 */
774 do {
775 rep_nop();
776 rdtscll(now);
777 } while ((now - start) < 200000UL);
778
8e19608e 779 if (t1 == hpet_readl(HPET_COUNTER)) {
075bcd1f
TG		 780 printk(KERN_WARNING
781 "HPET counter not counting. HPET disabled\n");
610bf2f1 782 return -ENODEV;
075bcd1f
TG		 783 }
784
f12a15be 785 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
610bf2f1
VP		 786 return 0;
787}
788
396e2c6f
JB		 789static u32 *hpet_boot_cfg;
790
b02a7f22
PM		 791/**
792 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
610bf2f1
VP		 793 */
794int __init hpet_enable(void)
795{
396e2c6f 796 u32 hpet_period, cfg, id;
ab0e08f1 797 u64 freq;
396e2c6f 798 unsigned int i, last;
610bf2f1
VP		 799
800 if (!is_hpet_capable())
801 return 0;
802
803 hpet_set_mapping();
804
805 /*
806 * Read the period and check for a sane value:
807 */
808 hpet_period = hpet_readl(HPET_PERIOD);
a6825f1c
TG		 809
810 /*
811 * AMD SB700 based systems with spread spectrum enabled use a
812 * SMM based HPET emulation to provide proper frequency
813 * setting. The SMM code is initialized with the first HPET
814 * register access and takes some time to complete. During
815 * this time the config register reads 0xffffffff. We check
816 * for max. 1000 loops whether the config register reads a non
817 * 0xffffffff value to make sure that HPET is up and running
818 * before we go further. A counting loop is safe, as the HPET
819 * access takes thousands of CPU cycles. On non SB700 based
820 * machines this check is only done once and has no side
821 * effects.
822 */
823 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
824 if (i == 1000) {
825 printk(KERN_WARNING
826 "HPET config register value = 0xFFFFFFFF. "
827 "Disabling HPET\n");
828 goto out_nohpet;
829 }
830 }
831
610bf2f1
VP		 832 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
833 goto out_nohpet;
834
ab0e08f1
TG		 835 /*
836 * The period is a femto seconds value. Convert it to a
837 * frequency.
838 */
839 freq = FSEC_PER_SEC;
840 do_div(freq, hpet_period);
841 hpet_freq = freq;
842
610bf2f1
VP		 843 /*
844 * Read the HPET ID register to retrieve the IRQ routing
845 * information and the number of channels
846 */
847 id = hpet_readl(HPET_ID);
b98103a5 848 hpet_print_config();
610bf2f1 849
396e2c6f
JB		 850 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
851
610bf2f1
VP		 852#ifdef CONFIG_HPET_EMULATE_RTC
853 /*
854 * The legacy routing mode needs at least two channels, tick timer
855 * and the rtc emulation channel.
856 */
396e2c6f 857 if (!last)
610bf2f1
VP		 858 goto out_nohpet;
859#endif
860
396e2c6f
JB		 861 cfg = hpet_readl(HPET_CFG);
862 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
863 GFP_KERNEL);
864 if (hpet_boot_cfg)
865 *hpet_boot_cfg = cfg;
866 else
867 pr_warn("HPET initial state will not be saved\n");
868 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
1b38a3a1 869 hpet_writel(cfg, HPET_CFG);
396e2c6f
JB		 870 if (cfg)
871 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
872 cfg);
873
874 for (i = 0; i <= last; ++i) {
875 cfg = hpet_readl(HPET_Tn_CFG(i));
876 if (hpet_boot_cfg)
877 hpet_boot_cfg[i + 1] = cfg;
878 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
879 hpet_writel(cfg, HPET_Tn_CFG(i));
880 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
881 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
882 | HPET_TN_FSB | HPET_TN_FSB_CAP);
883 if (cfg)
884 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
885 cfg, i);
886 }
887 hpet_print_config();
888
610bf2f1
VP		 889 if (hpet_clocksource_register())
890 goto out_nohpet;
891
e9e2cdb4 892 if (id & HPET_ID_LEGSUP) {
610bf2f1 893 hpet_legacy_clockevent_register();
e9e2cdb4
TG		 894 return 1;
895 }
896 return 0;
5d0cf410 897
e9e2cdb4 898out_nohpet:
06a24dec 899 hpet_clear_mapping();
bacbe999 900 hpet_address = 0;
e9e2cdb4
TG		 901 return 0;
902}
903
28769149
TG		 904/*
905 * Needs to be late, as the reserve_timer code calls kalloc !
906 *
907 * Not a problem on i386 as hpet_enable is called from late_time_init,
908 * but on x86_64 it is necessary !
909 */
910static __init int hpet_late_init(void)
911{
26afe5f2 912 int cpu;
913
59c69f2a 914 if (boot_hpet_disable)
28769149
TG		 915 return -ENODEV;
916
59c69f2a
VP		 917 if (!hpet_address) {
918 if (!force_hpet_address)
919 return -ENODEV;
920
921 hpet_address = force_hpet_address;
922 hpet_enable();
59c69f2a
VP		 923 }
924
39c04b55
JF		 925 if (!hpet_virt_address)
926 return -ENODEV;
927
39fe05e5
SL		 928 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
929 hpet_msi_capability_lookup(2);
930 else
931 hpet_msi_capability_lookup(0);
932
28769149 933 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
b98103a5 934 hpet_print_config();
59c69f2a 935
73472a46
PV		 936 if (hpet_msi_disable)
937 return 0;
938
39fe05e5
SL		 939 if (boot_cpu_has(X86_FEATURE_ARAT))
940 return 0;
941
9014ad2a 942 cpu_notifier_register_begin();
26afe5f2 943 for_each_online_cpu(cpu) {
944 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
945 }
946
947 /* This notifier should be called after workqueue is ready */
9014ad2a
SB		 948 __hotcpu_notifier(hpet_cpuhp_notify, -20);
949 cpu_notifier_register_done();
26afe5f2 950
28769149
TG		 951 return 0;
952}
953fs_initcall(hpet_late_init);
954
c86c7fbc
OH		 955void hpet_disable(void)
956{
ff487808 957 if (is_hpet_capable() && hpet_virt_address) {
396e2c6f 958 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
c86c7fbc 959
396e2c6f
JB		 960 if (hpet_boot_cfg)
961 cfg = *hpet_boot_cfg;
962 else if (hpet_legacy_int_enabled) {
c86c7fbc
OH		 963 cfg &= ~HPET_CFG_LEGACY;
964 hpet_legacy_int_enabled = 0;
965 }
966 cfg &= ~HPET_CFG_ENABLE;
967 hpet_writel(cfg, HPET_CFG);
396e2c6f
JB		 968
969 if (!hpet_boot_cfg)
970 return;
971
972 id = hpet_readl(HPET_ID);
973 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
974
975 for (id = 0; id <= last; ++id)
976 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
977
978 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
979 hpet_writel(*hpet_boot_cfg, HPET_CFG);
c86c7fbc
OH		 980 }
981}
982
e9e2cdb4
TG		 983#ifdef CONFIG_HPET_EMULATE_RTC
984
985/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
986 * is enabled, we support RTC interrupt functionality in software.
987 * RTC has 3 kinds of interrupts:
988 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
989 * is updated
990 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
991 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
992 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
993 * (1) and (2) above are implemented using polling at a frequency of
994 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
995 * overhead. (DEFAULT_RTC_INT_FREQ)
996 * For (3), we use interrupts at 64Hz or user specified periodic
997 * frequency, whichever is higher.
998 */
999#include <linux/mc146818rtc.h>
1000#include <linux/rtc.h>
1bdbdaac 1001#include <asm/rtc.h>
e9e2cdb4
TG		 1002
1003#define DEFAULT_RTC_INT_FREQ 64
1004#define DEFAULT_RTC_SHIFT 6
1005#define RTC_NUM_INTS 1
1006
1007static unsigned long hpet_rtc_flags;
7e2a31da 1008static int hpet_prev_update_sec;
e9e2cdb4
TG		 1009static struct rtc_time hpet_alarm_time;
1010static unsigned long hpet_pie_count;
ff08f76d 1011static u32 hpet_t1_cmp;
5946fa3d
JB		 1012static u32 hpet_default_delta;
1013static u32 hpet_pie_delta;
e9e2cdb4
TG		 1014static unsigned long hpet_pie_limit;
1015
1bdbdaac
BW		 1016static rtc_irq_handler irq_handler;
1017
ff08f76d
PE		 1018/*
1019 * Check that the hpet counter c1 is ahead of the c2
1020 */
1021static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1022{
1023 return (s32)(c2 - c1) < 0;
1024}
1025
1bdbdaac
BW		 1026/*
1027 * Registers a IRQ handler.
1028 */
1029int hpet_register_irq_handler(rtc_irq_handler handler)
1030{
1031 if (!is_hpet_enabled())
1032 return -ENODEV;
1033 if (irq_handler)
1034 return -EBUSY;
1035
1036 irq_handler = handler;
1037
1038 return 0;
1039}
1040EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1041
1042/*
1043 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1044 * and does cleanup.
1045 */
1046void hpet_unregister_irq_handler(rtc_irq_handler handler)
1047{
1048 if (!is_hpet_enabled())
1049 return;
1050
1051 irq_handler = NULL;
1052 hpet_rtc_flags = 0;
1053}
1054EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1055
e9e2cdb4
TG		 1056/*
1057 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1058 * is not supported by all HPET implementations for timer 1.
1059 *
1060 * hpet_rtc_timer_init() is called when the rtc is initialized.
1061 */
1062int hpet_rtc_timer_init(void)
1063{
5946fa3d
JB		 1064 unsigned int cfg, cnt, delta;
1065 unsigned long flags;
e9e2cdb4
TG		 1066
1067 if (!is_hpet_enabled())
1068 return 0;
1069
1070 if (!hpet_default_delta) {
1071 uint64_t clc;
1072
1073 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1074 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
5946fa3d 1075 hpet_default_delta = clc;
e9e2cdb4
TG		 1076 }
1077
1078 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1079 delta = hpet_default_delta;
1080 else
1081 delta = hpet_pie_delta;
1082
1083 local_irq_save(flags);
1084
1085 cnt = delta + hpet_readl(HPET_COUNTER);
1086 hpet_writel(cnt, HPET_T1_CMP);
1087 hpet_t1_cmp = cnt;
1088
1089 cfg = hpet_readl(HPET_T1_CFG);
1090 cfg &= ~HPET_TN_PERIODIC;
1091 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1092 hpet_writel(cfg, HPET_T1_CFG);
1093
1094 local_irq_restore(flags);
1095
1096 return 1;
1097}
1bdbdaac 1098EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
e9e2cdb4 1099
2ded6e6a
ML		 1100static void hpet_disable_rtc_channel(void)
1101{
1102 unsigned long cfg;
1103 cfg = hpet_readl(HPET_T1_CFG);
1104 cfg &= ~HPET_TN_ENABLE;
1105 hpet_writel(cfg, HPET_T1_CFG);
1106}
1107
e9e2cdb4
TG		 1108/*
1109 * The functions below are called from rtc driver.
1110 * Return 0 if HPET is not being used.
1111 * Otherwise do the necessary changes and return 1.
1112 */
1113int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1114{
1115 if (!is_hpet_enabled())
1116 return 0;
1117
1118 hpet_rtc_flags &= ~bit_mask;
2ded6e6a
ML		 1119 if (unlikely(!hpet_rtc_flags))
1120 hpet_disable_rtc_channel();
1121
e9e2cdb4
TG		 1122 return 1;
1123}
1bdbdaac 1124EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
e9e2cdb4
TG		 1125
1126int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1127{
1128 unsigned long oldbits = hpet_rtc_flags;
1129
1130 if (!is_hpet_enabled())
1131 return 0;
1132
1133 hpet_rtc_flags |= bit_mask;
1134
7e2a31da
DB		 1135 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1136 hpet_prev_update_sec = -1;
1137
e9e2cdb4
TG		 1138 if (!oldbits)
1139 hpet_rtc_timer_init();
1140
1141 return 1;
1142}
1bdbdaac 1143EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
e9e2cdb4
TG		 1144
1145int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1146 unsigned char sec)
1147{
1148 if (!is_hpet_enabled())
1149 return 0;
1150
1151 hpet_alarm_time.tm_hour = hrs;
1152 hpet_alarm_time.tm_min = min;
1153 hpet_alarm_time.tm_sec = sec;
1154
1155 return 1;
1156}
1bdbdaac 1157EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
e9e2cdb4
TG		 1158
1159int hpet_set_periodic_freq(unsigned long freq)
1160{
1161 uint64_t clc;
1162
1163 if (!is_hpet_enabled())
1164 return 0;
1165
1166 if (freq <= DEFAULT_RTC_INT_FREQ)
1167 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1168 else {
1169 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1170 do_div(clc, freq);
1171 clc >>= hpet_clockevent.shift;
5946fa3d 1172 hpet_pie_delta = clc;
b4a5e8a1 1173 hpet_pie_limit = 0;
e9e2cdb4
TG		 1174 }
1175 return 1;
1176}
1bdbdaac 1177EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
e9e2cdb4
TG		 1178
1179int hpet_rtc_dropped_irq(void)
1180{
1181 return is_hpet_enabled();
1182}
1bdbdaac 1183EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
e9e2cdb4
TG		 1184
1185static void hpet_rtc_timer_reinit(void)
1186{
2ded6e6a 1187 unsigned int delta;
e9e2cdb4
TG		 1188 int lost_ints = -1;
1189
2ded6e6a
ML		 1190 if (unlikely(!hpet_rtc_flags))
1191 hpet_disable_rtc_channel();
e9e2cdb4
TG		 1192
1193 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1194 delta = hpet_default_delta;
1195 else
1196 delta = hpet_pie_delta;
1197
1198 /*
1199 * Increment the comparator value until we are ahead of the
1200 * current count.
1201 */
1202 do {
1203 hpet_t1_cmp += delta;
1204 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1205 lost_ints++;
ff08f76d 1206 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
e9e2cdb4
TG		 1207
1208 if (lost_ints) {
1209 if (hpet_rtc_flags & RTC_PIE)
1210 hpet_pie_count += lost_ints;
1211 if (printk_ratelimit())
7e2a31da 1212 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
e9e2cdb4
TG		 1213 lost_ints);
1214 }
1215}
1216
1217irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1218{
1219 struct rtc_time curr_time;
1220 unsigned long rtc_int_flag = 0;
1221
1222 hpet_rtc_timer_reinit();
1bdbdaac 1223 memset(&curr_time, 0, sizeof(struct rtc_time));
e9e2cdb4
TG		 1224
1225 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1bdbdaac 1226 get_rtc_time(&curr_time);
e9e2cdb4
TG		 1227
1228 if (hpet_rtc_flags & RTC_UIE &&
1229 curr_time.tm_sec != hpet_prev_update_sec) {
7e2a31da
DB		 1230 if (hpet_prev_update_sec >= 0)
1231 rtc_int_flag = RTC_UF;
e9e2cdb4
TG		 1232 hpet_prev_update_sec = curr_time.tm_sec;
1233 }
1234
1235 if (hpet_rtc_flags & RTC_PIE &&
1236 ++hpet_pie_count >= hpet_pie_limit) {
1237 rtc_int_flag |= RTC_PF;
1238 hpet_pie_count = 0;
1239 }
1240
8ee291f8 1241 if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4
TG		 1242 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1243 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1244 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1245 rtc_int_flag |= RTC_AF;
1246
1247 if (rtc_int_flag) {
1248 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1bdbdaac
BW		 1249 if (irq_handler)
1250 irq_handler(rtc_int_flag, dev_id);
e9e2cdb4
TG		 1251 }
1252 return IRQ_HANDLED;
1253}
1bdbdaac 1254EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
e9e2cdb4 1255#endif
Linux 6.x block layer and io_uring tree(s)