[linux-2.6-block.git] / arch / x86 / kernel / hpet.c

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/hpet.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/pm.h>
#include <linux/delay.h>

#include <asm/fixmap.h>
#include <asm/hpet.h>
#include <asm/i8253.h>
#include <asm/io.h>

#define HPET_MASK	CLOCKSOURCE_MASK(32)
#define HPET_SHIFT	22

/* FSEC = 10^-15 NSEC = 10^-9 */
#define FSEC_PER_NSEC	1000000

/*
 * HPET address is set in acpi/boot.c, when an ACPI entry exists
 */
unsigned long hpet_address;
static void __iomem *hpet_virt_address;

unsigned long hpet_readl(unsigned long a)
{
	return readl(hpet_virt_address + a);
}

static inline void hpet_writel(unsigned long d, unsigned long a)
{
	writel(d, hpet_virt_address + a);
}

#ifdef CONFIG_X86_64

#include <asm/pgtable.h>

static inline void hpet_set_mapping(void)
{
	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
}

static inline void hpet_clear_mapping(void)
{
	hpet_virt_address = NULL;
}

#else

static inline void hpet_set_mapping(void)
{
	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
}

static inline void hpet_clear_mapping(void)
{
	iounmap(hpet_virt_address);
	hpet_virt_address = NULL;
}
#endif

/*
 * HPET command line enable / disable
 */
static int boot_hpet_disable;

static int __init hpet_setup(char* str)
{
	if (str) {
		if (!strncmp("disable", str, 7))
			boot_hpet_disable = 1;
	}
	return 1;
}
__setup("hpet=", hpet_setup);

static int __init disable_hpet(char *str)
{
	boot_hpet_disable = 1;
	return 1;
}
__setup("nohpet", disable_hpet);

static inline int is_hpet_capable(void)
{
	return (!boot_hpet_disable && hpet_address);
}

/*
 * HPET timer interrupt enable / disable
 */
static int hpet_legacy_int_enabled;

/**
 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 */
int is_hpet_enabled(void)
{
	return is_hpet_capable() && hpet_legacy_int_enabled;
}

/*
 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 * timer 0 and timer 1 in case of RTC emulation.
 */
#ifdef CONFIG_HPET
static void hpet_reserve_platform_timers(unsigned long id)
{
	struct hpet __iomem *hpet = hpet_virt_address;
	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	unsigned int nrtimers, i;
	struct hpet_data hd;

	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;

	memset(&hd, 0, sizeof (hd));
	hd.hd_phys_address = hpet_address;
	hd.hd_address = hpet;
	hd.hd_nirqs = nrtimers;
	hd.hd_flags = HPET_DATA_PLATFORM;
	hpet_reserve_timer(&hd, 0);

#ifdef CONFIG_HPET_EMULATE_RTC
	hpet_reserve_timer(&hd, 1);
#endif

	hd.hd_irq[0] = HPET_LEGACY_8254;
	hd.hd_irq[1] = HPET_LEGACY_RTC;

	for (i = 2; i < nrtimers; timer++, i++)
		hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
			Tn_INT_ROUTE_CNF_SHIFT;

	hpet_alloc(&hd);

}
#else
static void hpet_reserve_platform_timers(unsigned long id) { }
#endif

/*
 * Common hpet info
 */
static unsigned long hpet_period;

static void hpet_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt);
static int hpet_next_event(unsigned long delta,
			   struct clock_event_device *evt);

/*
 * The hpet clock event device
 */
static struct clock_event_device hpet_clockevent = {
	.name		= "hpet",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= hpet_set_mode,
	.set_next_event = hpet_next_event,
	.shift		= 32,
	.irq		= 0,
};

static void hpet_start_counter(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg &= ~HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
	hpet_writel(0, HPET_COUNTER);
	hpet_writel(0, HPET_COUNTER + 4);
	cfg |= HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
}

static void hpet_enable_int(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg |= HPET_CFG_LEGACY;
	hpet_writel(cfg, HPET_CFG);
	hpet_legacy_int_enabled = 1;
}

static void hpet_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	unsigned long cfg, cmp, now;
	uint64_t delta;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
		delta >>= hpet_clockevent.shift;
		now = hpet_readl(HPET_COUNTER);
		cmp = now + (unsigned long) delta;
		cfg = hpet_readl(HPET_T0_CFG);
		cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
		       HPET_TN_SETVAL | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		/*
		 * The first write after writing TN_SETVAL to the
		 * config register sets the counter value, the second
		 * write sets the period.
		 */
		hpet_writel(cmp, HPET_T0_CMP);
		udelay(1);
		hpet_writel((unsigned long) delta, HPET_T0_CMP);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_PERIODIC;
		cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_RESUME:
		hpet_enable_int();
		break;
	}
}

static int hpet_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	unsigned long cnt;

	cnt = hpet_readl(HPET_COUNTER);
	cnt += delta;
	hpet_writel(cnt, HPET_T0_CMP);

	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
}

/*
 * Clock source related code
 */
static cycle_t read_hpet(void)
{
	return (cycle_t)hpet_readl(HPET_COUNTER);
}

#ifdef CONFIG_X86_64
static cycle_t __vsyscall_fn vread_hpet(void)
{
	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
}
#endif

static struct clocksource clocksource_hpet = {
	.name		= "hpet",
	.rating		= 250,
	.read		= read_hpet,
	.mask		= HPET_MASK,
	.shift		= HPET_SHIFT,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= hpet_start_counter,
#ifdef CONFIG_X86_64
	.vread		= vread_hpet,
#endif
};

/*
 * Try to setup the HPET timer
 */
int __init hpet_enable(void)
{
	unsigned long id;
	uint64_t hpet_freq;
	u64 tmp, start, now;
	cycle_t t1;

	if (!is_hpet_capable())
		return 0;

	hpet_set_mapping();

	/*
	 * Read the period and check for a sane value:
	 */
	hpet_period = hpet_readl(HPET_PERIOD);
	if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
		goto out_nohpet;

	/*
	 * The period is a femto seconds value. We need to calculate the
	 * scaled math multiplication factor for nanosecond to hpet tick
	 * conversion.
	 */
	hpet_freq = 1000000000000000ULL;
	do_div(hpet_freq, hpet_period);
	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
				      NSEC_PER_SEC, 32);
	/* Calculate the min / max delta */
	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
							   &hpet_clockevent);
	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
							   &hpet_clockevent);

	/*
	 * Read the HPET ID register to retrieve the IRQ routing
	 * information and the number of channels
	 */
	id = hpet_readl(HPET_ID);

#ifdef CONFIG_HPET_EMULATE_RTC
	/*
	 * The legacy routing mode needs at least two channels, tick timer
	 * and the rtc emulation channel.
	 */
	if (!(id & HPET_ID_NUMBER))
		goto out_nohpet;
#endif

	/* Start the counter */
	hpet_start_counter();

	/* Verify whether hpet counter works */
	t1 = read_hpet();
	rdtscll(start);

	/*
	 * We don't know the TSC frequency yet, but waiting for
	 * 200000 TSC cycles is safe:
	 * 4 GHz == 50us
	 * 1 GHz == 200us
	 */
	do {
		rep_nop();
		rdtscll(now);
	} while ((now - start) < 200000UL);

	if (t1 == read_hpet()) {
		printk(KERN_WARNING
		       "HPET counter not counting. HPET disabled\n");
		goto out_nohpet;
	}

	/* Initialize and register HPET clocksource
	 *
	 * hpet period is in femto seconds per cycle
	 * so we need to convert this to ns/cyc units
	 * aproximated by mult/2^shift
	 *
	 *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	 *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	 *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	 *  (fsec/cyc << shift)/1000000 = mult
	 *  (hpet_period << shift)/FSEC_PER_NSEC = mult
	 */
	tmp = (u64)hpet_period << HPET_SHIFT;
	do_div(tmp, FSEC_PER_NSEC);
	clocksource_hpet.mult = (u32)tmp;

	clocksource_register(&clocksource_hpet);

	if (id & HPET_ID_LEGSUP) {
		hpet_enable_int();
		/*
		 * Start hpet with the boot cpu mask and make it
		 * global after the IO_APIC has been initialized.
		 */
		hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
		clockevents_register_device(&hpet_clockevent);
		global_clock_event = &hpet_clockevent;
		return 1;
	}
	return 0;

out_nohpet:
	hpet_clear_mapping();
	boot_hpet_disable = 1;
	return 0;
}

/*
 * Needs to be late, as the reserve_timer code calls kalloc !
 *
 * Not a problem on i386 as hpet_enable is called from late_time_init,
 * but on x86_64 it is necessary !
 */
static __init int hpet_late_init(void)
{
	if (!is_hpet_capable())
		return -ENODEV;

	hpet_reserve_platform_timers(hpet_readl(HPET_ID));
	return 0;
}
fs_initcall(hpet_late_init);

#ifdef CONFIG_HPET_EMULATE_RTC

/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 * is enabled, we support RTC interrupt functionality in software.
 * RTC has 3 kinds of interrupts:
 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 *    is updated
 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 * (1) and (2) above are implemented using polling at a frequency of
 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 * overhead. (DEFAULT_RTC_INT_FREQ)
 * For (3), we use interrupts at 64Hz or user specified periodic
 * frequency, whichever is higher.
 */
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>

#define DEFAULT_RTC_INT_FREQ	64
#define DEFAULT_RTC_SHIFT	6
#define RTC_NUM_INTS		1

static unsigned long hpet_rtc_flags;
static unsigned long hpet_prev_update_sec;
static struct rtc_time hpet_alarm_time;
static unsigned long hpet_pie_count;
static unsigned long hpet_t1_cmp;
static unsigned long hpet_default_delta;
static unsigned long hpet_pie_delta;
static unsigned long hpet_pie_limit;

/*
 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 * is not supported by all HPET implementations for timer 1.
 *
 * hpet_rtc_timer_init() is called when the rtc is initialized.
 */
int hpet_rtc_timer_init(void)
{
	unsigned long cfg, cnt, delta, flags;

	if (!is_hpet_enabled())
		return 0;

	if (!hpet_default_delta) {
		uint64_t clc;

		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
		hpet_default_delta = (unsigned long) clc;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	local_irq_save(flags);

	cnt = delta + hpet_readl(HPET_COUNTER);
	hpet_writel(cnt, HPET_T1_CMP);
	hpet_t1_cmp = cnt;

	cfg = hpet_readl(HPET_T1_CFG);
	cfg &= ~HPET_TN_PERIODIC;
	cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
	hpet_writel(cfg, HPET_T1_CFG);

	local_irq_restore(flags);

	return 1;
}

/*
 * The functions below are called from rtc driver.
 * Return 0 if HPET is not being used.
 * Otherwise do the necessary changes and return 1.
 */
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags &= ~bit_mask;
	return 1;
}

int hpet_set_rtc_irq_bit(unsigned long bit_mask)
{
	unsigned long oldbits = hpet_rtc_flags;

	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags |= bit_mask;

	if (!oldbits)
		hpet_rtc_timer_init();

	return 1;
}

int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
			unsigned char sec)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_alarm_time.tm_hour = hrs;
	hpet_alarm_time.tm_min = min;
	hpet_alarm_time.tm_sec = sec;

	return 1;
}

int hpet_set_periodic_freq(unsigned long freq)
{
	uint64_t clc;

	if (!is_hpet_enabled())
		return 0;

	if (freq <= DEFAULT_RTC_INT_FREQ)
		hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
	else {
		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		do_div(clc, freq);
		clc >>= hpet_clockevent.shift;
		hpet_pie_delta = (unsigned long) clc;
	}
	return 1;
}

int hpet_rtc_dropped_irq(void)
{
	return is_hpet_enabled();
}

static void hpet_rtc_timer_reinit(void)
{
	unsigned long cfg, delta;
	int lost_ints = -1;

	if (unlikely(!hpet_rtc_flags)) {
		cfg = hpet_readl(HPET_T1_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T1_CFG);
		return;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	/*
	 * Increment the comparator value until we are ahead of the
	 * current count.
	 */
	do {
		hpet_t1_cmp += delta;
		hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
		lost_ints++;
	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);

	if (lost_ints) {
		if (hpet_rtc_flags & RTC_PIE)
			hpet_pie_count += lost_ints;
		if (printk_ratelimit())
			printk(KERN_WARNING "rtc: lost %d interrupts\n",
				lost_ints);
	}
}

irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
{
	struct rtc_time curr_time;
	unsigned long rtc_int_flag = 0;

	hpet_rtc_timer_reinit();

	if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
		rtc_get_rtc_time(&curr_time);

	if (hpet_rtc_flags & RTC_UIE &&
	    curr_time.tm_sec != hpet_prev_update_sec) {
		rtc_int_flag = RTC_UF;
		hpet_prev_update_sec = curr_time.tm_sec;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    ++hpet_pie_count >= hpet_pie_limit) {
		rtc_int_flag |= RTC_PF;
		hpet_pie_count = 0;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	    (curr_time.tm_min == hpet_alarm_time.tm_min) &&
	    (curr_time.tm_hour == hpet_alarm_time.tm_hour))
			rtc_int_flag |= RTC_AF;

	if (rtc_int_flag) {
		rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
		rtc_interrupt(rtc_int_flag, dev_id);
	}
	return IRQ_HANDLED;
}
#endif
Commit	Line	Data
5d0cf410	1	#include <linux/clocksource.h>
e9e2cdb4	2	#include <linux/clockchips.h>
28769149	3	#include <linux/delay.h>
5d0cf410	4	#include <linux/errno.h>
	5	#include <linux/hpet.h>
	6	#include <linux/init.h>
399afa4f ML	7	#include <linux/sysdev.h>
399afa4f ML	8	#include <linux/pm.h>
0655d7c3	9	#include <linux/delay.h>
5d0cf410	10
28769149	11	#include <asm/fixmap.h>
5d0cf410	12	#include <asm/hpet.h>
06a24dec	13	#include <asm/i8253.h>
5d0cf410	14	#include <asm/io.h>
5d0cf410	15
7f9f303a	16	#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410	17	#define HPET_SHIFT 22
	18
	19	/* FSEC = 10^-15 NSEC = 10^-9 */
	20	#define FSEC_PER_NSEC 1000000
	21
e9e2cdb4 TG	22	/*
	23	* HPET address is set in acpi/boot.c, when an ACPI entry exists
	24	*/
	25	unsigned long hpet_address;
06a24dec	26	static void __iomem *hpet_virt_address;
e9e2cdb4	27
31c435d7	28	unsigned long hpet_readl(unsigned long a)
e9e2cdb4 TG	29	{
	30	return readl(hpet_virt_address + a);
	31	}
	32
	33	static inline void hpet_writel(unsigned long d, unsigned long a)
	34	{
	35	writel(d, hpet_virt_address + a);
	36	}
	37
28769149 TG	38	#ifdef CONFIG_X86_64
	39
	40	#include <asm/pgtable.h>
	41
	42	static inline void hpet_set_mapping(void)
	43	{
	44	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	45	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	46	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
	47	}
	48
	49	static inline void hpet_clear_mapping(void)
	50	{
	51	hpet_virt_address = NULL;
	52	}
	53
	54	#else
	55
06a24dec TG	56	static inline void hpet_set_mapping(void)
	57	{
	58	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
	59	}
	60
	61	static inline void hpet_clear_mapping(void)
	62	{
	63	iounmap(hpet_virt_address);
	64	hpet_virt_address = NULL;
	65	}
28769149	66	#endif
06a24dec	67
e9e2cdb4 TG	68	/*
	69	* HPET command line enable / disable
	70	*/
	71	static int boot_hpet_disable;
	72
	73	static int __init hpet_setup(char* str)
	74	{
	75	if (str) {
	76	if (!strncmp("disable", str, 7))
	77	boot_hpet_disable = 1;
	78	}
	79	return 1;
	80	}
	81	__setup("hpet=", hpet_setup);
	82
28769149 TG	83	static int __init disable_hpet(char *str)
	84	{
	85	boot_hpet_disable = 1;
	86	return 1;
	87	}
	88	__setup("nohpet", disable_hpet);
	89
e9e2cdb4 TG	90	static inline int is_hpet_capable(void)
	91	{
	92	return (!boot_hpet_disable && hpet_address);
	93	}
	94
	95	/*
	96	* HPET timer interrupt enable / disable
	97	*/
	98	static int hpet_legacy_int_enabled;
	99
	100	/**
	101	* is_hpet_enabled - check whether the hpet timer interrupt is enabled
	102	*/
	103	int is_hpet_enabled(void)
	104	{
	105	return is_hpet_capable() && hpet_legacy_int_enabled;
	106	}
	107
	108	/*
	109	* When the hpet driver (/dev/hpet) is enabled, we need to reserve
	110	* timer 0 and timer 1 in case of RTC emulation.
	111	*/
	112	#ifdef CONFIG_HPET
	113	static void hpet_reserve_platform_timers(unsigned long id)
	114	{
	115	struct hpet __iomem *hpet = hpet_virt_address;
	116	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	117	unsigned int nrtimers, i;
	118	struct hpet_data hd;
	119
	120	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
	121
	122	memset(&hd, 0, sizeof (hd));
	123	hd.hd_phys_address = hpet_address;
06a24dec	124	hd.hd_address = hpet;
e9e2cdb4 TG	125	hd.hd_nirqs = nrtimers;
	126	hd.hd_flags = HPET_DATA_PLATFORM;
	127	hpet_reserve_timer(&hd, 0);
	128
	129	#ifdef CONFIG_HPET_EMULATE_RTC
	130	hpet_reserve_timer(&hd, 1);
	131	#endif
	132
	133	hd.hd_irq[0] = HPET_LEGACY_8254;
	134	hd.hd_irq[1] = HPET_LEGACY_RTC;
	135
	136	for (i = 2; i < nrtimers; timer++, i++)
	137	hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
	138	Tn_INT_ROUTE_CNF_SHIFT;
	139
	140	hpet_alloc(&hd);
	141
	142	}
	143	#else
	144	static void hpet_reserve_platform_timers(unsigned long id) { }
	145	#endif
	146
	147	/*
	148	* Common hpet info
	149	*/
	150	static unsigned long hpet_period;
	151
	152	static void hpet_set_mode(enum clock_event_mode mode,
	153	struct clock_event_device *evt);
	154	static int hpet_next_event(unsigned long delta,
	155	struct clock_event_device *evt);
	156
	157	/*
	158	* The hpet clock event device
	159	*/
	160	static struct clock_event_device hpet_clockevent = {
	161	.name = "hpet",
	162	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	163	.set_mode = hpet_set_mode,
	164	.set_next_event = hpet_next_event,
	165	.shift = 32,
	166	.irq = 0,
	167	};
	168
	169	static void hpet_start_counter(void)
	170	{
	171	unsigned long cfg = hpet_readl(HPET_CFG);
	172
	173	cfg &= ~HPET_CFG_ENABLE;
	174	hpet_writel(cfg, HPET_CFG);
	175	hpet_writel(0, HPET_COUNTER);
	176	hpet_writel(0, HPET_COUNTER + 4);
	177	cfg \|= HPET_CFG_ENABLE;
	178	hpet_writel(cfg, HPET_CFG);
	179	}
	180
	181	static void hpet_enable_int(void)
	182	{
	183	unsigned long cfg = hpet_readl(HPET_CFG);
	184
	185	cfg \|= HPET_CFG_LEGACY;
	186	hpet_writel(cfg, HPET_CFG);
	187	hpet_legacy_int_enabled = 1;
	188	}
189
190	static void hpet_set_mode(enum clock_event_mode mode,
191	struct clock_event_device *evt)
192	{
193	unsigned long cfg, cmp, now;
194	uint64_t delta;
195
196	switch(mode) {
197	case CLOCK_EVT_MODE_PERIODIC:
198	delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
199	delta >>= hpet_clockevent.shift;
200	now = hpet_readl(HPET_COUNTER);
201	cmp = now + (unsigned long) delta;
202	cfg = hpet_readl(HPET_T0_CFG);
203	cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
204	HPET_TN_SETVAL \| HPET_TN_32BIT;
205	hpet_writel(cfg, HPET_T0_CFG);
206	/*
207	* The first write after writing TN_SETVAL to the
208	* config register sets the counter value, the second
209	* write sets the period.
210	*/
211	hpet_writel(cmp, HPET_T0_CMP);
212	udelay(1);
213	hpet_writel((unsigned long) delta, HPET_T0_CMP);
214	break;
215
216	case CLOCK_EVT_MODE_ONESHOT:
217	cfg = hpet_readl(HPET_T0_CFG);
218	cfg &= ~HPET_TN_PERIODIC;
219	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
220	hpet_writel(cfg, HPET_T0_CFG);
221	break;
222
223	case CLOCK_EVT_MODE_UNUSED:
224	case CLOCK_EVT_MODE_SHUTDOWN:
225	cfg = hpet_readl(HPET_T0_CFG);
226	cfg &= ~HPET_TN_ENABLE;
227	hpet_writel(cfg, HPET_T0_CFG);
228	break;
18de5bc4 TG	229
	230	case CLOCK_EVT_MODE_RESUME:
	231	hpet_enable_int();
	232	break;
e9e2cdb4 TG	233	}
	234	}
	235
	236	static int hpet_next_event(unsigned long delta,
	237	struct clock_event_device *evt)
	238	{
	239	unsigned long cnt;
	240
	241	cnt = hpet_readl(HPET_COUNTER);
	242	cnt += delta;
	243	hpet_writel(cnt, HPET_T0_CMP);
	244
c7f6d15f	245	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
e9e2cdb4 TG	246	}
e9e2cdb4 TG	247
6bb74df4	248	/*
	249	* Clock source related code
	250	*/
	251	static cycle_t read_hpet(void)
	252	{
	253	return (cycle_t)hpet_readl(HPET_COUNTER);
	254	}
	255
28769149 TG	256	#ifdef CONFIG_X86_64
	257	static cycle_t __vsyscall_fn vread_hpet(void)
	258	{
	259	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
	260	}
	261	#endif
	262
6bb74df4	263	static struct clocksource clocksource_hpet = {
	264	.name = "hpet",
	265	.rating = 250,
	266	.read = read_hpet,
	267	.mask = HPET_MASK,
	268	.shift = HPET_SHIFT,
	269	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
18de5bc4	270	.resume = hpet_start_counter,
28769149 TG	271	#ifdef CONFIG_X86_64
	272	.vread = vread_hpet,
	273	#endif
6bb74df4	274	};
6bb74df4	275
e9e2cdb4 TG	276	/*
	277	* Try to setup the HPET timer
	278	*/
	279	int __init hpet_enable(void)
	280	{
	281	unsigned long id;
	282	uint64_t hpet_freq;
075bcd1f TG	283	u64 tmp, start, now;
075bcd1f TG	284	cycle_t t1;
e9e2cdb4 TG	285
	286	if (!is_hpet_capable())
	287	return 0;
	288
06a24dec	289	hpet_set_mapping();
e9e2cdb4 TG	290
	291	/*
	292	* Read the period and check for a sane value:
	293	*/
	294	hpet_period = hpet_readl(HPET_PERIOD);
	295	if (hpet_period < HPET_MIN_PERIOD \|\| hpet_period > HPET_MAX_PERIOD)
	296	goto out_nohpet;
	297
	298	/*
	299	* The period is a femto seconds value. We need to calculate the
	300	* scaled math multiplication factor for nanosecond to hpet tick
	301	* conversion.
	302	*/
	303	hpet_freq = 1000000000000000ULL;
	304	do_div(hpet_freq, hpet_period);
	305	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
	306	NSEC_PER_SEC, 32);
	307	/* Calculate the min / max delta */
	308	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
	309	&hpet_clockevent);
	310	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
	311	&hpet_clockevent);
	312
	313	/*
	314	* Read the HPET ID register to retrieve the IRQ routing
	315	* information and the number of channels
	316	*/
	317	id = hpet_readl(HPET_ID);
	318
	319	#ifdef CONFIG_HPET_EMULATE_RTC
	320	/*
	321	* The legacy routing mode needs at least two channels, tick timer
	322	* and the rtc emulation channel.
	323	*/
	324	if (!(id & HPET_ID_NUMBER))
	325	goto out_nohpet;
	326	#endif
	327
	328	/* Start the counter */
	329	hpet_start_counter();
	330
075bcd1f TG	331	/* Verify whether hpet counter works */
	332	t1 = read_hpet();
	333	rdtscll(start);
	334
	335	/*
	336	* We don't know the TSC frequency yet, but waiting for
	337	* 200000 TSC cycles is safe:
	338	* 4 GHz == 50us
	339	* 1 GHz == 200us
	340	*/
	341	do {
	342	rep_nop();
	343	rdtscll(now);
	344	} while ((now - start) < 200000UL);
	345
	346	if (t1 == read_hpet()) {
	347	printk(KERN_WARNING
	348	"HPET counter not counting. HPET disabled\n");
	349	goto out_nohpet;
	350	}
	351
6bb74df4	352	/* Initialize and register HPET clocksource
	353	*
	354	* hpet period is in femto seconds per cycle
	355	* so we need to convert this to ns/cyc units
	356	* aproximated by mult/2^shift
	357	*
	358	* fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	359	* fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	360	* fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	361	* (fsec/cyc << shift)/1000000 = mult
	362	* (hpet_period << shift)/FSEC_PER_NSEC = mult
	363	*/
	364	tmp = (u64)hpet_period << HPET_SHIFT;
	365	do_div(tmp, FSEC_PER_NSEC);
	366	clocksource_hpet.mult = (u32)tmp;
	367
	368	clocksource_register(&clocksource_hpet);
	369
e9e2cdb4 TG	370	if (id & HPET_ID_LEGSUP) {
e9e2cdb4 TG	371	hpet_enable_int();
e9e2cdb4 TG	372	/*
	373	* Start hpet with the boot cpu mask and make it
	374	* global after the IO_APIC has been initialized.
	375	*/
43d6ca01	376	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
e9e2cdb4 TG	377	clockevents_register_device(&hpet_clockevent);
	378	global_clock_event = &hpet_clockevent;
	379	return 1;
	380	}
	381	return 0;
5d0cf410	382
e9e2cdb4	383	out_nohpet:
06a24dec	384	hpet_clear_mapping();
399afa4f	385	boot_hpet_disable = 1;
e9e2cdb4 TG	386	return 0;
	387	}
	388
28769149 TG	389	/*
	390	* Needs to be late, as the reserve_timer code calls kalloc !
	391	*
	392	* Not a problem on i386 as hpet_enable is called from late_time_init,
	393	* but on x86_64 it is necessary !
	394	*/
	395	static __init int hpet_late_init(void)
	396	{
	397	if (!is_hpet_capable())
	398	return -ENODEV;
	399
	400	hpet_reserve_platform_timers(hpet_readl(HPET_ID));
	401	return 0;
	402	}
	403	fs_initcall(hpet_late_init);
	404
e9e2cdb4 TG	405	#ifdef CONFIG_HPET_EMULATE_RTC
	406
	407	/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
	408	* is enabled, we support RTC interrupt functionality in software.
	409	* RTC has 3 kinds of interrupts:
	410	* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
	411	* is updated
	412	* 2) Alarm Interrupt - generate an interrupt at a specific time of day
	413	* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
	414	* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
	415	* (1) and (2) above are implemented using polling at a frequency of
	416	* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
	417	* overhead. (DEFAULT_RTC_INT_FREQ)
	418	* For (3), we use interrupts at 64Hz or user specified periodic
	419	* frequency, whichever is higher.
	420	*/
	421	#include <linux/mc146818rtc.h>
	422	#include <linux/rtc.h>
	423
	424	#define DEFAULT_RTC_INT_FREQ 64
	425	#define DEFAULT_RTC_SHIFT 6
	426	#define RTC_NUM_INTS 1
	427
	428	static unsigned long hpet_rtc_flags;
	429	static unsigned long hpet_prev_update_sec;
	430	static struct rtc_time hpet_alarm_time;
	431	static unsigned long hpet_pie_count;
	432	static unsigned long hpet_t1_cmp;
	433	static unsigned long hpet_default_delta;
	434	static unsigned long hpet_pie_delta;
	435	static unsigned long hpet_pie_limit;
	436
	437	/*
	438	* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
	439	* is not supported by all HPET implementations for timer 1.
	440	*
	441	* hpet_rtc_timer_init() is called when the rtc is initialized.
	442	*/
	443	int hpet_rtc_timer_init(void)
	444	{
	445	unsigned long cfg, cnt, delta, flags;
	446
	447	if (!is_hpet_enabled())
	448	return 0;
	449
	450	if (!hpet_default_delta) {
	451	uint64_t clc;
	452
	453	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
	454	clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
	455	hpet_default_delta = (unsigned long) clc;
	456	}
	457
	458	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
	459	delta = hpet_default_delta;
	460	else
	461	delta = hpet_pie_delta;
	462
	463	local_irq_save(flags);
	464
	465	cnt = delta + hpet_readl(HPET_COUNTER);
	466	hpet_writel(cnt, HPET_T1_CMP);
	467	hpet_t1_cmp = cnt;
	468
469	cfg = hpet_readl(HPET_T1_CFG);
470	cfg &= ~HPET_TN_PERIODIC;
471	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
472	hpet_writel(cfg, HPET_T1_CFG);
473
474	local_irq_restore(flags);
475
476	return 1;
477	}
478
479	/*
480	* The functions below are called from rtc driver.
481	* Return 0 if HPET is not being used.
482	* Otherwise do the necessary changes and return 1.
483	*/
484	int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
485	{
486	if (!is_hpet_enabled())
487	return 0;
488
489	hpet_rtc_flags &= ~bit_mask;
490	return 1;
491	}
492
493	int hpet_set_rtc_irq_bit(unsigned long bit_mask)
494	{
495	unsigned long oldbits = hpet_rtc_flags;
496
497	if (!is_hpet_enabled())
498	return 0;
499
500	hpet_rtc_flags \|= bit_mask;
501
502	if (!oldbits)
503	hpet_rtc_timer_init();
504
505	return 1;
506	}
507
508	int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
509	unsigned char sec)
510	{
511	if (!is_hpet_enabled())
512	return 0;
513
514	hpet_alarm_time.tm_hour = hrs;
515	hpet_alarm_time.tm_min = min;
516	hpet_alarm_time.tm_sec = sec;
517
518	return 1;
519	}
520
521	int hpet_set_periodic_freq(unsigned long freq)
522	{
523	uint64_t clc;
524
525	if (!is_hpet_enabled())
526	return 0;
527
528	if (freq <= DEFAULT_RTC_INT_FREQ)
529	hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
530	else {
531	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
532	do_div(clc, freq);
533	clc >>= hpet_clockevent.shift;
534	hpet_pie_delta = (unsigned long) clc;
535	}
536	return 1;
537	}
538
539	int hpet_rtc_dropped_irq(void)
540	{
541	return is_hpet_enabled();
542	}
543
544	static void hpet_rtc_timer_reinit(void)
545	{
546	unsigned long cfg, delta;
547	int lost_ints = -1;
548
549	if (unlikely(!hpet_rtc_flags)) {
550	cfg = hpet_readl(HPET_T1_CFG);
551	cfg &= ~HPET_TN_ENABLE;
552	hpet_writel(cfg, HPET_T1_CFG);
553	return;
554	}
555
556	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
557	delta = hpet_default_delta;
558	else
559	delta = hpet_pie_delta;
560
561	/*
562	* Increment the comparator value until we are ahead of the
563	* current count.
564	*/
565	do {
566	hpet_t1_cmp += delta;
567	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
568	lost_ints++;
569	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
570
571	if (lost_ints) {
572	if (hpet_rtc_flags & RTC_PIE)
573	hpet_pie_count += lost_ints;
574	if (printk_ratelimit())
575	printk(KERN_WARNING "rtc: lost %d interrupts\n",
576	lost_ints);
577	}
578	}
579
580	irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
581	{
582	struct rtc_time curr_time;
583	unsigned long rtc_int_flag = 0;
584
585	hpet_rtc_timer_reinit();
586
587	if (hpet_rtc_flags & (RTC_UIE \| RTC_AIE))
588	rtc_get_rtc_time(&curr_time);
589
590	if (hpet_rtc_flags & RTC_UIE &&
591	curr_time.tm_sec != hpet_prev_update_sec) {
592	rtc_int_flag = RTC_UF;
593	hpet_prev_update_sec = curr_time.tm_sec;
594	}
595
596	if (hpet_rtc_flags & RTC_PIE &&
597	++hpet_pie_count >= hpet_pie_limit) {
598	rtc_int_flag \|= RTC_PF;
599	hpet_pie_count = 0;
600	}
601
602	if (hpet_rtc_flags & RTC_PIE &&
603	(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
604	(curr_time.tm_min == hpet_alarm_time.tm_min) &&
605	(curr_time.tm_hour == hpet_alarm_time.tm_hour))
606	rtc_int_flag \|= RTC_AF;
607
608	if (rtc_int_flag) {
609	rtc_int_flag \|= (RTC_IRQF \| (RTC_NUM_INTS << 8));
610	rtc_interrupt(rtc_int_flag, dev_id);
611	}
612	return IRQ_HANDLED;
613	}
614	#endif