[linux-2.6-block.git] / arch / x86 / kernel / hpet.c

#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/hpet.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <linux/pm.h>

#include <asm/fixmap.h>
#include <asm/hpet.h>
#include <asm/i8253.h>
#include <asm/io.h>

#define HPET_MASK	CLOCKSOURCE_MASK(32)
#define HPET_SHIFT	22

/* FSEC = 10^-15
   NSEC = 10^-9 */
#define FSEC_PER_NSEC	1000000

/*
 * HPET address is set in acpi/boot.c, when an ACPI entry exists
 */
unsigned long hpet_address;
static void __iomem *hpet_virt_address;

unsigned long hpet_readl(unsigned long a)
{
	return readl(hpet_virt_address + a);
}

static inline void hpet_writel(unsigned long d, unsigned long a)
{
	writel(d, hpet_virt_address + a);
}

#ifdef CONFIG_X86_64

#include <asm/pgtable.h>

static inline void hpet_set_mapping(void)
{
	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
}

static inline void hpet_clear_mapping(void)
{
	hpet_virt_address = NULL;
}

#else

static inline void hpet_set_mapping(void)
{
	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
}

static inline void hpet_clear_mapping(void)
{
	iounmap(hpet_virt_address);
	hpet_virt_address = NULL;
}
#endif

/*
 * HPET command line enable / disable
 */
static int boot_hpet_disable;
int hpet_force_user;

static int __init hpet_setup(char* str)
{
	if (str) {
		if (!strncmp("disable", str, 7))
			boot_hpet_disable = 1;
		if (!strncmp("force", str, 5))
			hpet_force_user = 1;
	}
	return 1;
}
__setup("hpet=", hpet_setup);

static int __init disable_hpet(char *str)
{
	boot_hpet_disable = 1;
	return 1;
}
__setup("nohpet", disable_hpet);

static inline int is_hpet_capable(void)
{
	return (!boot_hpet_disable && hpet_address);
}

/*
 * HPET timer interrupt enable / disable
 */
static int hpet_legacy_int_enabled;

/**
 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 */
int is_hpet_enabled(void)
{
	return is_hpet_capable() && hpet_legacy_int_enabled;
}
EXPORT_SYMBOL_GPL(is_hpet_enabled);

/*
 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 * timer 0 and timer 1 in case of RTC emulation.
 */
#ifdef CONFIG_HPET
static void hpet_reserve_platform_timers(unsigned long id)
{
	struct hpet __iomem *hpet = hpet_virt_address;
	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
	unsigned int nrtimers, i;
	struct hpet_data hd;

	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;

	memset(&hd, 0, sizeof (hd));
	hd.hd_phys_address = hpet_address;
	hd.hd_address = hpet;
	hd.hd_nirqs = nrtimers;
	hd.hd_flags = HPET_DATA_PLATFORM;
	hpet_reserve_timer(&hd, 0);

#ifdef CONFIG_HPET_EMULATE_RTC
	hpet_reserve_timer(&hd, 1);
#endif

	hd.hd_irq[0] = HPET_LEGACY_8254;
	hd.hd_irq[1] = HPET_LEGACY_RTC;

	for (i = 2; i < nrtimers; timer++, i++) {
		hd.hd_irq[i] = (readl(&timer->hpet_config) & Tn_INT_ROUTE_CNF_MASK) >>
			Tn_INT_ROUTE_CNF_SHIFT;
	}

	hpet_alloc(&hd);

}
#else
static void hpet_reserve_platform_timers(unsigned long id) { }
#endif

/*
 * Common hpet info
 */
static unsigned long hpet_period;

static void hpet_legacy_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt);
static int hpet_legacy_next_event(unsigned long delta,
			   struct clock_event_device *evt);

/*
 * The hpet clock event device
 */
static struct clock_event_device hpet_clockevent = {
	.name		= "hpet",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= hpet_legacy_set_mode,
	.set_next_event = hpet_legacy_next_event,
	.shift		= 32,
	.irq		= 0,
	.rating		= 50,
};

static void hpet_start_counter(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg &= ~HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
	hpet_writel(0, HPET_COUNTER);
	hpet_writel(0, HPET_COUNTER + 4);
	cfg |= HPET_CFG_ENABLE;
	hpet_writel(cfg, HPET_CFG);
}

static void hpet_resume_device(void)
{
	force_hpet_resume();
}

static void hpet_restart_counter(void)
{
	hpet_resume_device();
	hpet_start_counter();
}

static void hpet_enable_legacy_int(void)
{
	unsigned long cfg = hpet_readl(HPET_CFG);

	cfg |= HPET_CFG_LEGACY;
	hpet_writel(cfg, HPET_CFG);
	hpet_legacy_int_enabled = 1;
}

static void hpet_legacy_clockevent_register(void)
{
	uint64_t hpet_freq;

	/* Start HPET legacy interrupts */
	hpet_enable_legacy_int();

	/*
	 * The period is a femto seconds value. We need to calculate the
	 * scaled math multiplication factor for nanosecond to hpet tick
	 * conversion.
	 */
	hpet_freq = 1000000000000000ULL;
	do_div(hpet_freq, hpet_period);
	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
				      NSEC_PER_SEC, hpet_clockevent.shift);
	/* Calculate the min / max delta */
	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
							   &hpet_clockevent);
	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
							   &hpet_clockevent);

	/*
	 * Start hpet with the boot cpu mask and make it
	 * global after the IO_APIC has been initialized.
	 */
	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
	clockevents_register_device(&hpet_clockevent);
	global_clock_event = &hpet_clockevent;
	printk(KERN_DEBUG "hpet clockevent registered\n");
}

static void hpet_legacy_set_mode(enum clock_event_mode mode,
			  struct clock_event_device *evt)
{
	unsigned long cfg, cmp, now;
	uint64_t delta;

	switch(mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
		delta >>= hpet_clockevent.shift;
		now = hpet_readl(HPET_COUNTER);
		cmp = now + (unsigned long) delta;
		cfg = hpet_readl(HPET_T0_CFG);
		cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
		       HPET_TN_SETVAL | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		/*
		 * The first write after writing TN_SETVAL to the
		 * config register sets the counter value, the second
		 * write sets the period.
		 */
		hpet_writel(cmp, HPET_T0_CMP);
		udelay(1);
		hpet_writel((unsigned long) delta, HPET_T0_CMP);
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_PERIODIC;
		cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		cfg = hpet_readl(HPET_T0_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T0_CFG);
		break;

	case CLOCK_EVT_MODE_RESUME:
		hpet_enable_legacy_int();
		break;
	}
}

static int hpet_legacy_next_event(unsigned long delta,
			   struct clock_event_device *evt)
{
	unsigned long cnt;

	cnt = hpet_readl(HPET_COUNTER);
	cnt += delta;
	hpet_writel(cnt, HPET_T0_CMP);

	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
}

/*
 * Clock source related code
 */
static cycle_t read_hpet(void)
{
	return (cycle_t)hpet_readl(HPET_COUNTER);
}

#ifdef CONFIG_X86_64
static cycle_t __vsyscall_fn vread_hpet(void)
{
	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
}
#endif

static struct clocksource clocksource_hpet = {
	.name		= "hpet",
	.rating		= 250,
	.read		= read_hpet,
	.mask		= HPET_MASK,
	.shift		= HPET_SHIFT,
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
	.resume		= hpet_restart_counter,
#ifdef CONFIG_X86_64
	.vread		= vread_hpet,
#endif
};

static int hpet_clocksource_register(void)
{
	u64 tmp, start, now;
	cycle_t t1;

	/* Start the counter */
	hpet_start_counter();

	/* Verify whether hpet counter works */
	t1 = read_hpet();
	rdtscll(start);

	/*
	 * We don't know the TSC frequency yet, but waiting for
	 * 200000 TSC cycles is safe:
	 * 4 GHz == 50us
	 * 1 GHz == 200us
	 */
	do {
		rep_nop();
		rdtscll(now);
	} while ((now - start) < 200000UL);

	if (t1 == read_hpet()) {
		printk(KERN_WARNING
		       "HPET counter not counting. HPET disabled\n");
		return -ENODEV;
	}

	/* Initialize and register HPET clocksource
	 *
	 * hpet period is in femto seconds per cycle
	 * so we need to convert this to ns/cyc units
	 * approximated by mult/2^shift
	 *
	 *  fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	 *  fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	 *  fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	 *  (fsec/cyc << shift)/1000000 = mult
	 *  (hpet_period << shift)/FSEC_PER_NSEC = mult
	 */
	tmp = (u64)hpet_period << HPET_SHIFT;
	do_div(tmp, FSEC_PER_NSEC);
	clocksource_hpet.mult = (u32)tmp;

	clocksource_register(&clocksource_hpet);

	return 0;
}

/**
 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 */
int __init hpet_enable(void)
{
	unsigned long id;

	if (!is_hpet_capable())
		return 0;

	hpet_set_mapping();

	/*
	 * Read the period and check for a sane value:
	 */
	hpet_period = hpet_readl(HPET_PERIOD);
	if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
		goto out_nohpet;

	/*
	 * Read the HPET ID register to retrieve the IRQ routing
	 * information and the number of channels
	 */
	id = hpet_readl(HPET_ID);

#ifdef CONFIG_HPET_EMULATE_RTC
	/*
	 * The legacy routing mode needs at least two channels, tick timer
	 * and the rtc emulation channel.
	 */
	if (!(id & HPET_ID_NUMBER))
		goto out_nohpet;
#endif

	if (hpet_clocksource_register())
		goto out_nohpet;

	if (id & HPET_ID_LEGSUP) {
		hpet_legacy_clockevent_register();
		return 1;
	}
	return 0;

out_nohpet:
	hpet_clear_mapping();
	boot_hpet_disable = 1;
	return 0;
}

/*
 * Needs to be late, as the reserve_timer code calls kalloc !
 *
 * Not a problem on i386 as hpet_enable is called from late_time_init,
 * but on x86_64 it is necessary !
 */
static __init int hpet_late_init(void)
{
	if (boot_hpet_disable)
		return -ENODEV;

	if (!hpet_address) {
		if (!force_hpet_address)
			return -ENODEV;

		hpet_address = force_hpet_address;
		hpet_enable();
		if (!hpet_virt_address)
			return -ENODEV;
	}

	hpet_reserve_platform_timers(hpet_readl(HPET_ID));

	return 0;
}
fs_initcall(hpet_late_init);

void hpet_disable(void)
{
	if (is_hpet_capable()) {
		unsigned long cfg = hpet_readl(HPET_CFG);

		if (hpet_legacy_int_enabled) {
			cfg &= ~HPET_CFG_LEGACY;
			hpet_legacy_int_enabled = 0;
		}
		cfg &= ~HPET_CFG_ENABLE;
		hpet_writel(cfg, HPET_CFG);
	}
}

#ifdef CONFIG_HPET_EMULATE_RTC

/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 * is enabled, we support RTC interrupt functionality in software.
 * RTC has 3 kinds of interrupts:
 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 *    is updated
 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 * (1) and (2) above are implemented using polling at a frequency of
 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 * overhead. (DEFAULT_RTC_INT_FREQ)
 * For (3), we use interrupts at 64Hz or user specified periodic
 * frequency, whichever is higher.
 */
#include <linux/mc146818rtc.h>
#include <linux/rtc.h>
#include <asm/rtc.h>

#define DEFAULT_RTC_INT_FREQ	64
#define DEFAULT_RTC_SHIFT	6
#define RTC_NUM_INTS		1

static unsigned long hpet_rtc_flags;
static unsigned long hpet_prev_update_sec;
static struct rtc_time hpet_alarm_time;
static unsigned long hpet_pie_count;
static unsigned long hpet_t1_cmp;
static unsigned long hpet_default_delta;
static unsigned long hpet_pie_delta;
static unsigned long hpet_pie_limit;

static rtc_irq_handler irq_handler;

/*
 * Registers a IRQ handler.
 */
int hpet_register_irq_handler(rtc_irq_handler handler)
{
	if (!is_hpet_enabled())
		return -ENODEV;
	if (irq_handler)
		return -EBUSY;

	irq_handler = handler;

	return 0;
}
EXPORT_SYMBOL_GPL(hpet_register_irq_handler);

/*
 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
 * and does cleanup.
 */
void hpet_unregister_irq_handler(rtc_irq_handler handler)
{
	if (!is_hpet_enabled())
		return;

	irq_handler = NULL;
	hpet_rtc_flags = 0;
}
EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);

/*
 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
 * is not supported by all HPET implementations for timer 1.
 *
 * hpet_rtc_timer_init() is called when the rtc is initialized.
 */
int hpet_rtc_timer_init(void)
{
	unsigned long cfg, cnt, delta, flags;

	if (!is_hpet_enabled())
		return 0;

	if (!hpet_default_delta) {
		uint64_t clc;

		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
		hpet_default_delta = (unsigned long) clc;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	local_irq_save(flags);

	cnt = delta + hpet_readl(HPET_COUNTER);
	hpet_writel(cnt, HPET_T1_CMP);
	hpet_t1_cmp = cnt;

	cfg = hpet_readl(HPET_T1_CFG);
	cfg &= ~HPET_TN_PERIODIC;
	cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
	hpet_writel(cfg, HPET_T1_CFG);

	local_irq_restore(flags);

	return 1;
}
EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);

/*
 * The functions below are called from rtc driver.
 * Return 0 if HPET is not being used.
 * Otherwise do the necessary changes and return 1.
 */
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags &= ~bit_mask;
	return 1;
}
EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);

int hpet_set_rtc_irq_bit(unsigned long bit_mask)
{
	unsigned long oldbits = hpet_rtc_flags;

	if (!is_hpet_enabled())
		return 0;

	hpet_rtc_flags |= bit_mask;

	if (!oldbits)
		hpet_rtc_timer_init();

	return 1;
}
EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);

int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
			unsigned char sec)
{
	if (!is_hpet_enabled())
		return 0;

	hpet_alarm_time.tm_hour = hrs;
	hpet_alarm_time.tm_min = min;
	hpet_alarm_time.tm_sec = sec;

	return 1;
}
EXPORT_SYMBOL_GPL(hpet_set_alarm_time);

int hpet_set_periodic_freq(unsigned long freq)
{
	uint64_t clc;

	if (!is_hpet_enabled())
		return 0;

	if (freq <= DEFAULT_RTC_INT_FREQ)
		hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
	else {
		clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
		do_div(clc, freq);
		clc >>= hpet_clockevent.shift;
		hpet_pie_delta = (unsigned long) clc;
	}
	return 1;
}
EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);

int hpet_rtc_dropped_irq(void)
{
	return is_hpet_enabled();
}
EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);

static void hpet_rtc_timer_reinit(void)
{
	unsigned long cfg, delta;
	int lost_ints = -1;

	if (unlikely(!hpet_rtc_flags)) {
		cfg = hpet_readl(HPET_T1_CFG);
		cfg &= ~HPET_TN_ENABLE;
		hpet_writel(cfg, HPET_T1_CFG);
		return;
	}

	if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
		delta = hpet_default_delta;
	else
		delta = hpet_pie_delta;

	/*
	 * Increment the comparator value until we are ahead of the
	 * current count.
	 */
	do {
		hpet_t1_cmp += delta;
		hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
		lost_ints++;
	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);

	if (lost_ints) {
		if (hpet_rtc_flags & RTC_PIE)
			hpet_pie_count += lost_ints;
		if (printk_ratelimit())
			printk(KERN_WARNING "rtc: lost %d interrupts\n",
				lost_ints);
	}
}

irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
{
	struct rtc_time curr_time;
	unsigned long rtc_int_flag = 0;

	hpet_rtc_timer_reinit();
	memset(&curr_time, 0, sizeof(struct rtc_time));

	if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
		get_rtc_time(&curr_time);

	if (hpet_rtc_flags & RTC_UIE &&
	    curr_time.tm_sec != hpet_prev_update_sec) {
		rtc_int_flag = RTC_UF;
		hpet_prev_update_sec = curr_time.tm_sec;
	}

	if (hpet_rtc_flags & RTC_PIE &&
	    ++hpet_pie_count >= hpet_pie_limit) {
		rtc_int_flag |= RTC_PF;
		hpet_pie_count = 0;
	}

	if (hpet_rtc_flags & RTC_AIE &&
	    (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	    (curr_time.tm_min == hpet_alarm_time.tm_min) &&
	    (curr_time.tm_hour == hpet_alarm_time.tm_hour))
			rtc_int_flag |= RTC_AF;

	if (rtc_int_flag) {
		rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
		if (irq_handler)
			irq_handler(rtc_int_flag, dev_id);
	}
	return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
#endif
Commit	Line	Data
5d0cf410	1	#include <linux/clocksource.h>
e9e2cdb4	2	#include <linux/clockchips.h>
28769149	3	#include <linux/delay.h>
5d0cf410	4	#include <linux/errno.h>
	5	#include <linux/hpet.h>
	6	#include <linux/init.h>
399afa4f ML	7	#include <linux/sysdev.h>
399afa4f ML	8	#include <linux/pm.h>
5d0cf410	9
28769149	10	#include <asm/fixmap.h>
5d0cf410	11	#include <asm/hpet.h>
06a24dec	12	#include <asm/i8253.h>
5d0cf410	13	#include <asm/io.h>
5d0cf410	14
7f9f303a	15	#define HPET_MASK CLOCKSOURCE_MASK(32)
5d0cf410	16	#define HPET_SHIFT 22
5d0cf410	17
b10db7f0 PM	18	/* FSEC = 10^-15
b10db7f0 PM	19	NSEC = 10^-9 */
5d0cf410	20	#define FSEC_PER_NSEC 1000000
5d0cf410	21
e9e2cdb4 TG	22	/*
	23	* HPET address is set in acpi/boot.c, when an ACPI entry exists
	24	*/
	25	unsigned long hpet_address;
06a24dec	26	static void __iomem *hpet_virt_address;
e9e2cdb4	27
31c435d7	28	unsigned long hpet_readl(unsigned long a)
e9e2cdb4 TG	29	{
	30	return readl(hpet_virt_address + a);
	31	}
	32
	33	static inline void hpet_writel(unsigned long d, unsigned long a)
	34	{
	35	writel(d, hpet_virt_address + a);
	36	}
	37
28769149 TG	38	#ifdef CONFIG_X86_64
	39
	40	#include <asm/pgtable.h>
	41
	42	static inline void hpet_set_mapping(void)
	43	{
	44	set_fixmap_nocache(FIX_HPET_BASE, hpet_address);
	45	__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
	46	hpet_virt_address = (void __iomem *)fix_to_virt(FIX_HPET_BASE);
	47	}
	48
	49	static inline void hpet_clear_mapping(void)
	50	{
	51	hpet_virt_address = NULL;
	52	}
	53
	54	#else
	55
06a24dec TG	56	static inline void hpet_set_mapping(void)
	57	{
	58	hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
	59	}
	60
	61	static inline void hpet_clear_mapping(void)
	62	{
	63	iounmap(hpet_virt_address);
	64	hpet_virt_address = NULL;
	65	}
28769149	66	#endif
06a24dec	67
e9e2cdb4 TG	68	/*
	69	* HPET command line enable / disable
	70	*/
	71	static int boot_hpet_disable;
b17530bd	72	int hpet_force_user;
e9e2cdb4 TG	73
	74	static int __init hpet_setup(char* str)
	75	{
	76	if (str) {
	77	if (!strncmp("disable", str, 7))
	78	boot_hpet_disable = 1;
b17530bd TG	79	if (!strncmp("force", str, 5))
b17530bd TG	80	hpet_force_user = 1;
e9e2cdb4 TG	81	}
	82	return 1;
	83	}
	84	__setup("hpet=", hpet_setup);
	85
28769149 TG	86	static int __init disable_hpet(char *str)
	87	{
	88	boot_hpet_disable = 1;
	89	return 1;
	90	}
	91	__setup("nohpet", disable_hpet);
	92
e9e2cdb4 TG	93	static inline int is_hpet_capable(void)
	94	{
	95	return (!boot_hpet_disable && hpet_address);
	96	}
	97
	98	/*
	99	* HPET timer interrupt enable / disable
	100	*/
	101	static int hpet_legacy_int_enabled;
	102
	103	/**
	104	* is_hpet_enabled - check whether the hpet timer interrupt is enabled
	105	*/
	106	int is_hpet_enabled(void)
	107	{
	108	return is_hpet_capable() && hpet_legacy_int_enabled;
	109	}
1bdbdaac	110	EXPORT_SYMBOL_GPL(is_hpet_enabled);
e9e2cdb4 TG	111
	112	/*
	113	* When the hpet driver (/dev/hpet) is enabled, we need to reserve
	114	* timer 0 and timer 1 in case of RTC emulation.
	115	*/
	116	#ifdef CONFIG_HPET
	117	static void hpet_reserve_platform_timers(unsigned long id)
	118	{
	119	struct hpet __iomem *hpet = hpet_virt_address;
37a47db8 BR	120	struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
37a47db8 BR	121	unsigned int nrtimers, i;
e9e2cdb4 TG	122	struct hpet_data hd;
	123
	124	nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
	125
	126	memset(&hd, 0, sizeof (hd));
	127	hd.hd_phys_address = hpet_address;
06a24dec	128	hd.hd_address = hpet;
e9e2cdb4 TG	129	hd.hd_nirqs = nrtimers;
	130	hd.hd_flags = HPET_DATA_PLATFORM;
	131	hpet_reserve_timer(&hd, 0);
	132
	133	#ifdef CONFIG_HPET_EMULATE_RTC
	134	hpet_reserve_timer(&hd, 1);
	135	#endif
5761d64b	136
e9e2cdb4 TG	137	hd.hd_irq[0] = HPET_LEGACY_8254;
	138	hd.hd_irq[1] = HPET_LEGACY_RTC;
	139
fc3fbc45 IM	140	for (i = 2; i < nrtimers; timer++, i++) {
fc3fbc45 IM	141	hd.hd_irq[i] = (readl(&timer->hpet_config) & Tn_INT_ROUTE_CNF_MASK) >>
5761d64b	142	Tn_INT_ROUTE_CNF_SHIFT;
fc3fbc45	143	}
5761d64b	144
e9e2cdb4	145	hpet_alloc(&hd);
5761d64b	146
e9e2cdb4 TG	147	}
	148	#else
	149	static void hpet_reserve_platform_timers(unsigned long id) { }
	150	#endif
	151
	152	/*
	153	* Common hpet info
	154	*/
	155	static unsigned long hpet_period;
	156
610bf2f1	157	static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4	158	struct clock_event_device *evt);
610bf2f1	159	static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4 TG	160	struct clock_event_device *evt);
	161
	162	/*
	163	* The hpet clock event device
	164	*/
	165	static struct clock_event_device hpet_clockevent = {
	166	.name = "hpet",
	167	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
610bf2f1 VP	168	.set_mode = hpet_legacy_set_mode,
610bf2f1 VP	169	.set_next_event = hpet_legacy_next_event,
e9e2cdb4 TG	170	.shift = 32,
e9e2cdb4 TG	171	.irq = 0,
59c69f2a	172	.rating = 50,
e9e2cdb4 TG	173	};
	174
	175	static void hpet_start_counter(void)
	176	{
	177	unsigned long cfg = hpet_readl(HPET_CFG);
	178
	179	cfg &= ~HPET_CFG_ENABLE;
	180	hpet_writel(cfg, HPET_CFG);
	181	hpet_writel(0, HPET_COUNTER);
	182	hpet_writel(0, HPET_COUNTER + 4);
	183	cfg \|= HPET_CFG_ENABLE;
	184	hpet_writel(cfg, HPET_CFG);
	185	}
	186
59c69f2a VP	187	static void hpet_resume_device(void)
59c69f2a VP	188	{
bfe0c1cc	189	force_hpet_resume();
59c69f2a VP	190	}
	191
	192	static void hpet_restart_counter(void)
	193	{
	194	hpet_resume_device();
	195	hpet_start_counter();
	196	}
	197
610bf2f1	198	static void hpet_enable_legacy_int(void)
e9e2cdb4 TG	199	{
	200	unsigned long cfg = hpet_readl(HPET_CFG);
	201
	202	cfg \|= HPET_CFG_LEGACY;
	203	hpet_writel(cfg, HPET_CFG);
	204	hpet_legacy_int_enabled = 1;
	205	}
	206
610bf2f1 VP	207	static void hpet_legacy_clockevent_register(void)
	208	{
	209	uint64_t hpet_freq;
	210
	211	/* Start HPET legacy interrupts */
	212	hpet_enable_legacy_int();
	213
	214	/*
	215	* The period is a femto seconds value. We need to calculate the
	216	* scaled math multiplication factor for nanosecond to hpet tick
	217	* conversion.
	218	*/
	219	hpet_freq = 1000000000000000ULL;
	220	do_div(hpet_freq, hpet_period);
	221	hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
877084fb	222	NSEC_PER_SEC, hpet_clockevent.shift);
610bf2f1 VP	223	/* Calculate the min / max delta */
	224	hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
	225	&hpet_clockevent);
	226	hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
	227	&hpet_clockevent);
	228
	229	/*
	230	* Start hpet with the boot cpu mask and make it
	231	* global after the IO_APIC has been initialized.
	232	*/
	233	hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
	234	clockevents_register_device(&hpet_clockevent);
	235	global_clock_event = &hpet_clockevent;
	236	printk(KERN_DEBUG "hpet clockevent registered\n");
	237	}
	238
	239	static void hpet_legacy_set_mode(enum clock_event_mode mode,
e9e2cdb4 TG	240	struct clock_event_device *evt)
	241	{
	242	unsigned long cfg, cmp, now;
	243	uint64_t delta;
	244
	245	switch(mode) {
	246	case CLOCK_EVT_MODE_PERIODIC:
	247	delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
	248	delta >>= hpet_clockevent.shift;
	249	now = hpet_readl(HPET_COUNTER);
	250	cmp = now + (unsigned long) delta;
	251	cfg = hpet_readl(HPET_T0_CFG);
	252	cfg \|= HPET_TN_ENABLE \| HPET_TN_PERIODIC \|
	253	HPET_TN_SETVAL \| HPET_TN_32BIT;
	254	hpet_writel(cfg, HPET_T0_CFG);
	255	/*
	256	* The first write after writing TN_SETVAL to the
	257	* config register sets the counter value, the second
	258	* write sets the period.
	259	*/
	260	hpet_writel(cmp, HPET_T0_CMP);
	261	udelay(1);
	262	hpet_writel((unsigned long) delta, HPET_T0_CMP);
	263	break;
	264
	265	case CLOCK_EVT_MODE_ONESHOT:
	266	cfg = hpet_readl(HPET_T0_CFG);
	267	cfg &= ~HPET_TN_PERIODIC;
	268	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
	269	hpet_writel(cfg, HPET_T0_CFG);
	270	break;
	271
	272	case CLOCK_EVT_MODE_UNUSED:
	273	case CLOCK_EVT_MODE_SHUTDOWN:
	274	cfg = hpet_readl(HPET_T0_CFG);
	275	cfg &= ~HPET_TN_ENABLE;
	276	hpet_writel(cfg, HPET_T0_CFG);
	277	break;
18de5bc4 TG	278
18de5bc4 TG	279	case CLOCK_EVT_MODE_RESUME:
610bf2f1	280	hpet_enable_legacy_int();
18de5bc4	281	break;
e9e2cdb4 TG	282	}
	283	}
	284
610bf2f1	285	static int hpet_legacy_next_event(unsigned long delta,
e9e2cdb4 TG	286	struct clock_event_device *evt)
	287	{
	288	unsigned long cnt;
	289
	290	cnt = hpet_readl(HPET_COUNTER);
	291	cnt += delta;
	292	hpet_writel(cnt, HPET_T0_CMP);
	293
c7f6d15f	294	return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
e9e2cdb4 TG	295	}
e9e2cdb4 TG	296
6bb74df4	297	/*
	298	* Clock source related code
	299	*/
	300	static cycle_t read_hpet(void)
	301	{
	302	return (cycle_t)hpet_readl(HPET_COUNTER);
	303	}
	304
28769149 TG	305	#ifdef CONFIG_X86_64
	306	static cycle_t __vsyscall_fn vread_hpet(void)
	307	{
	308	return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
	309	}
	310	#endif
	311
6bb74df4	312	static struct clocksource clocksource_hpet = {
	313	.name = "hpet",
	314	.rating = 250,
	315	.read = read_hpet,
	316	.mask = HPET_MASK,
	317	.shift = HPET_SHIFT,
	318	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
59c69f2a	319	.resume = hpet_restart_counter,
28769149 TG	320	#ifdef CONFIG_X86_64
	321	.vread = vread_hpet,
	322	#endif
6bb74df4	323	};
6bb74df4	324
610bf2f1	325	static int hpet_clocksource_register(void)
e9e2cdb4	326	{
075bcd1f TG	327	u64 tmp, start, now;
075bcd1f TG	328	cycle_t t1;
e9e2cdb4	329
e9e2cdb4 TG	330	/* Start the counter */
	331	hpet_start_counter();
	332
075bcd1f TG	333	/* Verify whether hpet counter works */
	334	t1 = read_hpet();
	335	rdtscll(start);
	336
	337	/*
	338	* We don't know the TSC frequency yet, but waiting for
	339	* 200000 TSC cycles is safe:
	340	* 4 GHz == 50us
	341	* 1 GHz == 200us
	342	*/
	343	do {
	344	rep_nop();
	345	rdtscll(now);
	346	} while ((now - start) < 200000UL);
	347
	348	if (t1 == read_hpet()) {
	349	printk(KERN_WARNING
	350	"HPET counter not counting. HPET disabled\n");
610bf2f1	351	return -ENODEV;
075bcd1f TG	352	}
075bcd1f TG	353
6bb74df4	354	/* Initialize and register HPET clocksource
	355	*
	356	* hpet period is in femto seconds per cycle
	357	* so we need to convert this to ns/cyc units
27b46d76	358	* approximated by mult/2^shift
6bb74df4	359	*
	360	* fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
	361	* fsec/cyc * 1ns/1000000fsec * 2^shift = mult
	362	* fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
	363	* (fsec/cyc << shift)/1000000 = mult
	364	* (hpet_period << shift)/FSEC_PER_NSEC = mult
	365	*/
	366	tmp = (u64)hpet_period << HPET_SHIFT;
	367	do_div(tmp, FSEC_PER_NSEC);
	368	clocksource_hpet.mult = (u32)tmp;
	369
	370	clocksource_register(&clocksource_hpet);
	371
610bf2f1 VP	372	return 0;
	373	}
	374
b02a7f22 PM	375	/**
b02a7f22 PM	376	* hpet_enable - Try to setup the HPET timer. Returns 1 on success.
610bf2f1 VP	377	*/
	378	int __init hpet_enable(void)
	379	{
	380	unsigned long id;
	381
	382	if (!is_hpet_capable())
	383	return 0;
	384
	385	hpet_set_mapping();
	386
	387	/*
	388	* Read the period and check for a sane value:
	389	*/
	390	hpet_period = hpet_readl(HPET_PERIOD);
	391	if (hpet_period < HPET_MIN_PERIOD \|\| hpet_period > HPET_MAX_PERIOD)
	392	goto out_nohpet;
	393
	394	/*
	395	* Read the HPET ID register to retrieve the IRQ routing
	396	* information and the number of channels
	397	*/
	398	id = hpet_readl(HPET_ID);
	399
	400	#ifdef CONFIG_HPET_EMULATE_RTC
	401	/*
	402	* The legacy routing mode needs at least two channels, tick timer
	403	* and the rtc emulation channel.
	404	*/
	405	if (!(id & HPET_ID_NUMBER))
	406	goto out_nohpet;
	407	#endif
	408
	409	if (hpet_clocksource_register())
	410	goto out_nohpet;
	411
e9e2cdb4	412	if (id & HPET_ID_LEGSUP) {
610bf2f1	413	hpet_legacy_clockevent_register();
e9e2cdb4 TG	414	return 1;
	415	}
	416	return 0;
5d0cf410	417
e9e2cdb4	418	out_nohpet:
06a24dec	419	hpet_clear_mapping();
399afa4f	420	boot_hpet_disable = 1;
e9e2cdb4 TG	421	return 0;
	422	}
	423
28769149 TG	424	/*
	425	* Needs to be late, as the reserve_timer code calls kalloc !
	426	*
	427	* Not a problem on i386 as hpet_enable is called from late_time_init,
	428	* but on x86_64 it is necessary !
	429	*/
	430	static __init int hpet_late_init(void)
	431	{
59c69f2a	432	if (boot_hpet_disable)
28769149 TG	433	return -ENODEV;
28769149 TG	434
59c69f2a VP	435	if (!hpet_address) {
	436	if (!force_hpet_address)
	437	return -ENODEV;
	438
	439	hpet_address = force_hpet_address;
	440	hpet_enable();
	441	if (!hpet_virt_address)
	442	return -ENODEV;
	443	}
	444
28769149	445	hpet_reserve_platform_timers(hpet_readl(HPET_ID));
59c69f2a	446
28769149 TG	447	return 0;
	448	}
	449	fs_initcall(hpet_late_init);
	450
c86c7fbc OH	451	void hpet_disable(void)
	452	{
	453	if (is_hpet_capable()) {
	454	unsigned long cfg = hpet_readl(HPET_CFG);
	455
	456	if (hpet_legacy_int_enabled) {
	457	cfg &= ~HPET_CFG_LEGACY;
	458	hpet_legacy_int_enabled = 0;
	459	}
	460	cfg &= ~HPET_CFG_ENABLE;
	461	hpet_writel(cfg, HPET_CFG);
	462	}
	463	}
	464
e9e2cdb4 TG	465	#ifdef CONFIG_HPET_EMULATE_RTC
	466
	467	/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
	468	* is enabled, we support RTC interrupt functionality in software.
	469	* RTC has 3 kinds of interrupts:
	470	* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
	471	* is updated
	472	* 2) Alarm Interrupt - generate an interrupt at a specific time of day
	473	* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
	474	* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
	475	* (1) and (2) above are implemented using polling at a frequency of
	476	* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
	477	* overhead. (DEFAULT_RTC_INT_FREQ)
	478	* For (3), we use interrupts at 64Hz or user specified periodic
	479	* frequency, whichever is higher.
	480	*/
	481	#include <linux/mc146818rtc.h>
	482	#include <linux/rtc.h>
1bdbdaac	483	#include <asm/rtc.h>
e9e2cdb4 TG	484
	485	#define DEFAULT_RTC_INT_FREQ 64
	486	#define DEFAULT_RTC_SHIFT 6
	487	#define RTC_NUM_INTS 1
	488
	489	static unsigned long hpet_rtc_flags;
	490	static unsigned long hpet_prev_update_sec;
	491	static struct rtc_time hpet_alarm_time;
	492	static unsigned long hpet_pie_count;
	493	static unsigned long hpet_t1_cmp;
	494	static unsigned long hpet_default_delta;
	495	static unsigned long hpet_pie_delta;
	496	static unsigned long hpet_pie_limit;
	497
1bdbdaac BW	498	static rtc_irq_handler irq_handler;
	499
	500	/*
	501	* Registers a IRQ handler.
	502	*/
	503	int hpet_register_irq_handler(rtc_irq_handler handler)
	504	{
	505	if (!is_hpet_enabled())
	506	return -ENODEV;
	507	if (irq_handler)
	508	return -EBUSY;
	509
	510	irq_handler = handler;
	511
	512	return 0;
	513	}
	514	EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
	515
	516	/*
	517	* Deregisters the IRQ handler registered with hpet_register_irq_handler()
	518	* and does cleanup.
	519	*/
	520	void hpet_unregister_irq_handler(rtc_irq_handler handler)
	521	{
	522	if (!is_hpet_enabled())
	523	return;
	524
	525	irq_handler = NULL;
	526	hpet_rtc_flags = 0;
	527	}
	528	EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
	529
e9e2cdb4 TG	530	/*
	531	* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
	532	* is not supported by all HPET implementations for timer 1.
	533	*
	534	* hpet_rtc_timer_init() is called when the rtc is initialized.
	535	*/
	536	int hpet_rtc_timer_init(void)
	537	{
	538	unsigned long cfg, cnt, delta, flags;
	539
	540	if (!is_hpet_enabled())
	541	return 0;
	542
	543	if (!hpet_default_delta) {
	544	uint64_t clc;
	545
	546	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
	547	clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
	548	hpet_default_delta = (unsigned long) clc;
	549	}
	550
	551	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
	552	delta = hpet_default_delta;
	553	else
	554	delta = hpet_pie_delta;
	555
	556	local_irq_save(flags);
	557
	558	cnt = delta + hpet_readl(HPET_COUNTER);
	559	hpet_writel(cnt, HPET_T1_CMP);
	560	hpet_t1_cmp = cnt;
	561
	562	cfg = hpet_readl(HPET_T1_CFG);
	563	cfg &= ~HPET_TN_PERIODIC;
	564	cfg \|= HPET_TN_ENABLE \| HPET_TN_32BIT;
	565	hpet_writel(cfg, HPET_T1_CFG);
	566
	567	local_irq_restore(flags);
	568
	569	return 1;
	570	}
1bdbdaac	571	EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
e9e2cdb4 TG	572
	573	/*
	574	* The functions below are called from rtc driver.
	575	* Return 0 if HPET is not being used.
	576	* Otherwise do the necessary changes and return 1.
	577	*/
	578	int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
	579	{
	580	if (!is_hpet_enabled())
	581	return 0;
	582
	583	hpet_rtc_flags &= ~bit_mask;
	584	return 1;
	585	}
1bdbdaac	586	EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
e9e2cdb4 TG	587
	588	int hpet_set_rtc_irq_bit(unsigned long bit_mask)
	589	{
	590	unsigned long oldbits = hpet_rtc_flags;
	591
	592	if (!is_hpet_enabled())
	593	return 0;
	594
	595	hpet_rtc_flags \|= bit_mask;
	596
	597	if (!oldbits)
	598	hpet_rtc_timer_init();
	599
	600	return 1;
	601	}
1bdbdaac	602	EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
e9e2cdb4 TG	603
	604	int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
	605	unsigned char sec)
	606	{
	607	if (!is_hpet_enabled())
	608	return 0;
	609
	610	hpet_alarm_time.tm_hour = hrs;
	611	hpet_alarm_time.tm_min = min;
	612	hpet_alarm_time.tm_sec = sec;
	613
	614	return 1;
	615	}
1bdbdaac	616	EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
e9e2cdb4 TG	617
	618	int hpet_set_periodic_freq(unsigned long freq)
	619	{
	620	uint64_t clc;
	621
	622	if (!is_hpet_enabled())
	623	return 0;
	624
	625	if (freq <= DEFAULT_RTC_INT_FREQ)
	626	hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
	627	else {
	628	clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
	629	do_div(clc, freq);
	630	clc >>= hpet_clockevent.shift;
	631	hpet_pie_delta = (unsigned long) clc;
	632	}
	633	return 1;
	634	}
1bdbdaac	635	EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
e9e2cdb4 TG	636
	637	int hpet_rtc_dropped_irq(void)
	638	{
	639	return is_hpet_enabled();
	640	}
1bdbdaac	641	EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
e9e2cdb4 TG	642
	643	static void hpet_rtc_timer_reinit(void)
	644	{
	645	unsigned long cfg, delta;
	646	int lost_ints = -1;
	647
	648	if (unlikely(!hpet_rtc_flags)) {
	649	cfg = hpet_readl(HPET_T1_CFG);
	650	cfg &= ~HPET_TN_ENABLE;
	651	hpet_writel(cfg, HPET_T1_CFG);
	652	return;
	653	}
	654
	655	if (!(hpet_rtc_flags & RTC_PIE) \|\| hpet_pie_limit)
	656	delta = hpet_default_delta;
	657	else
	658	delta = hpet_pie_delta;
	659
	660	/*
	661	* Increment the comparator value until we are ahead of the
	662	* current count.
	663	*/
	664	do {
	665	hpet_t1_cmp += delta;
	666	hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
	667	lost_ints++;
	668	} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
	669
	670	if (lost_ints) {
	671	if (hpet_rtc_flags & RTC_PIE)
	672	hpet_pie_count += lost_ints;
	673	if (printk_ratelimit())
	674	printk(KERN_WARNING "rtc: lost %d interrupts\n",
	675	lost_ints);
	676	}
	677	}
	678
	679	irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
	680	{
	681	struct rtc_time curr_time;
	682	unsigned long rtc_int_flag = 0;
	683
	684	hpet_rtc_timer_reinit();
1bdbdaac	685	memset(&curr_time, 0, sizeof(struct rtc_time));
e9e2cdb4 TG	686
e9e2cdb4 TG	687	if (hpet_rtc_flags & (RTC_UIE \| RTC_AIE))
1bdbdaac	688	get_rtc_time(&curr_time);
e9e2cdb4 TG	689
	690	if (hpet_rtc_flags & RTC_UIE &&
	691	curr_time.tm_sec != hpet_prev_update_sec) {
	692	rtc_int_flag = RTC_UF;
	693	hpet_prev_update_sec = curr_time.tm_sec;
	694	}
	695
	696	if (hpet_rtc_flags & RTC_PIE &&
	697	++hpet_pie_count >= hpet_pie_limit) {
	698	rtc_int_flag \|= RTC_PF;
	699	hpet_pie_count = 0;
	700	}
	701
8ee291f8	702	if (hpet_rtc_flags & RTC_AIE &&
e9e2cdb4 TG	703	(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
	704	(curr_time.tm_min == hpet_alarm_time.tm_min) &&
	705	(curr_time.tm_hour == hpet_alarm_time.tm_hour))
	706	rtc_int_flag \|= RTC_AF;
	707
	708	if (rtc_int_flag) {
	709	rtc_int_flag \|= (RTC_IRQF \| (RTC_NUM_INTS << 8));
1bdbdaac BW	710	if (irq_handler)
1bdbdaac BW	711	irq_handler(rtc_int_flag, dev_id);
e9e2cdb4 TG	712	}
	713	return IRQ_HANDLED;
	714	}
1bdbdaac	715	EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
e9e2cdb4	716	#endif