Commit | Line | Data |
---|---|---|
5d0cf410 | 1 | #include <linux/clocksource.h> |
e9e2cdb4 | 2 | #include <linux/clockchips.h> |
4588c1f0 IM |
3 | #include <linux/interrupt.h> |
4 | #include <linux/sysdev.h> | |
28769149 | 5 | #include <linux/delay.h> |
5d0cf410 | 6 | #include <linux/errno.h> |
7 | #include <linux/hpet.h> | |
8 | #include <linux/init.h> | |
58ac1e76 | 9 | #include <linux/cpu.h> |
4588c1f0 IM |
10 | #include <linux/pm.h> |
11 | #include <linux/io.h> | |
5d0cf410 | 12 | |
28769149 | 13 | #include <asm/fixmap.h> |
06a24dec | 14 | #include <asm/i8253.h> |
4588c1f0 | 15 | #include <asm/hpet.h> |
5d0cf410 | 16 | |
4588c1f0 IM |
17 | #define HPET_MASK CLOCKSOURCE_MASK(32) |
18 | #define HPET_SHIFT 22 | |
5d0cf410 | 19 | |
b10db7f0 PM |
20 | /* FSEC = 10^-15 |
21 | NSEC = 10^-9 */ | |
4588c1f0 | 22 | #define FSEC_PER_NSEC 1000000L |
5d0cf410 | 23 | |
26afe5f2 | 24 | #define HPET_DEV_USED_BIT 2 |
25 | #define HPET_DEV_USED (1 << HPET_DEV_USED_BIT) | |
26 | #define HPET_DEV_VALID 0x8 | |
27 | #define HPET_DEV_FSB_CAP 0x1000 | |
28 | #define HPET_DEV_PERI_CAP 0x2000 | |
29 | ||
30 | #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt) | |
31 | ||
e9e2cdb4 TG |
32 | /* |
33 | * HPET address is set in acpi/boot.c, when an ACPI entry exists | |
34 | */ | |
4588c1f0 | 35 | unsigned long hpet_address; |
26afe5f2 | 36 | unsigned long hpet_num_timers; |
4588c1f0 | 37 | static void __iomem *hpet_virt_address; |
e9e2cdb4 | 38 | |
58ac1e76 | 39 | struct hpet_dev { |
4588c1f0 IM |
40 | struct clock_event_device evt; |
41 | unsigned int num; | |
42 | int cpu; | |
43 | unsigned int irq; | |
44 | unsigned int flags; | |
45 | char name[10]; | |
58ac1e76 | 46 | }; |
47 | ||
26afe5f2 | 48 | static struct hpet_dev *hpet_devs; |
49 | ||
50 | static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev); | |
51 | ||
31c435d7 | 52 | unsigned long hpet_readl(unsigned long a) |
e9e2cdb4 TG |
53 | { |
54 | return readl(hpet_virt_address + a); | |
55 | } | |
56 | ||
57 | static inline void hpet_writel(unsigned long d, unsigned long a) | |
58 | { | |
59 | writel(d, hpet_virt_address + a); | |
60 | } | |
61 | ||
28769149 | 62 | #ifdef CONFIG_X86_64 |
28769149 | 63 | #include <asm/pgtable.h> |
2387ce57 | 64 | #endif |
28769149 | 65 | |
06a24dec TG |
66 | static inline void hpet_set_mapping(void) |
67 | { | |
68 | hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE); | |
2387ce57 YL |
69 | #ifdef CONFIG_X86_64 |
70 | __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE); | |
71 | #endif | |
06a24dec TG |
72 | } |
73 | ||
74 | static inline void hpet_clear_mapping(void) | |
75 | { | |
76 | iounmap(hpet_virt_address); | |
77 | hpet_virt_address = NULL; | |
78 | } | |
79 | ||
e9e2cdb4 TG |
80 | /* |
81 | * HPET command line enable / disable | |
82 | */ | |
83 | static int boot_hpet_disable; | |
b17530bd | 84 | int hpet_force_user; |
e9e2cdb4 | 85 | |
4588c1f0 | 86 | static int __init hpet_setup(char *str) |
e9e2cdb4 TG |
87 | { |
88 | if (str) { | |
89 | if (!strncmp("disable", str, 7)) | |
90 | boot_hpet_disable = 1; | |
b17530bd TG |
91 | if (!strncmp("force", str, 5)) |
92 | hpet_force_user = 1; | |
e9e2cdb4 TG |
93 | } |
94 | return 1; | |
95 | } | |
96 | __setup("hpet=", hpet_setup); | |
97 | ||
28769149 TG |
98 | static int __init disable_hpet(char *str) |
99 | { | |
100 | boot_hpet_disable = 1; | |
101 | return 1; | |
102 | } | |
103 | __setup("nohpet", disable_hpet); | |
104 | ||
e9e2cdb4 TG |
105 | static inline int is_hpet_capable(void) |
106 | { | |
4588c1f0 | 107 | return !boot_hpet_disable && hpet_address; |
e9e2cdb4 TG |
108 | } |
109 | ||
110 | /* | |
111 | * HPET timer interrupt enable / disable | |
112 | */ | |
113 | static int hpet_legacy_int_enabled; | |
114 | ||
115 | /** | |
116 | * is_hpet_enabled - check whether the hpet timer interrupt is enabled | |
117 | */ | |
118 | int is_hpet_enabled(void) | |
119 | { | |
120 | return is_hpet_capable() && hpet_legacy_int_enabled; | |
121 | } | |
1bdbdaac | 122 | EXPORT_SYMBOL_GPL(is_hpet_enabled); |
e9e2cdb4 TG |
123 | |
124 | /* | |
125 | * When the hpet driver (/dev/hpet) is enabled, we need to reserve | |
126 | * timer 0 and timer 1 in case of RTC emulation. | |
127 | */ | |
128 | #ifdef CONFIG_HPET | |
129 | static void hpet_reserve_platform_timers(unsigned long id) | |
130 | { | |
131 | struct hpet __iomem *hpet = hpet_virt_address; | |
37a47db8 BR |
132 | struct hpet_timer __iomem *timer = &hpet->hpet_timers[2]; |
133 | unsigned int nrtimers, i; | |
e9e2cdb4 TG |
134 | struct hpet_data hd; |
135 | ||
136 | nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1; | |
137 | ||
4588c1f0 IM |
138 | memset(&hd, 0, sizeof(hd)); |
139 | hd.hd_phys_address = hpet_address; | |
140 | hd.hd_address = hpet; | |
141 | hd.hd_nirqs = nrtimers; | |
e9e2cdb4 TG |
142 | hpet_reserve_timer(&hd, 0); |
143 | ||
144 | #ifdef CONFIG_HPET_EMULATE_RTC | |
145 | hpet_reserve_timer(&hd, 1); | |
146 | #endif | |
5761d64b | 147 | |
64a76f66 DB |
148 | /* |
149 | * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254 | |
150 | * is wrong for i8259!) not the output IRQ. Many BIOS writers | |
151 | * don't bother configuring *any* comparator interrupts. | |
152 | */ | |
e9e2cdb4 TG |
153 | hd.hd_irq[0] = HPET_LEGACY_8254; |
154 | hd.hd_irq[1] = HPET_LEGACY_RTC; | |
155 | ||
fc3fbc45 | 156 | for (i = 2; i < nrtimers; timer++, i++) { |
4588c1f0 IM |
157 | hd.hd_irq[i] = (readl(&timer->hpet_config) & |
158 | Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT; | |
fc3fbc45 | 159 | } |
5761d64b | 160 | |
26afe5f2 | 161 | for (i = 0; i < nrtimers; i++) { |
162 | struct hpet_dev *hdev = &hpet_devs[i]; | |
163 | ||
164 | if (!(hdev->flags & HPET_DEV_VALID)) | |
165 | continue; | |
166 | ||
167 | hd.hd_irq[hdev->num] = hdev->irq; | |
168 | hpet_reserve_timer(&hd, hdev->num); | |
169 | } | |
170 | ||
e9e2cdb4 | 171 | hpet_alloc(&hd); |
5761d64b | 172 | |
e9e2cdb4 TG |
173 | } |
174 | #else | |
175 | static void hpet_reserve_platform_timers(unsigned long id) { } | |
176 | #endif | |
177 | ||
178 | /* | |
179 | * Common hpet info | |
180 | */ | |
181 | static unsigned long hpet_period; | |
182 | ||
610bf2f1 | 183 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
e9e2cdb4 | 184 | struct clock_event_device *evt); |
610bf2f1 | 185 | static int hpet_legacy_next_event(unsigned long delta, |
e9e2cdb4 TG |
186 | struct clock_event_device *evt); |
187 | ||
188 | /* | |
189 | * The hpet clock event device | |
190 | */ | |
191 | static struct clock_event_device hpet_clockevent = { | |
192 | .name = "hpet", | |
193 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
610bf2f1 VP |
194 | .set_mode = hpet_legacy_set_mode, |
195 | .set_next_event = hpet_legacy_next_event, | |
e9e2cdb4 TG |
196 | .shift = 32, |
197 | .irq = 0, | |
59c69f2a | 198 | .rating = 50, |
e9e2cdb4 TG |
199 | }; |
200 | ||
201 | static void hpet_start_counter(void) | |
202 | { | |
203 | unsigned long cfg = hpet_readl(HPET_CFG); | |
204 | ||
205 | cfg &= ~HPET_CFG_ENABLE; | |
206 | hpet_writel(cfg, HPET_CFG); | |
207 | hpet_writel(0, HPET_COUNTER); | |
208 | hpet_writel(0, HPET_COUNTER + 4); | |
209 | cfg |= HPET_CFG_ENABLE; | |
210 | hpet_writel(cfg, HPET_CFG); | |
211 | } | |
212 | ||
59c69f2a VP |
213 | static void hpet_resume_device(void) |
214 | { | |
bfe0c1cc | 215 | force_hpet_resume(); |
59c69f2a VP |
216 | } |
217 | ||
218 | static void hpet_restart_counter(void) | |
219 | { | |
220 | hpet_resume_device(); | |
221 | hpet_start_counter(); | |
222 | } | |
223 | ||
610bf2f1 | 224 | static void hpet_enable_legacy_int(void) |
e9e2cdb4 TG |
225 | { |
226 | unsigned long cfg = hpet_readl(HPET_CFG); | |
227 | ||
228 | cfg |= HPET_CFG_LEGACY; | |
229 | hpet_writel(cfg, HPET_CFG); | |
230 | hpet_legacy_int_enabled = 1; | |
231 | } | |
232 | ||
610bf2f1 VP |
233 | static void hpet_legacy_clockevent_register(void) |
234 | { | |
610bf2f1 VP |
235 | /* Start HPET legacy interrupts */ |
236 | hpet_enable_legacy_int(); | |
237 | ||
238 | /* | |
6fd592da CM |
239 | * The mult factor is defined as (include/linux/clockchips.h) |
240 | * mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h) | |
241 | * hpet_period is in units of femtoseconds (per cycle), so | |
242 | * mult/2^shift = cyc/ns = 10^6/hpet_period | |
243 | * mult = (10^6 * 2^shift)/hpet_period | |
244 | * mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period | |
610bf2f1 | 245 | */ |
6fd592da CM |
246 | hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC, |
247 | hpet_period, hpet_clockevent.shift); | |
610bf2f1 VP |
248 | /* Calculate the min / max delta */ |
249 | hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, | |
250 | &hpet_clockevent); | |
7cfb0435 TG |
251 | /* 5 usec minimum reprogramming delta. */ |
252 | hpet_clockevent.min_delta_ns = 5000; | |
610bf2f1 VP |
253 | |
254 | /* | |
255 | * Start hpet with the boot cpu mask and make it | |
256 | * global after the IO_APIC has been initialized. | |
257 | */ | |
258 | hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id()); | |
259 | clockevents_register_device(&hpet_clockevent); | |
260 | global_clock_event = &hpet_clockevent; | |
261 | printk(KERN_DEBUG "hpet clockevent registered\n"); | |
262 | } | |
263 | ||
26afe5f2 | 264 | static int hpet_setup_msi_irq(unsigned int irq); |
265 | ||
b40d575b | 266 | static void hpet_set_mode(enum clock_event_mode mode, |
267 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 TG |
268 | { |
269 | unsigned long cfg, cmp, now; | |
270 | uint64_t delta; | |
271 | ||
4588c1f0 | 272 | switch (mode) { |
e9e2cdb4 | 273 | case CLOCK_EVT_MODE_PERIODIC: |
b40d575b | 274 | delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult; |
275 | delta >>= evt->shift; | |
e9e2cdb4 TG |
276 | now = hpet_readl(HPET_COUNTER); |
277 | cmp = now + (unsigned long) delta; | |
b40d575b | 278 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
279 | cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | |
280 | HPET_TN_SETVAL | HPET_TN_32BIT; | |
b40d575b | 281 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
282 | /* |
283 | * The first write after writing TN_SETVAL to the | |
284 | * config register sets the counter value, the second | |
285 | * write sets the period. | |
286 | */ | |
b40d575b | 287 | hpet_writel(cmp, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 288 | udelay(1); |
b40d575b | 289 | hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer)); |
e9e2cdb4 TG |
290 | break; |
291 | ||
292 | case CLOCK_EVT_MODE_ONESHOT: | |
b40d575b | 293 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
294 | cfg &= ~HPET_TN_PERIODIC; |
295 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
b40d575b | 296 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 TG |
297 | break; |
298 | ||
299 | case CLOCK_EVT_MODE_UNUSED: | |
300 | case CLOCK_EVT_MODE_SHUTDOWN: | |
b40d575b | 301 | cfg = hpet_readl(HPET_Tn_CFG(timer)); |
e9e2cdb4 | 302 | cfg &= ~HPET_TN_ENABLE; |
b40d575b | 303 | hpet_writel(cfg, HPET_Tn_CFG(timer)); |
e9e2cdb4 | 304 | break; |
18de5bc4 TG |
305 | |
306 | case CLOCK_EVT_MODE_RESUME: | |
26afe5f2 | 307 | if (timer == 0) { |
308 | hpet_enable_legacy_int(); | |
309 | } else { | |
310 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
311 | hpet_setup_msi_irq(hdev->irq); | |
312 | disable_irq(hdev->irq); | |
313 | irq_set_affinity(hdev->irq, cpumask_of_cpu(hdev->cpu)); | |
314 | enable_irq(hdev->irq); | |
315 | } | |
18de5bc4 | 316 | break; |
e9e2cdb4 TG |
317 | } |
318 | } | |
319 | ||
b40d575b | 320 | static int hpet_next_event(unsigned long delta, |
321 | struct clock_event_device *evt, int timer) | |
e9e2cdb4 | 322 | { |
f7676254 | 323 | u32 cnt; |
e9e2cdb4 TG |
324 | |
325 | cnt = hpet_readl(HPET_COUNTER); | |
f7676254 | 326 | cnt += (u32) delta; |
b40d575b | 327 | hpet_writel(cnt, HPET_Tn_CMP(timer)); |
e9e2cdb4 | 328 | |
72d43d9b TG |
329 | /* |
330 | * We need to read back the CMP register to make sure that | |
331 | * what we wrote hit the chip before we compare it to the | |
332 | * counter. | |
333 | */ | |
334 | WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt); | |
335 | ||
f7676254 | 336 | return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0; |
e9e2cdb4 TG |
337 | } |
338 | ||
b40d575b | 339 | static void hpet_legacy_set_mode(enum clock_event_mode mode, |
340 | struct clock_event_device *evt) | |
341 | { | |
342 | hpet_set_mode(mode, evt, 0); | |
343 | } | |
344 | ||
345 | static int hpet_legacy_next_event(unsigned long delta, | |
346 | struct clock_event_device *evt) | |
347 | { | |
348 | return hpet_next_event(delta, evt, 0); | |
349 | } | |
350 | ||
58ac1e76 | 351 | /* |
352 | * HPET MSI Support | |
353 | */ | |
26afe5f2 | 354 | #ifdef CONFIG_PCI_MSI |
58ac1e76 | 355 | void hpet_msi_unmask(unsigned int irq) |
356 | { | |
357 | struct hpet_dev *hdev = get_irq_data(irq); | |
358 | unsigned long cfg; | |
359 | ||
360 | /* unmask it */ | |
361 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
362 | cfg |= HPET_TN_FSB; | |
363 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
364 | } | |
365 | ||
366 | void hpet_msi_mask(unsigned int irq) | |
367 | { | |
368 | unsigned long cfg; | |
369 | struct hpet_dev *hdev = get_irq_data(irq); | |
370 | ||
371 | /* mask it */ | |
372 | cfg = hpet_readl(HPET_Tn_CFG(hdev->num)); | |
373 | cfg &= ~HPET_TN_FSB; | |
374 | hpet_writel(cfg, HPET_Tn_CFG(hdev->num)); | |
375 | } | |
376 | ||
377 | void hpet_msi_write(unsigned int irq, struct msi_msg *msg) | |
378 | { | |
379 | struct hpet_dev *hdev = get_irq_data(irq); | |
380 | ||
381 | hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num)); | |
382 | hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4); | |
383 | } | |
384 | ||
385 | void hpet_msi_read(unsigned int irq, struct msi_msg *msg) | |
386 | { | |
387 | struct hpet_dev *hdev = get_irq_data(irq); | |
388 | ||
389 | msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num)); | |
390 | msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4); | |
391 | msg->address_hi = 0; | |
392 | } | |
393 | ||
26afe5f2 | 394 | static void hpet_msi_set_mode(enum clock_event_mode mode, |
395 | struct clock_event_device *evt) | |
396 | { | |
397 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
398 | hpet_set_mode(mode, evt, hdev->num); | |
399 | } | |
400 | ||
401 | static int hpet_msi_next_event(unsigned long delta, | |
402 | struct clock_event_device *evt) | |
403 | { | |
404 | struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt); | |
405 | return hpet_next_event(delta, evt, hdev->num); | |
406 | } | |
407 | ||
408 | static int hpet_setup_msi_irq(unsigned int irq) | |
409 | { | |
410 | if (arch_setup_hpet_msi(irq)) { | |
411 | destroy_irq(irq); | |
412 | return -EINVAL; | |
413 | } | |
414 | return 0; | |
415 | } | |
416 | ||
417 | static int hpet_assign_irq(struct hpet_dev *dev) | |
418 | { | |
419 | unsigned int irq; | |
420 | ||
421 | irq = create_irq(); | |
422 | if (!irq) | |
423 | return -EINVAL; | |
424 | ||
425 | set_irq_data(irq, dev); | |
426 | ||
427 | if (hpet_setup_msi_irq(irq)) | |
428 | return -EINVAL; | |
429 | ||
430 | dev->irq = irq; | |
431 | return 0; | |
432 | } | |
433 | ||
434 | static irqreturn_t hpet_interrupt_handler(int irq, void *data) | |
435 | { | |
436 | struct hpet_dev *dev = (struct hpet_dev *)data; | |
437 | struct clock_event_device *hevt = &dev->evt; | |
438 | ||
439 | if (!hevt->event_handler) { | |
440 | printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n", | |
441 | dev->num); | |
442 | return IRQ_HANDLED; | |
443 | } | |
444 | ||
445 | hevt->event_handler(hevt); | |
446 | return IRQ_HANDLED; | |
447 | } | |
448 | ||
449 | static int hpet_setup_irq(struct hpet_dev *dev) | |
450 | { | |
451 | ||
452 | if (request_irq(dev->irq, hpet_interrupt_handler, | |
453 | IRQF_SHARED|IRQF_NOBALANCING, dev->name, dev)) | |
454 | return -1; | |
455 | ||
456 | disable_irq(dev->irq); | |
457 | irq_set_affinity(dev->irq, cpumask_of_cpu(dev->cpu)); | |
458 | enable_irq(dev->irq); | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | /* This should be called in specific @cpu */ | |
464 | static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu) | |
465 | { | |
466 | struct clock_event_device *evt = &hdev->evt; | |
467 | uint64_t hpet_freq; | |
468 | ||
469 | WARN_ON(cpu != smp_processor_id()); | |
470 | if (!(hdev->flags & HPET_DEV_VALID)) | |
471 | return; | |
472 | ||
473 | if (hpet_setup_msi_irq(hdev->irq)) | |
474 | return; | |
475 | ||
476 | hdev->cpu = cpu; | |
477 | per_cpu(cpu_hpet_dev, cpu) = hdev; | |
478 | evt->name = hdev->name; | |
479 | hpet_setup_irq(hdev); | |
480 | evt->irq = hdev->irq; | |
481 | ||
482 | evt->rating = 110; | |
483 | evt->features = CLOCK_EVT_FEAT_ONESHOT; | |
484 | if (hdev->flags & HPET_DEV_PERI_CAP) | |
485 | evt->features |= CLOCK_EVT_FEAT_PERIODIC; | |
486 | ||
487 | evt->set_mode = hpet_msi_set_mode; | |
488 | evt->set_next_event = hpet_msi_next_event; | |
489 | evt->shift = 32; | |
490 | ||
491 | /* | |
492 | * The period is a femto seconds value. We need to calculate the | |
493 | * scaled math multiplication factor for nanosecond to hpet tick | |
494 | * conversion. | |
495 | */ | |
496 | hpet_freq = 1000000000000000ULL; | |
497 | do_div(hpet_freq, hpet_period); | |
498 | evt->mult = div_sc((unsigned long) hpet_freq, | |
499 | NSEC_PER_SEC, evt->shift); | |
500 | /* Calculate the max delta */ | |
501 | evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt); | |
502 | /* 5 usec minimum reprogramming delta. */ | |
503 | evt->min_delta_ns = 5000; | |
504 | ||
505 | evt->cpumask = cpumask_of_cpu(hdev->cpu); | |
506 | clockevents_register_device(evt); | |
507 | } | |
508 | ||
509 | #ifdef CONFIG_HPET | |
510 | /* Reserve at least one timer for userspace (/dev/hpet) */ | |
511 | #define RESERVE_TIMERS 1 | |
512 | #else | |
513 | #define RESERVE_TIMERS 0 | |
514 | #endif | |
515 | void hpet_msi_capability_lookup(unsigned int start_timer) | |
516 | { | |
517 | unsigned int id; | |
518 | unsigned int num_timers; | |
519 | unsigned int num_timers_used = 0; | |
520 | int i; | |
521 | ||
522 | id = hpet_readl(HPET_ID); | |
523 | ||
524 | num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT); | |
525 | num_timers++; /* Value read out starts from 0 */ | |
526 | ||
527 | hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL); | |
528 | if (!hpet_devs) | |
529 | return; | |
530 | ||
531 | hpet_num_timers = num_timers; | |
532 | ||
533 | for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) { | |
534 | struct hpet_dev *hdev = &hpet_devs[num_timers_used]; | |
535 | unsigned long cfg = hpet_readl(HPET_Tn_CFG(i)); | |
536 | ||
537 | /* Only consider HPET timer with MSI support */ | |
538 | if (!(cfg & HPET_TN_FSB_CAP)) | |
539 | continue; | |
540 | ||
541 | hdev->flags = 0; | |
542 | if (cfg & HPET_TN_PERIODIC_CAP) | |
543 | hdev->flags |= HPET_DEV_PERI_CAP; | |
544 | hdev->num = i; | |
545 | ||
546 | sprintf(hdev->name, "hpet%d", i); | |
547 | if (hpet_assign_irq(hdev)) | |
548 | continue; | |
549 | ||
550 | hdev->flags |= HPET_DEV_FSB_CAP; | |
551 | hdev->flags |= HPET_DEV_VALID; | |
552 | num_timers_used++; | |
553 | if (num_timers_used == num_possible_cpus()) | |
554 | break; | |
555 | } | |
556 | ||
557 | printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n", | |
558 | num_timers, num_timers_used); | |
559 | } | |
560 | ||
561 | static struct hpet_dev *hpet_get_unused_timer(void) | |
562 | { | |
563 | int i; | |
564 | ||
565 | if (!hpet_devs) | |
566 | return NULL; | |
567 | ||
568 | for (i = 0; i < hpet_num_timers; i++) { | |
569 | struct hpet_dev *hdev = &hpet_devs[i]; | |
570 | ||
571 | if (!(hdev->flags & HPET_DEV_VALID)) | |
572 | continue; | |
573 | if (test_and_set_bit(HPET_DEV_USED_BIT, | |
574 | (unsigned long *)&hdev->flags)) | |
575 | continue; | |
576 | return hdev; | |
577 | } | |
578 | return NULL; | |
579 | } | |
580 | ||
581 | struct hpet_work_struct { | |
582 | struct delayed_work work; | |
583 | struct completion complete; | |
584 | }; | |
585 | ||
586 | static void hpet_work(struct work_struct *w) | |
587 | { | |
588 | struct hpet_dev *hdev; | |
589 | int cpu = smp_processor_id(); | |
590 | struct hpet_work_struct *hpet_work; | |
591 | ||
592 | hpet_work = container_of(w, struct hpet_work_struct, work.work); | |
593 | ||
594 | hdev = hpet_get_unused_timer(); | |
595 | if (hdev) | |
596 | init_one_hpet_msi_clockevent(hdev, cpu); | |
597 | ||
598 | complete(&hpet_work->complete); | |
599 | } | |
600 | ||
601 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
602 | unsigned long action, void *hcpu) | |
603 | { | |
604 | unsigned long cpu = (unsigned long)hcpu; | |
605 | struct hpet_work_struct work; | |
606 | struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu); | |
607 | ||
608 | switch (action & 0xf) { | |
609 | case CPU_ONLINE: | |
610 | INIT_DELAYED_WORK(&work.work, hpet_work); | |
611 | init_completion(&work.complete); | |
612 | /* FIXME: add schedule_work_on() */ | |
613 | schedule_delayed_work_on(cpu, &work.work, 0); | |
614 | wait_for_completion(&work.complete); | |
615 | break; | |
616 | case CPU_DEAD: | |
617 | if (hdev) { | |
618 | free_irq(hdev->irq, hdev); | |
619 | hdev->flags &= ~HPET_DEV_USED; | |
620 | per_cpu(cpu_hpet_dev, cpu) = NULL; | |
621 | } | |
622 | break; | |
623 | } | |
624 | return NOTIFY_OK; | |
625 | } | |
626 | #else | |
627 | ||
628 | void hpet_msi_capability_lookup(unsigned int start_timer) | |
629 | { | |
630 | return; | |
631 | } | |
632 | ||
633 | static int hpet_cpuhp_notify(struct notifier_block *n, | |
634 | unsigned long action, void *hcpu) | |
635 | { | |
636 | return NOTIFY_OK; | |
637 | } | |
638 | ||
639 | #endif | |
640 | ||
6bb74df4 | 641 | /* |
642 | * Clock source related code | |
643 | */ | |
644 | static cycle_t read_hpet(void) | |
645 | { | |
646 | return (cycle_t)hpet_readl(HPET_COUNTER); | |
647 | } | |
648 | ||
28769149 TG |
649 | #ifdef CONFIG_X86_64 |
650 | static cycle_t __vsyscall_fn vread_hpet(void) | |
651 | { | |
652 | return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0); | |
653 | } | |
654 | #endif | |
655 | ||
6bb74df4 | 656 | static struct clocksource clocksource_hpet = { |
657 | .name = "hpet", | |
658 | .rating = 250, | |
659 | .read = read_hpet, | |
660 | .mask = HPET_MASK, | |
661 | .shift = HPET_SHIFT, | |
662 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
59c69f2a | 663 | .resume = hpet_restart_counter, |
28769149 TG |
664 | #ifdef CONFIG_X86_64 |
665 | .vread = vread_hpet, | |
666 | #endif | |
6bb74df4 | 667 | }; |
668 | ||
610bf2f1 | 669 | static int hpet_clocksource_register(void) |
e9e2cdb4 | 670 | { |
6fd592da | 671 | u64 start, now; |
075bcd1f | 672 | cycle_t t1; |
e9e2cdb4 | 673 | |
e9e2cdb4 TG |
674 | /* Start the counter */ |
675 | hpet_start_counter(); | |
676 | ||
075bcd1f TG |
677 | /* Verify whether hpet counter works */ |
678 | t1 = read_hpet(); | |
679 | rdtscll(start); | |
680 | ||
681 | /* | |
682 | * We don't know the TSC frequency yet, but waiting for | |
683 | * 200000 TSC cycles is safe: | |
684 | * 4 GHz == 50us | |
685 | * 1 GHz == 200us | |
686 | */ | |
687 | do { | |
688 | rep_nop(); | |
689 | rdtscll(now); | |
690 | } while ((now - start) < 200000UL); | |
691 | ||
692 | if (t1 == read_hpet()) { | |
693 | printk(KERN_WARNING | |
694 | "HPET counter not counting. HPET disabled\n"); | |
610bf2f1 | 695 | return -ENODEV; |
075bcd1f TG |
696 | } |
697 | ||
6fd592da CM |
698 | /* |
699 | * The definition of mult is (include/linux/clocksource.h) | |
700 | * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc | |
701 | * so we first need to convert hpet_period to ns/cyc units: | |
702 | * mult/2^shift = ns/cyc = hpet_period/10^6 | |
703 | * mult = (hpet_period * 2^shift)/10^6 | |
704 | * mult = (hpet_period << shift)/FSEC_PER_NSEC | |
6bb74df4 | 705 | */ |
6fd592da | 706 | clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT); |
6bb74df4 | 707 | |
708 | clocksource_register(&clocksource_hpet); | |
709 | ||
610bf2f1 VP |
710 | return 0; |
711 | } | |
712 | ||
b02a7f22 PM |
713 | /** |
714 | * hpet_enable - Try to setup the HPET timer. Returns 1 on success. | |
610bf2f1 VP |
715 | */ |
716 | int __init hpet_enable(void) | |
717 | { | |
718 | unsigned long id; | |
a6825f1c | 719 | int i; |
610bf2f1 VP |
720 | |
721 | if (!is_hpet_capable()) | |
722 | return 0; | |
723 | ||
724 | hpet_set_mapping(); | |
725 | ||
726 | /* | |
727 | * Read the period and check for a sane value: | |
728 | */ | |
729 | hpet_period = hpet_readl(HPET_PERIOD); | |
a6825f1c TG |
730 | |
731 | /* | |
732 | * AMD SB700 based systems with spread spectrum enabled use a | |
733 | * SMM based HPET emulation to provide proper frequency | |
734 | * setting. The SMM code is initialized with the first HPET | |
735 | * register access and takes some time to complete. During | |
736 | * this time the config register reads 0xffffffff. We check | |
737 | * for max. 1000 loops whether the config register reads a non | |
738 | * 0xffffffff value to make sure that HPET is up and running | |
739 | * before we go further. A counting loop is safe, as the HPET | |
740 | * access takes thousands of CPU cycles. On non SB700 based | |
741 | * machines this check is only done once and has no side | |
742 | * effects. | |
743 | */ | |
744 | for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) { | |
745 | if (i == 1000) { | |
746 | printk(KERN_WARNING | |
747 | "HPET config register value = 0xFFFFFFFF. " | |
748 | "Disabling HPET\n"); | |
749 | goto out_nohpet; | |
750 | } | |
751 | } | |
752 | ||
610bf2f1 VP |
753 | if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD) |
754 | goto out_nohpet; | |
755 | ||
756 | /* | |
757 | * Read the HPET ID register to retrieve the IRQ routing | |
758 | * information and the number of channels | |
759 | */ | |
760 | id = hpet_readl(HPET_ID); | |
761 | ||
762 | #ifdef CONFIG_HPET_EMULATE_RTC | |
763 | /* | |
764 | * The legacy routing mode needs at least two channels, tick timer | |
765 | * and the rtc emulation channel. | |
766 | */ | |
767 | if (!(id & HPET_ID_NUMBER)) | |
768 | goto out_nohpet; | |
769 | #endif | |
770 | ||
771 | if (hpet_clocksource_register()) | |
772 | goto out_nohpet; | |
773 | ||
e9e2cdb4 | 774 | if (id & HPET_ID_LEGSUP) { |
610bf2f1 | 775 | hpet_legacy_clockevent_register(); |
26afe5f2 | 776 | hpet_msi_capability_lookup(2); |
e9e2cdb4 TG |
777 | return 1; |
778 | } | |
26afe5f2 | 779 | hpet_msi_capability_lookup(0); |
e9e2cdb4 | 780 | return 0; |
5d0cf410 | 781 | |
e9e2cdb4 | 782 | out_nohpet: |
06a24dec | 783 | hpet_clear_mapping(); |
399afa4f | 784 | boot_hpet_disable = 1; |
e9e2cdb4 TG |
785 | return 0; |
786 | } | |
787 | ||
28769149 TG |
788 | /* |
789 | * Needs to be late, as the reserve_timer code calls kalloc ! | |
790 | * | |
791 | * Not a problem on i386 as hpet_enable is called from late_time_init, | |
792 | * but on x86_64 it is necessary ! | |
793 | */ | |
794 | static __init int hpet_late_init(void) | |
795 | { | |
26afe5f2 | 796 | int cpu; |
797 | ||
59c69f2a | 798 | if (boot_hpet_disable) |
28769149 TG |
799 | return -ENODEV; |
800 | ||
59c69f2a VP |
801 | if (!hpet_address) { |
802 | if (!force_hpet_address) | |
803 | return -ENODEV; | |
804 | ||
805 | hpet_address = force_hpet_address; | |
806 | hpet_enable(); | |
807 | if (!hpet_virt_address) | |
808 | return -ENODEV; | |
809 | } | |
810 | ||
28769149 | 811 | hpet_reserve_platform_timers(hpet_readl(HPET_ID)); |
59c69f2a | 812 | |
26afe5f2 | 813 | for_each_online_cpu(cpu) { |
814 | hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu); | |
815 | } | |
816 | ||
817 | /* This notifier should be called after workqueue is ready */ | |
818 | hotcpu_notifier(hpet_cpuhp_notify, -20); | |
819 | ||
28769149 TG |
820 | return 0; |
821 | } | |
822 | fs_initcall(hpet_late_init); | |
823 | ||
c86c7fbc OH |
824 | void hpet_disable(void) |
825 | { | |
826 | if (is_hpet_capable()) { | |
827 | unsigned long cfg = hpet_readl(HPET_CFG); | |
828 | ||
829 | if (hpet_legacy_int_enabled) { | |
830 | cfg &= ~HPET_CFG_LEGACY; | |
831 | hpet_legacy_int_enabled = 0; | |
832 | } | |
833 | cfg &= ~HPET_CFG_ENABLE; | |
834 | hpet_writel(cfg, HPET_CFG); | |
835 | } | |
836 | } | |
837 | ||
e9e2cdb4 TG |
838 | #ifdef CONFIG_HPET_EMULATE_RTC |
839 | ||
840 | /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET | |
841 | * is enabled, we support RTC interrupt functionality in software. | |
842 | * RTC has 3 kinds of interrupts: | |
843 | * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock | |
844 | * is updated | |
845 | * 2) Alarm Interrupt - generate an interrupt at a specific time of day | |
846 | * 3) Periodic Interrupt - generate periodic interrupt, with frequencies | |
847 | * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2) | |
848 | * (1) and (2) above are implemented using polling at a frequency of | |
849 | * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt | |
850 | * overhead. (DEFAULT_RTC_INT_FREQ) | |
851 | * For (3), we use interrupts at 64Hz or user specified periodic | |
852 | * frequency, whichever is higher. | |
853 | */ | |
854 | #include <linux/mc146818rtc.h> | |
855 | #include <linux/rtc.h> | |
1bdbdaac | 856 | #include <asm/rtc.h> |
e9e2cdb4 TG |
857 | |
858 | #define DEFAULT_RTC_INT_FREQ 64 | |
859 | #define DEFAULT_RTC_SHIFT 6 | |
860 | #define RTC_NUM_INTS 1 | |
861 | ||
862 | static unsigned long hpet_rtc_flags; | |
7e2a31da | 863 | static int hpet_prev_update_sec; |
e9e2cdb4 TG |
864 | static struct rtc_time hpet_alarm_time; |
865 | static unsigned long hpet_pie_count; | |
866 | static unsigned long hpet_t1_cmp; | |
867 | static unsigned long hpet_default_delta; | |
868 | static unsigned long hpet_pie_delta; | |
869 | static unsigned long hpet_pie_limit; | |
870 | ||
1bdbdaac BW |
871 | static rtc_irq_handler irq_handler; |
872 | ||
873 | /* | |
874 | * Registers a IRQ handler. | |
875 | */ | |
876 | int hpet_register_irq_handler(rtc_irq_handler handler) | |
877 | { | |
878 | if (!is_hpet_enabled()) | |
879 | return -ENODEV; | |
880 | if (irq_handler) | |
881 | return -EBUSY; | |
882 | ||
883 | irq_handler = handler; | |
884 | ||
885 | return 0; | |
886 | } | |
887 | EXPORT_SYMBOL_GPL(hpet_register_irq_handler); | |
888 | ||
889 | /* | |
890 | * Deregisters the IRQ handler registered with hpet_register_irq_handler() | |
891 | * and does cleanup. | |
892 | */ | |
893 | void hpet_unregister_irq_handler(rtc_irq_handler handler) | |
894 | { | |
895 | if (!is_hpet_enabled()) | |
896 | return; | |
897 | ||
898 | irq_handler = NULL; | |
899 | hpet_rtc_flags = 0; | |
900 | } | |
901 | EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler); | |
902 | ||
e9e2cdb4 TG |
903 | /* |
904 | * Timer 1 for RTC emulation. We use one shot mode, as periodic mode | |
905 | * is not supported by all HPET implementations for timer 1. | |
906 | * | |
907 | * hpet_rtc_timer_init() is called when the rtc is initialized. | |
908 | */ | |
909 | int hpet_rtc_timer_init(void) | |
910 | { | |
911 | unsigned long cfg, cnt, delta, flags; | |
912 | ||
913 | if (!is_hpet_enabled()) | |
914 | return 0; | |
915 | ||
916 | if (!hpet_default_delta) { | |
917 | uint64_t clc; | |
918 | ||
919 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
920 | clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT; | |
921 | hpet_default_delta = (unsigned long) clc; | |
922 | } | |
923 | ||
924 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
925 | delta = hpet_default_delta; | |
926 | else | |
927 | delta = hpet_pie_delta; | |
928 | ||
929 | local_irq_save(flags); | |
930 | ||
931 | cnt = delta + hpet_readl(HPET_COUNTER); | |
932 | hpet_writel(cnt, HPET_T1_CMP); | |
933 | hpet_t1_cmp = cnt; | |
934 | ||
935 | cfg = hpet_readl(HPET_T1_CFG); | |
936 | cfg &= ~HPET_TN_PERIODIC; | |
937 | cfg |= HPET_TN_ENABLE | HPET_TN_32BIT; | |
938 | hpet_writel(cfg, HPET_T1_CFG); | |
939 | ||
940 | local_irq_restore(flags); | |
941 | ||
942 | return 1; | |
943 | } | |
1bdbdaac | 944 | EXPORT_SYMBOL_GPL(hpet_rtc_timer_init); |
e9e2cdb4 TG |
945 | |
946 | /* | |
947 | * The functions below are called from rtc driver. | |
948 | * Return 0 if HPET is not being used. | |
949 | * Otherwise do the necessary changes and return 1. | |
950 | */ | |
951 | int hpet_mask_rtc_irq_bit(unsigned long bit_mask) | |
952 | { | |
953 | if (!is_hpet_enabled()) | |
954 | return 0; | |
955 | ||
956 | hpet_rtc_flags &= ~bit_mask; | |
957 | return 1; | |
958 | } | |
1bdbdaac | 959 | EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit); |
e9e2cdb4 TG |
960 | |
961 | int hpet_set_rtc_irq_bit(unsigned long bit_mask) | |
962 | { | |
963 | unsigned long oldbits = hpet_rtc_flags; | |
964 | ||
965 | if (!is_hpet_enabled()) | |
966 | return 0; | |
967 | ||
968 | hpet_rtc_flags |= bit_mask; | |
969 | ||
7e2a31da DB |
970 | if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE)) |
971 | hpet_prev_update_sec = -1; | |
972 | ||
e9e2cdb4 TG |
973 | if (!oldbits) |
974 | hpet_rtc_timer_init(); | |
975 | ||
976 | return 1; | |
977 | } | |
1bdbdaac | 978 | EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit); |
e9e2cdb4 TG |
979 | |
980 | int hpet_set_alarm_time(unsigned char hrs, unsigned char min, | |
981 | unsigned char sec) | |
982 | { | |
983 | if (!is_hpet_enabled()) | |
984 | return 0; | |
985 | ||
986 | hpet_alarm_time.tm_hour = hrs; | |
987 | hpet_alarm_time.tm_min = min; | |
988 | hpet_alarm_time.tm_sec = sec; | |
989 | ||
990 | return 1; | |
991 | } | |
1bdbdaac | 992 | EXPORT_SYMBOL_GPL(hpet_set_alarm_time); |
e9e2cdb4 TG |
993 | |
994 | int hpet_set_periodic_freq(unsigned long freq) | |
995 | { | |
996 | uint64_t clc; | |
997 | ||
998 | if (!is_hpet_enabled()) | |
999 | return 0; | |
1000 | ||
1001 | if (freq <= DEFAULT_RTC_INT_FREQ) | |
1002 | hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq; | |
1003 | else { | |
1004 | clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC; | |
1005 | do_div(clc, freq); | |
1006 | clc >>= hpet_clockevent.shift; | |
1007 | hpet_pie_delta = (unsigned long) clc; | |
1008 | } | |
1009 | return 1; | |
1010 | } | |
1bdbdaac | 1011 | EXPORT_SYMBOL_GPL(hpet_set_periodic_freq); |
e9e2cdb4 TG |
1012 | |
1013 | int hpet_rtc_dropped_irq(void) | |
1014 | { | |
1015 | return is_hpet_enabled(); | |
1016 | } | |
1bdbdaac | 1017 | EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq); |
e9e2cdb4 TG |
1018 | |
1019 | static void hpet_rtc_timer_reinit(void) | |
1020 | { | |
1021 | unsigned long cfg, delta; | |
1022 | int lost_ints = -1; | |
1023 | ||
1024 | if (unlikely(!hpet_rtc_flags)) { | |
1025 | cfg = hpet_readl(HPET_T1_CFG); | |
1026 | cfg &= ~HPET_TN_ENABLE; | |
1027 | hpet_writel(cfg, HPET_T1_CFG); | |
1028 | return; | |
1029 | } | |
1030 | ||
1031 | if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit) | |
1032 | delta = hpet_default_delta; | |
1033 | else | |
1034 | delta = hpet_pie_delta; | |
1035 | ||
1036 | /* | |
1037 | * Increment the comparator value until we are ahead of the | |
1038 | * current count. | |
1039 | */ | |
1040 | do { | |
1041 | hpet_t1_cmp += delta; | |
1042 | hpet_writel(hpet_t1_cmp, HPET_T1_CMP); | |
1043 | lost_ints++; | |
1044 | } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); | |
1045 | ||
1046 | if (lost_ints) { | |
1047 | if (hpet_rtc_flags & RTC_PIE) | |
1048 | hpet_pie_count += lost_ints; | |
1049 | if (printk_ratelimit()) | |
7e2a31da | 1050 | printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n", |
e9e2cdb4 TG |
1051 | lost_ints); |
1052 | } | |
1053 | } | |
1054 | ||
1055 | irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id) | |
1056 | { | |
1057 | struct rtc_time curr_time; | |
1058 | unsigned long rtc_int_flag = 0; | |
1059 | ||
1060 | hpet_rtc_timer_reinit(); | |
1bdbdaac | 1061 | memset(&curr_time, 0, sizeof(struct rtc_time)); |
e9e2cdb4 TG |
1062 | |
1063 | if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) | |
1bdbdaac | 1064 | get_rtc_time(&curr_time); |
e9e2cdb4 TG |
1065 | |
1066 | if (hpet_rtc_flags & RTC_UIE && | |
1067 | curr_time.tm_sec != hpet_prev_update_sec) { | |
7e2a31da DB |
1068 | if (hpet_prev_update_sec >= 0) |
1069 | rtc_int_flag = RTC_UF; | |
e9e2cdb4 TG |
1070 | hpet_prev_update_sec = curr_time.tm_sec; |
1071 | } | |
1072 | ||
1073 | if (hpet_rtc_flags & RTC_PIE && | |
1074 | ++hpet_pie_count >= hpet_pie_limit) { | |
1075 | rtc_int_flag |= RTC_PF; | |
1076 | hpet_pie_count = 0; | |
1077 | } | |
1078 | ||
8ee291f8 | 1079 | if (hpet_rtc_flags & RTC_AIE && |
e9e2cdb4 TG |
1080 | (curr_time.tm_sec == hpet_alarm_time.tm_sec) && |
1081 | (curr_time.tm_min == hpet_alarm_time.tm_min) && | |
1082 | (curr_time.tm_hour == hpet_alarm_time.tm_hour)) | |
1083 | rtc_int_flag |= RTC_AF; | |
1084 | ||
1085 | if (rtc_int_flag) { | |
1086 | rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8)); | |
1bdbdaac BW |
1087 | if (irq_handler) |
1088 | irq_handler(rtc_int_flag, dev_id); | |
e9e2cdb4 TG |
1089 | } |
1090 | return IRQ_HANDLED; | |
1091 | } | |
1bdbdaac | 1092 | EXPORT_SYMBOL_GPL(hpet_rtc_interrupt); |
e9e2cdb4 | 1093 | #endif |