Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
59a36d16 | 8 | |
df6b35f4 | 9 | #include <asm/fpu/api.h> |
78f7f1e5 | 10 | #include <asm/fpu/internal.h> |
fcbc99c4 | 11 | #include <asm/fpu/signal.h> |
59a36d16 | 12 | #include <asm/fpu/regset.h> |
b992c660 | 13 | |
375074cc | 14 | #include <asm/tlbflush.h> |
dc1e35c6 | 15 | |
5b073430 IM |
16 | static const char *xfeature_names[] = |
17 | { | |
18 | "x87 floating point registers" , | |
19 | "SSE registers" , | |
20 | "AVX registers" , | |
21 | "MPX bounds registers" , | |
22 | "MPX CSR" , | |
23 | "AVX-512 opmask" , | |
24 | "AVX-512 Hi256" , | |
25 | "AVX-512 ZMM_Hi256" , | |
26 | "unknown xstate feature" , | |
27 | }; | |
28 | ||
dc1e35c6 | 29 | /* |
614df7fb | 30 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 31 | */ |
5b073430 | 32 | u64 xfeatures_mask __read_mostly; |
dc1e35c6 | 33 | |
dad8c4fe DH |
34 | static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1}; |
35 | static unsigned int xstate_sizes[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1}; | |
614df7fb | 36 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 | 37 | |
0a265375 DH |
38 | /* |
39 | * Clear all of the X86_FEATURE_* bits that are unavailable | |
40 | * when the CPU has no XSAVE support. | |
41 | */ | |
42 | void fpu__xstate_clear_all_cpu_caps(void) | |
43 | { | |
44 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
45 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
46 | setup_clear_cpu_cap(X86_FEATURE_XSAVEC); | |
47 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
48 | setup_clear_cpu_cap(X86_FEATURE_AVX); | |
49 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
50 | setup_clear_cpu_cap(X86_FEATURE_AVX512F); | |
51 | setup_clear_cpu_cap(X86_FEATURE_AVX512PF); | |
52 | setup_clear_cpu_cap(X86_FEATURE_AVX512ER); | |
53 | setup_clear_cpu_cap(X86_FEATURE_AVX512CD); | |
d0500494 FY |
54 | setup_clear_cpu_cap(X86_FEATURE_AVX512DQ); |
55 | setup_clear_cpu_cap(X86_FEATURE_AVX512BW); | |
56 | setup_clear_cpu_cap(X86_FEATURE_AVX512VL); | |
0a265375 | 57 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
eb7c5f87 | 58 | setup_clear_cpu_cap(X86_FEATURE_XGETBV1); |
0a265375 DH |
59 | } |
60 | ||
5b073430 IM |
61 | /* |
62 | * Return whether the system supports a given xfeature. | |
63 | * | |
64 | * Also return the name of the (most advanced) feature that the caller requested: | |
65 | */ | |
66 | int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name) | |
67 | { | |
68 | u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; | |
69 | ||
70 | if (unlikely(feature_name)) { | |
71 | long xfeature_idx, max_idx; | |
72 | u64 xfeatures_print; | |
73 | /* | |
74 | * So we use FLS here to be able to print the most advanced | |
75 | * feature that was requested but is missing. So if a driver | |
d91cab78 | 76 | * asks about "XFEATURE_MASK_SSE | XFEATURE_MASK_YMM" we'll print the |
5b073430 IM |
77 | * missing AVX feature - this is the most informative message |
78 | * to users: | |
79 | */ | |
80 | if (xfeatures_missing) | |
81 | xfeatures_print = xfeatures_missing; | |
82 | else | |
83 | xfeatures_print = xfeatures_needed; | |
84 | ||
85 | xfeature_idx = fls64(xfeatures_print)-1; | |
86 | max_idx = ARRAY_SIZE(xfeature_names)-1; | |
87 | xfeature_idx = min(xfeature_idx, max_idx); | |
88 | ||
89 | *feature_name = xfeature_names[xfeature_idx]; | |
90 | } | |
91 | ||
92 | if (xfeatures_missing) | |
93 | return 0; | |
94 | ||
95 | return 1; | |
96 | } | |
97 | EXPORT_SYMBOL_GPL(cpu_has_xfeatures); | |
98 | ||
29104e10 | 99 | /* |
aeb997b9 IM |
100 | * When executing XSAVEOPT (or other optimized XSAVE instructions), if |
101 | * a processor implementation detects that an FPU state component is still | |
102 | * (or is again) in its initialized state, it may clear the corresponding | |
103 | * bit in the header.xfeatures field, and can skip the writeout of registers | |
104 | * to the corresponding memory layout. | |
73a3aeb3 IM |
105 | * |
106 | * This means that when the bit is zero, the state component might still contain | |
107 | * some previous - non-initialized register state. | |
108 | * | |
109 | * Before writing xstate information to user-space we sanitize those components, | |
110 | * to always ensure that the memory layout of a feature will be in the init state | |
111 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
112 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 | 113 | */ |
36e49e7f | 114 | void fpstate_sanitize_xstate(struct fpu *fpu) |
29104e10 | 115 | { |
c47ada30 | 116 | struct fxregs_state *fx = &fpu->state.fxsave; |
73a3aeb3 | 117 | int feature_bit; |
400e4b20 | 118 | u64 xfeatures; |
29104e10 | 119 | |
1ac91a76 | 120 | if (!use_xsaveopt()) |
29104e10 SS |
121 | return; |
122 | ||
36e49e7f | 123 | xfeatures = fpu->state.xsave.header.xfeatures; |
29104e10 SS |
124 | |
125 | /* | |
126 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 127 | * to do for us, as the memory layout is up to date. |
29104e10 | 128 | */ |
400e4b20 | 129 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
130 | return; |
131 | ||
132 | /* | |
133 | * FP is in init state | |
134 | */ | |
d91cab78 | 135 | if (!(xfeatures & XFEATURE_MASK_FP)) { |
29104e10 SS |
136 | fx->cwd = 0x37f; |
137 | fx->swd = 0; | |
138 | fx->twd = 0; | |
139 | fx->fop = 0; | |
140 | fx->rip = 0; | |
141 | fx->rdp = 0; | |
142 | memset(&fx->st_space[0], 0, 128); | |
143 | } | |
144 | ||
145 | /* | |
146 | * SSE is in init state | |
147 | */ | |
d91cab78 | 148 | if (!(xfeatures & XFEATURE_MASK_SSE)) |
29104e10 SS |
149 | memset(&fx->xmm_space[0], 0, 256); |
150 | ||
73a3aeb3 IM |
151 | /* |
152 | * First two features are FPU and SSE, which above we handled | |
153 | * in a special way already: | |
154 | */ | |
155 | feature_bit = 0x2; | |
400e4b20 | 156 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
157 | |
158 | /* | |
73a3aeb3 IM |
159 | * Update all the remaining memory layouts according to their |
160 | * standard xstate layout, if their header bit is in the init | |
161 | * state: | |
29104e10 | 162 | */ |
400e4b20 IM |
163 | while (xfeatures) { |
164 | if (xfeatures & 0x1) { | |
29104e10 SS |
165 | int offset = xstate_offsets[feature_bit]; |
166 | int size = xstate_sizes[feature_bit]; | |
167 | ||
73a3aeb3 | 168 | memcpy((void *)fx + offset, |
6f575023 | 169 | (void *)&init_fpstate.xsave + offset, |
29104e10 SS |
170 | size); |
171 | } | |
172 | ||
400e4b20 | 173 | xfeatures >>= 1; |
29104e10 SS |
174 | feature_bit++; |
175 | } | |
176 | } | |
177 | ||
dc1e35c6 | 178 | /* |
55cc4678 IM |
179 | * Enable the extended processor state save/restore feature. |
180 | * Called once per CPU onlining. | |
dc1e35c6 | 181 | */ |
55cc4678 | 182 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 183 | { |
e84611fc | 184 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
185 | return; |
186 | ||
375074cc | 187 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 188 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
189 | } |
190 | ||
e6e888f9 DH |
191 | /* |
192 | * Note that in the future we will likely need a pair of | |
193 | * functions here: one for user xstates and the other for | |
194 | * system xstates. For now, they are the same. | |
195 | */ | |
196 | static int xfeature_enabled(enum xfeature xfeature) | |
197 | { | |
198 | return !!(xfeatures_mask & (1UL << xfeature)); | |
199 | } | |
200 | ||
a1488f8b | 201 | /* |
39f1acd2 IM |
202 | * Record the offsets and sizes of various xstates contained |
203 | * in the XSAVE state memory layout. | |
a1488f8b | 204 | */ |
4995b9db | 205 | static void __init setup_xstate_features(void) |
a1488f8b | 206 | { |
ee9ae257 | 207 | u32 eax, ebx, ecx, edx, i; |
e6e888f9 DH |
208 | /* start at the beginnning of the "extended state" */ |
209 | unsigned int last_good_offset = offsetof(struct xregs_state, | |
210 | extended_state_area); | |
a1488f8b | 211 | |
ee9ae257 | 212 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { |
e6e888f9 DH |
213 | if (!xfeature_enabled(i)) |
214 | continue; | |
a1488f8b | 215 | |
e6e888f9 | 216 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
ee9ae257 DH |
217 | xstate_offsets[i] = ebx; |
218 | xstate_sizes[i] = eax; | |
e6e888f9 DH |
219 | /* |
220 | * In our xstate size checks, we assume that the | |
221 | * highest-numbered xstate feature has the | |
222 | * highest offset in the buffer. Ensure it does. | |
223 | */ | |
224 | WARN_ONCE(last_good_offset > xstate_offsets[i], | |
225 | "x86/fpu: misordered xstate at %d\n", last_good_offset); | |
226 | last_good_offset = xstate_offsets[i]; | |
a1488f8b | 227 | |
ee9ae257 | 228 | printk(KERN_INFO "x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n", i, ebx, i, eax); |
39f1acd2 | 229 | } |
a1488f8b SS |
230 | } |
231 | ||
32231879 | 232 | static void __init print_xstate_feature(u64 xstate_mask) |
69496e10 | 233 | { |
33588b52 | 234 | const char *feature_name; |
69496e10 | 235 | |
33588b52 IM |
236 | if (cpu_has_xfeatures(xstate_mask, &feature_name)) |
237 | pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name); | |
69496e10 IM |
238 | } |
239 | ||
240 | /* | |
241 | * Print out all the supported xstate features: | |
242 | */ | |
32231879 | 243 | static void __init print_xstate_features(void) |
69496e10 | 244 | { |
d91cab78 DH |
245 | print_xstate_feature(XFEATURE_MASK_FP); |
246 | print_xstate_feature(XFEATURE_MASK_SSE); | |
247 | print_xstate_feature(XFEATURE_MASK_YMM); | |
248 | print_xstate_feature(XFEATURE_MASK_BNDREGS); | |
249 | print_xstate_feature(XFEATURE_MASK_BNDCSR); | |
250 | print_xstate_feature(XFEATURE_MASK_OPMASK); | |
251 | print_xstate_feature(XFEATURE_MASK_ZMM_Hi256); | |
252 | print_xstate_feature(XFEATURE_MASK_Hi16_ZMM); | |
69496e10 IM |
253 | } |
254 | ||
7496d645 FY |
255 | /* |
256 | * This function sets up offsets and sizes of all extended states in | |
257 | * xsave area. This supports both standard format and compacted format | |
258 | * of the xsave aread. | |
7496d645 | 259 | */ |
32231879 | 260 | static void __init setup_xstate_comp(void) |
7496d645 | 261 | { |
614df7fb | 262 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
263 | int i; |
264 | ||
8ff925e1 FY |
265 | /* |
266 | * The FP xstates and SSE xstates are legacy states. They are always | |
267 | * in the fixed offsets in the xsave area in either compacted form | |
268 | * or standard form. | |
269 | */ | |
270 | xstate_comp_offsets[0] = 0; | |
c47ada30 | 271 | xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space); |
7496d645 FY |
272 | |
273 | if (!cpu_has_xsaves) { | |
ee9ae257 | 274 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { |
633d54c4 | 275 | if (xfeature_enabled(i)) { |
7496d645 FY |
276 | xstate_comp_offsets[i] = xstate_offsets[i]; |
277 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
278 | } | |
279 | } | |
280 | return; | |
281 | } | |
282 | ||
8a93c9e0 DH |
283 | xstate_comp_offsets[FIRST_EXTENDED_XFEATURE] = |
284 | FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
7496d645 | 285 | |
ee9ae257 | 286 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { |
633d54c4 | 287 | if (xfeature_enabled(i)) |
7496d645 FY |
288 | xstate_comp_sizes[i] = xstate_sizes[i]; |
289 | else | |
290 | xstate_comp_sizes[i] = 0; | |
291 | ||
8a93c9e0 | 292 | if (i > FIRST_EXTENDED_XFEATURE) |
7496d645 FY |
293 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] |
294 | + xstate_comp_sizes[i-1]; | |
295 | ||
296 | } | |
297 | } | |
298 | ||
dc1e35c6 SS |
299 | /* |
300 | * setup the xstate image representing the init state | |
301 | */ | |
32231879 | 302 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 303 | { |
e49a449b | 304 | static int on_boot_cpu __initdata = 1; |
e97131a8 IM |
305 | |
306 | WARN_ON_FPU(!on_boot_cpu); | |
307 | on_boot_cpu = 0; | |
308 | ||
5d2bd700 SS |
309 | if (!cpu_has_xsave) |
310 | return; | |
311 | ||
312 | setup_xstate_features(); | |
69496e10 | 313 | print_xstate_features(); |
a1488f8b | 314 | |
47c2f292 | 315 | if (cpu_has_xsaves) { |
6f575023 IM |
316 | init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
317 | init_fpstate.xsave.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
318 | } |
319 | ||
29104e10 SS |
320 | /* |
321 | * Init all the features state with header_bv being 0x0 | |
322 | */ | |
d65fcd60 | 323 | copy_kernel_to_xregs_booting(&init_fpstate.xsave); |
3e261c14 | 324 | |
29104e10 SS |
325 | /* |
326 | * Dump the init state again. This is to identify the init state | |
327 | * of any feature which is not represented by all zero's. | |
328 | */ | |
c6813144 | 329 | copy_xregs_to_kernel_booting(&init_fpstate.xsave); |
dc1e35c6 SS |
330 | } |
331 | ||
65ac2e9b DH |
332 | static int xfeature_is_supervisor(int xfeature_nr) |
333 | { | |
334 | /* | |
335 | * We currently do not support supervisor states, but if | |
336 | * we did, we could find out like this. | |
337 | * | |
338 | * SDM says: If state component i is a user state component, | |
339 | * ECX[0] return 0; if state component i is a supervisor | |
340 | * state component, ECX[0] returns 1. | |
341 | u32 eax, ebx, ecx, edx; | |
342 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx; | |
343 | return !!(ecx & 1); | |
344 | */ | |
345 | return 0; | |
346 | } | |
347 | /* | |
348 | static int xfeature_is_user(int xfeature_nr) | |
349 | { | |
350 | return !xfeature_is_supervisor(xfeature_nr); | |
351 | } | |
352 | */ | |
353 | ||
354 | /* | |
355 | * This check is important because it is easy to get XSTATE_* | |
356 | * confused with XSTATE_BIT_*. | |
357 | */ | |
358 | #define CHECK_XFEATURE(nr) do { \ | |
359 | WARN_ON(nr < FIRST_EXTENDED_XFEATURE); \ | |
360 | WARN_ON(nr >= XFEATURE_MAX); \ | |
361 | } while (0) | |
362 | ||
363 | /* | |
364 | * We could cache this like xstate_size[], but we only use | |
365 | * it here, so it would be a waste of space. | |
366 | */ | |
367 | static int xfeature_is_aligned(int xfeature_nr) | |
368 | { | |
369 | u32 eax, ebx, ecx, edx; | |
370 | ||
371 | CHECK_XFEATURE(xfeature_nr); | |
372 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); | |
373 | /* | |
374 | * The value returned by ECX[1] indicates the alignment | |
375 | * of state component i when the compacted format | |
376 | * of the extended region of an XSAVE area is used | |
377 | */ | |
378 | return !!(ecx & 2); | |
379 | } | |
380 | ||
381 | static int xfeature_uncompacted_offset(int xfeature_nr) | |
382 | { | |
383 | u32 eax, ebx, ecx, edx; | |
384 | ||
385 | CHECK_XFEATURE(xfeature_nr); | |
386 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); | |
387 | return ebx; | |
388 | } | |
389 | ||
390 | static int xfeature_size(int xfeature_nr) | |
391 | { | |
392 | u32 eax, ebx, ecx, edx; | |
393 | ||
394 | CHECK_XFEATURE(xfeature_nr); | |
395 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); | |
396 | return eax; | |
397 | } | |
398 | ||
399 | /* | |
400 | * 'XSAVES' implies two different things: | |
401 | * 1. saving of supervisor/system state | |
402 | * 2. using the compacted format | |
403 | * | |
404 | * Use this function when dealing with the compacted format so | |
405 | * that it is obvious which aspect of 'XSAVES' is being handled | |
406 | * by the calling code. | |
407 | */ | |
408 | static int using_compacted_format(void) | |
409 | { | |
410 | return cpu_has_xsaves; | |
411 | } | |
412 | ||
413 | static void __xstate_dump_leaves(void) | |
414 | { | |
415 | int i; | |
416 | u32 eax, ebx, ecx, edx; | |
417 | static int should_dump = 1; | |
418 | ||
419 | if (!should_dump) | |
420 | return; | |
421 | should_dump = 0; | |
422 | /* | |
423 | * Dump out a few leaves past the ones that we support | |
424 | * just in case there are some goodies up there | |
425 | */ | |
426 | for (i = 0; i < XFEATURE_MAX + 10; i++) { | |
427 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); | |
428 | pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n", | |
429 | XSTATE_CPUID, i, eax, ebx, ecx, edx); | |
430 | } | |
431 | } | |
432 | ||
433 | #define XSTATE_WARN_ON(x) do { \ | |
434 | if (WARN_ONCE(x, "XSAVE consistency problem, dumping leaves")) { \ | |
435 | __xstate_dump_leaves(); \ | |
436 | } \ | |
437 | } while (0) | |
438 | ||
ef78f2a4 DH |
439 | #define XCHECK_SZ(sz, nr, nr_macro, __struct) do { \ |
440 | if ((nr == nr_macro) && \ | |
441 | WARN_ONCE(sz != sizeof(__struct), \ | |
442 | "%s: struct is %zu bytes, cpu state %d bytes\n", \ | |
443 | __stringify(nr_macro), sizeof(__struct), sz)) { \ | |
444 | __xstate_dump_leaves(); \ | |
445 | } \ | |
446 | } while (0) | |
447 | ||
448 | /* | |
449 | * We have a C struct for each 'xstate'. We need to ensure | |
450 | * that our software representation matches what the CPU | |
451 | * tells us about the state's size. | |
452 | */ | |
453 | static void check_xstate_against_struct(int nr) | |
454 | { | |
455 | /* | |
456 | * Ask the CPU for the size of the state. | |
457 | */ | |
458 | int sz = xfeature_size(nr); | |
459 | /* | |
460 | * Match each CPU state with the corresponding software | |
461 | * structure. | |
462 | */ | |
463 | XCHECK_SZ(sz, nr, XFEATURE_YMM, struct ymmh_struct); | |
464 | XCHECK_SZ(sz, nr, XFEATURE_BNDREGS, struct mpx_bndreg_state); | |
465 | XCHECK_SZ(sz, nr, XFEATURE_BNDCSR, struct mpx_bndcsr_state); | |
466 | XCHECK_SZ(sz, nr, XFEATURE_OPMASK, struct avx_512_opmask_state); | |
467 | XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state); | |
468 | XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state); | |
469 | ||
470 | /* | |
471 | * Make *SURE* to add any feature numbers in below if | |
472 | * there are "holes" in the xsave state component | |
473 | * numbers. | |
474 | */ | |
475 | if ((nr < XFEATURE_YMM) || | |
476 | (nr >= XFEATURE_MAX)) { | |
477 | WARN_ONCE(1, "no structure for xstate: %d\n", nr); | |
478 | XSTATE_WARN_ON(1); | |
479 | } | |
480 | } | |
481 | ||
65ac2e9b DH |
482 | /* |
483 | * This essentially double-checks what the cpu told us about | |
484 | * how large the XSAVE buffer needs to be. We are recalculating | |
485 | * it to be safe. | |
486 | */ | |
487 | static void do_extra_xstate_size_checks(void) | |
488 | { | |
489 | int paranoid_xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
490 | int i; | |
491 | ||
492 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { | |
493 | if (!xfeature_enabled(i)) | |
494 | continue; | |
ef78f2a4 DH |
495 | |
496 | check_xstate_against_struct(i); | |
65ac2e9b DH |
497 | /* |
498 | * Supervisor state components can be managed only by | |
499 | * XSAVES, which is compacted-format only. | |
500 | */ | |
501 | if (!using_compacted_format()) | |
502 | XSTATE_WARN_ON(xfeature_is_supervisor(i)); | |
503 | ||
504 | /* Align from the end of the previous feature */ | |
505 | if (xfeature_is_aligned(i)) | |
506 | paranoid_xstate_size = ALIGN(paranoid_xstate_size, 64); | |
507 | /* | |
508 | * The offset of a given state in the non-compacted | |
509 | * format is given to us in a CPUID leaf. We check | |
510 | * them for being ordered (increasing offsets) in | |
511 | * setup_xstate_features(). | |
512 | */ | |
513 | if (!using_compacted_format()) | |
514 | paranoid_xstate_size = xfeature_uncompacted_offset(i); | |
515 | /* | |
516 | * The compacted-format offset always depends on where | |
517 | * the previous state ended. | |
518 | */ | |
519 | paranoid_xstate_size += xfeature_size(i); | |
520 | } | |
521 | XSTATE_WARN_ON(paranoid_xstate_size != xstate_size); | |
522 | } | |
523 | ||
7e7ce87f | 524 | /* |
614df7fb | 525 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
65ac2e9b DH |
526 | * |
527 | * Note the SDM's wording here. "sub-function 0" only enumerates | |
528 | * the size of the *user* states. If we use it to size a buffer | |
529 | * that we use 'XSAVES' on, we could potentially overflow the | |
530 | * buffer because 'XSAVES' saves system states too. | |
531 | * | |
532 | * Note that we do not currently set any bits on IA32_XSS so | |
533 | * 'XCR0 | IA32_XSS == XCR0' for now. | |
7e7ce87f | 534 | */ |
4109ca06 | 535 | static unsigned int __init calculate_xstate_size(void) |
7e7ce87f FY |
536 | { |
537 | unsigned int eax, ebx, ecx, edx; | |
4109ca06 | 538 | unsigned int calculated_xstate_size; |
7e7ce87f FY |
539 | |
540 | if (!cpu_has_xsaves) { | |
65ac2e9b DH |
541 | /* |
542 | * - CPUID function 0DH, sub-function 0: | |
543 | * EBX enumerates the size (in bytes) required by | |
544 | * the XSAVE instruction for an XSAVE area | |
545 | * containing all the *user* state components | |
546 | * corresponding to bits currently set in XCR0. | |
547 | */ | |
7e7ce87f | 548 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); |
4109ca06 | 549 | calculated_xstate_size = ebx; |
65ac2e9b DH |
550 | } else { |
551 | /* | |
552 | * - CPUID function 0DH, sub-function 1: | |
553 | * EBX enumerates the size (in bytes) required by | |
554 | * the XSAVES instruction for an XSAVE area | |
555 | * containing all the state components | |
556 | * corresponding to bits currently set in | |
557 | * XCR0 | IA32_XSS. | |
558 | */ | |
559 | cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx); | |
560 | calculated_xstate_size = ebx; | |
7e7ce87f | 561 | } |
4109ca06 DH |
562 | return calculated_xstate_size; |
563 | } | |
564 | ||
565 | /* | |
566 | * Will the runtime-enumerated 'xstate_size' fit in the init | |
567 | * task's statically-allocated buffer? | |
568 | */ | |
569 | static bool is_supported_xstate_size(unsigned int test_xstate_size) | |
570 | { | |
571 | if (test_xstate_size <= sizeof(union fpregs_state)) | |
572 | return true; | |
573 | ||
574 | pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n", | |
575 | sizeof(union fpregs_state), test_xstate_size); | |
576 | return false; | |
577 | } | |
578 | ||
579 | static int init_xstate_size(void) | |
580 | { | |
581 | /* Recompute the context size for enabled features: */ | |
582 | unsigned int possible_xstate_size = calculate_xstate_size(); | |
583 | ||
584 | /* Ensure we have the space to store all enabled: */ | |
585 | if (!is_supported_xstate_size(possible_xstate_size)) | |
586 | return -EINVAL; | |
587 | ||
588 | /* | |
589 | * The size is OK, we are definitely going to use xsave, | |
590 | * make it known to the world that we need more space. | |
591 | */ | |
592 | xstate_size = possible_xstate_size; | |
65ac2e9b | 593 | do_extra_xstate_size_checks(); |
4109ca06 DH |
594 | return 0; |
595 | } | |
596 | ||
d91cab78 DH |
597 | /* |
598 | * We enabled the XSAVE hardware, but something went wrong and | |
599 | * we can not use it. Disable it. | |
600 | */ | |
601 | static void fpu__init_disable_system_xstate(void) | |
4109ca06 DH |
602 | { |
603 | xfeatures_mask = 0; | |
604 | cr4_clear_bits(X86_CR4_OSXSAVE); | |
605 | fpu__xstate_clear_all_cpu_caps(); | |
7e7ce87f FY |
606 | } |
607 | ||
dc1e35c6 SS |
608 | /* |
609 | * Enable and initialize the xsave feature. | |
55cc4678 | 610 | * Called once per system bootup. |
dc1e35c6 | 611 | */ |
32231879 | 612 | void __init fpu__init_system_xstate(void) |
dc1e35c6 SS |
613 | { |
614 | unsigned int eax, ebx, ecx, edx; | |
e49a449b | 615 | static int on_boot_cpu __initdata = 1; |
4109ca06 | 616 | int err; |
e97131a8 IM |
617 | |
618 | WARN_ON_FPU(!on_boot_cpu); | |
619 | on_boot_cpu = 0; | |
dc1e35c6 | 620 | |
e9dbfd67 IM |
621 | if (!cpu_has_xsave) { |
622 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
623 | return; | |
624 | } | |
625 | ||
ee813d53 | 626 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
e97131a8 | 627 | WARN_ON_FPU(1); |
ee813d53 RR |
628 | return; |
629 | } | |
630 | ||
631 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 632 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 633 | |
d91cab78 | 634 | if ((xfeatures_mask & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) { |
614df7fb | 635 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); |
dc1e35c6 SS |
636 | BUG(); |
637 | } | |
638 | ||
a5fe93a5 | 639 | xfeatures_mask &= fpu__get_supported_xfeatures_mask(); |
97e80a70 | 640 | |
55cc4678 IM |
641 | /* Enable xstate instructions to be able to continue with initialization: */ |
642 | fpu__init_cpu_xstate(); | |
4109ca06 DH |
643 | err = init_xstate_size(); |
644 | if (err) { | |
645 | /* something went wrong, boot without any XSAVE support */ | |
646 | fpu__init_disable_system_xstate(); | |
647 | return; | |
648 | } | |
dc1e35c6 | 649 | |
614df7fb | 650 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
b992c660 | 651 | fpu__init_prepare_fx_sw_frame(); |
5d2bd700 | 652 | setup_init_fpu_buf(); |
5fd402df | 653 | setup_xstate_comp(); |
dc1e35c6 | 654 | |
b0815359 | 655 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n", |
614df7fb | 656 | xfeatures_mask, |
32d4d9cc IM |
657 | xstate_size, |
658 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 659 | } |
82d4150c | 660 | |
9254aaa0 IM |
661 | /* |
662 | * Restore minimal FPU state after suspend: | |
663 | */ | |
664 | void fpu__resume_cpu(void) | |
665 | { | |
666 | /* | |
667 | * Restore XCR0 on xsave capable CPUs: | |
668 | */ | |
669 | if (cpu_has_xsave) | |
670 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
671 | } | |
672 | ||
7496d645 FY |
673 | /* |
674 | * Given the xsave area and a state inside, this function returns the | |
675 | * address of the state. | |
676 | * | |
677 | * This is the API that is called to get xstate address in either | |
678 | * standard format or compacted format of xsave area. | |
679 | * | |
0c4109be DH |
680 | * Note that if there is no data for the field in the xsave buffer |
681 | * this will return NULL. | |
682 | * | |
7496d645 | 683 | * Inputs: |
0c4109be DH |
684 | * xstate: the thread's storage area for all FPU data |
685 | * xstate_feature: state which is defined in xsave.h (e.g. | |
d91cab78 | 686 | * XFEATURE_MASK_FP, XFEATURE_MASK_SSE, etc...) |
7496d645 | 687 | * Output: |
0c4109be DH |
688 | * address of the state in the xsave area, or NULL if the |
689 | * field is not present in the xsave buffer. | |
7496d645 | 690 | */ |
0c4109be | 691 | void *get_xsave_addr(struct xregs_state *xsave, int xstate_feature) |
7496d645 | 692 | { |
0c4109be DH |
693 | int feature_nr = fls64(xstate_feature) - 1; |
694 | /* | |
695 | * Do we even *have* xsave state? | |
696 | */ | |
697 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) | |
698 | return NULL; | |
699 | ||
0c4109be DH |
700 | /* |
701 | * We should not ever be requesting features that we | |
702 | * have not enabled. Remember that pcntxt_mask is | |
703 | * what we write to the XCR0 register. | |
704 | */ | |
705 | WARN_ONCE(!(xfeatures_mask & xstate_feature), | |
706 | "get of unsupported state"); | |
707 | /* | |
708 | * This assumes the last 'xsave*' instruction to | |
709 | * have requested that 'xstate_feature' be saved. | |
710 | * If it did not, we might be seeing and old value | |
711 | * of the field in the buffer. | |
712 | * | |
713 | * This can happen because the last 'xsave' did not | |
714 | * request that this feature be saved (unlikely) | |
715 | * or because the "init optimization" caused it | |
716 | * to not be saved. | |
717 | */ | |
718 | if (!(xsave->header.xfeatures & xstate_feature)) | |
7496d645 FY |
719 | return NULL; |
720 | ||
0c4109be | 721 | return (void *)xsave + xstate_comp_offsets[feature_nr]; |
7496d645 | 722 | } |
ba7b3920 | 723 | EXPORT_SYMBOL_GPL(get_xsave_addr); |
04cd027b DH |
724 | |
725 | /* | |
726 | * This wraps up the common operations that need to occur when retrieving | |
727 | * data from xsave state. It first ensures that the current task was | |
728 | * using the FPU and retrieves the data in to a buffer. It then calculates | |
729 | * the offset of the requested field in the buffer. | |
730 | * | |
731 | * This function is safe to call whether the FPU is in use or not. | |
732 | * | |
733 | * Note that this only works on the current task. | |
734 | * | |
735 | * Inputs: | |
d91cab78 DH |
736 | * @xsave_state: state which is defined in xsave.h (e.g. XFEATURE_MASK_FP, |
737 | * XFEATURE_MASK_SSE, etc...) | |
04cd027b DH |
738 | * Output: |
739 | * address of the state in the xsave area or NULL if the state | |
740 | * is not present or is in its 'init state'. | |
741 | */ | |
742 | const void *get_xsave_field_ptr(int xsave_state) | |
743 | { | |
744 | struct fpu *fpu = ¤t->thread.fpu; | |
745 | ||
746 | if (!fpu->fpstate_active) | |
747 | return NULL; | |
748 | /* | |
749 | * fpu__save() takes the CPU's xstate registers | |
750 | * and saves them off to the 'fpu memory buffer. | |
751 | */ | |
752 | fpu__save(fpu); | |
753 | ||
754 | return get_xsave_addr(&fpu->state.xsave, xsave_state); | |
755 | } |