[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_p6.c

#include <linux/perf_event.h>
#include <linux/types.h>

#include "perf_event.h"

/*
 * Not sure about some of these
 */
static const u64 p6_perfmon_event_map[] =
{
  [PERF_COUNT_HW_CPU_CYCLES]		= 0x0079,	/* CPU_CLK_UNHALTED */
  [PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,	/* INST_RETIRED     */
  [PERF_COUNT_HW_CACHE_REFERENCES]	= 0x0f2e,	/* L2_RQSTS:M:E:S:I */
  [PERF_COUNT_HW_CACHE_MISSES]		= 0x012e,	/* L2_RQSTS:I       */
  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,	/* BR_INST_RETIRED  */
  [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,	/* BR_MISS_PRED_RETIRED */
  [PERF_COUNT_HW_BUS_CYCLES]		= 0x0062,	/* BUS_DRDY_CLOCKS  */
  [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2,	/* RESOURCE_STALLS  */

};

static const u64 __initconst p6_hw_cache_event_ids
				[PERF_COUNT_HW_CACHE_MAX]
				[PERF_COUNT_HW_CACHE_OP_MAX]
				[PERF_COUNT_HW_CACHE_RESULT_MAX] =
{
 [ C(L1D) ] = {
	[ C(OP_READ) ] = {
		[ C(RESULT_ACCESS) ] = 0x0043,	/* DATA_MEM_REFS       */
                [ C(RESULT_MISS)   ] = 0x0045,	/* DCU_LINES_IN        */
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0x0f29,	/* L2_LD:M:E:S:I       */
	},
        [ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0,
        },
 },
 [ C(L1I ) ] = {
	[ C(OP_READ) ] = {
		[ C(RESULT_ACCESS) ] = 0x0080,	/* IFU_IFETCH         */
		[ C(RESULT_MISS)   ] = 0x0f28,	/* L2_IFETCH:M:E:S:I  */
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = -1,
		[ C(RESULT_MISS)   ] = -1,
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0,
	},
 },
 [ C(LL  ) ] = {
	[ C(OP_READ) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0,
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0x0025,	/* L2_M_LINES_INM     */
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0,
	},
 },
 [ C(DTLB) ] = {
	[ C(OP_READ) ] = {
		[ C(RESULT_ACCESS) ] = 0x0043,	/* DATA_MEM_REFS      */
		[ C(RESULT_MISS)   ] = 0,
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0,
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = 0,
		[ C(RESULT_MISS)   ] = 0,
	},
 },
 [ C(ITLB) ] = {
	[ C(OP_READ) ] = {
		[ C(RESULT_ACCESS) ] = 0x0080,	/* IFU_IFETCH         */
		[ C(RESULT_MISS)   ] = 0x0085,	/* ITLB_MISS          */
	},
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = -1,
		[ C(RESULT_MISS)   ] = -1,
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = -1,
		[ C(RESULT_MISS)   ] = -1,
	},
 },
 [ C(BPU ) ] = {
	[ C(OP_READ) ] = {
		[ C(RESULT_ACCESS) ] = 0x00c4,	/* BR_INST_RETIRED      */
		[ C(RESULT_MISS)   ] = 0x00c5,	/* BR_MISS_PRED_RETIRED */
        },
	[ C(OP_WRITE) ] = {
		[ C(RESULT_ACCESS) ] = -1,
		[ C(RESULT_MISS)   ] = -1,
	},
	[ C(OP_PREFETCH) ] = {
		[ C(RESULT_ACCESS) ] = -1,
		[ C(RESULT_MISS)   ] = -1,
	},
 },
};

static u64 p6_pmu_event_map(int hw_event)
{
	return p6_perfmon_event_map[hw_event];
}

/*
 * Event setting that is specified not to count anything.
 * We use this to effectively disable a counter.
 *
 * L2_RQSTS with 0 MESI unit mask.
 */
#define P6_NOP_EVENT			0x0000002EULL

static struct event_constraint p6_event_constraints[] =
{
	INTEL_EVENT_CONSTRAINT(0xc1, 0x1),	/* FLOPS */
	INTEL_EVENT_CONSTRAINT(0x10, 0x1),	/* FP_COMP_OPS_EXE */
	INTEL_EVENT_CONSTRAINT(0x11, 0x2),	/* FP_ASSIST */
	INTEL_EVENT_CONSTRAINT(0x12, 0x2),	/* MUL */
	INTEL_EVENT_CONSTRAINT(0x13, 0x2),	/* DIV */
	INTEL_EVENT_CONSTRAINT(0x14, 0x1),	/* CYCLES_DIV_BUSY */
	EVENT_CONSTRAINT_END
};

static void p6_pmu_disable_all(void)
{
	u64 val;

	/* p6 only has one enable register */
	rdmsrl(MSR_P6_EVNTSEL0, val);
	val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
	wrmsrl(MSR_P6_EVNTSEL0, val);
}

static void p6_pmu_enable_all(int added)
{
	unsigned long val;

	/* p6 only has one enable register */
	rdmsrl(MSR_P6_EVNTSEL0, val);
	val |= ARCH_PERFMON_EVENTSEL_ENABLE;
	wrmsrl(MSR_P6_EVNTSEL0, val);
}

static inline void
p6_pmu_disable_event(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;
	u64 val = P6_NOP_EVENT;

	(void)wrmsrl_safe(hwc->config_base, val);
}

static void p6_pmu_enable_event(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;
	u64 val;

	val = hwc->config;

	/*
	 * p6 only has a global event enable, set on PerfEvtSel0
	 * We "disable" events by programming P6_NOP_EVENT
	 * and we rely on p6_pmu_enable_all() being called
	 * to actually enable the events.
	 */

	(void)wrmsrl_safe(hwc->config_base, val);
}

PMU_FORMAT_ATTR(event,	"config:0-7"	);
PMU_FORMAT_ATTR(umask,	"config:8-15"	);
PMU_FORMAT_ATTR(edge,	"config:18"	);
PMU_FORMAT_ATTR(pc,	"config:19"	);
PMU_FORMAT_ATTR(inv,	"config:23"	);
PMU_FORMAT_ATTR(cmask,	"config:24-31"	);

static struct attribute *intel_p6_formats_attr[] = {
	&format_attr_event.attr,
	&format_attr_umask.attr,
	&format_attr_edge.attr,
	&format_attr_pc.attr,
	&format_attr_inv.attr,
	&format_attr_cmask.attr,
	NULL,
};

static __initconst const struct x86_pmu p6_pmu = {
	.name			= "p6",
	.handle_irq		= x86_pmu_handle_irq,
	.disable_all		= p6_pmu_disable_all,
	.enable_all		= p6_pmu_enable_all,
	.enable			= p6_pmu_enable_event,
	.disable		= p6_pmu_disable_event,
	.hw_config		= x86_pmu_hw_config,
	.schedule_events	= x86_schedule_events,
	.eventsel		= MSR_P6_EVNTSEL0,
	.perfctr		= MSR_P6_PERFCTR0,
	.event_map		= p6_pmu_event_map,
	.max_events		= ARRAY_SIZE(p6_perfmon_event_map),
	.apic			= 1,
	.max_period		= (1ULL << 31) - 1,
	.version		= 0,
	.num_counters		= 2,
	/*
	 * Events have 40 bits implemented. However they are designed such
	 * that bits [32-39] are sign extensions of bit 31. As such the
	 * effective width of a event for P6-like PMU is 32 bits only.
	 *
	 * See IA-32 Intel Architecture Software developer manual Vol 3B
	 */
	.cntval_bits		= 32,
	.cntval_mask		= (1ULL << 32) - 1,
	.get_event_constraints	= x86_get_event_constraints,
	.event_constraints	= p6_event_constraints,

	.format_attrs		= intel_p6_formats_attr,
	.events_sysfs_show	= intel_event_sysfs_show,

};

static __init void p6_pmu_rdpmc_quirk(void)
{
	if (boot_cpu_data.x86_mask < 9) {
		/*
		 * PPro erratum 26; fixed in stepping 9 and above.
		 */
		pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
		x86_pmu.attr_rdpmc_broken = 1;
		x86_pmu.attr_rdpmc = 0;
	}
}

__init int p6_pmu_init(void)
{
	x86_pmu = p6_pmu;

	switch (boot_cpu_data.x86_model) {
	case  1: /* Pentium Pro */
		x86_add_quirk(p6_pmu_rdpmc_quirk);
		break;

	case  3: /* Pentium II - Klamath */
	case  5: /* Pentium II - Deschutes */
	case  6: /* Pentium II - Mendocino */
		break;

	case  7: /* Pentium III - Katmai */
	case  8: /* Pentium III - Coppermine */
	case 10: /* Pentium III Xeon */
	case 11: /* Pentium III - Tualatin */
		break;

	case  9: /* Pentium M - Banias */
	case 13: /* Pentium M - Dothan */
		break;

	default:
		pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
		return -ENODEV;
	}

	memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
		sizeof(hw_cache_event_ids));

	return 0;
}
Commit	Line	Data
de0428a7 KW	1	#include <linux/perf_event.h>
	2	#include <linux/types.h>
	3
	4	#include "perf_event.h"
f22f54f4 PZ	5
	6	/*
	7	* Not sure about some of these
	8	*/
	9	static const u64 p6_perfmon_event_map[] =
	10	{
e09df478 VW	11	[PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */
	12	[PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */
	13	[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */
	14	[PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */
	15	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */
	16	[PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */
	17	[PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */
	18	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */
	19
	20	};
	21
c391c788	22	static const u64 __initconst p6_hw_cache_event_ids
e09df478 VW	23	[PERF_COUNT_HW_CACHE_MAX]
	24	[PERF_COUNT_HW_CACHE_OP_MAX]
	25	[PERF_COUNT_HW_CACHE_RESULT_MAX] =
	26	{
	27	[ C(L1D) ] = {
	28	[ C(OP_READ) ] = {
	29	[ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
	30	[ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
	31	},
	32	[ C(OP_WRITE) ] = {
	33	[ C(RESULT_ACCESS) ] = 0,
	34	[ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
	35	},
	36	[ C(OP_PREFETCH) ] = {
	37	[ C(RESULT_ACCESS) ] = 0,
	38	[ C(RESULT_MISS) ] = 0,
	39	},
	40	},
	41	[ C(L1I ) ] = {
	42	[ C(OP_READ) ] = {
	43	[ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
	44	[ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */
	45	},
	46	[ C(OP_WRITE) ] = {
	47	[ C(RESULT_ACCESS) ] = -1,
	48	[ C(RESULT_MISS) ] = -1,
	49	},
	50	[ C(OP_PREFETCH) ] = {
	51	[ C(RESULT_ACCESS) ] = 0,
	52	[ C(RESULT_MISS) ] = 0,
	53	},
	54	},
	55	[ C(LL ) ] = {
	56	[ C(OP_READ) ] = {
	57	[ C(RESULT_ACCESS) ] = 0,
	58	[ C(RESULT_MISS) ] = 0,
	59	},
	60	[ C(OP_WRITE) ] = {
	61	[ C(RESULT_ACCESS) ] = 0,
	62	[ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */
	63	},
	64	[ C(OP_PREFETCH) ] = {
	65	[ C(RESULT_ACCESS) ] = 0,
	66	[ C(RESULT_MISS) ] = 0,
	67	},
	68	},
	69	[ C(DTLB) ] = {
	70	[ C(OP_READ) ] = {
	71	[ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
	72	[ C(RESULT_MISS) ] = 0,
	73	},
	74	[ C(OP_WRITE) ] = {
	75	[ C(RESULT_ACCESS) ] = 0,
	76	[ C(RESULT_MISS) ] = 0,
	77	},
	78	[ C(OP_PREFETCH) ] = {
	79	[ C(RESULT_ACCESS) ] = 0,
	80	[ C(RESULT_MISS) ] = 0,
	81	},
	82	},
	83	[ C(ITLB) ] = {
	84	[ C(OP_READ) ] = {
	85	[ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
	86	[ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */
87	},
88	[ C(OP_WRITE) ] = {
89	[ C(RESULT_ACCESS) ] = -1,
90	[ C(RESULT_MISS) ] = -1,
91	},
92	[ C(OP_PREFETCH) ] = {
93	[ C(RESULT_ACCESS) ] = -1,
94	[ C(RESULT_MISS) ] = -1,
95	},
96	},
97	[ C(BPU ) ] = {
98	[ C(OP_READ) ] = {
99	[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */
100	[ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */
101	},
102	[ C(OP_WRITE) ] = {
103	[ C(RESULT_ACCESS) ] = -1,
104	[ C(RESULT_MISS) ] = -1,
105	},
106	[ C(OP_PREFETCH) ] = {
107	[ C(RESULT_ACCESS) ] = -1,
108	[ C(RESULT_MISS) ] = -1,
109	},
110	},
f22f54f4 PZ	111	};
	112
	113	static u64 p6_pmu_event_map(int hw_event)
	114	{
	115	return p6_perfmon_event_map[hw_event];
	116	}
	117
	118	/*
	119	* Event setting that is specified not to count anything.
	120	* We use this to effectively disable a counter.
	121	*
	122	* L2_RQSTS with 0 MESI unit mask.
	123	*/
	124	#define P6_NOP_EVENT 0x0000002EULL
	125
f22f54f4 PZ	126	static struct event_constraint p6_event_constraints[] =
	127	{
	128	INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
	129	INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
7991c9ca	130	INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
f22f54f4 PZ	131	INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
	132	INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
	133	INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
	134	EVENT_CONSTRAINT_END
	135	};
	136
	137	static void p6_pmu_disable_all(void)
	138	{
	139	u64 val;
	140
	141	/* p6 only has one enable register */
	142	rdmsrl(MSR_P6_EVNTSEL0, val);
bb1165d6	143	val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
f22f54f4 PZ	144	wrmsrl(MSR_P6_EVNTSEL0, val);
	145	}
	146
11164cd4	147	static void p6_pmu_enable_all(int added)
f22f54f4 PZ	148	{
	149	unsigned long val;
	150
	151	/* p6 only has one enable register */
	152	rdmsrl(MSR_P6_EVNTSEL0, val);
bb1165d6	153	val \|= ARCH_PERFMON_EVENTSEL_ENABLE;
f22f54f4 PZ	154	wrmsrl(MSR_P6_EVNTSEL0, val);
	155	}
	156
	157	static inline void
aff3d91a	158	p6_pmu_disable_event(struct perf_event *event)
f22f54f4	159	{
aff3d91a	160	struct hw_perf_event *hwc = &event->hw;
f22f54f4 PZ	161	u64 val = P6_NOP_EVENT;
f22f54f4 PZ	162
715c85b1	163	(void)wrmsrl_safe(hwc->config_base, val);
f22f54f4 PZ	164	}
f22f54f4 PZ	165
aff3d91a	166	static void p6_pmu_enable_event(struct perf_event *event)
f22f54f4	167	{
aff3d91a	168	struct hw_perf_event *hwc = &event->hw;
f22f54f4 PZ	169	u64 val;
	170
	171	val = hwc->config;
58e9eaf0 VW	172
	173	/*
	174	* p6 only has a global event enable, set on PerfEvtSel0
	175	* We "disable" events by programming P6_NOP_EVENT
	176	* and we rely on p6_pmu_enable_all() being called
	177	* to actually enable the events.
	178	*/
f22f54f4	179
715c85b1	180	(void)wrmsrl_safe(hwc->config_base, val);
f22f54f4 PZ	181	}
f22f54f4 PZ	182
641cc938 JO	183	PMU_FORMAT_ATTR(event, "config:0-7" );
	184	PMU_FORMAT_ATTR(umask, "config:8-15" );
	185	PMU_FORMAT_ATTR(edge, "config:18" );
	186	PMU_FORMAT_ATTR(pc, "config:19" );
	187	PMU_FORMAT_ATTR(inv, "config:23" );
	188	PMU_FORMAT_ATTR(cmask, "config:24-31" );
	189
	190	static struct attribute *intel_p6_formats_attr[] = {
	191	&format_attr_event.attr,
	192	&format_attr_umask.attr,
	193	&format_attr_edge.attr,
	194	&format_attr_pc.attr,
	195	&format_attr_inv.attr,
	196	&format_attr_cmask.attr,
	197	NULL,
	198	};
	199
caaa8be3	200	static __initconst const struct x86_pmu p6_pmu = {
f22f54f4 PZ	201	.name = "p6",
	202	.handle_irq = x86_pmu_handle_irq,
	203	.disable_all = p6_pmu_disable_all,
	204	.enable_all = p6_pmu_enable_all,
	205	.enable = p6_pmu_enable_event,
	206	.disable = p6_pmu_disable_event,
b4cdc5c2	207	.hw_config = x86_pmu_hw_config,
a072738e	208	.schedule_events = x86_schedule_events,
f22f54f4 PZ	209	.eventsel = MSR_P6_EVNTSEL0,
	210	.perfctr = MSR_P6_PERFCTR0,
	211	.event_map = p6_pmu_event_map,
f22f54f4 PZ	212	.max_events = ARRAY_SIZE(p6_perfmon_event_map),
	213	.apic = 1,
	214	.max_period = (1ULL << 31) - 1,
	215	.version = 0,
948b1bb8	216	.num_counters = 2,
f22f54f4 PZ	217	/*
	218	* Events have 40 bits implemented. However they are designed such
	219	* that bits [32-39] are sign extensions of bit 31. As such the
	220	* effective width of a event for P6-like PMU is 32 bits only.
	221	*
	222	* See IA-32 Intel Architecture Software developer manual Vol 3B
	223	*/
948b1bb8 RR	224	.cntval_bits = 32,
948b1bb8 RR	225	.cntval_mask = (1ULL << 32) - 1,
f22f54f4 PZ	226	.get_event_constraints = x86_get_event_constraints,
f22f54f4 PZ	227	.event_constraints = p6_event_constraints,
641cc938 JO	228
641cc938 JO	229	.format_attrs = intel_p6_formats_attr,
20550a43 JO	230	.events_sysfs_show = intel_event_sysfs_show,
20550a43 JO	231
f22f54f4 PZ	232	};
f22f54f4 PZ	233
e97df763 PZ	234	static __init void p6_pmu_rdpmc_quirk(void)
	235	{
	236	if (boot_cpu_data.x86_mask < 9) {
	237	/*
	238	* PPro erratum 26; fixed in stepping 9 and above.
	239	*/
	240	pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
	241	x86_pmu.attr_rdpmc_broken = 1;
	242	x86_pmu.attr_rdpmc = 0;
	243	}
	244	}
	245
de0428a7	246	__init int p6_pmu_init(void)
f22f54f4	247	{
e97df763 PZ	248	x86_pmu = p6_pmu;
e97df763 PZ	249
f22f54f4	250	switch (boot_cpu_data.x86_model) {
e97df763 PZ	251	case 1: /* Pentium Pro */
	252	x86_add_quirk(p6_pmu_rdpmc_quirk);
	253	break;
	254
	255	case 3: /* Pentium II - Klamath */
	256	case 5: /* Pentium II - Deschutes */
	257	case 6: /* Pentium II - Mendocino */
f22f54f4	258	break;
e97df763 PZ	259
	260	case 7: /* Pentium III - Katmai */
	261	case 8: /* Pentium III - Coppermine */
	262	case 10: /* Pentium III Xeon */
	263	case 11: /* Pentium III - Tualatin */
	264	break;
	265
	266	case 9: /* Pentium M - Banias */
	267	case 13: /* Pentium M - Dothan */
	268	break;
	269
f22f54f4	270	default:
e97df763	271	pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
f22f54f4 PZ	272	return -ENODEV;
	273	}
	274
e09df478 VW	275	memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
	276	sizeof(hw_cache_event_ids));
	277
f22f54f4 PZ	278	return 0;
f22f54f4 PZ	279	}