[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel_uncore.h

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/perf_event.h>
#include "perf_event.h"

#define UNCORE_PMU_NAME_LEN		32
#define UNCORE_PMU_HRTIMER_INTERVAL	(60LL * NSEC_PER_SEC)
#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)

#define UNCORE_FIXED_EVENT		0xff
#define UNCORE_PMC_IDX_MAX_GENERIC	8
#define UNCORE_PMC_IDX_FIXED		UNCORE_PMC_IDX_MAX_GENERIC
#define UNCORE_PMC_IDX_MAX		(UNCORE_PMC_IDX_FIXED + 1)

#define UNCORE_PCI_DEV_DATA(type, idx)	((type << 8) | idx)
#define UNCORE_PCI_DEV_TYPE(data)	((data >> 8) & 0xff)
#define UNCORE_PCI_DEV_IDX(data)	(data & 0xff)
#define UNCORE_EXTRA_PCI_DEV		0xff
#define UNCORE_EXTRA_PCI_DEV_MAX	3

/* support up to 8 sockets */
#define UNCORE_SOCKET_MAX		8

#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)

struct intel_uncore_ops;
struct intel_uncore_pmu;
struct intel_uncore_box;
struct uncore_event_desc;

struct intel_uncore_type {
	const char *name;
	int num_counters;
	int num_boxes;
	int perf_ctr_bits;
	int fixed_ctr_bits;
	unsigned perf_ctr;
	unsigned event_ctl;
	unsigned event_mask;
	unsigned fixed_ctr;
	unsigned fixed_ctl;
	unsigned box_ctl;
	unsigned msr_offset;
	unsigned num_shared_regs:8;
	unsigned single_fixed:1;
	unsigned pair_ctr_ctl:1;
	unsigned *msr_offsets;
	struct event_constraint unconstrainted;
	struct event_constraint *constraints;
	struct intel_uncore_pmu *pmus;
	struct intel_uncore_ops *ops;
	struct uncore_event_desc *event_descs;
	const struct attribute_group *attr_groups[4];
	struct pmu *pmu; /* for custom pmu ops */
};

#define pmu_group attr_groups[0]
#define format_group attr_groups[1]
#define events_group attr_groups[2]

struct intel_uncore_ops {
	void (*init_box)(struct intel_uncore_box *);
	void (*disable_box)(struct intel_uncore_box *);
	void (*enable_box)(struct intel_uncore_box *);
	void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
	void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
	u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
	int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
	struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
						   struct perf_event *);
	void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
};

struct intel_uncore_pmu {
	struct pmu pmu;
	char name[UNCORE_PMU_NAME_LEN];
	int pmu_idx;
	int func_id;
	struct intel_uncore_type *type;
	struct intel_uncore_box ** __percpu box;
	struct list_head box_list;
};

struct intel_uncore_extra_reg {
	raw_spinlock_t lock;
	u64 config, config1, config2;
	atomic_t ref;
};

struct intel_uncore_box {
	int phys_id;
	int n_active;	/* number of active events */
	int n_events;
	int cpu;	/* cpu to collect events */
	unsigned long flags;
	atomic_t refcnt;
	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
	u64 tags[UNCORE_PMC_IDX_MAX];
	struct pci_dev *pci_dev;
	struct intel_uncore_pmu *pmu;
	u64 hrtimer_duration; /* hrtimer timeout for this box */
	struct hrtimer hrtimer;
	struct list_head list;
	struct list_head active_list;
	void *io_addr;
	struct intel_uncore_extra_reg shared_regs[0];
};

#define UNCORE_BOX_FLAG_INITIATED	0

struct uncore_event_desc {
	struct kobj_attribute attr;
	const char *config;
};

ssize_t uncore_event_show(struct kobject *kobj,
			  struct kobj_attribute *attr, char *buf);

#define INTEL_UNCORE_EVENT_DESC(_name, _config)			\
{								\
	.attr	= __ATTR(_name, 0444, uncore_event_show, NULL),	\
	.config	= _config,					\
}

#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)			\
static ssize_t __uncore_##_var##_show(struct kobject *kobj,		\
				struct kobj_attribute *attr,		\
				char *page)				\
{									\
	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);			\
	return sprintf(page, _format "\n");				\
}									\
static struct kobj_attribute format_attr_##_var =			\
	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)

static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->box_ctl;
}

static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctl;
}

static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr;
}

static inline
unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
{
	return idx * 4 + box->pmu->type->event_ctl;
}

static inline
unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return idx * 8 + box->pmu->type->perf_ctr;
}

static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
{
	struct intel_uncore_pmu *pmu = box->pmu;
	return pmu->type->msr_offsets ?
		pmu->type->msr_offsets[pmu->pmu_idx] :
		pmu->type->msr_offset * pmu->pmu_idx;
}

static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->box_ctl)
		return 0;
	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->fixed_ctl)
		return 0;
	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->event_ctl +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->perf_ctr +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctl(box);
	else
		return uncore_msr_fixed_ctl(box);
}

static inline
unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctr(box);
	else
		return uncore_msr_fixed_ctr(box);
}

static inline
unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_event_ctl(box, idx);
	else
		return uncore_msr_event_ctl(box, idx);
}

static inline
unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_perf_ctr(box, idx);
	else
		return uncore_msr_perf_ctr(box, idx);
}

static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->perf_ctr_bits;
}

static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr_bits;
}

static inline int uncore_num_counters(struct intel_uncore_box *box)
{
	return box->pmu->type->num_counters;
}

static inline void uncore_box_init(struct intel_uncore_box *box)
{
	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->init_box)
			box->pmu->type->ops->init_box(box);
	}
}

static inline void uncore_disable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->disable_box)
		box->pmu->type->ops->disable_box(box);
}

static inline void uncore_enable_box(struct intel_uncore_box *box)
{
	uncore_box_init(box);

	if (box->pmu->type->ops->enable_box)
		box->pmu->type->ops->enable_box(box);
}

static inline void uncore_disable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->disable_event(box, event);
}

static inline void uncore_enable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->enable_event(box, event);
}

static inline u64 uncore_read_counter(struct intel_uncore_box *box,
				struct perf_event *event)
{
	return box->pmu->type->ops->read_counter(box, event);
}

static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
{
	return (box->phys_id < 0);
}

struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event);
struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
struct intel_uncore_box *uncore_event_to_box(struct perf_event *event);
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_event_read(struct perf_event *event);
void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
struct event_constraint *
uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);

extern struct intel_uncore_type **uncore_msr_uncores;
extern struct intel_uncore_type **uncore_pci_uncores;
extern struct pci_driver *uncore_pci_driver;
extern int uncore_pcibus_to_physid[256];
extern struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
extern struct event_constraint uncore_constraint_empty;

/* perf_event_intel_uncore_snb.c */
int snb_uncore_pci_init(void);
int ivb_uncore_pci_init(void);
int hsw_uncore_pci_init(void);
void snb_uncore_cpu_init(void);
void nhm_uncore_cpu_init(void);

/* perf_event_intel_uncore_snbep.c */
int snbep_uncore_pci_init(void);
void snbep_uncore_cpu_init(void);
int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);

/* perf_event_intel_uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
Commit	Line	Data
087bfbb0 YZ	1	#include <linux/module.h>
087bfbb0 YZ	2	#include <linux/slab.h>
14371cce	3	#include <linux/pci.h>
087bfbb0 YZ	4	#include <linux/perf_event.h>
	5	#include "perf_event.h"
	6
	7	#define UNCORE_PMU_NAME_LEN 32
7740dfc0	8	#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
ced2efb0	9	#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
087bfbb0	10
eca26c99	11	#define UNCORE_FIXED_EVENT 0xff
087bfbb0 YZ	12	#define UNCORE_PMC_IDX_MAX_GENERIC 8
	13	#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
	14	#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
	15
899396cf YZ	16	#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) \| idx)
	17	#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
	18	#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
	19	#define UNCORE_EXTRA_PCI_DEV 0xff
5306c31c	20	#define UNCORE_EXTRA_PCI_DEV_MAX 3
899396cf YZ	21
	22	/* support up to 8 sockets */
	23	#define UNCORE_SOCKET_MAX 8
	24
087bfbb0 YZ	25	#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
	26
	27	struct intel_uncore_ops;
	28	struct intel_uncore_pmu;
	29	struct intel_uncore_box;
	30	struct uncore_event_desc;
	31
	32	struct intel_uncore_type {
	33	const char *name;
	34	int num_counters;
	35	int num_boxes;
	36	int perf_ctr_bits;
	37	int fixed_ctr_bits;
087bfbb0 YZ	38	unsigned perf_ctr;
	39	unsigned event_ctl;
	40	unsigned event_mask;
	41	unsigned fixed_ctr;
	42	unsigned fixed_ctl;
	43	unsigned box_ctl;
	44	unsigned msr_offset;
6a67943a YZ	45	unsigned num_shared_regs:8;
6a67943a YZ	46	unsigned single_fixed:1;
254298c7	47	unsigned pair_ctr_ctl:1;
cb37af77	48	unsigned *msr_offsets;
087bfbb0 YZ	49	struct event_constraint unconstrainted;
	50	struct event_constraint *constraints;
	51	struct intel_uncore_pmu *pmus;
	52	struct intel_uncore_ops *ops;
	53	struct uncore_event_desc *event_descs;
314d9f63	54	const struct attribute_group *attr_groups[4];
d64b25b6	55	struct pmu pmu; / for custom pmu ops */
087bfbb0 YZ	56	};
087bfbb0 YZ	57
314d9f63 YZ	58	#define pmu_group attr_groups[0]
	59	#define format_group attr_groups[1]
	60	#define events_group attr_groups[2]
087bfbb0 YZ	61
	62	struct intel_uncore_ops {
	63	void (init_box)(struct intel_uncore_box );
	64	void (disable_box)(struct intel_uncore_box );
	65	void (enable_box)(struct intel_uncore_box );
	66	void (disable_event)(struct intel_uncore_box , struct perf_event *);
	67	void (enable_event)(struct intel_uncore_box , struct perf_event *);
	68	u64 (read_counter)(struct intel_uncore_box , struct perf_event *);
6a67943a YZ	69	int (hw_config)(struct intel_uncore_box , struct perf_event *);
	70	struct event_constraint (get_constraint)(struct intel_uncore_box *,
	71	struct perf_event *);
	72	void (put_constraint)(struct intel_uncore_box , struct perf_event *);
087bfbb0 YZ	73	};
	74
	75	struct intel_uncore_pmu {
	76	struct pmu pmu;
	77	char name[UNCORE_PMU_NAME_LEN];
	78	int pmu_idx;
	79	int func_id;
	80	struct intel_uncore_type *type;
	81	struct intel_uncore_box ** __percpu box;
14371cce	82	struct list_head box_list;
087bfbb0 YZ	83	};
087bfbb0 YZ	84
6a67943a YZ	85	struct intel_uncore_extra_reg {
6a67943a YZ	86	raw_spinlock_t lock;
254298c7	87	u64 config, config1, config2;
6a67943a YZ	88	atomic_t ref;
	89	};
	90
087bfbb0 YZ	91	struct intel_uncore_box {
	92	int phys_id;
	93	int n_active; /* number of active events */
	94	int n_events;
	95	int cpu; /* cpu to collect events */
	96	unsigned long flags;
	97	atomic_t refcnt;
	98	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	99	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
	100	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
	101	u64 tags[UNCORE_PMC_IDX_MAX];
14371cce	102	struct pci_dev *pci_dev;
087bfbb0	103	struct intel_uncore_pmu *pmu;
79859cce	104	u64 hrtimer_duration; /* hrtimer timeout for this box */
087bfbb0 YZ	105	struct hrtimer hrtimer;
087bfbb0 YZ	106	struct list_head list;
ced2efb0	107	struct list_head active_list;
b9e1ab6d	108	void *io_addr;
6a67943a	109	struct intel_uncore_extra_reg shared_regs[0];
087bfbb0 YZ	110	};
	111
	112	#define UNCORE_BOX_FLAG_INITIATED 0
	113
	114	struct uncore_event_desc {
	115	struct kobj_attribute attr;
	116	const char *config;
	117	};
	118
514b2346 YZ	119	ssize_t uncore_event_show(struct kobject *kobj,
	120	struct kobj_attribute attr, char buf);
	121
087bfbb0 YZ	122	#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
	123	{ \
	124	.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
	125	.config = _config, \
	126	}
	127
	128	#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
	129	static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
	130	struct kobj_attribute *attr, \
	131	char *page) \
	132	{ \
	133	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
	134	return sprintf(page, _format "\n"); \
	135	} \
	136	static struct kobj_attribute format_attr_##_var = \
	137	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
	138
14371cce YZ	139	static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
	140	{
	141	return box->pmu->type->box_ctl;
	142	}
	143
	144	static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
	145	{
	146	return box->pmu->type->fixed_ctl;
	147	}
	148
	149	static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
	150	{
	151	return box->pmu->type->fixed_ctr;
	152	}
	153
	154	static inline
	155	unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
	156	{
	157	return idx * 4 + box->pmu->type->event_ctl;
	158	}
	159
	160	static inline
	161	unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
	162	{
	163	return idx * 8 + box->pmu->type->perf_ctr;
	164	}
	165
cb37af77 YZ	166	static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
	167	{
	168	struct intel_uncore_pmu *pmu = box->pmu;
	169	return pmu->type->msr_offsets ?
	170	pmu->type->msr_offsets[pmu->pmu_idx] :
	171	pmu->type->msr_offset * pmu->pmu_idx;
	172	}
	173
	174	static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	175	{
	176	if (!box->pmu->type->box_ctl)
	177	return 0;
cb37af77	178	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	179	}
087bfbb0 YZ	180
cb37af77	181	static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	182	{
	183	if (!box->pmu->type->fixed_ctl)
	184	return 0;
cb37af77	185	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	186	}
087bfbb0 YZ	187
cb37af77	188	static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
087bfbb0	189	{
cb37af77	190	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
087bfbb0 YZ	191	}
	192
	193	static inline
	194	unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
	195	{
254298c7 YZ	196	return box->pmu->type->event_ctl +
254298c7 YZ	197	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	198	uncore_msr_box_offset(box);
087bfbb0 YZ	199	}
	200
	201	static inline
	202	unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
	203	{
254298c7 YZ	204	return box->pmu->type->perf_ctr +
254298c7 YZ	205	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	206	uncore_msr_box_offset(box);
087bfbb0 YZ	207	}
087bfbb0 YZ	208
14371cce YZ	209	static inline
	210	unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
	211	{
	212	if (box->pci_dev)
	213	return uncore_pci_fixed_ctl(box);
	214	else
	215	return uncore_msr_fixed_ctl(box);
	216	}
	217
	218	static inline
	219	unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
	220	{
	221	if (box->pci_dev)
	222	return uncore_pci_fixed_ctr(box);
	223	else
	224	return uncore_msr_fixed_ctr(box);
	225	}
	226
	227	static inline
	228	unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
	229	{
	230	if (box->pci_dev)
	231	return uncore_pci_event_ctl(box, idx);
	232	else
	233	return uncore_msr_event_ctl(box, idx);
	234	}
	235
	236	static inline
	237	unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
	238	{
	239	if (box->pci_dev)
	240	return uncore_pci_perf_ctr(box, idx);
	241	else
	242	return uncore_msr_perf_ctr(box, idx);
	243	}
	244
087bfbb0 YZ	245	static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
	246	{
	247	return box->pmu->type->perf_ctr_bits;
	248	}
	249
	250	static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
	251	{
	252	return box->pmu->type->fixed_ctr_bits;
	253	}
	254
	255	static inline int uncore_num_counters(struct intel_uncore_box *box)
	256	{
	257	return box->pmu->type->num_counters;
	258	}
	259
c05199e5 KL	260	static inline void uncore_box_init(struct intel_uncore_box *box)
	261	{
	262	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	263	if (box->pmu->type->ops->init_box)
	264	box->pmu->type->ops->init_box(box);
	265	}
	266	}
	267
087bfbb0 YZ	268	static inline void uncore_disable_box(struct intel_uncore_box *box)
	269	{
	270	if (box->pmu->type->ops->disable_box)
	271	box->pmu->type->ops->disable_box(box);
	272	}
	273
	274	static inline void uncore_enable_box(struct intel_uncore_box *box)
	275	{
c05199e5 KL	276	uncore_box_init(box);
c05199e5 KL	277
087bfbb0 YZ	278	if (box->pmu->type->ops->enable_box)
	279	box->pmu->type->ops->enable_box(box);
	280	}
	281
	282	static inline void uncore_disable_event(struct intel_uncore_box *box,
	283	struct perf_event *event)
	284	{
	285	box->pmu->type->ops->disable_event(box, event);
	286	}
	287
	288	static inline void uncore_enable_event(struct intel_uncore_box *box,
	289	struct perf_event *event)
	290	{
	291	box->pmu->type->ops->enable_event(box, event);
	292	}
	293
	294	static inline u64 uncore_read_counter(struct intel_uncore_box *box,
	295	struct perf_event *event)
	296	{
	297	return box->pmu->type->ops->read_counter(box, event);
	298	}
	299
254298c7 YZ	300	static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
	301	{
	302	return (box->phys_id < 0);
	303	}
514b2346 YZ	304
	305	struct intel_uncore_pmu uncore_event_to_pmu(struct perf_event event);
	306	struct intel_uncore_box uncore_pmu_to_box(struct intel_uncore_pmu pmu, int cpu);
	307	struct intel_uncore_box uncore_event_to_box(struct perf_event event);
	308	u64 uncore_msr_read_counter(struct intel_uncore_box box, struct perf_event event);
	309	void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
	310	void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
	311	void uncore_pmu_event_read(struct perf_event *event);
	312	void uncore_perf_event_update(struct intel_uncore_box box, struct perf_event event);
	313	struct event_constraint *
	314	uncore_get_constraint(struct intel_uncore_box box, struct perf_event event);
	315	void uncore_put_constraint(struct intel_uncore_box box, struct perf_event event);
	316	u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
	317
	318	extern struct intel_uncore_type **uncore_msr_uncores;
	319	extern struct intel_uncore_type **uncore_pci_uncores;
	320	extern struct pci_driver *uncore_pci_driver;
	321	extern int uncore_pcibus_to_physid[256];
	322	extern struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
	323	extern struct event_constraint uncore_constraint_empty;
92807ffd YZ	324
	325	/* perf_event_intel_uncore_snb.c */
	326	int snb_uncore_pci_init(void);
	327	int ivb_uncore_pci_init(void);
	328	int hsw_uncore_pci_init(void);
	329	void snb_uncore_cpu_init(void);
	330	void nhm_uncore_cpu_init(void);
8268fdfc YZ	331
	332	/* perf_event_intel_uncore_snbep.c */
	333	int snbep_uncore_pci_init(void);
	334	void snbep_uncore_cpu_init(void);
ddcd0973 PZ	335	int ivbep_uncore_pci_init(void);
ddcd0973 PZ	336	void ivbep_uncore_cpu_init(void);
e735b9db YZ	337	int hswep_uncore_pci_init(void);
e735b9db YZ	338	void hswep_uncore_cpu_init(void);
c1e46580 YZ	339
	340	/* perf_event_intel_uncore_nhmex.c */
	341	void nhmex_uncore_cpu_init(void);