[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel_uncore.h

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/perf_event.h>
#include "perf_event.h"

#define UNCORE_PMU_NAME_LEN		32
#define UNCORE_PMU_HRTIMER_INTERVAL	(60LL * NSEC_PER_SEC)
#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)

#define UNCORE_FIXED_EVENT		0xff
#define UNCORE_PMC_IDX_MAX_GENERIC	8
#define UNCORE_PMC_IDX_FIXED		UNCORE_PMC_IDX_MAX_GENERIC
#define UNCORE_PMC_IDX_MAX		(UNCORE_PMC_IDX_FIXED + 1)

#define UNCORE_PCI_DEV_DATA(type, idx)	((type << 8) | idx)
#define UNCORE_PCI_DEV_TYPE(data)	((data >> 8) & 0xff)
#define UNCORE_PCI_DEV_IDX(data)	(data & 0xff)
#define UNCORE_EXTRA_PCI_DEV		0xff
#define UNCORE_EXTRA_PCI_DEV_MAX	3

/* support up to 8 sockets */
#define UNCORE_SOCKET_MAX		8

#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)

struct intel_uncore_ops;
struct intel_uncore_pmu;
struct intel_uncore_box;
struct uncore_event_desc;

struct intel_uncore_type {
	const char *name;
	int num_counters;
	int num_boxes;
	int perf_ctr_bits;
	int fixed_ctr_bits;
	unsigned perf_ctr;
	unsigned event_ctl;
	unsigned event_mask;
	unsigned fixed_ctr;
	unsigned fixed_ctl;
	unsigned box_ctl;
	unsigned msr_offset;
	unsigned num_shared_regs:8;
	unsigned single_fixed:1;
	unsigned pair_ctr_ctl:1;
	unsigned *msr_offsets;
	struct event_constraint unconstrainted;
	struct event_constraint *constraints;
	struct intel_uncore_pmu *pmus;
	struct intel_uncore_ops *ops;
	struct uncore_event_desc *event_descs;
	const struct attribute_group *attr_groups[4];
	struct pmu *pmu; /* for custom pmu ops */
};

#define pmu_group attr_groups[0]
#define format_group attr_groups[1]
#define events_group attr_groups[2]

struct intel_uncore_ops {
	void (*init_box)(struct intel_uncore_box *);
	void (*disable_box)(struct intel_uncore_box *);
	void (*enable_box)(struct intel_uncore_box *);
	void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
	void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
	u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
	int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
	struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
						   struct perf_event *);
	void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
};

struct intel_uncore_pmu {
	struct pmu pmu;
	char name[UNCORE_PMU_NAME_LEN];
	int pmu_idx;
	int func_id;
	struct intel_uncore_type *type;
	struct intel_uncore_box ** __percpu box;
	struct list_head box_list;
};

struct intel_uncore_extra_reg {
	raw_spinlock_t lock;
	u64 config, config1, config2;
	atomic_t ref;
};

struct intel_uncore_box {
	int phys_id;
	int n_active;	/* number of active events */
	int n_events;
	int cpu;	/* cpu to collect events */
	unsigned long flags;
	atomic_t refcnt;
	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
	u64 tags[UNCORE_PMC_IDX_MAX];
	struct pci_dev *pci_dev;
	struct intel_uncore_pmu *pmu;
	u64 hrtimer_duration; /* hrtimer timeout for this box */
	struct hrtimer hrtimer;
	struct list_head list;
	struct list_head active_list;
	void *io_addr;
	struct intel_uncore_extra_reg shared_regs[0];
};

#define UNCORE_BOX_FLAG_INITIATED	0

struct uncore_event_desc {
	struct kobj_attribute attr;
	const char *config;
};

ssize_t uncore_event_show(struct kobject *kobj,
			  struct kobj_attribute *attr, char *buf);

#define INTEL_UNCORE_EVENT_DESC(_name, _config)			\
{								\
	.attr	= __ATTR(_name, 0444, uncore_event_show, NULL),	\
	.config	= _config,					\
}

#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)			\
static ssize_t __uncore_##_var##_show(struct kobject *kobj,		\
				struct kobj_attribute *attr,		\
				char *page)				\
{									\
	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);			\
	return sprintf(page, _format "\n");				\
}									\
static struct kobj_attribute format_attr_##_var =			\
	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)

static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->box_ctl;
}

static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctl;
}

static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr;
}

static inline
unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
{
	return idx * 4 + box->pmu->type->event_ctl;
}

static inline
unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return idx * 8 + box->pmu->type->perf_ctr;
}

static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
{
	struct intel_uncore_pmu *pmu = box->pmu;
	return pmu->type->msr_offsets ?
		pmu->type->msr_offsets[pmu->pmu_idx] :
		pmu->type->msr_offset * pmu->pmu_idx;
}

static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->box_ctl)
		return 0;
	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
{
	if (!box->pmu->type->fixed_ctl)
		return 0;
	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
}

static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->event_ctl +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
{
	return box->pmu->type->perf_ctr +
		(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
		uncore_msr_box_offset(box);
}

static inline
unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctl(box);
	else
		return uncore_msr_fixed_ctl(box);
}

static inline
unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
{
	if (box->pci_dev)
		return uncore_pci_fixed_ctr(box);
	else
		return uncore_msr_fixed_ctr(box);
}

static inline
unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_event_ctl(box, idx);
	else
		return uncore_msr_event_ctl(box, idx);
}

static inline
unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
{
	if (box->pci_dev)
		return uncore_pci_perf_ctr(box, idx);
	else
		return uncore_msr_perf_ctr(box, idx);
}

static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->perf_ctr_bits;
}

static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
{
	return box->pmu->type->fixed_ctr_bits;
}

static inline int uncore_num_counters(struct intel_uncore_box *box)
{
	return box->pmu->type->num_counters;
}

static inline void uncore_disable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->disable_box)
		box->pmu->type->ops->disable_box(box);
}

static inline void uncore_enable_box(struct intel_uncore_box *box)
{
	if (box->pmu->type->ops->enable_box)
		box->pmu->type->ops->enable_box(box);
}

static inline void uncore_disable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->disable_event(box, event);
}

static inline void uncore_enable_event(struct intel_uncore_box *box,
				struct perf_event *event)
{
	box->pmu->type->ops->enable_event(box, event);
}

static inline u64 uncore_read_counter(struct intel_uncore_box *box,
				struct perf_event *event)
{
	return box->pmu->type->ops->read_counter(box, event);
}

static inline void uncore_box_init(struct intel_uncore_box *box)
{
	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
		if (box->pmu->type->ops->init_box)
			box->pmu->type->ops->init_box(box);
	}
}

static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
{
	return (box->phys_id < 0);
}

struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event);
struct intel_uncore_box *uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu);
struct intel_uncore_box *uncore_event_to_box(struct perf_event *event);
u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event);
void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
void uncore_pmu_event_read(struct perf_event *event);
void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event);
struct event_constraint *
uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event);
void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event);
u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);

extern struct intel_uncore_type **uncore_msr_uncores;
extern struct intel_uncore_type **uncore_pci_uncores;
extern struct pci_driver *uncore_pci_driver;
extern int uncore_pcibus_to_physid[256];
extern struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
extern struct event_constraint uncore_constraint_empty;

/* perf_event_intel_uncore_snb.c */
int snb_uncore_pci_init(void);
int ivb_uncore_pci_init(void);
int hsw_uncore_pci_init(void);
void snb_uncore_cpu_init(void);
void nhm_uncore_cpu_init(void);

/* perf_event_intel_uncore_snbep.c */
int snbep_uncore_pci_init(void);
void snbep_uncore_cpu_init(void);
int ivbep_uncore_pci_init(void);
void ivbep_uncore_cpu_init(void);
int hswep_uncore_pci_init(void);
void hswep_uncore_cpu_init(void);

/* perf_event_intel_uncore_nhmex.c */
void nhmex_uncore_cpu_init(void);
Commit	Line	Data
087bfbb0 YZ	1	#include <linux/module.h>
087bfbb0 YZ	2	#include <linux/slab.h>
14371cce	3	#include <linux/pci.h>
087bfbb0 YZ	4	#include <linux/perf_event.h>
	5	#include "perf_event.h"
	6
	7	#define UNCORE_PMU_NAME_LEN 32
7740dfc0	8	#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
ced2efb0	9	#define UNCORE_SNB_IMC_HRTIMER_INTERVAL (5ULL * NSEC_PER_SEC)
087bfbb0	10
eca26c99	11	#define UNCORE_FIXED_EVENT 0xff
087bfbb0 YZ	12	#define UNCORE_PMC_IDX_MAX_GENERIC 8
	13	#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
	14	#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
	15
899396cf YZ	16	#define UNCORE_PCI_DEV_DATA(type, idx) ((type << 8) \| idx)
	17	#define UNCORE_PCI_DEV_TYPE(data) ((data >> 8) & 0xff)
	18	#define UNCORE_PCI_DEV_IDX(data) (data & 0xff)
	19	#define UNCORE_EXTRA_PCI_DEV 0xff
5306c31c	20	#define UNCORE_EXTRA_PCI_DEV_MAX 3
899396cf YZ	21
	22	/* support up to 8 sockets */
	23	#define UNCORE_SOCKET_MAX 8
	24
087bfbb0 YZ	25	#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
	26
	27	struct intel_uncore_ops;
	28	struct intel_uncore_pmu;
	29	struct intel_uncore_box;
	30	struct uncore_event_desc;
	31
	32	struct intel_uncore_type {
	33	const char *name;
	34	int num_counters;
	35	int num_boxes;
	36	int perf_ctr_bits;
	37	int fixed_ctr_bits;
087bfbb0 YZ	38	unsigned perf_ctr;
	39	unsigned event_ctl;
	40	unsigned event_mask;
	41	unsigned fixed_ctr;
	42	unsigned fixed_ctl;
	43	unsigned box_ctl;
	44	unsigned msr_offset;
6a67943a YZ	45	unsigned num_shared_regs:8;
6a67943a YZ	46	unsigned single_fixed:1;
254298c7	47	unsigned pair_ctr_ctl:1;
cb37af77	48	unsigned *msr_offsets;
087bfbb0 YZ	49	struct event_constraint unconstrainted;
	50	struct event_constraint *constraints;
	51	struct intel_uncore_pmu *pmus;
	52	struct intel_uncore_ops *ops;
	53	struct uncore_event_desc *event_descs;
314d9f63	54	const struct attribute_group *attr_groups[4];
d64b25b6	55	struct pmu pmu; / for custom pmu ops */
087bfbb0 YZ	56	};
087bfbb0 YZ	57
314d9f63 YZ	58	#define pmu_group attr_groups[0]
	59	#define format_group attr_groups[1]
	60	#define events_group attr_groups[2]
087bfbb0 YZ	61
	62	struct intel_uncore_ops {
	63	void (init_box)(struct intel_uncore_box );
	64	void (disable_box)(struct intel_uncore_box );
	65	void (enable_box)(struct intel_uncore_box );
	66	void (disable_event)(struct intel_uncore_box , struct perf_event *);
	67	void (enable_event)(struct intel_uncore_box , struct perf_event *);
	68	u64 (read_counter)(struct intel_uncore_box , struct perf_event *);
6a67943a YZ	69	int (hw_config)(struct intel_uncore_box , struct perf_event *);
	70	struct event_constraint (get_constraint)(struct intel_uncore_box *,
	71	struct perf_event *);
	72	void (put_constraint)(struct intel_uncore_box , struct perf_event *);
087bfbb0 YZ	73	};
	74
	75	struct intel_uncore_pmu {
	76	struct pmu pmu;
	77	char name[UNCORE_PMU_NAME_LEN];
	78	int pmu_idx;
	79	int func_id;
	80	struct intel_uncore_type *type;
	81	struct intel_uncore_box ** __percpu box;
14371cce	82	struct list_head box_list;
087bfbb0 YZ	83	};
087bfbb0 YZ	84
6a67943a YZ	85	struct intel_uncore_extra_reg {
6a67943a YZ	86	raw_spinlock_t lock;
254298c7	87	u64 config, config1, config2;
6a67943a YZ	88	atomic_t ref;
	89	};
	90
087bfbb0 YZ	91	struct intel_uncore_box {
	92	int phys_id;
	93	int n_active; /* number of active events */
	94	int n_events;
	95	int cpu; /* cpu to collect events */
	96	unsigned long flags;
	97	atomic_t refcnt;
	98	struct perf_event *events[UNCORE_PMC_IDX_MAX];
	99	struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
b371b594	100	struct event_constraint *event_constraint[UNCORE_PMC_IDX_MAX];
087bfbb0 YZ	101	unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
087bfbb0 YZ	102	u64 tags[UNCORE_PMC_IDX_MAX];
14371cce	103	struct pci_dev *pci_dev;
087bfbb0	104	struct intel_uncore_pmu *pmu;
79859cce	105	u64 hrtimer_duration; /* hrtimer timeout for this box */
087bfbb0 YZ	106	struct hrtimer hrtimer;
087bfbb0 YZ	107	struct list_head list;
ced2efb0	108	struct list_head active_list;
b9e1ab6d	109	void *io_addr;
6a67943a	110	struct intel_uncore_extra_reg shared_regs[0];
087bfbb0 YZ	111	};
	112
	113	#define UNCORE_BOX_FLAG_INITIATED 0
	114
	115	struct uncore_event_desc {
	116	struct kobj_attribute attr;
	117	const char *config;
	118	};
	119
514b2346 YZ	120	ssize_t uncore_event_show(struct kobject *kobj,
	121	struct kobj_attribute attr, char buf);
	122
087bfbb0 YZ	123	#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
	124	{ \
	125	.attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
	126	.config = _config, \
	127	}
	128
	129	#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
	130	static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
	131	struct kobj_attribute *attr, \
	132	char *page) \
	133	{ \
	134	BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
	135	return sprintf(page, _format "\n"); \
	136	} \
	137	static struct kobj_attribute format_attr_##_var = \
	138	__ATTR(_name, 0444, __uncore_##_var##_show, NULL)
	139
14371cce YZ	140	static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
	141	{
	142	return box->pmu->type->box_ctl;
	143	}
	144
	145	static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
	146	{
	147	return box->pmu->type->fixed_ctl;
	148	}
	149
	150	static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
	151	{
	152	return box->pmu->type->fixed_ctr;
	153	}
	154
	155	static inline
	156	unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
	157	{
	158	return idx * 4 + box->pmu->type->event_ctl;
	159	}
	160
	161	static inline
	162	unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
	163	{
	164	return idx * 8 + box->pmu->type->perf_ctr;
	165	}
	166
cb37af77 YZ	167	static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
	168	{
	169	struct intel_uncore_pmu *pmu = box->pmu;
	170	return pmu->type->msr_offsets ?
	171	pmu->type->msr_offsets[pmu->pmu_idx] :
	172	pmu->type->msr_offset * pmu->pmu_idx;
	173	}
	174
	175	static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	176	{
	177	if (!box->pmu->type->box_ctl)
	178	return 0;
cb37af77	179	return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	180	}
087bfbb0 YZ	181
cb37af77	182	static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
087bfbb0 YZ	183	{
	184	if (!box->pmu->type->fixed_ctl)
	185	return 0;
cb37af77	186	return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
087bfbb0 YZ	187	}
087bfbb0 YZ	188
cb37af77	189	static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
087bfbb0	190	{
cb37af77	191	return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
087bfbb0 YZ	192	}
	193
	194	static inline
	195	unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
	196	{
254298c7 YZ	197	return box->pmu->type->event_ctl +
254298c7 YZ	198	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	199	uncore_msr_box_offset(box);
087bfbb0 YZ	200	}
	201
	202	static inline
	203	unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
	204	{
254298c7 YZ	205	return box->pmu->type->perf_ctr +
254298c7 YZ	206	(box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
cb37af77	207	uncore_msr_box_offset(box);
087bfbb0 YZ	208	}
087bfbb0 YZ	209
14371cce YZ	210	static inline
	211	unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
	212	{
	213	if (box->pci_dev)
	214	return uncore_pci_fixed_ctl(box);
	215	else
	216	return uncore_msr_fixed_ctl(box);
	217	}
	218
	219	static inline
	220	unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
	221	{
	222	if (box->pci_dev)
	223	return uncore_pci_fixed_ctr(box);
	224	else
	225	return uncore_msr_fixed_ctr(box);
	226	}
	227
	228	static inline
	229	unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
	230	{
	231	if (box->pci_dev)
	232	return uncore_pci_event_ctl(box, idx);
	233	else
	234	return uncore_msr_event_ctl(box, idx);
	235	}
	236
	237	static inline
	238	unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
	239	{
	240	if (box->pci_dev)
	241	return uncore_pci_perf_ctr(box, idx);
	242	else
	243	return uncore_msr_perf_ctr(box, idx);
	244	}
	245
087bfbb0 YZ	246	static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
	247	{
	248	return box->pmu->type->perf_ctr_bits;
	249	}
	250
	251	static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
	252	{
	253	return box->pmu->type->fixed_ctr_bits;
	254	}
	255
	256	static inline int uncore_num_counters(struct intel_uncore_box *box)
	257	{
	258	return box->pmu->type->num_counters;
	259	}
	260
	261	static inline void uncore_disable_box(struct intel_uncore_box *box)
	262	{
	263	if (box->pmu->type->ops->disable_box)
	264	box->pmu->type->ops->disable_box(box);
	265	}
	266
	267	static inline void uncore_enable_box(struct intel_uncore_box *box)
	268	{
	269	if (box->pmu->type->ops->enable_box)
	270	box->pmu->type->ops->enable_box(box);
	271	}
	272
	273	static inline void uncore_disable_event(struct intel_uncore_box *box,
	274	struct perf_event *event)
	275	{
	276	box->pmu->type->ops->disable_event(box, event);
	277	}
	278
	279	static inline void uncore_enable_event(struct intel_uncore_box *box,
	280	struct perf_event *event)
	281	{
	282	box->pmu->type->ops->enable_event(box, event);
	283	}
	284
	285	static inline u64 uncore_read_counter(struct intel_uncore_box *box,
	286	struct perf_event *event)
	287	{
	288	return box->pmu->type->ops->read_counter(box, event);
	289	}
	290
15c12479 IM	291	static inline void uncore_box_init(struct intel_uncore_box *box)
	292	{
	293	if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
	294	if (box->pmu->type->ops->init_box)
	295	box->pmu->type->ops->init_box(box);
	296	}
	297	}
	298
254298c7 YZ	299	static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
	300	{
	301	return (box->phys_id < 0);
	302	}
514b2346 YZ	303
	304	struct intel_uncore_pmu uncore_event_to_pmu(struct perf_event event);
	305	struct intel_uncore_box uncore_pmu_to_box(struct intel_uncore_pmu pmu, int cpu);
	306	struct intel_uncore_box uncore_event_to_box(struct perf_event event);
	307	u64 uncore_msr_read_counter(struct intel_uncore_box box, struct perf_event event);
	308	void uncore_pmu_start_hrtimer(struct intel_uncore_box *box);
	309	void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box);
	310	void uncore_pmu_event_read(struct perf_event *event);
	311	void uncore_perf_event_update(struct intel_uncore_box box, struct perf_event event);
	312	struct event_constraint *
	313	uncore_get_constraint(struct intel_uncore_box box, struct perf_event event);
	314	void uncore_put_constraint(struct intel_uncore_box box, struct perf_event event);
	315	u64 uncore_shared_reg_config(struct intel_uncore_box *box, int idx);
	316
	317	extern struct intel_uncore_type **uncore_msr_uncores;
	318	extern struct intel_uncore_type **uncore_pci_uncores;
	319	extern struct pci_driver *uncore_pci_driver;
	320	extern int uncore_pcibus_to_physid[256];
	321	extern struct pci_dev *uncore_extra_pci_dev[UNCORE_SOCKET_MAX][UNCORE_EXTRA_PCI_DEV_MAX];
	322	extern struct event_constraint uncore_constraint_empty;
92807ffd YZ	323
	324	/* perf_event_intel_uncore_snb.c */
	325	int snb_uncore_pci_init(void);
	326	int ivb_uncore_pci_init(void);
	327	int hsw_uncore_pci_init(void);
	328	void snb_uncore_cpu_init(void);
	329	void nhm_uncore_cpu_init(void);
8268fdfc YZ	330
	331	/* perf_event_intel_uncore_snbep.c */
	332	int snbep_uncore_pci_init(void);
	333	void snbep_uncore_cpu_init(void);
ddcd0973 PZ	334	int ivbep_uncore_pci_init(void);
ddcd0973 PZ	335	void ivbep_uncore_cpu_init(void);
e735b9db YZ	336	int hswep_uncore_pci_init(void);
e735b9db YZ	337	void hswep_uncore_cpu_init(void);
c1e46580 YZ	338
	339	/* perf_event_intel_uncore_nhmex.c */
	340	void nhmex_uncore_cpu_init(void);