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perf/x86/intel/pebs: Add PEBS frontend profiling for Skylake
[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
aacfbe6a 15#include <linux/nmi.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7
KW		 18#include <asm/hardirq.h>
19#include <asm/apic.h>
20
21#include "perf_event.h"
a7e3ed1e 22
f22f54f4 23/*
b622d644 24 * Intel PerfMon, used on Core and later.
f22f54f4 25 */
ec75a716 26static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 27{
c3b7cdf1
PE		 28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 36};
37
5c543e3c 38static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 39{
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
46 EVENT_CONSTRAINT_END
47};
48
5c543e3c 49static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 50{
b622d644
PZ		 51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
64 EVENT_CONSTRAINT_END
65};
66
5c543e3c 67static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 68{
b622d644
PZ		 69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
80 EVENT_CONSTRAINT_END
81};
82
5c543e3c 83static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 84{
53ad0447
YZ		 85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 88 EVENT_EXTRA_END
89};
90
5c543e3c 91static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 92{
b622d644
PZ		 93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 100 EVENT_CONSTRAINT_END
101};
102
5c543e3c 103static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 104{
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c
MD		 117
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
122
b06b3d49
LM		 123 EVENT_CONSTRAINT_END
124};
125
69943182
SE		 126static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
127{
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c
MD		 141
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
146
69943182
SE		 147 EVENT_CONSTRAINT_END
148};
149
5c543e3c 150static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 151{
53ad0447
YZ		 152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 156 EVENT_EXTRA_END
157};
158
0af3ac1f
AK		 159static struct event_constraint intel_v1_event_constraints[] __read_mostly =
160{
161 EVENT_CONSTRAINT_END
162};
163
5c543e3c 164static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 165{
b622d644
PZ		 166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 169 EVENT_CONSTRAINT_END
170};
171
1fa64180
YZ		 172static struct event_constraint intel_slm_event_constraints[] __read_mostly =
173{
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
177 EVENT_CONSTRAINT_END
178};
179
9a92e16f
AK		 180struct event_constraint intel_skl_event_constraints[] = {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
185 EVENT_CONSTRAINT_END
186};
187
ee89cbc2 188static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 192 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 193 EVENT_EXTRA_END
194};
195
196static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 197 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
198 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
199 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 200 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 201 EVENT_EXTRA_END
202};
203
9a92e16f
AK		 204static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
205 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
206 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
207 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
d0dc8494 208 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE),
9a92e16f
AK		 209 EVENT_EXTRA_END
210};
211
7f2ee91f
IM		 212EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
213EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
214EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 215
216struct attribute *nhm_events_attrs[] = {
217 EVENT_PTR(mem_ld_nhm),
218 NULL,
219};
220
221struct attribute *snb_events_attrs[] = {
222 EVENT_PTR(mem_ld_snb),
9ad64c0f 223 EVENT_PTR(mem_st_snb),
f20093ee
SE		 224 NULL,
225};
226
3a632cb2
AK		 227static struct event_constraint intel_hsw_event_constraints[] = {
228 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
229 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
230 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
231 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
232 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
233 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
234 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 235 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 236 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 237 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 238 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 239 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c
MD		 240
241 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
242 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
243 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
244 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
245
3a632cb2
AK		 246 EVENT_CONSTRAINT_END
247};
248
91f1b705
AK		 249struct event_constraint intel_bdw_event_constraints[] = {
250 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
251 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
252 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
253 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
5e176213 254 INTEL_UEVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
91f1b705
AK		 255 EVENT_CONSTRAINT_END
256};
257
f22f54f4
PZ		 258static u64 intel_pmu_event_map(int hw_event)
259{
260 return intel_perfmon_event_map[hw_event];
261}
262
9a92e16f
AK		 263/*
264 * Notes on the events:
265 * - data reads do not include code reads (comparable to earlier tables)
266 * - data counts include speculative execution (except L1 write, dtlb, bpu)
267 * - remote node access includes remote memory, remote cache, remote mmio.
268 * - prefetches are not included in the counts.
269 * - icache miss does not include decoded icache
270 */
271
272#define SKL_DEMAND_DATA_RD BIT_ULL(0)
273#define SKL_DEMAND_RFO BIT_ULL(1)
274#define SKL_ANY_RESPONSE BIT_ULL(16)
275#define SKL_SUPPLIER_NONE BIT_ULL(17)
276#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
277#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
278#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
279#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
280#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
281 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
282 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
283 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
284#define SKL_SPL_HIT BIT_ULL(30)
285#define SKL_SNOOP_NONE BIT_ULL(31)
286#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
287#define SKL_SNOOP_MISS BIT_ULL(33)
288#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
289#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
290#define SKL_SNOOP_HITM BIT_ULL(36)
291#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
292#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
293 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
294 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
295 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
296#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
297#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
298 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
299 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
300 SKL_SNOOP_HITM|SKL_SPL_HIT)
301#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
302#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
303#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
304 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
305 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
306
307static __initconst const u64 skl_hw_cache_event_ids
308 [PERF_COUNT_HW_CACHE_MAX]
309 [PERF_COUNT_HW_CACHE_OP_MAX]
310 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
311{
312 [ C(L1D ) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
315 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
319 [ C(RESULT_MISS) ] = 0x0,
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x0,
324 },
325 },
326 [ C(L1I ) ] = {
327 [ C(OP_READ) ] = {
328 [ C(RESULT_ACCESS) ] = 0x0,
329 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
330 },
331 [ C(OP_WRITE) ] = {
332 [ C(RESULT_ACCESS) ] = -1,
333 [ C(RESULT_MISS) ] = -1,
334 },
335 [ C(OP_PREFETCH) ] = {
336 [ C(RESULT_ACCESS) ] = 0x0,
337 [ C(RESULT_MISS) ] = 0x0,
338 },
339 },
340 [ C(LL ) ] = {
341 [ C(OP_READ) ] = {
342 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
343 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
344 },
345 [ C(OP_WRITE) ] = {
346 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
347 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
348 },
349 [ C(OP_PREFETCH) ] = {
350 [ C(RESULT_ACCESS) ] = 0x0,
351 [ C(RESULT_MISS) ] = 0x0,
352 },
353 },
354 [ C(DTLB) ] = {
355 [ C(OP_READ) ] = {
356 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
357 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
358 },
359 [ C(OP_WRITE) ] = {
360 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
361 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
362 },
363 [ C(OP_PREFETCH) ] = {
364 [ C(RESULT_ACCESS) ] = 0x0,
365 [ C(RESULT_MISS) ] = 0x0,
366 },
367 },
368 [ C(ITLB) ] = {
369 [ C(OP_READ) ] = {
370 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
371 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
372 },
373 [ C(OP_WRITE) ] = {
374 [ C(RESULT_ACCESS) ] = -1,
375 [ C(RESULT_MISS) ] = -1,
376 },
377 [ C(OP_PREFETCH) ] = {
378 [ C(RESULT_ACCESS) ] = -1,
379 [ C(RESULT_MISS) ] = -1,
380 },
381 },
382 [ C(BPU ) ] = {
383 [ C(OP_READ) ] = {
384 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
385 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
386 },
387 [ C(OP_WRITE) ] = {
388 [ C(RESULT_ACCESS) ] = -1,
389 [ C(RESULT_MISS) ] = -1,
390 },
391 [ C(OP_PREFETCH) ] = {
392 [ C(RESULT_ACCESS) ] = -1,
393 [ C(RESULT_MISS) ] = -1,
394 },
395 },
396 [ C(NODE) ] = {
397 [ C(OP_READ) ] = {
398 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
399 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
400 },
401 [ C(OP_WRITE) ] = {
402 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
403 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
404 },
405 [ C(OP_PREFETCH) ] = {
406 [ C(RESULT_ACCESS) ] = 0x0,
407 [ C(RESULT_MISS) ] = 0x0,
408 },
409 },
410};
411
412static __initconst const u64 skl_hw_cache_extra_regs
413 [PERF_COUNT_HW_CACHE_MAX]
414 [PERF_COUNT_HW_CACHE_OP_MAX]
415 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
416{
417 [ C(LL ) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
420 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
421 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
422 SKL_L3_MISS|SKL_ANY_SNOOP|
423 SKL_SUPPLIER_NONE,
424 },
425 [ C(OP_WRITE) ] = {
426 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
427 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
428 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
429 SKL_L3_MISS|SKL_ANY_SNOOP|
430 SKL_SUPPLIER_NONE,
431 },
432 [ C(OP_PREFETCH) ] = {
433 [ C(RESULT_ACCESS) ] = 0x0,
434 [ C(RESULT_MISS) ] = 0x0,
435 },
436 },
437 [ C(NODE) ] = {
438 [ C(OP_READ) ] = {
439 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
440 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
441 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
442 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
443 },
444 [ C(OP_WRITE) ] = {
445 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
446 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
447 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
448 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
449 },
450 [ C(OP_PREFETCH) ] = {
451 [ C(RESULT_ACCESS) ] = 0x0,
452 [ C(RESULT_MISS) ] = 0x0,
453 },
454 },
455};
456
74e6543f
YZ		 457#define SNB_DMND_DATA_RD (1ULL << 0)
458#define SNB_DMND_RFO (1ULL << 1)
459#define SNB_DMND_IFETCH (1ULL << 2)
460#define SNB_DMND_WB (1ULL << 3)
461#define SNB_PF_DATA_RD (1ULL << 4)
462#define SNB_PF_RFO (1ULL << 5)
463#define SNB_PF_IFETCH (1ULL << 6)
464#define SNB_LLC_DATA_RD (1ULL << 7)
465#define SNB_LLC_RFO (1ULL << 8)
466#define SNB_LLC_IFETCH (1ULL << 9)
467#define SNB_BUS_LOCKS (1ULL << 10)
468#define SNB_STRM_ST (1ULL << 11)
469#define SNB_OTHER (1ULL << 15)
470#define SNB_RESP_ANY (1ULL << 16)
471#define SNB_NO_SUPP (1ULL << 17)
472#define SNB_LLC_HITM (1ULL << 18)
473#define SNB_LLC_HITE (1ULL << 19)
474#define SNB_LLC_HITS (1ULL << 20)
475#define SNB_LLC_HITF (1ULL << 21)
476#define SNB_LOCAL (1ULL << 22)
477#define SNB_REMOTE (0xffULL << 23)
478#define SNB_SNP_NONE (1ULL << 31)
479#define SNB_SNP_NOT_NEEDED (1ULL << 32)
480#define SNB_SNP_MISS (1ULL << 33)
481#define SNB_NO_FWD (1ULL << 34)
482#define SNB_SNP_FWD (1ULL << 35)
483#define SNB_HITM (1ULL << 36)
484#define SNB_NON_DRAM (1ULL << 37)
485
486#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
487#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
488#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
489
490#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
491 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
492 SNB_HITM)
493
494#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
495#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
496
497#define SNB_L3_ACCESS SNB_RESP_ANY
498#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
499
500static __initconst const u64 snb_hw_cache_extra_regs
501 [PERF_COUNT_HW_CACHE_MAX]
502 [PERF_COUNT_HW_CACHE_OP_MAX]
503 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
504{
505 [ C(LL ) ] = {
506 [ C(OP_READ) ] = {
507 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
508 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
509 },
510 [ C(OP_WRITE) ] = {
511 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
512 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
513 },
514 [ C(OP_PREFETCH) ] = {
515 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
516 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
517 },
518 },
519 [ C(NODE) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
522 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
523 },
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
526 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
527 },
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
530 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
531 },
532 },
533};
534
b06b3d49
LM		 535static __initconst const u64 snb_hw_cache_event_ids
536 [PERF_COUNT_HW_CACHE_MAX]
537 [PERF_COUNT_HW_CACHE_OP_MAX]
538 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
539{
540 [ C(L1D) ] = {
541 [ C(OP_READ) ] = {
542 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
543 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
544 },
545 [ C(OP_WRITE) ] = {
546 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
547 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
548 },
549 [ C(OP_PREFETCH) ] = {
550 [ C(RESULT_ACCESS) ] = 0x0,
551 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
552 },
553 },
554 [ C(L1I ) ] = {
555 [ C(OP_READ) ] = {
556 [ C(RESULT_ACCESS) ] = 0x0,
557 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
558 },
559 [ C(OP_WRITE) ] = {
560 [ C(RESULT_ACCESS) ] = -1,
561 [ C(RESULT_MISS) ] = -1,
562 },
563 [ C(OP_PREFETCH) ] = {
564 [ C(RESULT_ACCESS) ] = 0x0,
565 [ C(RESULT_MISS) ] = 0x0,
566 },
567 },
568 [ C(LL ) ] = {
b06b3d49 569 [ C(OP_READ) ] = {
63b6a675 570 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 571 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 572 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
573 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 574 },
575 [ C(OP_WRITE) ] = {
63b6a675 576 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 577 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 578 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
579 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 580 },
581 [ C(OP_PREFETCH) ] = {
63b6a675 582 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 583 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 584 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
585 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 586 },
587 },
588 [ C(DTLB) ] = {
589 [ C(OP_READ) ] = {
590 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
591 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
592 },
593 [ C(OP_WRITE) ] = {
594 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
595 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
596 },
597 [ C(OP_PREFETCH) ] = {
598 [ C(RESULT_ACCESS) ] = 0x0,
599 [ C(RESULT_MISS) ] = 0x0,
600 },
601 },
602 [ C(ITLB) ] = {
603 [ C(OP_READ) ] = {
604 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
605 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
606 },
607 [ C(OP_WRITE) ] = {
608 [ C(RESULT_ACCESS) ] = -1,
609 [ C(RESULT_MISS) ] = -1,
610 },
611 [ C(OP_PREFETCH) ] = {
612 [ C(RESULT_ACCESS) ] = -1,
613 [ C(RESULT_MISS) ] = -1,
614 },
615 },
616 [ C(BPU ) ] = {
617 [ C(OP_READ) ] = {
618 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
619 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
620 },
621 [ C(OP_WRITE) ] = {
622 [ C(RESULT_ACCESS) ] = -1,
623 [ C(RESULT_MISS) ] = -1,
624 },
625 [ C(OP_PREFETCH) ] = {
626 [ C(RESULT_ACCESS) ] = -1,
627 [ C(RESULT_MISS) ] = -1,
628 },
629 },
89d6c0b5
PZ		 630 [ C(NODE) ] = {
631 [ C(OP_READ) ] = {
74e6543f
YZ		 632 [ C(RESULT_ACCESS) ] = 0x01b7,
633 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 634 },
635 [ C(OP_WRITE) ] = {
74e6543f
YZ		 636 [ C(RESULT_ACCESS) ] = 0x01b7,
637 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 638 },
639 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 640 [ C(RESULT_ACCESS) ] = 0x01b7,
641 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 642 },
643 },
644
b06b3d49
LM		 645};
646
0f1b5ca2
AK		 647/*
648 * Notes on the events:
649 * - data reads do not include code reads (comparable to earlier tables)
650 * - data counts include speculative execution (except L1 write, dtlb, bpu)
651 * - remote node access includes remote memory, remote cache, remote mmio.
652 * - prefetches are not included in the counts because they are not
653 * reliably counted.
654 */
655
656#define HSW_DEMAND_DATA_RD BIT_ULL(0)
657#define HSW_DEMAND_RFO BIT_ULL(1)
658#define HSW_ANY_RESPONSE BIT_ULL(16)
659#define HSW_SUPPLIER_NONE BIT_ULL(17)
660#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
661#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
662#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
663#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
664#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
665 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
666 HSW_L3_MISS_REMOTE_HOP2P)
667#define HSW_SNOOP_NONE BIT_ULL(31)
668#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
669#define HSW_SNOOP_MISS BIT_ULL(33)
670#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
671#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
672#define HSW_SNOOP_HITM BIT_ULL(36)
673#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
674#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
675 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
676 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
677 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
678#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
679#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
680#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
681#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
682 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
683#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
684
91f1b705
AK		 685#define BDW_L3_MISS_LOCAL BIT(26)
686#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
687 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
688 HSW_L3_MISS_REMOTE_HOP2P)
689
690
0f1b5ca2
AK		 691static __initconst const u64 hsw_hw_cache_event_ids
692 [PERF_COUNT_HW_CACHE_MAX]
693 [PERF_COUNT_HW_CACHE_OP_MAX]
694 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
695{
696 [ C(L1D ) ] = {
697 [ C(OP_READ) ] = {
698 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
699 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
700 },
701 [ C(OP_WRITE) ] = {
702 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
703 [ C(RESULT_MISS) ] = 0x0,
704 },
705 [ C(OP_PREFETCH) ] = {
706 [ C(RESULT_ACCESS) ] = 0x0,
707 [ C(RESULT_MISS) ] = 0x0,
708 },
709 },
710 [ C(L1I ) ] = {
711 [ C(OP_READ) ] = {
712 [ C(RESULT_ACCESS) ] = 0x0,
713 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
714 },
715 [ C(OP_WRITE) ] = {
716 [ C(RESULT_ACCESS) ] = -1,
717 [ C(RESULT_MISS) ] = -1,
718 },
719 [ C(OP_PREFETCH) ] = {
720 [ C(RESULT_ACCESS) ] = 0x0,
721 [ C(RESULT_MISS) ] = 0x0,
722 },
723 },
724 [ C(LL ) ] = {
725 [ C(OP_READ) ] = {
726 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
727 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
728 },
729 [ C(OP_WRITE) ] = {
730 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
731 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
732 },
733 [ C(OP_PREFETCH) ] = {
734 [ C(RESULT_ACCESS) ] = 0x0,
735 [ C(RESULT_MISS) ] = 0x0,
736 },
737 },
738 [ C(DTLB) ] = {
739 [ C(OP_READ) ] = {
740 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
741 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
742 },
743 [ C(OP_WRITE) ] = {
744 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
745 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
746 },
747 [ C(OP_PREFETCH) ] = {
748 [ C(RESULT_ACCESS) ] = 0x0,
749 [ C(RESULT_MISS) ] = 0x0,
750 },
751 },
752 [ C(ITLB) ] = {
753 [ C(OP_READ) ] = {
754 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
755 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
756 },
757 [ C(OP_WRITE) ] = {
758 [ C(RESULT_ACCESS) ] = -1,
759 [ C(RESULT_MISS) ] = -1,
760 },
761 [ C(OP_PREFETCH) ] = {
762 [ C(RESULT_ACCESS) ] = -1,
763 [ C(RESULT_MISS) ] = -1,
764 },
765 },
766 [ C(BPU ) ] = {
767 [ C(OP_READ) ] = {
768 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
769 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
770 },
771 [ C(OP_WRITE) ] = {
772 [ C(RESULT_ACCESS) ] = -1,
773 [ C(RESULT_MISS) ] = -1,
774 },
775 [ C(OP_PREFETCH) ] = {
776 [ C(RESULT_ACCESS) ] = -1,
777 [ C(RESULT_MISS) ] = -1,
778 },
779 },
780 [ C(NODE) ] = {
781 [ C(OP_READ) ] = {
782 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
783 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
784 },
785 [ C(OP_WRITE) ] = {
786 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
787 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
788 },
789 [ C(OP_PREFETCH) ] = {
790 [ C(RESULT_ACCESS) ] = 0x0,
791 [ C(RESULT_MISS) ] = 0x0,
792 },
793 },
794};
795
796static __initconst const u64 hsw_hw_cache_extra_regs
797 [PERF_COUNT_HW_CACHE_MAX]
798 [PERF_COUNT_HW_CACHE_OP_MAX]
799 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
800{
801 [ C(LL ) ] = {
802 [ C(OP_READ) ] = {
803 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
804 HSW_LLC_ACCESS,
805 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
806 HSW_L3_MISS|HSW_ANY_SNOOP,
807 },
808 [ C(OP_WRITE) ] = {
809 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
810 HSW_LLC_ACCESS,
811 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
812 HSW_L3_MISS|HSW_ANY_SNOOP,
813 },
814 [ C(OP_PREFETCH) ] = {
815 [ C(RESULT_ACCESS) ] = 0x0,
816 [ C(RESULT_MISS) ] = 0x0,
817 },
818 },
819 [ C(NODE) ] = {
820 [ C(OP_READ) ] = {
821 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
822 HSW_L3_MISS_LOCAL_DRAM|
823 HSW_SNOOP_DRAM,
824 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
825 HSW_L3_MISS_REMOTE|
826 HSW_SNOOP_DRAM,
827 },
828 [ C(OP_WRITE) ] = {
829 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
830 HSW_L3_MISS_LOCAL_DRAM|
831 HSW_SNOOP_DRAM,
832 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
833 HSW_L3_MISS_REMOTE|
834 HSW_SNOOP_DRAM,
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0x0,
838 [ C(RESULT_MISS) ] = 0x0,
839 },
840 },
841};
842
caaa8be3 843static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 844 [PERF_COUNT_HW_CACHE_MAX]
845 [PERF_COUNT_HW_CACHE_OP_MAX]
846 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
847{
848 [ C(L1D) ] = {
849 [ C(OP_READ) ] = {
850 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
851 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
852 },
853 [ C(OP_WRITE) ] = {
854 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
855 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
856 },
857 [ C(OP_PREFETCH) ] = {
858 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
859 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
860 },
861 },
862 [ C(L1I ) ] = {
863 [ C(OP_READ) ] = {
864 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
865 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
866 },
867 [ C(OP_WRITE) ] = {
868 [ C(RESULT_ACCESS) ] = -1,
869 [ C(RESULT_MISS) ] = -1,
870 },
871 [ C(OP_PREFETCH) ] = {
872 [ C(RESULT_ACCESS) ] = 0x0,
873 [ C(RESULT_MISS) ] = 0x0,
874 },
875 },
876 [ C(LL ) ] = {
877 [ C(OP_READ) ] = {
63b6a675 878 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 879 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 880 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
881 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 882 },
e994d7d2
AK		 883 /*
884 * Use RFO, not WRITEBACK, because a write miss would typically occur
885 * on RFO.
886 */
f22f54f4 887 [ C(OP_WRITE) ] = {
63b6a675
PZ		 888 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
889 [ C(RESULT_ACCESS) ] = 0x01b7,
890 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 891 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 892 },
893 [ C(OP_PREFETCH) ] = {
63b6a675 894 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 895 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 896 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
897 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 898 },
899 },
900 [ C(DTLB) ] = {
901 [ C(OP_READ) ] = {
902 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
903 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
907 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
908 },
909 [ C(OP_PREFETCH) ] = {
910 [ C(RESULT_ACCESS) ] = 0x0,
911 [ C(RESULT_MISS) ] = 0x0,
912 },
913 },
914 [ C(ITLB) ] = {
915 [ C(OP_READ) ] = {
916 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
917 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
918 },
919 [ C(OP_WRITE) ] = {
920 [ C(RESULT_ACCESS) ] = -1,
921 [ C(RESULT_MISS) ] = -1,
922 },
923 [ C(OP_PREFETCH) ] = {
924 [ C(RESULT_ACCESS) ] = -1,
925 [ C(RESULT_MISS) ] = -1,
926 },
927 },
928 [ C(BPU ) ] = {
929 [ C(OP_READ) ] = {
930 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
931 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
932 },
933 [ C(OP_WRITE) ] = {
934 [ C(RESULT_ACCESS) ] = -1,
935 [ C(RESULT_MISS) ] = -1,
936 },
937 [ C(OP_PREFETCH) ] = {
938 [ C(RESULT_ACCESS) ] = -1,
939 [ C(RESULT_MISS) ] = -1,
940 },
941 },
89d6c0b5
PZ		 942 [ C(NODE) ] = {
943 [ C(OP_READ) ] = {
944 [ C(RESULT_ACCESS) ] = 0x01b7,
945 [ C(RESULT_MISS) ] = 0x01b7,
946 },
947 [ C(OP_WRITE) ] = {
948 [ C(RESULT_ACCESS) ] = 0x01b7,
949 [ C(RESULT_MISS) ] = 0x01b7,
950 },
951 [ C(OP_PREFETCH) ] = {
952 [ C(RESULT_ACCESS) ] = 0x01b7,
953 [ C(RESULT_MISS) ] = 0x01b7,
954 },
955 },
f22f54f4
PZ		 956};
957
e994d7d2 958/*
63b6a675
PZ		 959 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
960 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 961 */
962
63b6a675
PZ		 963#define NHM_DMND_DATA_RD (1 << 0)
964#define NHM_DMND_RFO (1 << 1)
965#define NHM_DMND_IFETCH (1 << 2)
966#define NHM_DMND_WB (1 << 3)
967#define NHM_PF_DATA_RD (1 << 4)
968#define NHM_PF_DATA_RFO (1 << 5)
969#define NHM_PF_IFETCH (1 << 6)
970#define NHM_OFFCORE_OTHER (1 << 7)
971#define NHM_UNCORE_HIT (1 << 8)
972#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
973#define NHM_OTHER_CORE_HITM (1 << 10)
974 /* reserved */
975#define NHM_REMOTE_CACHE_FWD (1 << 12)
976#define NHM_REMOTE_DRAM (1 << 13)
977#define NHM_LOCAL_DRAM (1 << 14)
978#define NHM_NON_DRAM (1 << 15)
979
87e24f4b
PZ		 980#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
981#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 982
983#define NHM_DMND_READ (NHM_DMND_DATA_RD)
984#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
985#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
986
987#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 988#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 989#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 990
991static __initconst const u64 nehalem_hw_cache_extra_regs
992 [PERF_COUNT_HW_CACHE_MAX]
993 [PERF_COUNT_HW_CACHE_OP_MAX]
994 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
995{
996 [ C(LL ) ] = {
997 [ C(OP_READ) ] = {
63b6a675
PZ		 998 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
999 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 1000 },
1001 [ C(OP_WRITE) ] = {
63b6a675
PZ		 1002 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1003 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 1004 },
1005 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 1006 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1007 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 1008 },
89d6c0b5
PZ		 1009 },
1010 [ C(NODE) ] = {
1011 [ C(OP_READ) ] = {
87e24f4b
PZ		 1012 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1013 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 1014 },
1015 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 1016 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1017 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 1018 },
1019 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 1020 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1021 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 1022 },
1023 },
e994d7d2
AK		 1024};
1025
caaa8be3 1026static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 1027 [PERF_COUNT_HW_CACHE_MAX]
1028 [PERF_COUNT_HW_CACHE_OP_MAX]
1029 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1030{
1031 [ C(L1D) ] = {
1032 [ C(OP_READ) ] = {
f4929bd3
PZ		 1033 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1034 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 1035 },
1036 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 1037 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1038 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 1039 },
1040 [ C(OP_PREFETCH) ] = {
1041 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1042 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1043 },
1044 },
1045 [ C(L1I ) ] = {
1046 [ C(OP_READ) ] = {
1047 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1048 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1049 },
1050 [ C(OP_WRITE) ] = {
1051 [ C(RESULT_ACCESS) ] = -1,
1052 [ C(RESULT_MISS) ] = -1,
1053 },
1054 [ C(OP_PREFETCH) ] = {
1055 [ C(RESULT_ACCESS) ] = 0x0,
1056 [ C(RESULT_MISS) ] = 0x0,
1057 },
1058 },
1059 [ C(LL ) ] = {
1060 [ C(OP_READ) ] = {
e994d7d2
AK		 1061 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1062 [ C(RESULT_ACCESS) ] = 0x01b7,
1063 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1064 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 1065 },
e994d7d2
AK		 1066 /*
1067 * Use RFO, not WRITEBACK, because a write miss would typically occur
1068 * on RFO.
1069 */
f22f54f4 1070 [ C(OP_WRITE) ] = {
e994d7d2
AK		 1071 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1072 [ C(RESULT_ACCESS) ] = 0x01b7,
1073 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1074 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1075 },
1076 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 1077 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1078 [ C(RESULT_ACCESS) ] = 0x01b7,
1079 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1080 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1081 },
1082 },
1083 [ C(DTLB) ] = {
1084 [ C(OP_READ) ] = {
1085 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1086 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1087 },
1088 [ C(OP_WRITE) ] = {
1089 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1090 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1091 },
1092 [ C(OP_PREFETCH) ] = {
1093 [ C(RESULT_ACCESS) ] = 0x0,
1094 [ C(RESULT_MISS) ] = 0x0,
1095 },
1096 },
1097 [ C(ITLB) ] = {
1098 [ C(OP_READ) ] = {
1099 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1100 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1101 },
1102 [ C(OP_WRITE) ] = {
1103 [ C(RESULT_ACCESS) ] = -1,
1104 [ C(RESULT_MISS) ] = -1,
1105 },
1106 [ C(OP_PREFETCH) ] = {
1107 [ C(RESULT_ACCESS) ] = -1,
1108 [ C(RESULT_MISS) ] = -1,
1109 },
1110 },
1111 [ C(BPU ) ] = {
1112 [ C(OP_READ) ] = {
1113 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1114 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1115 },
1116 [ C(OP_WRITE) ] = {
1117 [ C(RESULT_ACCESS) ] = -1,
1118 [ C(RESULT_MISS) ] = -1,
1119 },
1120 [ C(OP_PREFETCH) ] = {
1121 [ C(RESULT_ACCESS) ] = -1,
1122 [ C(RESULT_MISS) ] = -1,
1123 },
1124 },
89d6c0b5
PZ		 1125 [ C(NODE) ] = {
1126 [ C(OP_READ) ] = {
1127 [ C(RESULT_ACCESS) ] = 0x01b7,
1128 [ C(RESULT_MISS) ] = 0x01b7,
1129 },
1130 [ C(OP_WRITE) ] = {
1131 [ C(RESULT_ACCESS) ] = 0x01b7,
1132 [ C(RESULT_MISS) ] = 0x01b7,
1133 },
1134 [ C(OP_PREFETCH) ] = {
1135 [ C(RESULT_ACCESS) ] = 0x01b7,
1136 [ C(RESULT_MISS) ] = 0x01b7,
1137 },
1138 },
f22f54f4
PZ		 1139};
1140
caaa8be3 1141static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 1142 [PERF_COUNT_HW_CACHE_MAX]
1143 [PERF_COUNT_HW_CACHE_OP_MAX]
1144 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1145{
1146 [ C(L1D) ] = {
1147 [ C(OP_READ) ] = {
1148 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1149 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1150 },
1151 [ C(OP_WRITE) ] = {
1152 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1153 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1154 },
1155 [ C(OP_PREFETCH) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1157 [ C(RESULT_MISS) ] = 0,
1158 },
1159 },
1160 [ C(L1I ) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1163 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1164 },
1165 [ C(OP_WRITE) ] = {
1166 [ C(RESULT_ACCESS) ] = -1,
1167 [ C(RESULT_MISS) ] = -1,
1168 },
1169 [ C(OP_PREFETCH) ] = {
1170 [ C(RESULT_ACCESS) ] = 0,
1171 [ C(RESULT_MISS) ] = 0,
1172 },
1173 },
1174 [ C(LL ) ] = {
1175 [ C(OP_READ) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1177 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1178 },
1179 [ C(OP_WRITE) ] = {
1180 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1181 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1182 },
1183 [ C(OP_PREFETCH) ] = {
1184 [ C(RESULT_ACCESS) ] = 0,
1185 [ C(RESULT_MISS) ] = 0,
1186 },
1187 },
1188 [ C(DTLB) ] = {
1189 [ C(OP_READ) ] = {
1190 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1191 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1192 },
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1195 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1196 },
1197 [ C(OP_PREFETCH) ] = {
1198 [ C(RESULT_ACCESS) ] = 0,
1199 [ C(RESULT_MISS) ] = 0,
1200 },
1201 },
1202 [ C(ITLB) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1205 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = -1,
1209 [ C(RESULT_MISS) ] = -1,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = -1,
1213 [ C(RESULT_MISS) ] = -1,
1214 },
1215 },
1216 [ C(BPU ) ] = {
1217 [ C(OP_READ) ] = {
1218 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1219 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1220 },
1221 [ C(OP_WRITE) ] = {
1222 [ C(RESULT_ACCESS) ] = -1,
1223 [ C(RESULT_MISS) ] = -1,
1224 },
1225 [ C(OP_PREFETCH) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1228 },
1229 },
1230};
1231
caaa8be3 1232static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1233 [PERF_COUNT_HW_CACHE_MAX]
1234 [PERF_COUNT_HW_CACHE_OP_MAX]
1235 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1236{
1237 [ C(L1D) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1240 [ C(RESULT_MISS) ] = 0,
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1244 [ C(RESULT_MISS) ] = 0,
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0x0,
1248 [ C(RESULT_MISS) ] = 0,
1249 },
1250 },
1251 [ C(L1I ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1254 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = -1,
1258 [ C(RESULT_MISS) ] = -1,
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0,
1262 [ C(RESULT_MISS) ] = 0,
1263 },
1264 },
1265 [ C(LL ) ] = {
1266 [ C(OP_READ) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1268 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1269 },
1270 [ C(OP_WRITE) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1272 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1273 },
1274 [ C(OP_PREFETCH) ] = {
1275 [ C(RESULT_ACCESS) ] = 0,
1276 [ C(RESULT_MISS) ] = 0,
1277 },
1278 },
1279 [ C(DTLB) ] = {
1280 [ C(OP_READ) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1282 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1283 },
1284 [ C(OP_WRITE) ] = {
1285 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1286 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 [ C(RESULT_ACCESS) ] = 0,
1290 [ C(RESULT_MISS) ] = 0,
1291 },
1292 },
1293 [ C(ITLB) ] = {
1294 [ C(OP_READ) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1296 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1297 },
1298 [ C(OP_WRITE) ] = {
1299 [ C(RESULT_ACCESS) ] = -1,
1300 [ C(RESULT_MISS) ] = -1,
1301 },
1302 [ C(OP_PREFETCH) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 },
1307 [ C(BPU ) ] = {
1308 [ C(OP_READ) ] = {
1309 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1310 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1311 },
1312 [ C(OP_WRITE) ] = {
1313 [ C(RESULT_ACCESS) ] = -1,
1314 [ C(RESULT_MISS) ] = -1,
1315 },
1316 [ C(OP_PREFETCH) ] = {
1317 [ C(RESULT_ACCESS) ] = -1,
1318 [ C(RESULT_MISS) ] = -1,
1319 },
1320 },
1321};
1322
1fa64180
YZ		 1323static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1324{
1325 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1 1326 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
ae3f011f 1327 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1fa64180
YZ		 1328 EVENT_EXTRA_END
1329};
1330
1331#define SLM_DMND_READ SNB_DMND_DATA_RD
1332#define SLM_DMND_WRITE SNB_DMND_RFO
1333#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1334
1335#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1336#define SLM_LLC_ACCESS SNB_RESP_ANY
1337#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1338
1339static __initconst const u64 slm_hw_cache_extra_regs
1340 [PERF_COUNT_HW_CACHE_MAX]
1341 [PERF_COUNT_HW_CACHE_OP_MAX]
1342 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1343{
1344 [ C(LL ) ] = {
1345 [ C(OP_READ) ] = {
1346 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1347 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1348 },
1349 [ C(OP_WRITE) ] = {
1350 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1351 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1352 },
1353 [ C(OP_PREFETCH) ] = {
1354 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1355 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1356 },
1357 },
1358};
1359
1360static __initconst const u64 slm_hw_cache_event_ids
1361 [PERF_COUNT_HW_CACHE_MAX]
1362 [PERF_COUNT_HW_CACHE_OP_MAX]
1363 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1364{
1365 [ C(L1D) ] = {
1366 [ C(OP_READ) ] = {
1367 [ C(RESULT_ACCESS) ] = 0,
1368 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1369 },
1370 [ C(OP_WRITE) ] = {
1371 [ C(RESULT_ACCESS) ] = 0,
1372 [ C(RESULT_MISS) ] = 0,
1373 },
1374 [ C(OP_PREFETCH) ] = {
1375 [ C(RESULT_ACCESS) ] = 0,
1376 [ C(RESULT_MISS) ] = 0,
1377 },
1378 },
1379 [ C(L1I ) ] = {
1380 [ C(OP_READ) ] = {
1381 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1382 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1383 },
1384 [ C(OP_WRITE) ] = {
1385 [ C(RESULT_ACCESS) ] = -1,
1386 [ C(RESULT_MISS) ] = -1,
1387 },
1388 [ C(OP_PREFETCH) ] = {
1389 [ C(RESULT_ACCESS) ] = 0,
1390 [ C(RESULT_MISS) ] = 0,
1391 },
1392 },
1393 [ C(LL ) ] = {
1394 [ C(OP_READ) ] = {
1395 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1396 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1397 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1398 },
1399 [ C(OP_WRITE) ] = {
1400 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1401 [ C(RESULT_ACCESS) ] = 0x01b7,
1402 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1403 [ C(RESULT_MISS) ] = 0x01b7,
1404 },
1405 [ C(OP_PREFETCH) ] = {
1406 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1407 [ C(RESULT_ACCESS) ] = 0x01b7,
1408 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1409 [ C(RESULT_MISS) ] = 0x01b7,
1410 },
1411 },
1412 [ C(DTLB) ] = {
1413 [ C(OP_READ) ] = {
1414 [ C(RESULT_ACCESS) ] = 0,
1415 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1416 },
1417 [ C(OP_WRITE) ] = {
1418 [ C(RESULT_ACCESS) ] = 0,
1419 [ C(RESULT_MISS) ] = 0,
1420 },
1421 [ C(OP_PREFETCH) ] = {
1422 [ C(RESULT_ACCESS) ] = 0,
1423 [ C(RESULT_MISS) ] = 0,
1424 },
1425 },
1426 [ C(ITLB) ] = {
1427 [ C(OP_READ) ] = {
1428 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1429 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1430 },
1431 [ C(OP_WRITE) ] = {
1432 [ C(RESULT_ACCESS) ] = -1,
1433 [ C(RESULT_MISS) ] = -1,
1434 },
1435 [ C(OP_PREFETCH) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1438 },
1439 },
1440 [ C(BPU ) ] = {
1441 [ C(OP_READ) ] = {
1442 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1443 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1444 },
1445 [ C(OP_WRITE) ] = {
1446 [ C(RESULT_ACCESS) ] = -1,
1447 [ C(RESULT_MISS) ] = -1,
1448 },
1449 [ C(OP_PREFETCH) ] = {
1450 [ C(RESULT_ACCESS) ] = -1,
1451 [ C(RESULT_MISS) ] = -1,
1452 },
1453 },
1454};
1455
1a78d937
AK		 1456/*
1457 * Use from PMIs where the LBRs are already disabled.
1458 */
1459static void __intel_pmu_disable_all(void)
f22f54f4 1460{
89cbc767 1461 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1462
1463 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1464
15c7ad51 1465 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1466 intel_pmu_disable_bts();
8062382c
AS		 1467 else
1468 intel_bts_disable_local();
ca037701
PZ		 1469
1470 intel_pmu_pebs_disable_all();
1a78d937
AK		 1471}
1472
1473static void intel_pmu_disable_all(void)
1474{
1475 __intel_pmu_disable_all();
caff2bef 1476 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1477}
1478
1a78d937 1479static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1480{
89cbc767 1481 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1482
d329527e 1483 intel_pmu_pebs_enable_all();
1a78d937 1484 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1485 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1486 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1487
15c7ad51 1488 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1489 struct perf_event *event =
15c7ad51 1490 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1491
1492 if (WARN_ON_ONCE(!event))
1493 return;
1494
1495 intel_pmu_enable_bts(event->hw.config);
8062382c
AS		 1496 } else
1497 intel_bts_enable_local();
f22f54f4
PZ		 1498}
1499
1a78d937
AK		 1500static void intel_pmu_enable_all(int added)
1501{
1502 __intel_pmu_enable_all(added, false);
1503}
1504
11164cd4
PZ		 1505/*
1506 * Workaround for:
1507 * Intel Errata AAK100 (model 26)
1508 * Intel Errata AAP53 (model 30)
40b91cd1 1509 * Intel Errata BD53 (model 44)
11164cd4 1510 *
351af072
ZY		 1511 * The official story:
1512 * These chips need to be 'reset' when adding counters by programming the
1513 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1514 * in sequence on the same PMC or on different PMCs.
1515 *
1516 * In practise it appears some of these events do in fact count, and
1517 * we need to programm all 4 events.
11164cd4 1518 */
351af072 1519static void intel_pmu_nhm_workaround(void)
11164cd4 1520{
89cbc767 1521 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1522 static const unsigned long nhm_magic[4] = {
1523 0x4300B5,
1524 0x4300D2,
1525 0x4300B1,
1526 0x4300B1
1527 };
1528 struct perf_event *event;
1529 int i;
11164cd4 1530
351af072
ZY		 1531 /*
1532 * The Errata requires below steps:
1533 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1534 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1535 * the corresponding PMCx;
1536 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1537 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1538 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1539 */
11164cd4 1540
351af072
ZY		 1541 /*
1542 * The real steps we choose are a little different from above.
1543 * A) To reduce MSR operations, we don't run step 1) as they
1544 * are already cleared before this function is called;
1545 * B) Call x86_perf_event_update to save PMCx before configuring
1546 * PERFEVTSELx with magic number;
1547 * C) With step 5), we do clear only when the PERFEVTSELx is
1548 * not used currently.
1549 * D) Call x86_perf_event_set_period to restore PMCx;
1550 */
11164cd4 1551
351af072
ZY		 1552 /* We always operate 4 pairs of PERF Counters */
1553 for (i = 0; i < 4; i++) {
1554 event = cpuc->events[i];
1555 if (event)
1556 x86_perf_event_update(event);
1557 }
11164cd4 1558
351af072
ZY		 1559 for (i = 0; i < 4; i++) {
1560 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1561 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1562 }
1563
1564 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1565 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1566
351af072
ZY		 1567 for (i = 0; i < 4; i++) {
1568 event = cpuc->events[i];
1569
1570 if (event) {
1571 x86_perf_event_set_period(event);
31fa58af 1572 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1573 ARCH_PERFMON_EVENTSEL_ENABLE);
1574 } else
1575 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1576 }
351af072
ZY		 1577}
1578
1579static void intel_pmu_nhm_enable_all(int added)
1580{
1581 if (added)
1582 intel_pmu_nhm_workaround();
11164cd4
PZ		 1583 intel_pmu_enable_all(added);
1584}
1585
f22f54f4
PZ		 1586static inline u64 intel_pmu_get_status(void)
1587{
1588 u64 status;
1589
1590 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1591
1592 return status;
1593}
1594
1595static inline void intel_pmu_ack_status(u64 ack)
1596{
1597 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1598}
1599
ca037701 1600static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1601{
15c7ad51 1602 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1603 u64 ctrl_val, mask;
1604
1605 mask = 0xfULL << (idx * 4);
1606
1607 rdmsrl(hwc->config_base, ctrl_val);
1608 ctrl_val &= ~mask;
7645a24c 1609 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1610}
1611
2b9e344d
PZ		 1612static inline bool event_is_checkpointed(struct perf_event *event)
1613{
1614 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1615}
1616
ca037701 1617static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1618{
aff3d91a 1619 struct hw_perf_event *hwc = &event->hw;
89cbc767 1620 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1621
15c7ad51 1622 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1623 intel_pmu_disable_bts();
1624 intel_pmu_drain_bts_buffer();
1625 return;
1626 }
1627
144d31e6
GN		 1628 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1629 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1630 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1631
60ce0fbd
SE		 1632 /*
1633 * must disable before any actual event
1634 * because any event may be combined with LBR
1635 */
a46a2300 1636 if (needs_branch_stack(event))
60ce0fbd
SE		 1637 intel_pmu_lbr_disable(event);
1638
f22f54f4 1639 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1640 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1641 return;
1642 }
1643
aff3d91a 1644 x86_pmu_disable_event(event);
ca037701 1645
ab608344 1646 if (unlikely(event->attr.precise_ip))
ef21f683 1647 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1648}
1649
ca037701 1650static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1651{
15c7ad51 1652 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1653 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1654
1655 /*
1656 * Enable IRQ generation (0x8),
1657 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1658 * if requested:
1659 */
1660 bits = 0x8ULL;
1661 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1662 bits |= 0x2;
1663 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1664 bits |= 0x1;
1665
1666 /*
1667 * ANY bit is supported in v3 and up
1668 */
1669 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1670 bits |= 0x4;
1671
1672 bits <<= (idx * 4);
1673 mask = 0xfULL << (idx * 4);
1674
1675 rdmsrl(hwc->config_base, ctrl_val);
1676 ctrl_val &= ~mask;
1677 ctrl_val |= bits;
7645a24c 1678 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1679}
1680
aff3d91a 1681static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1682{
aff3d91a 1683 struct hw_perf_event *hwc = &event->hw;
89cbc767 1684 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1685
15c7ad51 1686 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1687 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1688 return;
1689
1690 intel_pmu_enable_bts(hwc->config);
1691 return;
1692 }
60ce0fbd
SE		 1693 /*
1694 * must enabled before any actual event
1695 * because any event may be combined with LBR
1696 */
a46a2300 1697 if (needs_branch_stack(event))
60ce0fbd 1698 intel_pmu_lbr_enable(event);
f22f54f4 1699
144d31e6
GN		 1700 if (event->attr.exclude_host)
1701 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1702 if (event->attr.exclude_guest)
1703 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1704
2b9e344d
PZ		 1705 if (unlikely(event_is_checkpointed(event)))
1706 cpuc->intel_cp_status |= (1ull << hwc->idx);
1707
f22f54f4 1708 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1709 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1710 return;
1711 }
1712
ab608344 1713 if (unlikely(event->attr.precise_ip))
ef21f683 1714 intel_pmu_pebs_enable(event);
ca037701 1715
31fa58af 1716 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1717}
1718
1719/*
1720 * Save and restart an expired event. Called by NMI contexts,
1721 * so it has to be careful about preempting normal event ops:
1722 */
de0428a7 1723int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1724{
cc2ad4ba 1725 x86_perf_event_update(event);
2dbf0116
AK		 1726 /*
1727 * For a checkpointed counter always reset back to 0. This
1728 * avoids a situation where the counter overflows, aborts the
1729 * transaction and is then set back to shortly before the
1730 * overflow, and overflows and aborts again.
1731 */
1732 if (unlikely(event_is_checkpointed(event))) {
1733 /* No race with NMIs because the counter should not be armed */
1734 wrmsrl(event->hw.event_base, 0);
1735 local64_set(&event->hw.prev_count, 0);
1736 }
cc2ad4ba 1737 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1738}
1739
1740static void intel_pmu_reset(void)
1741{
0a3aee0d 1742 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1743 unsigned long flags;
1744 int idx;
1745
948b1bb8 1746 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1747 return;
1748
1749 local_irq_save(flags);
1750
c767a54b 1751 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1752
948b1bb8 1753 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1754 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1755 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1756 }
948b1bb8 1757 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1758 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1759
f22f54f4
PZ		 1760 if (ds)
1761 ds->bts_index = ds->bts_buffer_base;
1762
8882edf7
AK		 1763 /* Ack all overflows and disable fixed counters */
1764 if (x86_pmu.version >= 2) {
1765 intel_pmu_ack_status(intel_pmu_get_status());
1766 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1767 }
1768
1769 /* Reset LBRs and LBR freezing */
1770 if (x86_pmu.lbr_nr) {
1771 update_debugctlmsr(get_debugctlmsr() &
1772 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1773 }
1774
f22f54f4
PZ		 1775 local_irq_restore(flags);
1776}
1777
1778/*
1779 * This handler is triggered by the local APIC, so the APIC IRQ handling
1780 * rules apply:
1781 */
1782static int intel_pmu_handle_irq(struct pt_regs *regs)
1783{
1784 struct perf_sample_data data;
1785 struct cpu_hw_events *cpuc;
1786 int bit, loops;
2e556b5b 1787 u64 status;
b0b2072d 1788 int handled;
f22f54f4 1789
89cbc767 1790 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1791
2bce5dac 1792 /*
72db5596
AK		 1793 * No known reason to not always do late ACK,
1794 * but just in case do it opt-in.
2bce5dac 1795 */
72db5596
AK		 1796 if (!x86_pmu.late_ack)
1797 apic_write(APIC_LVTPC, APIC_DM_NMI);
1a78d937 1798 __intel_pmu_disable_all();
b0b2072d 1799 handled = intel_pmu_drain_bts_buffer();
8062382c 1800 handled += intel_bts_interrupt();
f22f54f4 1801 status = intel_pmu_get_status();
a3ef2229
MM		 1802 if (!status)
1803 goto done;
f22f54f4
PZ		 1804
1805 loops = 0;
1806again:
0f29e573 1807 intel_pmu_lbr_read();
2e556b5b 1808 intel_pmu_ack_status(status);
f22f54f4 1809 if (++loops > 100) {
ae0def05
DH		 1810 static bool warned = false;
1811 if (!warned) {
1812 WARN(1, "perfevents: irq loop stuck!\n");
1813 perf_event_print_debug();
1814 warned = true;
1815 }
f22f54f4 1816 intel_pmu_reset();
3fb2b8dd 1817 goto done;
f22f54f4
PZ		 1818 }
1819
1820 inc_irq_stat(apic_perf_irqs);
ca037701 1821
caff2bef 1822
b292d7a1 1823 /*
d8020bee
AK		 1824 * Ignore a range of extra bits in status that do not indicate
1825 * overflow by themselves.
b292d7a1 1826 */
d8020bee
AK		 1827 status &= ~(GLOBAL_STATUS_COND_CHG |
1828 GLOBAL_STATUS_ASIF |
1829 GLOBAL_STATUS_LBRS_FROZEN);
1830 if (!status)
1831 goto done;
b292d7a1 1832
ca037701
PZ		 1833 /*
1834 * PEBS overflow sets bit 62 in the global status register
1835 */
de725dec
PZ		 1836 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1837 handled++;
ca037701 1838 x86_pmu.drain_pebs(regs);
de725dec 1839 }
ca037701 1840
52ca9ced
AS		 1841 /*
1842 * Intel PT
1843 */
1844 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1845 handled++;
1846 intel_pt_interrupt();
1847 }
1848
2dbf0116 1849 /*
2b9e344d
PZ		 1850 * Checkpointed counters can lead to 'spurious' PMIs because the
1851 * rollback caused by the PMI will have cleared the overflow status
1852 * bit. Therefore always force probe these counters.
2dbf0116 1853 */
2b9e344d 1854 status |= cpuc->intel_cp_status;
2dbf0116 1855
984b3f57 1856 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1857 struct perf_event *event = cpuc->events[bit];
1858
de725dec
PZ		 1859 handled++;
1860
f22f54f4
PZ		 1861 if (!test_bit(bit, cpuc->active_mask))
1862 continue;
1863
1864 if (!intel_pmu_save_and_restart(event))
1865 continue;
1866
fd0d000b 1867 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1868
60ce0fbd
SE		 1869 if (has_branch_stack(event))
1870 data.br_stack = &cpuc->lbr_stack;
1871
a8b0ca17 1872 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1873 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1874 }
1875
f22f54f4
PZ		 1876 /*
1877 * Repeat if there is more work to be done:
1878 */
1879 status = intel_pmu_get_status();
1880 if (status)
1881 goto again;
1882
3fb2b8dd 1883done:
1a78d937 1884 __intel_pmu_enable_all(0, true);
72db5596
AK		 1885 /*
1886 * Only unmask the NMI after the overflow counters
1887 * have been reset. This avoids spurious NMIs on
1888 * Haswell CPUs.
1889 */
1890 if (x86_pmu.late_ack)
1891 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1892 return handled;
f22f54f4
PZ		 1893}
1894
f22f54f4 1895static struct event_constraint *
ca037701 1896intel_bts_constraints(struct perf_event *event)
f22f54f4 1897{
ca037701
PZ		 1898 struct hw_perf_event *hwc = &event->hw;
1899 unsigned int hw_event, bts_event;
f22f54f4 1900
18a073a3
PZ		 1901 if (event->attr.freq)
1902 return NULL;
1903
ca037701
PZ		 1904 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1905 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1906
ca037701 1907 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1908 return &bts_constraint;
ca037701 1909
f22f54f4
PZ		 1910 return NULL;
1911}
1912
ae3f011f 1913static int intel_alt_er(int idx, u64 config)
b79e8941 1914{
ae3f011f 1915 int alt_idx;
9a5e3fb5 1916 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 1917 return idx;
b79e8941 1918
5a425294 1919 if (idx == EXTRA_REG_RSP_0)
ae3f011f 1920 alt_idx = EXTRA_REG_RSP_1;
5a425294
PZ		 1921
1922 if (idx == EXTRA_REG_RSP_1)
ae3f011f 1923 alt_idx = EXTRA_REG_RSP_0;
5a425294 1924
ae3f011f
KL		 1925 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
1926 return idx;
1927
1928 return alt_idx;
5a425294
PZ		 1929}
1930
1931static void intel_fixup_er(struct perf_event *event, int idx)
1932{
1933 event->hw.extra_reg.idx = idx;
1934
1935 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1936 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1937 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1938 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1939 } else if (idx == EXTRA_REG_RSP_1) {
1940 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1941 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1942 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1943 }
b79e8941
PZ		 1944}
1945
efc9f05d
SE		 1946/*
1947 * manage allocation of shared extra msr for certain events
1948 *
1949 * sharing can be:
1950 * per-cpu: to be shared between the various events on a single PMU
1951 * per-core: per-cpu + shared by HT threads
1952 */
a7e3ed1e 1953static struct event_constraint *
efc9f05d 1954__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1955 struct perf_event *event,
1956 struct hw_perf_event_extra *reg)
a7e3ed1e 1957{
efc9f05d 1958 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1959 struct er_account *era;
cd8a38d3 1960 unsigned long flags;
5a425294 1961 int idx = reg->idx;
a7e3ed1e 1962
5a425294
PZ		 1963 /*
1964 * reg->alloc can be set due to existing state, so for fake cpuc we
1965 * need to ignore this, otherwise we might fail to allocate proper fake
1966 * state for this extra reg constraint. Also see the comment below.
1967 */
1968 if (reg->alloc && !cpuc->is_fake)
b36817e8 1969 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1970
b79e8941 1971again:
5a425294 1972 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1973 /*
1974 * we use spin_lock_irqsave() to avoid lockdep issues when
1975 * passing a fake cpuc
1976 */
1977 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1978
1979 if (!atomic_read(&era->ref) || era->config == reg->config) {
1980
5a425294
PZ		 1981 /*
1982 * If its a fake cpuc -- as per validate_{group,event}() we
1983 * shouldn't touch event state and we can avoid doing so
1984 * since both will only call get_event_constraints() once
1985 * on each event, this avoids the need for reg->alloc.
1986 *
1987 * Not doing the ER fixup will only result in era->reg being
1988 * wrong, but since we won't actually try and program hardware
1989 * this isn't a problem either.
1990 */
1991 if (!cpuc->is_fake) {
1992 if (idx != reg->idx)
1993 intel_fixup_er(event, idx);
1994
1995 /*
1996 * x86_schedule_events() can call get_event_constraints()
1997 * multiple times on events in the case of incremental
1998 * scheduling(). reg->alloc ensures we only do the ER
1999 * allocation once.
2000 */
2001 reg->alloc = 1;
2002 }
2003
efc9f05d
SE		 2004 /* lock in msr value */
2005 era->config = reg->config;
2006 era->reg = reg->reg;
2007
2008 /* one more user */
2009 atomic_inc(&era->ref);
2010
a7e3ed1e 2011 /*
b36817e8
SE		 2012 * need to call x86_get_event_constraint()
2013 * to check if associated event has constraints
a7e3ed1e 2014 */
b36817e8 2015 c = NULL;
5a425294 2016 } else {
ae3f011f 2017 idx = intel_alt_er(idx, reg->config);
5a425294
PZ		 2018 if (idx != reg->idx) {
2019 raw_spin_unlock_irqrestore(&era->lock, flags);
2020 goto again;
2021 }
a7e3ed1e 2022 }
cd8a38d3 2023 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 2024
efc9f05d
SE		 2025 return c;
2026}
2027
2028static void
2029__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2030 struct hw_perf_event_extra *reg)
2031{
2032 struct er_account *era;
2033
2034 /*
5a425294
PZ		 2035 * Only put constraint if extra reg was actually allocated. Also takes
2036 * care of event which do not use an extra shared reg.
2037 *
2038 * Also, if this is a fake cpuc we shouldn't touch any event state
2039 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2040 * either since it'll be thrown out.
efc9f05d 2041 */
5a425294 2042 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 2043 return;
2044
2045 era = &cpuc->shared_regs->regs[reg->idx];
2046
2047 /* one fewer user */
2048 atomic_dec(&era->ref);
2049
2050 /* allocate again next time */
2051 reg->alloc = 0;
2052}
2053
2054static struct event_constraint *
2055intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2056 struct perf_event *event)
2057{
b36817e8
SE		 2058 struct event_constraint *c = NULL, *d;
2059 struct hw_perf_event_extra *xreg, *breg;
2060
2061 xreg = &event->hw.extra_reg;
2062 if (xreg->idx != EXTRA_REG_NONE) {
2063 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2064 if (c == &emptyconstraint)
2065 return c;
2066 }
2067 breg = &event->hw.branch_reg;
2068 if (breg->idx != EXTRA_REG_NONE) {
2069 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2070 if (d == &emptyconstraint) {
2071 __intel_shared_reg_put_constraints(cpuc, xreg);
2072 c = d;
2073 }
2074 }
efc9f05d 2075 return c;
a7e3ed1e
AK		 2076}
2077
de0428a7 2078struct event_constraint *
79cba822
SE		 2079x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2080 struct perf_event *event)
de0428a7
KW		 2081{
2082 struct event_constraint *c;
2083
2084 if (x86_pmu.event_constraints) {
2085 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 2086 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 2087 event->hw.flags |= c->flags;
de0428a7 2088 return c;
9fac2cf3 2089 }
de0428a7
KW		 2090 }
2091 }
2092
2093 return &unconstrained;
2094}
2095
f22f54f4 2096static struct event_constraint *
e979121b 2097__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 2098 struct perf_event *event)
f22f54f4
PZ		 2099{
2100 struct event_constraint *c;
2101
ca037701
PZ		 2102 c = intel_bts_constraints(event);
2103 if (c)
2104 return c;
2105
687805e4 2106 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 2107 if (c)
2108 return c;
2109
687805e4 2110 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 2111 if (c)
2112 return c;
2113
79cba822 2114 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 2115}
2116
e979121b
MD		 2117static void
2118intel_start_scheduling(struct cpu_hw_events *cpuc)
2119{
2120 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2121 struct intel_excl_states *xl;
e979121b 2122 int tid = cpuc->excl_thread_id;
e979121b
MD		 2123
2124 /*
2125 * nothing needed if in group validation mode
2126 */
b37609c3 2127 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 2128 return;
b37609c3 2129
e979121b
MD		 2130 /*
2131 * no exclusion needed
2132 */
17186ccd 2133 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2134 return;
2135
e979121b
MD		 2136 xl = &excl_cntrs->states[tid];
2137
2138 xl->sched_started = true;
e979121b
MD		 2139 /*
2140 * lock shared state until we are done scheduling
2141 * in stop_event_scheduling()
2142 * makes scheduling appear as a transaction
2143 */
e979121b 2144 raw_spin_lock(&excl_cntrs->lock);
e979121b
MD		 2145}
2146
0c41e756
PZ		 2147static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2148{
2149 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2150 struct event_constraint *c = cpuc->event_constraint[idx];
2151 struct intel_excl_states *xl;
2152 int tid = cpuc->excl_thread_id;
2153
2154 if (cpuc->is_fake || !is_ht_workaround_enabled())
2155 return;
2156
2157 if (WARN_ON_ONCE(!excl_cntrs))
2158 return;
2159
2160 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2161 return;
2162
2163 xl = &excl_cntrs->states[tid];
2164
2165 lockdep_assert_held(&excl_cntrs->lock);
2166
1fe684e3 2167 if (c->flags & PERF_X86_EVENT_EXCL)
43ef205b 2168 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1fe684e3 2169 else
43ef205b 2170 xl->state[cntr] = INTEL_EXCL_SHARED;
0c41e756
PZ		 2171}
2172
e979121b
MD		 2173static void
2174intel_stop_scheduling(struct cpu_hw_events *cpuc)
2175{
2176 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2177 struct intel_excl_states *xl;
e979121b 2178 int tid = cpuc->excl_thread_id;
e979121b
MD		 2179
2180 /*
2181 * nothing needed if in group validation mode
2182 */
b37609c3 2183 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 2184 return;
2185 /*
2186 * no exclusion needed
2187 */
17186ccd 2188 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2189 return;
2190
e979121b
MD		 2191 xl = &excl_cntrs->states[tid];
2192
e979121b
MD		 2193 xl->sched_started = false;
2194 /*
2195 * release shared state lock (acquired in intel_start_scheduling())
2196 */
2197 raw_spin_unlock(&excl_cntrs->lock);
2198}
2199
2200static struct event_constraint *
2201intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2202 int idx, struct event_constraint *c)
2203{
e979121b 2204 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2205 struct intel_excl_states *xlo;
e979121b 2206 int tid = cpuc->excl_thread_id;
1c565833 2207 int is_excl, i;
e979121b
MD		 2208
2209 /*
2210 * validating a group does not require
2211 * enforcing cross-thread exclusion
2212 */
b37609c3
SE		 2213 if (cpuc->is_fake || !is_ht_workaround_enabled())
2214 return c;
2215
2216 /*
2217 * no exclusion needed
2218 */
17186ccd 2219 if (WARN_ON_ONCE(!excl_cntrs))
e979121b 2220 return c;
e979121b 2221
e979121b
MD		 2222 /*
2223 * because we modify the constraint, we need
2224 * to make a copy. Static constraints come
2225 * from static const tables.
2226 *
2227 * only needed when constraint has not yet
2228 * been cloned (marked dynamic)
2229 */
2230 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
aaf932e8 2231 struct event_constraint *cx;
e979121b 2232
e979121b
MD		 2233 /*
2234 * grab pre-allocated constraint entry
2235 */
2236 cx = &cpuc->constraint_list[idx];
2237
2238 /*
2239 * initialize dynamic constraint
2240 * with static constraint
2241 */
aaf932e8 2242 *cx = *c;
e979121b
MD		 2243
2244 /*
2245 * mark constraint as dynamic, so we
2246 * can free it later on
2247 */
2248 cx->flags |= PERF_X86_EVENT_DYNAMIC;
aaf932e8 2249 c = cx;
e979121b
MD		 2250 }
2251
2252 /*
2253 * From here on, the constraint is dynamic.
2254 * Either it was just allocated above, or it
2255 * was allocated during a earlier invocation
2256 * of this function
2257 */
2258
1c565833
PZ		 2259 /*
2260 * state of sibling HT
2261 */
2262 xlo = &excl_cntrs->states[tid ^ 1];
2263
2264 /*
2265 * event requires exclusive counter access
2266 * across HT threads
2267 */
2268 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2269 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2270 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2271 if (!cpuc->n_excl++)
2272 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2273 }
2274
e979121b
MD		 2275 /*
2276 * Modify static constraint with current dynamic
2277 * state of thread
2278 *
2279 * EXCLUSIVE: sibling counter measuring exclusive event
2280 * SHARED : sibling counter measuring non-exclusive event
2281 * UNUSED : sibling counter unused
2282 */
aaf932e8 2283 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
e979121b
MD		 2284 /*
2285 * exclusive event in sibling counter
2286 * our corresponding counter cannot be used
2287 * regardless of our event
2288 */
1c565833 2289 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
aaf932e8 2290 __clear_bit(i, c->idxmsk);
e979121b
MD		 2291 /*
2292 * if measuring an exclusive event, sibling
2293 * measuring non-exclusive, then counter cannot
2294 * be used
2295 */
1c565833 2296 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
aaf932e8 2297 __clear_bit(i, c->idxmsk);
e979121b
MD		 2298 }
2299
2300 /*
2301 * recompute actual bit weight for scheduling algorithm
2302 */
aaf932e8 2303 c->weight = hweight64(c->idxmsk64);
e979121b
MD		 2304
2305 /*
2306 * if we return an empty mask, then switch
2307 * back to static empty constraint to avoid
2308 * the cost of freeing later on
2309 */
aaf932e8
PZ		 2310 if (c->weight == 0)
2311 c = &emptyconstraint;
e979121b 2312
aaf932e8 2313 return c;
e979121b
MD		 2314}
2315
2316static struct event_constraint *
2317intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2318 struct perf_event *event)
2319{
ebfb4988 2320 struct event_constraint *c1 = NULL;
a90738c2 2321 struct event_constraint *c2;
e979121b 2322
ebfb4988
PZ		 2323 if (idx >= 0) /* fake does < 0 */
2324 c1 = cpuc->event_constraint[idx];
2325
e979121b
MD		 2326 /*
2327 * first time only
2328 * - static constraint: no change across incremental scheduling calls
2329 * - dynamic constraint: handled by intel_get_excl_constraints()
2330 */
a90738c2
SE		 2331 c2 = __intel_get_event_constraints(cpuc, idx, event);
2332 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2333 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2334 c1->weight = c2->weight;
2335 c2 = c1;
2336 }
e979121b
MD		 2337
2338 if (cpuc->excl_cntrs)
a90738c2 2339 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2340
a90738c2 2341 return c2;
e979121b
MD		 2342}
2343
2344static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2345 struct perf_event *event)
2346{
2347 struct hw_perf_event *hwc = &event->hw;
2348 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
e979121b 2349 int tid = cpuc->excl_thread_id;
1c565833 2350 struct intel_excl_states *xl;
e979121b
MD		 2351
2352 /*
2353 * nothing needed if in group validation mode
2354 */
2355 if (cpuc->is_fake)
2356 return;
2357
17186ccd 2358 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2359 return;
2360
cc1790cf
PZ		 2361 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2362 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2363 if (!--cpuc->n_excl)
2364 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2365 }
e979121b
MD		 2366
2367 /*
ba040653
PZ		 2368 * If event was actually assigned, then mark the counter state as
2369 * unused now.
e979121b 2370 */
ba040653
PZ		 2371 if (hwc->idx >= 0) {
2372 xl = &excl_cntrs->states[tid];
2373
2374 /*
2375 * put_constraint may be called from x86_schedule_events()
2376 * which already has the lock held so here make locking
2377 * conditional.
2378 */
2379 if (!xl->sched_started)
2380 raw_spin_lock(&excl_cntrs->lock);
e979121b 2381
1c565833 2382 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
e979121b 2383
ba040653
PZ		 2384 if (!xl->sched_started)
2385 raw_spin_unlock(&excl_cntrs->lock);
2386 }
e979121b
MD		 2387}
2388
efc9f05d
SE		 2389static void
2390intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2391 struct perf_event *event)
2392{
efc9f05d 2393 struct hw_perf_event_extra *reg;
a7e3ed1e 2394
efc9f05d
SE		 2395 reg = &event->hw.extra_reg;
2396 if (reg->idx != EXTRA_REG_NONE)
2397 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2398
2399 reg = &event->hw.branch_reg;
2400 if (reg->idx != EXTRA_REG_NONE)
2401 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2402}
a7e3ed1e 2403
efc9f05d
SE		 2404static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2405 struct perf_event *event)
2406{
2407 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2408
2409 /*
2410 * is PMU has exclusive counter restrictions, then
2411 * all events are subject to and must call the
2412 * put_excl_constraints() routine
2413 */
b371b594 2414 if (cpuc->excl_cntrs)
e979121b 2415 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2416}
2417
0780c927 2418static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2419{
0780c927 2420 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2421 /*
2422 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2423 * (0x003c) so that we can use it with PEBS.
2424 *
2425 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2426 * PEBS capable. However we can use INST_RETIRED.ANY_P
2427 * (0x00c0), which is a PEBS capable event, to get the same
2428 * count.
2429 *
2430 * INST_RETIRED.ANY_P counts the number of cycles that retires
2431 * CNTMASK instructions. By setting CNTMASK to a value (16)
2432 * larger than the maximum number of instructions that can be
2433 * retired per cycle (4) and then inverting the condition, we
2434 * count all cycles that retire 16 or less instructions, which
2435 * is every cycle.
2436 *
2437 * Thereby we gain a PEBS capable cycle counter.
2438 */
f9b4eeb8
PZ		 2439 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2440
0780c927
PZ		 2441 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2442 event->hw.config = alt_config;
2443 }
2444}
2445
2446static void intel_pebs_aliases_snb(struct perf_event *event)
2447{
2448 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2449 /*
2450 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2451 * (0x003c) so that we can use it with PEBS.
2452 *
2453 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2454 * PEBS capable. However we can use UOPS_RETIRED.ALL
2455 * (0x01c2), which is a PEBS capable event, to get the same
2456 * count.
2457 *
2458 * UOPS_RETIRED.ALL counts the number of cycles that retires
2459 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2460 * larger than the maximum number of micro-ops that can be
2461 * retired per cycle (4) and then inverting the condition, we
2462 * count all cycles that retire 16 or less micro-ops, which
2463 * is every cycle.
2464 *
2465 * Thereby we gain a PEBS capable cycle counter.
2466 */
2467 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2468
2469 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2470 event->hw.config = alt_config;
2471 }
0780c927
PZ		 2472}
2473
a7b58d21
AK		 2474static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2475{
2476 unsigned long flags = x86_pmu.free_running_flags;
2477
2478 if (event->attr.use_clockid)
2479 flags &= ~PERF_SAMPLE_TIME;
2480 return flags;
2481}
2482
0780c927
PZ		 2483static int intel_pmu_hw_config(struct perf_event *event)
2484{
2485 int ret = x86_pmu_hw_config(event);
2486
2487 if (ret)
2488 return ret;
2489
851559e3 2490 if (event->attr.precise_ip) {
3569c0d7 2491 if (!event->attr.freq) {
851559e3 2492 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
a7b58d21
AK		 2493 if (!(event->attr.sample_type &
2494 ~intel_pmu_free_running_flags(event)))
3569c0d7
YZ		 2495 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2496 }
851559e3
YZ		 2497 if (x86_pmu.pebs_aliases)
2498 x86_pmu.pebs_aliases(event);
2499 }
7639dae0 2500
a46a2300 2501 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2502 ret = intel_pmu_setup_lbr_filter(event);
2503 if (ret)
2504 return ret;
48070342
AS		 2505
2506 /*
2507 * BTS is set up earlier in this path, so don't account twice
2508 */
2509 if (!intel_pmu_has_bts(event)) {
2510 /* disallow lbr if conflicting events are present */
2511 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2512 return -EBUSY;
2513
2514 event->destroy = hw_perf_lbr_event_destroy;
2515 }
60ce0fbd
SE		 2516 }
2517
b4cdc5c2
PZ		 2518 if (event->attr.type != PERF_TYPE_RAW)
2519 return 0;
2520
2521 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2522 return 0;
2523
2524 if (x86_pmu.version < 3)
2525 return -EINVAL;
2526
2527 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2528 return -EACCES;
2529
2530 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2531
2532 return 0;
2533}
2534
144d31e6
GN		 2535struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2536{
2537 if (x86_pmu.guest_get_msrs)
2538 return x86_pmu.guest_get_msrs(nr);
2539 *nr = 0;
2540 return NULL;
2541}
2542EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2543
2544static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2545{
89cbc767 2546 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2547 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2548
2549 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2550 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2551 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2552 /*
2553 * If PMU counter has PEBS enabled it is not enough to disable counter
2554 * on a guest entry since PEBS memory write can overshoot guest entry
2555 * and corrupt guest memory. Disabling PEBS solves the problem.
2556 */
2557 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2558 arr[1].host = cpuc->pebs_enabled;
2559 arr[1].guest = 0;
144d31e6 2560
26a4f3c0 2561 *nr = 2;
144d31e6
GN		 2562 return arr;
2563}
2564
2565static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2566{
89cbc767 2567 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2568 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2569 int idx;
2570
2571 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2572 struct perf_event *event = cpuc->events[idx];
2573
2574 arr[idx].msr = x86_pmu_config_addr(idx);
2575 arr[idx].host = arr[idx].guest = 0;
2576
2577 if (!test_bit(idx, cpuc->active_mask))
2578 continue;
2579
2580 arr[idx].host = arr[idx].guest =
2581 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2582
2583 if (event->attr.exclude_host)
2584 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2585 else if (event->attr.exclude_guest)
2586 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2587 }
2588
2589 *nr = x86_pmu.num_counters;
2590 return arr;
2591}
2592
2593static void core_pmu_enable_event(struct perf_event *event)
2594{
2595 if (!event->attr.exclude_host)
2596 x86_pmu_enable_event(event);
2597}
2598
2599static void core_pmu_enable_all(int added)
2600{
89cbc767 2601 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2602 int idx;
2603
2604 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2605 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2606
2607 if (!test_bit(idx, cpuc->active_mask) ||
2608 cpuc->events[idx]->attr.exclude_host)
2609 continue;
2610
2611 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2612 }
2613}
2614
3a632cb2
AK		 2615static int hsw_hw_config(struct perf_event *event)
2616{
2617 int ret = intel_pmu_hw_config(event);
2618
2619 if (ret)
2620 return ret;
2621 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2622 return 0;
2623 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2624
2625 /*
2626 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2627 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2628 * this combination.
2629 */
2630 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2631 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2632 event->attr.precise_ip > 0))
2633 return -EOPNOTSUPP;
2634
2dbf0116
AK		 2635 if (event_is_checkpointed(event)) {
2636 /*
2637 * Sampling of checkpointed events can cause situations where
2638 * the CPU constantly aborts because of a overflow, which is
2639 * then checkpointed back and ignored. Forbid checkpointing
2640 * for sampling.
2641 *
2642 * But still allow a long sampling period, so that perf stat
2643 * from KVM works.
2644 */
2645 if (event->attr.sample_period > 0 &&
2646 event->attr.sample_period < 0x7fffffff)
2647 return -EOPNOTSUPP;
2648 }
3a632cb2
AK		 2649 return 0;
2650}
2651
2652static struct event_constraint counter2_constraint =
2653 EVENT_CONSTRAINT(0, 0x4, 0);
2654
2655static struct event_constraint *
79cba822
SE		 2656hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2657 struct perf_event *event)
3a632cb2 2658{
79cba822
SE		 2659 struct event_constraint *c;
2660
2661 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2662
2663 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2664 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2665 if (c->idxmsk64 & (1U << 2))
2666 return &counter2_constraint;
2667 return &emptyconstraint;
2668 }
2669
2670 return c;
2671}
2672
294fe0f5
AK		 2673/*
2674 * Broadwell:
2675 *
2676 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2677 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2678 * the two to enforce a minimum period of 128 (the smallest value that has bits
2679 * 0-5 cleared and >= 100).
2680 *
2681 * Because of how the code in x86_perf_event_set_period() works, the truncation
2682 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2683 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2684 *
2685 * Therefore the effective (average) period matches the requested period,
2686 * despite coarser hardware granularity.
2687 */
2688static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2689{
2690 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2691 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2692 if (left < 128)
2693 left = 128;
2694 left &= ~0x3fu;
2695 }
2696 return left;
2697}
2698
641cc938
JO		 2699PMU_FORMAT_ATTR(event, "config:0-7" );
2700PMU_FORMAT_ATTR(umask, "config:8-15" );
2701PMU_FORMAT_ATTR(edge, "config:18" );
2702PMU_FORMAT_ATTR(pc, "config:19" );
2703PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2704PMU_FORMAT_ATTR(inv, "config:23" );
2705PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2706PMU_FORMAT_ATTR(in_tx, "config:32");
2707PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2708
2709static struct attribute *intel_arch_formats_attr[] = {
2710 &format_attr_event.attr,
2711 &format_attr_umask.attr,
2712 &format_attr_edge.attr,
2713 &format_attr_pc.attr,
2714 &format_attr_inv.attr,
2715 &format_attr_cmask.attr,
2716 NULL,
2717};
2718
0bf79d44
JO		 2719ssize_t intel_event_sysfs_show(char *page, u64 config)
2720{
2721 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2722
2723 return x86_event_sysfs_show(page, config, event);
2724}
2725
de0428a7 2726struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2727{
2728 struct intel_shared_regs *regs;
2729 int i;
2730
2731 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2732 GFP_KERNEL, cpu_to_node(cpu));
2733 if (regs) {
2734 /*
2735 * initialize the locks to keep lockdep happy
2736 */
2737 for (i = 0; i < EXTRA_REG_MAX; i++)
2738 raw_spin_lock_init(&regs->regs[i].lock);
2739
2740 regs->core_id = -1;
2741 }
2742 return regs;
2743}
2744
6f6539ca
MD		 2745static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2746{
2747 struct intel_excl_cntrs *c;
6f6539ca
MD		 2748
2749 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2750 GFP_KERNEL, cpu_to_node(cpu));
2751 if (c) {
2752 raw_spin_lock_init(&c->lock);
6f6539ca
MD		 2753 c->core_id = -1;
2754 }
2755 return c;
2756}
2757
a7e3ed1e
AK		 2758static int intel_pmu_cpu_prepare(int cpu)
2759{
2760 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2761
6f6539ca
MD		 2762 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2763 cpuc->shared_regs = allocate_shared_regs(cpu);
2764 if (!cpuc->shared_regs)
dbc72b7a 2765 goto err;
6f6539ca 2766 }
69092624 2767
6f6539ca
MD		 2768 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2769 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2770
2771 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2772 if (!cpuc->constraint_list)
dbc72b7a 2773 goto err_shared_regs;
6f6539ca
MD		 2774
2775 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
dbc72b7a
PZ		 2776 if (!cpuc->excl_cntrs)
2777 goto err_constraint_list;
2778
6f6539ca
MD		 2779 cpuc->excl_thread_id = 0;
2780 }
a7e3ed1e 2781
a7e3ed1e 2782 return NOTIFY_OK;
dbc72b7a
PZ		 2783
2784err_constraint_list:
2785 kfree(cpuc->constraint_list);
2786 cpuc->constraint_list = NULL;
2787
2788err_shared_regs:
2789 kfree(cpuc->shared_regs);
2790 cpuc->shared_regs = NULL;
2791
2792err:
2793 return NOTIFY_BAD;
a7e3ed1e
AK		 2794}
2795
74846d35
PZ		 2796static void intel_pmu_cpu_starting(int cpu)
2797{
a7e3ed1e
AK		 2798 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2799 int core_id = topology_core_id(cpu);
2800 int i;
2801
69092624
LM		 2802 init_debug_store_on_cpu(cpu);
2803 /*
2804 * Deal with CPUs that don't clear their LBRs on power-up.
2805 */
2806 intel_pmu_lbr_reset();
2807
b36817e8
SE		 2808 cpuc->lbr_sel = NULL;
2809
2810 if (!cpuc->shared_regs)
69092624
LM		 2811 return;
2812
9a5e3fb5 2813 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
90413464
SE		 2814 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2815
06931e62 2816 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
b36817e8 2817 struct intel_shared_regs *pc;
a7e3ed1e 2818
b36817e8
SE		 2819 pc = per_cpu(cpu_hw_events, i).shared_regs;
2820 if (pc && pc->core_id == core_id) {
90413464 2821 *onln = cpuc->shared_regs;
b36817e8
SE		 2822 cpuc->shared_regs = pc;
2823 break;
2824 }
a7e3ed1e 2825 }
b36817e8
SE		 2826 cpuc->shared_regs->core_id = core_id;
2827 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2828 }
2829
b36817e8
SE		 2830 if (x86_pmu.lbr_sel_map)
2831 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 2832
2833 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
06931e62 2834 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6f6539ca
MD		 2835 struct intel_excl_cntrs *c;
2836
2837 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2838 if (c && c->core_id == core_id) {
2839 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2840 cpuc->excl_cntrs = c;
2841 cpuc->excl_thread_id = 1;
2842 break;
2843 }
2844 }
2845 cpuc->excl_cntrs->core_id = core_id;
2846 cpuc->excl_cntrs->refcnt++;
2847 }
74846d35
PZ		 2848}
2849
b37609c3 2850static void free_excl_cntrs(int cpu)
74846d35 2851{
a7e3ed1e 2852 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 2853 struct intel_excl_cntrs *c;
a7e3ed1e 2854
6f6539ca
MD		 2855 c = cpuc->excl_cntrs;
2856 if (c) {
2857 if (c->core_id == -1 || --c->refcnt == 0)
2858 kfree(c);
2859 cpuc->excl_cntrs = NULL;
2860 kfree(cpuc->constraint_list);
2861 cpuc->constraint_list = NULL;
2862 }
b37609c3 2863}
a7e3ed1e 2864
b37609c3
SE		 2865static void intel_pmu_cpu_dying(int cpu)
2866{
2867 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2868 struct intel_shared_regs *pc;
2869
2870 pc = cpuc->shared_regs;
2871 if (pc) {
2872 if (pc->core_id == -1 || --pc->refcnt == 0)
2873 kfree(pc);
2874 cpuc->shared_regs = NULL;
e979121b
MD		 2875 }
2876
b37609c3
SE		 2877 free_excl_cntrs(cpu);
2878
74846d35
PZ		 2879 fini_debug_store_on_cpu(cpu);
2880}
2881
9c964efa
YZ		 2882static void intel_pmu_sched_task(struct perf_event_context *ctx,
2883 bool sched_in)
2884{
2885 if (x86_pmu.pebs_active)
2886 intel_pmu_pebs_sched_task(ctx, sched_in);
2887 if (x86_pmu.lbr_nr)
2888 intel_pmu_lbr_sched_task(ctx, sched_in);
2889}
2890
641cc938
JO		 2891PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2892
a63fcab4
SE		 2893PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2894
d0dc8494
AK		 2895PMU_FORMAT_ATTR(frontend, "config1:0-23");
2896
641cc938
JO		 2897static struct attribute *intel_arch3_formats_attr[] = {
2898 &format_attr_event.attr,
2899 &format_attr_umask.attr,
2900 &format_attr_edge.attr,
2901 &format_attr_pc.attr,
2902 &format_attr_any.attr,
2903 &format_attr_inv.attr,
2904 &format_attr_cmask.attr,
3a632cb2
AK		 2905 &format_attr_in_tx.attr,
2906 &format_attr_in_tx_cp.attr,
641cc938
JO		 2907
2908 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 2909 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 2910 NULL,
2911};
2912
d0dc8494
AK		 2913static struct attribute *skl_format_attr[] = {
2914 &format_attr_frontend.attr,
2915 NULL,
2916};
2917
3b6e0421
JO		 2918static __initconst const struct x86_pmu core_pmu = {
2919 .name = "core",
2920 .handle_irq = x86_pmu_handle_irq,
2921 .disable_all = x86_pmu_disable_all,
2922 .enable_all = core_pmu_enable_all,
2923 .enable = core_pmu_enable_event,
2924 .disable = x86_pmu_disable_event,
2925 .hw_config = x86_pmu_hw_config,
2926 .schedule_events = x86_schedule_events,
2927 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2928 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2929 .event_map = intel_pmu_event_map,
2930 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2931 .apic = 1,
a7b58d21
AK		 2932 .free_running_flags = PEBS_FREERUNNING_FLAGS,
2933
3b6e0421
JO		 2934 /*
2935 * Intel PMCs cannot be accessed sanely above 32-bit width,
2936 * so we install an artificial 1<<31 period regardless of
2937 * the generic event period:
2938 */
2939 .max_period = (1ULL<<31) - 1,
2940 .get_event_constraints = intel_get_event_constraints,
2941 .put_event_constraints = intel_put_event_constraints,
2942 .event_constraints = intel_core_event_constraints,
2943 .guest_get_msrs = core_guest_get_msrs,
2944 .format_attrs = intel_arch_formats_attr,
2945 .events_sysfs_show = intel_event_sysfs_show,
2946
2947 /*
2948 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
2949 * together with PMU version 1 and thus be using core_pmu with
2950 * shared_regs. We need following callbacks here to allocate
2951 * it properly.
2952 */
2953 .cpu_prepare = intel_pmu_cpu_prepare,
2954 .cpu_starting = intel_pmu_cpu_starting,
2955 .cpu_dying = intel_pmu_cpu_dying,
2956};
2957
caaa8be3 2958static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 2959 .name = "Intel",
2960 .handle_irq = intel_pmu_handle_irq,
2961 .disable_all = intel_pmu_disable_all,
2962 .enable_all = intel_pmu_enable_all,
2963 .enable = intel_pmu_enable_event,
2964 .disable = intel_pmu_disable_event,
b4cdc5c2 2965 .hw_config = intel_pmu_hw_config,
a072738e 2966 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2967 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2968 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2969 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2970 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2971 .apic = 1,
a7b58d21 2972 .free_running_flags = PEBS_FREERUNNING_FLAGS,
f22f54f4
PZ		 2973 /*
2974 * Intel PMCs cannot be accessed sanely above 32 bit width,
2975 * so we install an artificial 1<<31 period regardless of
2976 * the generic event period:
2977 */
2978 .max_period = (1ULL << 31) - 1,
3f6da390 2979 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2980 .put_event_constraints = intel_put_event_constraints,
0780c927 2981 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 2982
641cc938 2983 .format_attrs = intel_arch3_formats_attr,
0bf79d44 2984 .events_sysfs_show = intel_event_sysfs_show,
641cc938 2985
a7e3ed1e 2986 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 2987 .cpu_starting = intel_pmu_cpu_starting,
2988 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 2989 .guest_get_msrs = intel_guest_get_msrs,
9c964efa 2990 .sched_task = intel_pmu_sched_task,
f22f54f4
PZ		 2991};
2992
c1d6f42f 2993static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 2994{
2995 /*
2996 * PEBS is unreliable due to:
2997 *
2998 * AJ67 - PEBS may experience CPL leaks
2999 * AJ68 - PEBS PMI may be delayed by one event
3000 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3001 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3002 *
3003 * AJ67 could be worked around by restricting the OS/USR flags.
3004 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3005 *
3006 * AJ106 could possibly be worked around by not allowing LBR
3007 * usage from PEBS, including the fixup.
3008 * AJ68 could possibly be worked around by always programming
ec75a716 3009 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 3010 *
3011 * But taken together it might just make sense to not enable PEBS on
3012 * these chips.
3013 */
c767a54b 3014 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 3015 x86_pmu.pebs = 0;
3016 x86_pmu.pebs_constraints = NULL;
3017}
3018
c93dc84c
PZ		 3019static int intel_snb_pebs_broken(int cpu)
3020{
3021 u32 rev = UINT_MAX; /* default to broken for unknown models */
3022
3023 switch (cpu_data(cpu).x86_model) {
3024 case 42: /* SNB */
3025 rev = 0x28;
3026 break;
3027
3028 case 45: /* SNB-EP */
3029 switch (cpu_data(cpu).x86_mask) {
3030 case 6: rev = 0x618; break;
3031 case 7: rev = 0x70c; break;
3032 }
3033 }
3034
3035 return (cpu_data(cpu).microcode < rev);
3036}
3037
3038static void intel_snb_check_microcode(void)
3039{
3040 int pebs_broken = 0;
3041 int cpu;
3042
3043 get_online_cpus();
3044 for_each_online_cpu(cpu) {
3045 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3046 break;
3047 }
3048 put_online_cpus();
3049
3050 if (pebs_broken == x86_pmu.pebs_broken)
3051 return;
3052
3053 /*
3054 * Serialized by the microcode lock..
3055 */
3056 if (x86_pmu.pebs_broken) {
3057 pr_info("PEBS enabled due to microcode update\n");
3058 x86_pmu.pebs_broken = 0;
3059 } else {
3060 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3061 x86_pmu.pebs_broken = 1;
3062 }
3063}
3064
338b522c
KL		 3065/*
3066 * Under certain circumstances, access certain MSR may cause #GP.
3067 * The function tests if the input MSR can be safely accessed.
3068 */
3069static bool check_msr(unsigned long msr, u64 mask)
3070{
3071 u64 val_old, val_new, val_tmp;
3072
3073 /*
3074 * Read the current value, change it and read it back to see if it
3075 * matches, this is needed to detect certain hardware emulators
3076 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3077 */
3078 if (rdmsrl_safe(msr, &val_old))
3079 return false;
3080
3081 /*
3082 * Only change the bits which can be updated by wrmsrl.
3083 */
3084 val_tmp = val_old ^ mask;
3085 if (wrmsrl_safe(msr, val_tmp) ||
3086 rdmsrl_safe(msr, &val_new))
3087 return false;
3088
3089 if (val_new != val_tmp)
3090 return false;
3091
3092 /* Here it's sure that the MSR can be safely accessed.
3093 * Restore the old value and return.
3094 */
3095 wrmsrl(msr, val_old);
3096
3097 return true;
3098}
3099
c1d6f42f 3100static __init void intel_sandybridge_quirk(void)
6a600a8b 3101{
c93dc84c
PZ		 3102 x86_pmu.check_microcode = intel_snb_check_microcode;
3103 intel_snb_check_microcode();
6a600a8b
PZ		 3104}
3105
c1d6f42f
PZ		 3106static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3107 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3108 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3109 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3110 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3111 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3112 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3113 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 3114};
3115
c1d6f42f
PZ		 3116static __init void intel_arch_events_quirk(void)
3117{
3118 int bit;
3119
3120 /* disable event that reported as not presend by cpuid */
3121 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3122 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 3123 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3124 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 3125 }
3126}
3127
3128static __init void intel_nehalem_quirk(void)
3129{
3130 union cpuid10_ebx ebx;
3131
3132 ebx.full = x86_pmu.events_maskl;
3133 if (ebx.split.no_branch_misses_retired) {
3134 /*
3135 * Erratum AAJ80 detected, we work it around by using
3136 * the BR_MISP_EXEC.ANY event. This will over-count
3137 * branch-misses, but it's still much better than the
3138 * architectural event which is often completely bogus:
3139 */
3140 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3141 ebx.split.no_branch_misses_retired = 0;
3142 x86_pmu.events_maskl = ebx.full;
c767a54b 3143 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 3144 }
3145}
3146
93fcf72c
MD		 3147/*
3148 * enable software workaround for errata:
3149 * SNB: BJ122
3150 * IVB: BV98
3151 * HSW: HSD29
3152 *
3153 * Only needed when HT is enabled. However detecting
b37609c3
SE		 3154 * if HT is enabled is difficult (model specific). So instead,
3155 * we enable the workaround in the early boot, and verify if
3156 * it is needed in a later initcall phase once we have valid
3157 * topology information to check if HT is actually enabled
93fcf72c
MD		 3158 */
3159static __init void intel_ht_bug(void)
3160{
b37609c3 3161 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c 3162
93fcf72c 3163 x86_pmu.start_scheduling = intel_start_scheduling;
0c41e756 3164 x86_pmu.commit_scheduling = intel_commit_scheduling;
93fcf72c 3165 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 3166}
3167
7f2ee91f
IM		 3168EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3169EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 3170
4b2c4f1f 3171/* Haswell special events */
7f2ee91f
IM		 3172EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3173EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3174EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3175EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3176EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3177EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3178EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3179EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3180EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3181EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3182EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3183EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 3184
f9134f36 3185static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 3186 EVENT_PTR(tx_start),
3187 EVENT_PTR(tx_commit),
3188 EVENT_PTR(tx_abort),
3189 EVENT_PTR(tx_capacity),
3190 EVENT_PTR(tx_conflict),
3191 EVENT_PTR(el_start),
3192 EVENT_PTR(el_commit),
3193 EVENT_PTR(el_abort),
3194 EVENT_PTR(el_capacity),
3195 EVENT_PTR(el_conflict),
3196 EVENT_PTR(cycles_t),
3197 EVENT_PTR(cycles_ct),
f9134f36
AK		 3198 EVENT_PTR(mem_ld_hsw),
3199 EVENT_PTR(mem_st_hsw),
3200 NULL
3201};
3202
de0428a7 3203__init int intel_pmu_init(void)
f22f54f4
PZ		 3204{
3205 union cpuid10_edx edx;
3206 union cpuid10_eax eax;
ffb871bc 3207 union cpuid10_ebx ebx;
a1eac7ac 3208 struct event_constraint *c;
f22f54f4 3209 unsigned int unused;
338b522c
KL		 3210 struct extra_reg *er;
3211 int version, i;
f22f54f4
PZ		 3212
3213 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 3214 switch (boot_cpu_data.x86) {
3215 case 0x6:
3216 return p6_pmu_init();
e717bf4e
VW		 3217 case 0xb:
3218 return knc_pmu_init();
a072738e
CG		 3219 case 0xf:
3220 return p4_pmu_init();
3221 }
f22f54f4 3222 return -ENODEV;
f22f54f4
PZ		 3223 }
3224
3225 /*
3226 * Check whether the Architectural PerfMon supports
3227 * Branch Misses Retired hw_event or not.
3228 */
ffb871bc
GN		 3229 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3230 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 3231 return -ENODEV;
3232
3233 version = eax.split.version_id;
3234 if (version < 2)
3235 x86_pmu = core_pmu;
3236 else
3237 x86_pmu = intel_pmu;
3238
3239 x86_pmu.version = version;
948b1bb8
RR		 3240 x86_pmu.num_counters = eax.split.num_counters;
3241 x86_pmu.cntval_bits = eax.split.bit_width;
3242 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 3243
c1d6f42f
PZ		 3244 x86_pmu.events_maskl = ebx.full;
3245 x86_pmu.events_mask_len = eax.split.mask_length;
3246
70ab7003
AK		 3247 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3248
f22f54f4
PZ		 3249 /*
3250 * Quirk: v2 perfmon does not report fixed-purpose events, so
3251 * assume at least 3 events:
3252 */
3253 if (version > 1)
948b1bb8 3254 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 3255
c9b08884 3256 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 3257 u64 capabilities;
3258
3259 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3260 x86_pmu.intel_cap.capabilities = capabilities;
3261 }
3262
ca037701
PZ		 3263 intel_ds_init();
3264
c1d6f42f
PZ		 3265 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3266
f22f54f4
PZ		 3267 /*
3268 * Install the hw-cache-events table:
3269 */
3270 switch (boot_cpu_data.x86_model) {
0f7c29ce 3271 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 3272 pr_cont("Core events, ");
3273 break;
3274
0f7c29ce 3275 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 3276 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 3277 case 22: /* 65nm Core2 "Merom-L" */
3278 case 23: /* 45nm Core2 "Penryn" */
3279 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 3280 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3281 sizeof(hw_cache_event_ids));
3282
caff2bef
PZ		 3283 intel_pmu_lbr_init_core();
3284
f22f54f4 3285 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3286 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3287 pr_cont("Core2 events, ");
3288 break;
3289
0f7c29ce
PZ		 3290 case 30: /* 45nm Nehalem */
3291 case 26: /* 45nm Nehalem-EP */
3292 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 3293 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3294 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3295 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3296 sizeof(hw_cache_extra_regs));
f22f54f4 3297
caff2bef
PZ		 3298 intel_pmu_lbr_init_nhm();
3299
f22f54f4 3300 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3301 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3302 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3303 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3304
f20093ee
SE		 3305 x86_pmu.cpu_events = nhm_events_attrs;
3306
91fc4cc0 3307 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3308 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3309 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3310 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3311 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3312 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3313
c1d6f42f 3314 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3315
11164cd4 3316 pr_cont("Nehalem events, ");
f22f54f4 3317 break;
caff2bef 3318
0f7c29ce
PZ		 3319 case 28: /* 45nm Atom "Pineview" */
3320 case 38: /* 45nm Atom "Lincroft" */
3321 case 39: /* 32nm Atom "Penwell" */
3322 case 53: /* 32nm Atom "Cloverview" */
3323 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 3324 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3325 sizeof(hw_cache_event_ids));
3326
caff2bef
PZ		 3327 intel_pmu_lbr_init_atom();
3328
f22f54f4 3329 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3330 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 3331 pr_cont("Atom events, ");
3332 break;
3333
0f7c29ce 3334 case 55: /* 22nm Atom "Silvermont" */
ef454cae 3335 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 3336 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 3337 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3338 sizeof(hw_cache_event_ids));
3339 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3340 sizeof(hw_cache_extra_regs));
3341
3342 intel_pmu_lbr_init_atom();
3343
3344 x86_pmu.event_constraints = intel_slm_event_constraints;
3345 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3346 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3347 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
1fa64180
YZ		 3348 pr_cont("Silvermont events, ");
3349 break;
3350
0f7c29ce
PZ		 3351 case 37: /* 32nm Westmere */
3352 case 44: /* 32nm Westmere-EP */
3353 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 3354 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3355 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3356 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3357 sizeof(hw_cache_extra_regs));
f22f54f4 3358
caff2bef
PZ		 3359 intel_pmu_lbr_init_nhm();
3360
f22f54f4 3361 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3362 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3363 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3364 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3365 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3366
f20093ee
SE		 3367 x86_pmu.cpu_events = nhm_events_attrs;
3368
30112039 3369 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3370 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3371 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3372 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3373 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3374 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3375
f22f54f4
PZ		 3376 pr_cont("Westmere events, ");
3377 break;
b622d644 3378
0f7c29ce
PZ		 3379 case 42: /* 32nm SandyBridge */
3380 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 3381 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3382 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3383 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3384 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3385 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3386 sizeof(hw_cache_extra_regs));
b06b3d49 3387
c5cc2cd9 3388 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3389
3390 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3391 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3392 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3393 if (boot_cpu_data.x86_model == 45)
3394 x86_pmu.extra_regs = intel_snbep_extra_regs;
3395 else
3396 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3397
3398
ee89cbc2 3399 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3400 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3401 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3402
f20093ee
SE		 3403 x86_pmu.cpu_events = snb_events_attrs;
3404
e04d1b23 3405 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3406 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3407 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3408 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3409 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3410 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3411
b06b3d49
LM		 3412 pr_cont("SandyBridge events, ");
3413 break;
0f7c29ce
PZ		 3414
3415 case 58: /* 22nm IvyBridge */
3416 case 62: /* 22nm IvyBridge-EP/EX */
93fcf72c 3417 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3418 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3419 sizeof(hw_cache_event_ids));
1996388e
VW		 3420 /* dTLB-load-misses on IVB is different than SNB */
3421 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3422
20a36e39
SE		 3423 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3424 sizeof(hw_cache_extra_regs));
3425
3426 intel_pmu_lbr_init_snb();
3427
69943182 3428 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 3429 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3430 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3431 if (boot_cpu_data.x86_model == 62)
3432 x86_pmu.extra_regs = intel_snbep_extra_regs;
3433 else
3434 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3435 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3436 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3437 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3438
f20093ee
SE		 3439 x86_pmu.cpu_events = snb_events_attrs;
3440
20a36e39
SE		 3441 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3442 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3443 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3444
3445 pr_cont("IvyBridge events, ");
3446 break;
3447
b06b3d49 3448
d86c8eaf
AK		 3449 case 60: /* 22nm Haswell Core */
3450 case 63: /* 22nm Haswell Server */
3451 case 69: /* 22nm Haswell ULT */
3452 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
93fcf72c 3453 x86_add_quirk(intel_ht_bug);
72db5596 3454 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3455 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3456 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3457
e9d7f7cd 3458 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3459
3460 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3461 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3462 x86_pmu.extra_regs = intel_snbep_extra_regs;
3044318f 3463 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2 3464 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3465 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3466 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3467
3468 x86_pmu.hw_config = hsw_hw_config;
3469 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3470 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3471 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3472 pr_cont("Haswell events, ");
3473 break;
3474
91f1b705
AK		 3475 case 61: /* 14nm Broadwell Core-M */
3476 case 86: /* 14nm Broadwell Xeon D */
4b36f1a4
AK		 3477 case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3478 case 79: /* 14nm Broadwell Server */
91f1b705
AK		 3479 x86_pmu.late_ack = true;
3480 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3481 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3482
3483 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3484 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3485 BDW_L3_MISS|HSW_SNOOP_DRAM;
3486 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3487 HSW_SNOOP_DRAM;
3488 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3489 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3490 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3491 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3492
78d504bc 3493 intel_pmu_lbr_init_hsw();
91f1b705
AK		 3494
3495 x86_pmu.event_constraints = intel_bdw_event_constraints;
3496 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3497 x86_pmu.extra_regs = intel_snbep_extra_regs;
3498 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3499 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3500 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3501 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3502
3503 x86_pmu.hw_config = hsw_hw_config;
3504 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3505 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3506 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3507 pr_cont("Broadwell events, ");
3508 break;
3509
9a92e16f
AK		 3510 case 78: /* 14nm Skylake Mobile */
3511 case 94: /* 14nm Skylake Desktop */
3512 x86_pmu.late_ack = true;
3513 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3514 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3515 intel_pmu_lbr_init_skl();
3516
3517 x86_pmu.event_constraints = intel_skl_event_constraints;
3518 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3519 x86_pmu.extra_regs = intel_skl_extra_regs;
3520 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3521 /* all extra regs are per-cpu when HT is on */
3522 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3523 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3524
3525 x86_pmu.hw_config = hsw_hw_config;
3526 x86_pmu.get_event_constraints = hsw_get_event_constraints;
d0dc8494
AK		 3527 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3528 skl_format_attr);
9a92e16f
AK		 3529 WARN_ON(!x86_pmu.format_attrs);
3530 x86_pmu.cpu_events = hsw_events_attrs;
3531 pr_cont("Skylake events, ");
3532 break;
3533
f22f54f4 3534 default:
0af3ac1f
AK		 3535 switch (x86_pmu.version) {
3536 case 1:
3537 x86_pmu.event_constraints = intel_v1_event_constraints;
3538 pr_cont("generic architected perfmon v1, ");
3539 break;
3540 default:
3541 /*
3542 * default constraints for v2 and up
3543 */
3544 x86_pmu.event_constraints = intel_gen_event_constraints;
3545 pr_cont("generic architected perfmon, ");
3546 break;
3547 }
f22f54f4 3548 }
ffb871bc 3549
a1eac7ac
RR		 3550 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3551 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3552 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3553 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3554 }
3555 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3556
3557 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3558 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3559 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3560 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3561 }
3562
3563 x86_pmu.intel_ctrl |=
3564 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3565
3566 if (x86_pmu.event_constraints) {
3567 /*
3568 * event on fixed counter2 (REF_CYCLES) only works on this
3569 * counter, so do not extend mask to generic counters
3570 */
3571 for_each_event_constraint(c, x86_pmu.event_constraints) {
2c33645d
PI		 3572 if (c->cmask == FIXED_EVENT_FLAGS
3573 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3574 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac 3575 }
2c33645d
PI		 3576 c->idxmsk64 &=
3577 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3578 c->weight = hweight64(c->idxmsk64);
a1eac7ac
RR		 3579 }
3580 }
3581
338b522c
KL		 3582 /*
3583 * Access LBR MSR may cause #GP under certain circumstances.
3584 * E.g. KVM doesn't support LBR MSR
3585 * Check all LBT MSR here.
3586 * Disable LBR access if any LBR MSRs can not be accessed.
3587 */
3588 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3589 x86_pmu.lbr_nr = 0;
3590 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3591 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3592 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3593 x86_pmu.lbr_nr = 0;
3594 }
3595
3596 /*
3597 * Access extra MSR may cause #GP under certain circumstances.
3598 * E.g. KVM doesn't support offcore event
3599 * Check all extra_regs here.
3600 */
3601 if (x86_pmu.extra_regs) {
3602 for (er = x86_pmu.extra_regs; er->msr; er++) {
8c4fe709 3603 er->extra_msr_access = check_msr(er->msr, 0x11UL);
338b522c
KL		 3604 /* Disable LBR select mapping */
3605 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3606 x86_pmu.lbr_sel_map = NULL;
3607 }
3608 }
3609
069e0c3c
AK		 3610 /* Support full width counters using alternative MSR range */
3611 if (x86_pmu.intel_cap.full_width_write) {
3612 x86_pmu.max_period = x86_pmu.cntval_mask;
3613 x86_pmu.perfctr = MSR_IA32_PMC0;
3614 pr_cont("full-width counters, ");
3615 }
3616
f22f54f4
PZ		 3617 return 0;
3618}
b37609c3
SE		 3619
3620/*
3621 * HT bug: phase 2 init
3622 * Called once we have valid topology information to check
3623 * whether or not HT is enabled
3624 * If HT is off, then we disable the workaround
3625 */
3626static __init int fixup_ht_bug(void)
3627{
3628 int cpu = smp_processor_id();
3629 int w, c;
3630 /*
3631 * problem not present on this CPU model, nothing to do
3632 */
3633 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3634 return 0;
3635
06931e62 3636 w = cpumask_weight(topology_sibling_cpumask(cpu));
b37609c3
SE		 3637 if (w > 1) {
3638 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3639 return 0;
3640 }
3641
ec6a9066 3642 if (lockup_detector_suspend() != 0) {
999bbe49
UO		 3643 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3644 return 0;
3645 }
b37609c3
SE		 3646
3647 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3648
b37609c3 3649 x86_pmu.start_scheduling = NULL;
0c41e756 3650 x86_pmu.commit_scheduling = NULL;
b37609c3
SE		 3651 x86_pmu.stop_scheduling = NULL;
3652
ec6a9066 3653 lockup_detector_resume();
b37609c3
SE		 3654
3655 get_online_cpus();
3656
3657 for_each_online_cpu(c) {
3658 free_excl_cntrs(c);
3659 }
3660
3661 put_online_cpus();
3662 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3663 return 0;
3664}
3665subsys_initcall(fixup_ht_bug)
Linux 6.x block layer and io_uring tree(s)