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perf, intel: Try alternative OFFCORE encodings
[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
f22f54f4
PZ		 1#ifdef CONFIG_CPU_SUP_INTEL
2
a7e3ed1e 3/*
efc9f05d
SE		 4 * Per core/cpu state
5 *
6 * Used to coordinate shared registers between HT threads or
7 * among events on a single PMU.
a7e3ed1e 8 */
efc9f05d
SE		 9struct intel_shared_regs {
10 struct er_account regs[EXTRA_REG_MAX];
11 int refcnt; /* per-core: #HT threads */
12 unsigned core_id; /* per-core: core id */
a7e3ed1e
AK		 13};
14
f22f54f4 15/*
b622d644 16 * Intel PerfMon, used on Core and later.
f22f54f4 17 */
ec75a716 18static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4
PZ		 19{
20 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
21 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
22 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
23 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
24 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
25 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
26 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
27};
28
5c543e3c 29static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 30{
31 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
32 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
33 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
34 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
35 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
36 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
37 EVENT_CONSTRAINT_END
38};
39
5c543e3c 40static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 41{
b622d644
PZ		 42 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
43 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
44 /*
45 * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
46 * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
47 * ratio between these counters.
48 */
49 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 50 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
51 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
52 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
53 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
54 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
55 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
56 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
57 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 58 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 59 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
60 EVENT_CONSTRAINT_END
61};
62
5c543e3c 63static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 64{
b622d644
PZ		 65 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
66 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
67 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 68 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
69 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
70 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
71 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
72 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
73 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
74 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
75 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
76 EVENT_CONSTRAINT_END
77};
78
5c543e3c 79static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 80{
efc9f05d 81 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
a7e3ed1e
AK		 82 EVENT_EXTRA_END
83};
84
5c543e3c 85static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 86{
b622d644
PZ		 87 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
88 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
89 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 90 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
91 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
92 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 93 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 94 EVENT_CONSTRAINT_END
95};
96
5c543e3c 97static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 98{
99 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
100 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
101 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
102 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 103 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
104 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
105 EVENT_CONSTRAINT_END
106};
107
5c543e3c 108static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 109{
efc9f05d
SE		 110 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
111 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
a7e3ed1e
AK		 112 EVENT_EXTRA_END
113};
114
5c543e3c 115static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 116{
b622d644
PZ		 117 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
118 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
119 /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 120 EVENT_CONSTRAINT_END
121};
122
ee89cbc2
SE		 123static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
124 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
125 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
126 EVENT_EXTRA_END
127};
128
f22f54f4
PZ		 129static u64 intel_pmu_event_map(int hw_event)
130{
131 return intel_perfmon_event_map[hw_event];
132}
133
b06b3d49
LM		 134static __initconst const u64 snb_hw_cache_event_ids
135 [PERF_COUNT_HW_CACHE_MAX]
136 [PERF_COUNT_HW_CACHE_OP_MAX]
137 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
138{
139 [ C(L1D) ] = {
140 [ C(OP_READ) ] = {
141 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
142 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
143 },
144 [ C(OP_WRITE) ] = {
145 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
146 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
147 },
148 [ C(OP_PREFETCH) ] = {
149 [ C(RESULT_ACCESS) ] = 0x0,
150 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
151 },
152 },
153 [ C(L1I ) ] = {
154 [ C(OP_READ) ] = {
155 [ C(RESULT_ACCESS) ] = 0x0,
156 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
157 },
158 [ C(OP_WRITE) ] = {
159 [ C(RESULT_ACCESS) ] = -1,
160 [ C(RESULT_MISS) ] = -1,
161 },
162 [ C(OP_PREFETCH) ] = {
163 [ C(RESULT_ACCESS) ] = 0x0,
164 [ C(RESULT_MISS) ] = 0x0,
165 },
166 },
167 [ C(LL ) ] = {
b06b3d49 168 [ C(OP_READ) ] = {
63b6a675 169 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 170 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 171 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
172 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 173 },
174 [ C(OP_WRITE) ] = {
63b6a675 175 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 176 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 177 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
178 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 179 },
180 [ C(OP_PREFETCH) ] = {
63b6a675 181 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 182 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 183 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
184 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 185 },
186 },
187 [ C(DTLB) ] = {
188 [ C(OP_READ) ] = {
189 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
190 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
191 },
192 [ C(OP_WRITE) ] = {
193 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
194 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
195 },
196 [ C(OP_PREFETCH) ] = {
197 [ C(RESULT_ACCESS) ] = 0x0,
198 [ C(RESULT_MISS) ] = 0x0,
199 },
200 },
201 [ C(ITLB) ] = {
202 [ C(OP_READ) ] = {
203 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
204 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
205 },
206 [ C(OP_WRITE) ] = {
207 [ C(RESULT_ACCESS) ] = -1,
208 [ C(RESULT_MISS) ] = -1,
209 },
210 [ C(OP_PREFETCH) ] = {
211 [ C(RESULT_ACCESS) ] = -1,
212 [ C(RESULT_MISS) ] = -1,
213 },
214 },
215 [ C(BPU ) ] = {
216 [ C(OP_READ) ] = {
217 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
218 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
219 },
220 [ C(OP_WRITE) ] = {
221 [ C(RESULT_ACCESS) ] = -1,
222 [ C(RESULT_MISS) ] = -1,
223 },
224 [ C(OP_PREFETCH) ] = {
225 [ C(RESULT_ACCESS) ] = -1,
226 [ C(RESULT_MISS) ] = -1,
227 },
228 },
229};
230
caaa8be3 231static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 232 [PERF_COUNT_HW_CACHE_MAX]
233 [PERF_COUNT_HW_CACHE_OP_MAX]
234 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
235{
236 [ C(L1D) ] = {
237 [ C(OP_READ) ] = {
238 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
239 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
240 },
241 [ C(OP_WRITE) ] = {
242 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
243 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
244 },
245 [ C(OP_PREFETCH) ] = {
246 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
247 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
248 },
249 },
250 [ C(L1I ) ] = {
251 [ C(OP_READ) ] = {
252 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
253 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
254 },
255 [ C(OP_WRITE) ] = {
256 [ C(RESULT_ACCESS) ] = -1,
257 [ C(RESULT_MISS) ] = -1,
258 },
259 [ C(OP_PREFETCH) ] = {
260 [ C(RESULT_ACCESS) ] = 0x0,
261 [ C(RESULT_MISS) ] = 0x0,
262 },
263 },
264 [ C(LL ) ] = {
265 [ C(OP_READ) ] = {
63b6a675 266 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 267 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 268 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
269 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 270 },
e994d7d2
AK		 271 /*
272 * Use RFO, not WRITEBACK, because a write miss would typically occur
273 * on RFO.
274 */
f22f54f4 275 [ C(OP_WRITE) ] = {
63b6a675
PZ		 276 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
277 [ C(RESULT_ACCESS) ] = 0x01b7,
278 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 279 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 280 },
281 [ C(OP_PREFETCH) ] = {
63b6a675 282 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 283 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 284 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
285 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 286 },
287 },
288 [ C(DTLB) ] = {
289 [ C(OP_READ) ] = {
290 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
291 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
292 },
293 [ C(OP_WRITE) ] = {
294 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
295 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
296 },
297 [ C(OP_PREFETCH) ] = {
298 [ C(RESULT_ACCESS) ] = 0x0,
299 [ C(RESULT_MISS) ] = 0x0,
300 },
301 },
302 [ C(ITLB) ] = {
303 [ C(OP_READ) ] = {
304 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
305 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
306 },
307 [ C(OP_WRITE) ] = {
308 [ C(RESULT_ACCESS) ] = -1,
309 [ C(RESULT_MISS) ] = -1,
310 },
311 [ C(OP_PREFETCH) ] = {
312 [ C(RESULT_ACCESS) ] = -1,
313 [ C(RESULT_MISS) ] = -1,
314 },
315 },
316 [ C(BPU ) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
319 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
320 },
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = -1,
323 [ C(RESULT_MISS) ] = -1,
324 },
325 [ C(OP_PREFETCH) ] = {
326 [ C(RESULT_ACCESS) ] = -1,
327 [ C(RESULT_MISS) ] = -1,
328 },
329 },
330};
331
e994d7d2 332/*
63b6a675
PZ		 333 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
334 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 335 */
336
63b6a675
PZ		 337#define NHM_DMND_DATA_RD (1 << 0)
338#define NHM_DMND_RFO (1 << 1)
339#define NHM_DMND_IFETCH (1 << 2)
340#define NHM_DMND_WB (1 << 3)
341#define NHM_PF_DATA_RD (1 << 4)
342#define NHM_PF_DATA_RFO (1 << 5)
343#define NHM_PF_IFETCH (1 << 6)
344#define NHM_OFFCORE_OTHER (1 << 7)
345#define NHM_UNCORE_HIT (1 << 8)
346#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
347#define NHM_OTHER_CORE_HITM (1 << 10)
348 /* reserved */
349#define NHM_REMOTE_CACHE_FWD (1 << 12)
350#define NHM_REMOTE_DRAM (1 << 13)
351#define NHM_LOCAL_DRAM (1 << 14)
352#define NHM_NON_DRAM (1 << 15)
353
354#define NHM_ALL_DRAM (NHM_REMOTE_DRAM|NHM_LOCAL_DRAM)
355
356#define NHM_DMND_READ (NHM_DMND_DATA_RD)
357#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
358#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
359
360#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
361#define NHM_L3_MISS (NHM_NON_DRAM|NHM_ALL_DRAM|NHM_REMOTE_CACHE_FWD)
362#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 363
364static __initconst const u64 nehalem_hw_cache_extra_regs
365 [PERF_COUNT_HW_CACHE_MAX]
366 [PERF_COUNT_HW_CACHE_OP_MAX]
367 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
368{
369 [ C(LL ) ] = {
370 [ C(OP_READ) ] = {
63b6a675
PZ		 371 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
372 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 373 },
374 [ C(OP_WRITE) ] = {
63b6a675
PZ		 375 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
376 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 377 },
378 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 379 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
380 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2
AK		 381 },
382 }
383};
384
caaa8be3 385static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 386 [PERF_COUNT_HW_CACHE_MAX]
387 [PERF_COUNT_HW_CACHE_OP_MAX]
388 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
389{
390 [ C(L1D) ] = {
391 [ C(OP_READ) ] = {
f4929bd3
PZ		 392 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
393 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 394 },
395 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 396 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
397 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 398 },
399 [ C(OP_PREFETCH) ] = {
400 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
401 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
402 },
403 },
404 [ C(L1I ) ] = {
405 [ C(OP_READ) ] = {
406 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
407 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
408 },
409 [ C(OP_WRITE) ] = {
410 [ C(RESULT_ACCESS) ] = -1,
411 [ C(RESULT_MISS) ] = -1,
412 },
413 [ C(OP_PREFETCH) ] = {
414 [ C(RESULT_ACCESS) ] = 0x0,
415 [ C(RESULT_MISS) ] = 0x0,
416 },
417 },
418 [ C(LL ) ] = {
419 [ C(OP_READ) ] = {
e994d7d2
AK		 420 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
421 [ C(RESULT_ACCESS) ] = 0x01b7,
422 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
423 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 424 },
e994d7d2
AK		 425 /*
426 * Use RFO, not WRITEBACK, because a write miss would typically occur
427 * on RFO.
428 */
f22f54f4 429 [ C(OP_WRITE) ] = {
e994d7d2
AK		 430 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
431 [ C(RESULT_ACCESS) ] = 0x01b7,
432 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
433 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 434 },
435 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 436 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
437 [ C(RESULT_ACCESS) ] = 0x01b7,
438 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
439 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 440 },
441 },
442 [ C(DTLB) ] = {
443 [ C(OP_READ) ] = {
444 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
445 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
446 },
447 [ C(OP_WRITE) ] = {
448 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
449 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
450 },
451 [ C(OP_PREFETCH) ] = {
452 [ C(RESULT_ACCESS) ] = 0x0,
453 [ C(RESULT_MISS) ] = 0x0,
454 },
455 },
456 [ C(ITLB) ] = {
457 [ C(OP_READ) ] = {
458 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
459 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
460 },
461 [ C(OP_WRITE) ] = {
462 [ C(RESULT_ACCESS) ] = -1,
463 [ C(RESULT_MISS) ] = -1,
464 },
465 [ C(OP_PREFETCH) ] = {
466 [ C(RESULT_ACCESS) ] = -1,
467 [ C(RESULT_MISS) ] = -1,
468 },
469 },
470 [ C(BPU ) ] = {
471 [ C(OP_READ) ] = {
472 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
473 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
474 },
475 [ C(OP_WRITE) ] = {
476 [ C(RESULT_ACCESS) ] = -1,
477 [ C(RESULT_MISS) ] = -1,
478 },
479 [ C(OP_PREFETCH) ] = {
480 [ C(RESULT_ACCESS) ] = -1,
481 [ C(RESULT_MISS) ] = -1,
482 },
483 },
484};
485
caaa8be3 486static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 487 [PERF_COUNT_HW_CACHE_MAX]
488 [PERF_COUNT_HW_CACHE_OP_MAX]
489 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
490{
491 [ C(L1D) ] = {
492 [ C(OP_READ) ] = {
493 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
494 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
495 },
496 [ C(OP_WRITE) ] = {
497 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
498 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
499 },
500 [ C(OP_PREFETCH) ] = {
501 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
502 [ C(RESULT_MISS) ] = 0,
503 },
504 },
505 [ C(L1I ) ] = {
506 [ C(OP_READ) ] = {
507 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
508 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
509 },
510 [ C(OP_WRITE) ] = {
511 [ C(RESULT_ACCESS) ] = -1,
512 [ C(RESULT_MISS) ] = -1,
513 },
514 [ C(OP_PREFETCH) ] = {
515 [ C(RESULT_ACCESS) ] = 0,
516 [ C(RESULT_MISS) ] = 0,
517 },
518 },
519 [ C(LL ) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
522 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
523 },
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
526 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
527 },
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = 0,
530 [ C(RESULT_MISS) ] = 0,
531 },
532 },
533 [ C(DTLB) ] = {
534 [ C(OP_READ) ] = {
535 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
536 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
537 },
538 [ C(OP_WRITE) ] = {
539 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
540 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
541 },
542 [ C(OP_PREFETCH) ] = {
543 [ C(RESULT_ACCESS) ] = 0,
544 [ C(RESULT_MISS) ] = 0,
545 },
546 },
547 [ C(ITLB) ] = {
548 [ C(OP_READ) ] = {
549 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
550 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
551 },
552 [ C(OP_WRITE) ] = {
553 [ C(RESULT_ACCESS) ] = -1,
554 [ C(RESULT_MISS) ] = -1,
555 },
556 [ C(OP_PREFETCH) ] = {
557 [ C(RESULT_ACCESS) ] = -1,
558 [ C(RESULT_MISS) ] = -1,
559 },
560 },
561 [ C(BPU ) ] = {
562 [ C(OP_READ) ] = {
563 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
564 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
565 },
566 [ C(OP_WRITE) ] = {
567 [ C(RESULT_ACCESS) ] = -1,
568 [ C(RESULT_MISS) ] = -1,
569 },
570 [ C(OP_PREFETCH) ] = {
571 [ C(RESULT_ACCESS) ] = -1,
572 [ C(RESULT_MISS) ] = -1,
573 },
574 },
575};
576
caaa8be3 577static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 578 [PERF_COUNT_HW_CACHE_MAX]
579 [PERF_COUNT_HW_CACHE_OP_MAX]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
581{
582 [ C(L1D) ] = {
583 [ C(OP_READ) ] = {
584 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
585 [ C(RESULT_MISS) ] = 0,
586 },
587 [ C(OP_WRITE) ] = {
588 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
589 [ C(RESULT_MISS) ] = 0,
590 },
591 [ C(OP_PREFETCH) ] = {
592 [ C(RESULT_ACCESS) ] = 0x0,
593 [ C(RESULT_MISS) ] = 0,
594 },
595 },
596 [ C(L1I ) ] = {
597 [ C(OP_READ) ] = {
598 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
599 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
600 },
601 [ C(OP_WRITE) ] = {
602 [ C(RESULT_ACCESS) ] = -1,
603 [ C(RESULT_MISS) ] = -1,
604 },
605 [ C(OP_PREFETCH) ] = {
606 [ C(RESULT_ACCESS) ] = 0,
607 [ C(RESULT_MISS) ] = 0,
608 },
609 },
610 [ C(LL ) ] = {
611 [ C(OP_READ) ] = {
612 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
613 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
614 },
615 [ C(OP_WRITE) ] = {
616 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
617 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
618 },
619 [ C(OP_PREFETCH) ] = {
620 [ C(RESULT_ACCESS) ] = 0,
621 [ C(RESULT_MISS) ] = 0,
622 },
623 },
624 [ C(DTLB) ] = {
625 [ C(OP_READ) ] = {
626 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
627 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
628 },
629 [ C(OP_WRITE) ] = {
630 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
631 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
632 },
633 [ C(OP_PREFETCH) ] = {
634 [ C(RESULT_ACCESS) ] = 0,
635 [ C(RESULT_MISS) ] = 0,
636 },
637 },
638 [ C(ITLB) ] = {
639 [ C(OP_READ) ] = {
640 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
641 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
642 },
643 [ C(OP_WRITE) ] = {
644 [ C(RESULT_ACCESS) ] = -1,
645 [ C(RESULT_MISS) ] = -1,
646 },
647 [ C(OP_PREFETCH) ] = {
648 [ C(RESULT_ACCESS) ] = -1,
649 [ C(RESULT_MISS) ] = -1,
650 },
651 },
652 [ C(BPU ) ] = {
653 [ C(OP_READ) ] = {
654 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
655 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
656 },
657 [ C(OP_WRITE) ] = {
658 [ C(RESULT_ACCESS) ] = -1,
659 [ C(RESULT_MISS) ] = -1,
660 },
661 [ C(OP_PREFETCH) ] = {
662 [ C(RESULT_ACCESS) ] = -1,
663 [ C(RESULT_MISS) ] = -1,
664 },
665 },
666};
667
f22f54f4
PZ		 668static void intel_pmu_disable_all(void)
669{
670 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
671
672 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
673
674 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
675 intel_pmu_disable_bts();
ca037701
PZ		 676
677 intel_pmu_pebs_disable_all();
caff2bef 678 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 679}
680
11164cd4 681static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 682{
683 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
684
d329527e
PZ		 685 intel_pmu_pebs_enable_all();
686 intel_pmu_lbr_enable_all();
f22f54f4
PZ		 687 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
688
689 if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
690 struct perf_event *event =
691 cpuc->events[X86_PMC_IDX_FIXED_BTS];
692
693 if (WARN_ON_ONCE(!event))
694 return;
695
696 intel_pmu_enable_bts(event->hw.config);
697 }
698}
699
11164cd4
PZ		 700/*
701 * Workaround for:
702 * Intel Errata AAK100 (model 26)
703 * Intel Errata AAP53 (model 30)
40b91cd1 704 * Intel Errata BD53 (model 44)
11164cd4 705 *
351af072
ZY		 706 * The official story:
707 * These chips need to be 'reset' when adding counters by programming the
708 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
709 * in sequence on the same PMC or on different PMCs.
710 *
711 * In practise it appears some of these events do in fact count, and
712 * we need to programm all 4 events.
11164cd4 713 */
351af072 714static void intel_pmu_nhm_workaround(void)
11164cd4 715{
351af072
ZY		 716 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
717 static const unsigned long nhm_magic[4] = {
718 0x4300B5,
719 0x4300D2,
720 0x4300B1,
721 0x4300B1
722 };
723 struct perf_event *event;
724 int i;
11164cd4 725
351af072
ZY		 726 /*
727 * The Errata requires below steps:
728 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
729 * 2) Configure 4 PERFEVTSELx with the magic events and clear
730 * the corresponding PMCx;
731 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
732 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
733 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
734 */
11164cd4 735
351af072
ZY		 736 /*
737 * The real steps we choose are a little different from above.
738 * A) To reduce MSR operations, we don't run step 1) as they
739 * are already cleared before this function is called;
740 * B) Call x86_perf_event_update to save PMCx before configuring
741 * PERFEVTSELx with magic number;
742 * C) With step 5), we do clear only when the PERFEVTSELx is
743 * not used currently.
744 * D) Call x86_perf_event_set_period to restore PMCx;
745 */
11164cd4 746
351af072
ZY		 747 /* We always operate 4 pairs of PERF Counters */
748 for (i = 0; i < 4; i++) {
749 event = cpuc->events[i];
750 if (event)
751 x86_perf_event_update(event);
752 }
11164cd4 753
351af072
ZY		 754 for (i = 0; i < 4; i++) {
755 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
756 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
757 }
758
759 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
760 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 761
351af072
ZY		 762 for (i = 0; i < 4; i++) {
763 event = cpuc->events[i];
764
765 if (event) {
766 x86_perf_event_set_period(event);
31fa58af 767 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 768 ARCH_PERFMON_EVENTSEL_ENABLE);
769 } else
770 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 771 }
351af072
ZY		 772}
773
774static void intel_pmu_nhm_enable_all(int added)
775{
776 if (added)
777 intel_pmu_nhm_workaround();
11164cd4
PZ		 778 intel_pmu_enable_all(added);
779}
780
f22f54f4
PZ		 781static inline u64 intel_pmu_get_status(void)
782{
783 u64 status;
784
785 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
786
787 return status;
788}
789
790static inline void intel_pmu_ack_status(u64 ack)
791{
792 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
793}
794
ca037701 795static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 796{
aff3d91a 797 int idx = hwc->idx - X86_PMC_IDX_FIXED;
f22f54f4
PZ		 798 u64 ctrl_val, mask;
799
800 mask = 0xfULL << (idx * 4);
801
802 rdmsrl(hwc->config_base, ctrl_val);
803 ctrl_val &= ~mask;
7645a24c 804 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 805}
806
ca037701 807static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 808{
aff3d91a
PZ		 809 struct hw_perf_event *hwc = &event->hw;
810
811 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 812 intel_pmu_disable_bts();
813 intel_pmu_drain_bts_buffer();
814 return;
815 }
816
817 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 818 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 819 return;
820 }
821
aff3d91a 822 x86_pmu_disable_event(event);
ca037701 823
ab608344 824 if (unlikely(event->attr.precise_ip))
ef21f683 825 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 826}
827
ca037701 828static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 829{
aff3d91a 830 int idx = hwc->idx - X86_PMC_IDX_FIXED;
f22f54f4 831 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 832
833 /*
834 * Enable IRQ generation (0x8),
835 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
836 * if requested:
837 */
838 bits = 0x8ULL;
839 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
840 bits |= 0x2;
841 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
842 bits |= 0x1;
843
844 /*
845 * ANY bit is supported in v3 and up
846 */
847 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
848 bits |= 0x4;
849
850 bits <<= (idx * 4);
851 mask = 0xfULL << (idx * 4);
852
853 rdmsrl(hwc->config_base, ctrl_val);
854 ctrl_val &= ~mask;
855 ctrl_val |= bits;
7645a24c 856 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 857}
858
aff3d91a 859static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 860{
aff3d91a
PZ		 861 struct hw_perf_event *hwc = &event->hw;
862
863 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
0a3aee0d 864 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 865 return;
866
867 intel_pmu_enable_bts(hwc->config);
868 return;
869 }
870
871 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 872 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 873 return;
874 }
875
ab608344 876 if (unlikely(event->attr.precise_ip))
ef21f683 877 intel_pmu_pebs_enable(event);
ca037701 878
31fa58af 879 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 880}
881
882/*
883 * Save and restart an expired event. Called by NMI contexts,
884 * so it has to be careful about preempting normal event ops:
885 */
886static int intel_pmu_save_and_restart(struct perf_event *event)
887{
cc2ad4ba
PZ		 888 x86_perf_event_update(event);
889 return x86_perf_event_set_period(event);
f22f54f4
PZ		 890}
891
892static void intel_pmu_reset(void)
893{
0a3aee0d 894 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 895 unsigned long flags;
896 int idx;
897
948b1bb8 898 if (!x86_pmu.num_counters)
f22f54f4
PZ		 899 return;
900
901 local_irq_save(flags);
902
903 printk("clearing PMU state on CPU#%d\n", smp_processor_id());
904
948b1bb8 905 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
41bf4989
RR		 906 checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
907 checking_wrmsrl(x86_pmu_event_addr(idx), 0ull);
f22f54f4 908 }
948b1bb8 909 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
f22f54f4 910 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 911
f22f54f4
PZ		 912 if (ds)
913 ds->bts_index = ds->bts_buffer_base;
914
915 local_irq_restore(flags);
916}
917
918/*
919 * This handler is triggered by the local APIC, so the APIC IRQ handling
920 * rules apply:
921 */
922static int intel_pmu_handle_irq(struct pt_regs *regs)
923{
924 struct perf_sample_data data;
925 struct cpu_hw_events *cpuc;
926 int bit, loops;
2e556b5b 927 u64 status;
b0b2072d 928 int handled;
f22f54f4 929
dc1d628a 930 perf_sample_data_init(&data, 0);
f22f54f4
PZ		 931
932 cpuc = &__get_cpu_var(cpu_hw_events);
933
2bce5dac
DZ		 934 /*
935 * Some chipsets need to unmask the LVTPC in a particular spot
936 * inside the nmi handler. As a result, the unmasking was pushed
937 * into all the nmi handlers.
938 *
939 * This handler doesn't seem to have any issues with the unmasking
940 * so it was left at the top.
941 */
942 apic_write(APIC_LVTPC, APIC_DM_NMI);
943
3fb2b8dd 944 intel_pmu_disable_all();
b0b2072d 945 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 946 status = intel_pmu_get_status();
947 if (!status) {
11164cd4 948 intel_pmu_enable_all(0);
b0b2072d 949 return handled;
f22f54f4
PZ		 950 }
951
952 loops = 0;
953again:
2e556b5b 954 intel_pmu_ack_status(status);
f22f54f4
PZ		 955 if (++loops > 100) {
956 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
957 perf_event_print_debug();
958 intel_pmu_reset();
3fb2b8dd 959 goto done;
f22f54f4
PZ		 960 }
961
962 inc_irq_stat(apic_perf_irqs);
ca037701 963
caff2bef
PZ		 964 intel_pmu_lbr_read();
965
ca037701
PZ		 966 /*
967 * PEBS overflow sets bit 62 in the global status register
968 */
de725dec
PZ		 969 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
970 handled++;
ca037701 971 x86_pmu.drain_pebs(regs);
de725dec 972 }
ca037701 973
984b3f57 974 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 975 struct perf_event *event = cpuc->events[bit];
976
de725dec
PZ		 977 handled++;
978
f22f54f4
PZ		 979 if (!test_bit(bit, cpuc->active_mask))
980 continue;
981
982 if (!intel_pmu_save_and_restart(event))
983 continue;
984
985 data.period = event->hw.last_period;
986
a8b0ca17 987 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 988 x86_pmu_stop(event, 0);
f22f54f4
PZ		 989 }
990
f22f54f4
PZ		 991 /*
992 * Repeat if there is more work to be done:
993 */
994 status = intel_pmu_get_status();
995 if (status)
996 goto again;
997
3fb2b8dd 998done:
11164cd4 999 intel_pmu_enable_all(0);
de725dec 1000 return handled;
f22f54f4
PZ		 1001}
1002
f22f54f4 1003static struct event_constraint *
ca037701 1004intel_bts_constraints(struct perf_event *event)
f22f54f4 1005{
ca037701
PZ		 1006 struct hw_perf_event *hwc = &event->hw;
1007 unsigned int hw_event, bts_event;
f22f54f4 1008
18a073a3
PZ		 1009 if (event->attr.freq)
1010 return NULL;
1011
ca037701
PZ		 1012 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1013 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1014
ca037701 1015 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1016 return &bts_constraint;
ca037701 1017
f22f54f4
PZ		 1018 return NULL;
1019}
1020
b79e8941
PZ		 1021static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
1022{
1023 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
1024 return false;
1025
1026 if (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
1027 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1028 event->hw.config |= 0x01bb;
1029 event->hw.extra_reg.idx = EXTRA_REG_RSP_1;
1030 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
1031 } else if (event->hw.extra_reg.idx == EXTRA_REG_RSP_1) {
1032 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1033 event->hw.config |= 0x01b7;
1034 event->hw.extra_reg.idx = EXTRA_REG_RSP_0;
1035 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
1036 }
1037
1038 if (event->hw.extra_reg.idx == orig_idx)
1039 return false;
1040
1041 return true;
1042}
1043
efc9f05d
SE		 1044/*
1045 * manage allocation of shared extra msr for certain events
1046 *
1047 * sharing can be:
1048 * per-cpu: to be shared between the various events on a single PMU
1049 * per-core: per-cpu + shared by HT threads
1050 */
a7e3ed1e 1051static struct event_constraint *
efc9f05d 1052__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b79e8941 1053 struct perf_event *event)
a7e3ed1e 1054{
efc9f05d 1055 struct event_constraint *c = &emptyconstraint;
b79e8941 1056 struct hw_perf_event_extra *reg = &event->hw.extra_reg;
a7e3ed1e 1057 struct er_account *era;
cd8a38d3 1058 unsigned long flags;
b79e8941 1059 int orig_idx = reg->idx;
a7e3ed1e 1060
efc9f05d 1061 /* already allocated shared msr */
cd8a38d3 1062 if (reg->alloc)
efc9f05d 1063 return &unconstrained;
a7e3ed1e 1064
b79e8941 1065again:
efc9f05d 1066 era = &cpuc->shared_regs->regs[reg->idx];
cd8a38d3
SE		 1067 /*
1068 * we use spin_lock_irqsave() to avoid lockdep issues when
1069 * passing a fake cpuc
1070 */
1071 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1072
1073 if (!atomic_read(&era->ref) || era->config == reg->config) {
1074
1075 /* lock in msr value */
1076 era->config = reg->config;
1077 era->reg = reg->reg;
1078
1079 /* one more user */
1080 atomic_inc(&era->ref);
1081
1082 /* no need to reallocate during incremental event scheduling */
1083 reg->alloc = 1;
a7e3ed1e
AK		 1084
1085 /*
efc9f05d
SE		 1086 * All events using extra_reg are unconstrained.
1087 * Avoids calling x86_get_event_constraints()
1088 *
1089 * Must revisit if extra_reg controlling events
1090 * ever have constraints. Worst case we go through
1091 * the regular event constraint table.
a7e3ed1e 1092 */
efc9f05d 1093 c = &unconstrained;
b79e8941
PZ		 1094 } else if (intel_try_alt_er(event, orig_idx)) {
1095 raw_spin_unlock(&era->lock);
1096 goto again;
a7e3ed1e 1097 }
cd8a38d3 1098 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1099
efc9f05d
SE		 1100 return c;
1101}
1102
1103static void
1104__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1105 struct hw_perf_event_extra *reg)
1106{
1107 struct er_account *era;
1108
1109 /*
1110 * only put constraint if extra reg was actually
1111 * allocated. Also takes care of event which do
1112 * not use an extra shared reg
1113 */
1114 if (!reg->alloc)
1115 return;
1116
1117 era = &cpuc->shared_regs->regs[reg->idx];
1118
1119 /* one fewer user */
1120 atomic_dec(&era->ref);
1121
1122 /* allocate again next time */
1123 reg->alloc = 0;
1124}
1125
1126static struct event_constraint *
1127intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1128 struct perf_event *event)
1129{
1130 struct event_constraint *c = NULL;
efc9f05d 1131
b79e8941
PZ		 1132 if (event->hw.extra_reg.idx != EXTRA_REG_NONE)
1133 c = __intel_shared_reg_get_constraints(cpuc, event);
1134
efc9f05d 1135 return c;
a7e3ed1e
AK		 1136}
1137
f22f54f4
PZ		 1138static struct event_constraint *
1139intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1140{
1141 struct event_constraint *c;
1142
ca037701
PZ		 1143 c = intel_bts_constraints(event);
1144 if (c)
1145 return c;
1146
1147 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1148 if (c)
1149 return c;
1150
efc9f05d 1151 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1152 if (c)
1153 return c;
1154
f22f54f4
PZ		 1155 return x86_get_event_constraints(cpuc, event);
1156}
1157
efc9f05d
SE		 1158static void
1159intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1160 struct perf_event *event)
1161{
efc9f05d 1162 struct hw_perf_event_extra *reg;
a7e3ed1e 1163
efc9f05d
SE		 1164 reg = &event->hw.extra_reg;
1165 if (reg->idx != EXTRA_REG_NONE)
1166 __intel_shared_reg_put_constraints(cpuc, reg);
1167}
a7e3ed1e 1168
efc9f05d
SE		 1169static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1170 struct perf_event *event)
1171{
1172 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1173}
1174
b4cdc5c2
PZ		 1175static int intel_pmu_hw_config(struct perf_event *event)
1176{
1177 int ret = x86_pmu_hw_config(event);
1178
1179 if (ret)
1180 return ret;
1181
7639dae0
PZ		 1182 if (event->attr.precise_ip &&
1183 (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1184 /*
1185 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1186 * (0x003c) so that we can use it with PEBS.
1187 *
1188 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1189 * PEBS capable. However we can use INST_RETIRED.ANY_P
1190 * (0x00c0), which is a PEBS capable event, to get the same
1191 * count.
1192 *
1193 * INST_RETIRED.ANY_P counts the number of cycles that retires
1194 * CNTMASK instructions. By setting CNTMASK to a value (16)
1195 * larger than the maximum number of instructions that can be
1196 * retired per cycle (4) and then inverting the condition, we
1197 * count all cycles that retire 16 or less instructions, which
1198 * is every cycle.
1199 *
1200 * Thereby we gain a PEBS capable cycle counter.
1201 */
1202 u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
1203
1204 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1205 event->hw.config = alt_config;
1206 }
1207
b4cdc5c2
PZ		 1208 if (event->attr.type != PERF_TYPE_RAW)
1209 return 0;
1210
1211 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1212 return 0;
1213
1214 if (x86_pmu.version < 3)
1215 return -EINVAL;
1216
1217 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1218 return -EACCES;
1219
1220 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1221
1222 return 0;
1223}
1224
caaa8be3 1225static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1226 .name = "core",
1227 .handle_irq = x86_pmu_handle_irq,
1228 .disable_all = x86_pmu_disable_all,
1229 .enable_all = x86_pmu_enable_all,
1230 .enable = x86_pmu_enable_event,
1231 .disable = x86_pmu_disable_event,
b4cdc5c2 1232 .hw_config = x86_pmu_hw_config,
a072738e 1233 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1234 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1235 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1236 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1237 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1238 .apic = 1,
1239 /*
1240 * Intel PMCs cannot be accessed sanely above 32 bit width,
1241 * so we install an artificial 1<<31 period regardless of
1242 * the generic event period:
1243 */
1244 .max_period = (1ULL << 31) - 1,
1245 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1246 .put_event_constraints = intel_put_event_constraints,
f22f54f4
PZ		 1247 .event_constraints = intel_core_event_constraints,
1248};
1249
efc9f05d
SE		 1250static struct intel_shared_regs *allocate_shared_regs(int cpu)
1251{
1252 struct intel_shared_regs *regs;
1253 int i;
1254
1255 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1256 GFP_KERNEL, cpu_to_node(cpu));
1257 if (regs) {
1258 /*
1259 * initialize the locks to keep lockdep happy
1260 */
1261 for (i = 0; i < EXTRA_REG_MAX; i++)
1262 raw_spin_lock_init(&regs->regs[i].lock);
1263
1264 regs->core_id = -1;
1265 }
1266 return regs;
1267}
1268
a7e3ed1e
AK		 1269static int intel_pmu_cpu_prepare(int cpu)
1270{
1271 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1272
efc9f05d 1273 if (!x86_pmu.extra_regs)
69092624
LM		 1274 return NOTIFY_OK;
1275
efc9f05d
SE		 1276 cpuc->shared_regs = allocate_shared_regs(cpu);
1277 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1278 return NOTIFY_BAD;
1279
a7e3ed1e
AK		 1280 return NOTIFY_OK;
1281}
1282
74846d35
PZ		 1283static void intel_pmu_cpu_starting(int cpu)
1284{
a7e3ed1e
AK		 1285 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1286 int core_id = topology_core_id(cpu);
1287 int i;
1288
69092624
LM		 1289 init_debug_store_on_cpu(cpu);
1290 /*
1291 * Deal with CPUs that don't clear their LBRs on power-up.
1292 */
1293 intel_pmu_lbr_reset();
1294
b79e8941 1295 if (!cpuc->shared_regs || (x86_pmu.er_flags & ERF_NO_HT_SHARING))
69092624
LM		 1296 return;
1297
a7e3ed1e 1298 for_each_cpu(i, topology_thread_cpumask(cpu)) {
efc9f05d 1299 struct intel_shared_regs *pc;
a7e3ed1e 1300
efc9f05d 1301 pc = per_cpu(cpu_hw_events, i).shared_regs;
a7e3ed1e 1302 if (pc && pc->core_id == core_id) {
efc9f05d
SE		 1303 kfree(cpuc->shared_regs);
1304 cpuc->shared_regs = pc;
a7e3ed1e
AK		 1305 break;
1306 }
1307 }
1308
efc9f05d
SE		 1309 cpuc->shared_regs->core_id = core_id;
1310 cpuc->shared_regs->refcnt++;
74846d35
PZ		 1311}
1312
1313static void intel_pmu_cpu_dying(int cpu)
1314{
a7e3ed1e 1315 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1316 struct intel_shared_regs *pc;
a7e3ed1e 1317
efc9f05d 1318 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1319 if (pc) {
1320 if (pc->core_id == -1 || --pc->refcnt == 0)
1321 kfree(pc);
efc9f05d 1322 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1323 }
1324
74846d35
PZ		 1325 fini_debug_store_on_cpu(cpu);
1326}
1327
caaa8be3 1328static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1329 .name = "Intel",
1330 .handle_irq = intel_pmu_handle_irq,
1331 .disable_all = intel_pmu_disable_all,
1332 .enable_all = intel_pmu_enable_all,
1333 .enable = intel_pmu_enable_event,
1334 .disable = intel_pmu_disable_event,
b4cdc5c2 1335 .hw_config = intel_pmu_hw_config,
a072738e 1336 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1337 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1338 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1339 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1340 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1341 .apic = 1,
1342 /*
1343 * Intel PMCs cannot be accessed sanely above 32 bit width,
1344 * so we install an artificial 1<<31 period regardless of
1345 * the generic event period:
1346 */
1347 .max_period = (1ULL << 31) - 1,
3f6da390 1348 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1349 .put_event_constraints = intel_put_event_constraints,
3f6da390 1350
a7e3ed1e 1351 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1352 .cpu_starting = intel_pmu_cpu_starting,
1353 .cpu_dying = intel_pmu_cpu_dying,
f22f54f4
PZ		 1354};
1355
3c44780b
PZ		 1356static void intel_clovertown_quirks(void)
1357{
1358 /*
1359 * PEBS is unreliable due to:
1360 *
1361 * AJ67 - PEBS may experience CPL leaks
1362 * AJ68 - PEBS PMI may be delayed by one event
1363 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1364 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1365 *
1366 * AJ67 could be worked around by restricting the OS/USR flags.
1367 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1368 *
1369 * AJ106 could possibly be worked around by not allowing LBR
1370 * usage from PEBS, including the fixup.
1371 * AJ68 could possibly be worked around by always programming
ec75a716 1372 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1373 *
1374 * But taken together it might just make sense to not enable PEBS on
1375 * these chips.
1376 */
1377 printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
1378 x86_pmu.pebs = 0;
1379 x86_pmu.pebs_constraints = NULL;
1380}
1381
f22f54f4
PZ		 1382static __init int intel_pmu_init(void)
1383{
1384 union cpuid10_edx edx;
1385 union cpuid10_eax eax;
1386 unsigned int unused;
1387 unsigned int ebx;
1388 int version;
1389
1390 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 1391 switch (boot_cpu_data.x86) {
1392 case 0x6:
1393 return p6_pmu_init();
1394 case 0xf:
1395 return p4_pmu_init();
1396 }
f22f54f4 1397 return -ENODEV;
f22f54f4
PZ		 1398 }
1399
1400 /*
1401 * Check whether the Architectural PerfMon supports
1402 * Branch Misses Retired hw_event or not.
1403 */
1404 cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1405 if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1406 return -ENODEV;
1407
1408 version = eax.split.version_id;
1409 if (version < 2)
1410 x86_pmu = core_pmu;
1411 else
1412 x86_pmu = intel_pmu;
1413
1414 x86_pmu.version = version;
948b1bb8
RR		 1415 x86_pmu.num_counters = eax.split.num_counters;
1416 x86_pmu.cntval_bits = eax.split.bit_width;
1417 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4
PZ		 1418
1419 /*
1420 * Quirk: v2 perfmon does not report fixed-purpose events, so
1421 * assume at least 3 events:
1422 */
1423 if (version > 1)
948b1bb8 1424 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 1425
8db909a7
PZ		 1426 /*
1427 * v2 and above have a perf capabilities MSR
1428 */
1429 if (version > 1) {
1430 u64 capabilities;
1431
1432 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1433 x86_pmu.intel_cap.capabilities = capabilities;
1434 }
1435
ca037701
PZ		 1436 intel_ds_init();
1437
f22f54f4
PZ		 1438 /*
1439 * Install the hw-cache-events table:
1440 */
1441 switch (boot_cpu_data.x86_model) {
1442 case 14: /* 65 nm core solo/duo, "Yonah" */
1443 pr_cont("Core events, ");
1444 break;
1445
1446 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
3c44780b 1447 x86_pmu.quirks = intel_clovertown_quirks;
f22f54f4
PZ		 1448 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1449 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1450 case 29: /* six-core 45 nm xeon "Dunnington" */
1451 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1452 sizeof(hw_cache_event_ids));
1453
caff2bef
PZ		 1454 intel_pmu_lbr_init_core();
1455
f22f54f4 1456 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 1457 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 1458 pr_cont("Core2 events, ");
1459 break;
1460
1461 case 26: /* 45 nm nehalem, "Bloomfield" */
1462 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 1463 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 1464 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1465 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1466 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1467 sizeof(hw_cache_extra_regs));
f22f54f4 1468
caff2bef
PZ		 1469 intel_pmu_lbr_init_nhm();
1470
f22f54f4 1471 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 1472 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 1473 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 1474 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 1475
91fc4cc0
IM		 1476 /* UOPS_ISSUED.STALLED_CYCLES */
1477 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1478 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8f622422 1479 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
94403f88 1480
ec75a716
IM		 1481 if (ebx & 0x40) {
1482 /*
1483 * Erratum AAJ80 detected, we work it around by using
1484 * the BR_MISP_EXEC.ANY event. This will over-count
1485 * branch-misses, but it's still much better than the
1486 * architectural event which is often completely bogus:
1487 */
1488 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
1489
1490 pr_cont("erratum AAJ80 worked around, ");
1491 }
11164cd4 1492 pr_cont("Nehalem events, ");
f22f54f4 1493 break;
caff2bef 1494
b622d644 1495 case 28: /* Atom */
f22f54f4
PZ		 1496 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1497 sizeof(hw_cache_event_ids));
1498
caff2bef
PZ		 1499 intel_pmu_lbr_init_atom();
1500
f22f54f4 1501 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 1502 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 1503 pr_cont("Atom events, ");
1504 break;
1505
1506 case 37: /* 32 nm nehalem, "Clarkdale" */
1507 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 1508 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 1509 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1510 sizeof(hw_cache_event_ids));
e994d7d2
AK		 1511 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
1512 sizeof(hw_cache_extra_regs));
f22f54f4 1513
caff2bef
PZ		 1514 intel_pmu_lbr_init_nhm();
1515
f22f54f4 1516 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 1517 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 1518 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 1519 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 1520 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039
IM		 1521
1522 /* UOPS_ISSUED.STALLED_CYCLES */
1523 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1524 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
1525 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x1803fb1;
1526
f22f54f4
PZ		 1527 pr_cont("Westmere events, ");
1528 break;
b622d644 1529
b06b3d49
LM		 1530 case 42: /* SandyBridge */
1531 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1532 sizeof(hw_cache_event_ids));
1533
1534 intel_pmu_lbr_init_nhm();
1535
1536 x86_pmu.event_constraints = intel_snb_event_constraints;
1537 x86_pmu.pebs_constraints = intel_snb_pebs_events;
ee89cbc2
SE		 1538 x86_pmu.extra_regs = intel_snb_extra_regs;
1539 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 1540 x86_pmu.er_flags |= ERF_HAS_RSP_1;
1541 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23
LM		 1542
1543 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
1544 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x180010e;
1545 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
1546 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x18001b1;
1547
b06b3d49
LM		 1548 pr_cont("SandyBridge events, ");
1549 break;
1550
f22f54f4
PZ		 1551 default:
1552 /*
1553 * default constraints for v2 and up
1554 */
1555 x86_pmu.event_constraints = intel_gen_event_constraints;
1556 pr_cont("generic architected perfmon, ");
1557 }
1558 return 0;
1559}
1560
1561#else /* CONFIG_CPU_SUP_INTEL */
1562
1563static int intel_pmu_init(void)
1564{
1565 return 0;
1566}
1567
cd8a38d3
SE		 1568static struct intel_shared_regs *allocate_shared_regs(int cpu)
1569{
1570 return NULL;
1571}
f22f54f4 1572#endif /* CONFIG_CPU_SUP_INTEL */
Linux 6.x block layer and io_uring tree(s)