projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
perf/x86/intel: Make the CYCLE_ACTIVITY.* constraint on Broadwell more specific
[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
aacfbe6a 15#include <linux/nmi.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7
KW		 18#include <asm/hardirq.h>
19#include <asm/apic.h>
20
21#include "perf_event.h"
a7e3ed1e 22
f22f54f4 23/*
b622d644 24 * Intel PerfMon, used on Core and later.
f22f54f4 25 */
ec75a716 26static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 27{
c3b7cdf1
PE		 28 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
29 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
30 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
31 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
32 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
33 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
34 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
35 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 36};
37
5c543e3c 38static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 39{
40 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
41 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
42 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
43 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
44 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
45 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
46 EVENT_CONSTRAINT_END
47};
48
5c543e3c 49static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 50{
b622d644
PZ		 51 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
52 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 53 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 54 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
55 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
56 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
57 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
58 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
59 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
60 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
61 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 62 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 63 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
64 EVENT_CONSTRAINT_END
65};
66
5c543e3c 67static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 68{
b622d644
PZ		 69 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
70 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 71 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 72 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
73 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
74 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
75 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
76 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
77 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
78 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
79 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
80 EVENT_CONSTRAINT_END
81};
82
5c543e3c 83static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 84{
53ad0447
YZ		 85 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
86 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 87 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 88 EVENT_EXTRA_END
89};
90
5c543e3c 91static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 92{
b622d644
PZ		 93 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
94 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 95 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 96 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
97 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
98 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 99 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 100 EVENT_CONSTRAINT_END
101};
102
5c543e3c 103static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 104{
105 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
106 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 107 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 108 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
109 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 112 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 113 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
114 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c
MD		 117
118 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
121 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
122
b06b3d49
LM		 123 EVENT_CONSTRAINT_END
124};
125
69943182
SE		 126static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
127{
128 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
129 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
130 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
131 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
133 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 134 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 135 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
136 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
138 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c
MD		 141
142 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
145 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
146
69943182
SE		 147 EVENT_CONSTRAINT_END
148};
149
5c543e3c 150static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 151{
53ad0447
YZ		 152 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
153 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
154 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 155 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 156 EVENT_EXTRA_END
157};
158
0af3ac1f
AK		 159static struct event_constraint intel_v1_event_constraints[] __read_mostly =
160{
161 EVENT_CONSTRAINT_END
162};
163
5c543e3c 164static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 165{
b622d644
PZ		 166 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
167 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 168 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 169 EVENT_CONSTRAINT_END
170};
171
1fa64180
YZ		 172static struct event_constraint intel_slm_event_constraints[] __read_mostly =
173{
174 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
175 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 176 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
177 EVENT_CONSTRAINT_END
178};
179
9a92e16f
AK		 180struct event_constraint intel_skl_event_constraints[] = {
181 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
185 EVENT_CONSTRAINT_END
186};
187
ee89cbc2 188static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 189 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
190 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
191 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 192 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 193 EVENT_EXTRA_END
194};
195
196static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 197 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
198 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
199 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 200 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 201 EVENT_EXTRA_END
202};
203
9a92e16f
AK		 204static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
205 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
206 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
207 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
208 EVENT_EXTRA_END
209};
210
7f2ee91f
IM		 211EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
212EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
213EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 214
215struct attribute *nhm_events_attrs[] = {
216 EVENT_PTR(mem_ld_nhm),
217 NULL,
218};
219
220struct attribute *snb_events_attrs[] = {
221 EVENT_PTR(mem_ld_snb),
9ad64c0f 222 EVENT_PTR(mem_st_snb),
f20093ee
SE		 223 NULL,
224};
225
3a632cb2
AK		 226static struct event_constraint intel_hsw_event_constraints[] = {
227 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
228 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
229 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
230 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
231 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
232 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
233 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 234 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 235 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 236 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 237 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 238 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c
MD		 239
240 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
241 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
242 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
243 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
244
3a632cb2
AK		 245 EVENT_CONSTRAINT_END
246};
247
91f1b705
AK		 248struct event_constraint intel_bdw_event_constraints[] = {
249 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
250 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
251 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
252 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
5e176213 253 INTEL_UEVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
91f1b705
AK		 254 EVENT_CONSTRAINT_END
255};
256
f22f54f4
PZ		 257static u64 intel_pmu_event_map(int hw_event)
258{
259 return intel_perfmon_event_map[hw_event];
260}
261
9a92e16f
AK		 262/*
263 * Notes on the events:
264 * - data reads do not include code reads (comparable to earlier tables)
265 * - data counts include speculative execution (except L1 write, dtlb, bpu)
266 * - remote node access includes remote memory, remote cache, remote mmio.
267 * - prefetches are not included in the counts.
268 * - icache miss does not include decoded icache
269 */
270
271#define SKL_DEMAND_DATA_RD BIT_ULL(0)
272#define SKL_DEMAND_RFO BIT_ULL(1)
273#define SKL_ANY_RESPONSE BIT_ULL(16)
274#define SKL_SUPPLIER_NONE BIT_ULL(17)
275#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
276#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
277#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
278#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
279#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
280 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
281 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
282 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
283#define SKL_SPL_HIT BIT_ULL(30)
284#define SKL_SNOOP_NONE BIT_ULL(31)
285#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
286#define SKL_SNOOP_MISS BIT_ULL(33)
287#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
288#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
289#define SKL_SNOOP_HITM BIT_ULL(36)
290#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
291#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
292 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
293 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
294 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
295#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
296#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
297 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
298 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
299 SKL_SNOOP_HITM|SKL_SPL_HIT)
300#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
301#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
302#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
303 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
304 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
305
306static __initconst const u64 skl_hw_cache_event_ids
307 [PERF_COUNT_HW_CACHE_MAX]
308 [PERF_COUNT_HW_CACHE_OP_MAX]
309 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
310{
311 [ C(L1D ) ] = {
312 [ C(OP_READ) ] = {
313 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
314 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
315 },
316 [ C(OP_WRITE) ] = {
317 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
318 [ C(RESULT_MISS) ] = 0x0,
319 },
320 [ C(OP_PREFETCH) ] = {
321 [ C(RESULT_ACCESS) ] = 0x0,
322 [ C(RESULT_MISS) ] = 0x0,
323 },
324 },
325 [ C(L1I ) ] = {
326 [ C(OP_READ) ] = {
327 [ C(RESULT_ACCESS) ] = 0x0,
328 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
329 },
330 [ C(OP_WRITE) ] = {
331 [ C(RESULT_ACCESS) ] = -1,
332 [ C(RESULT_MISS) ] = -1,
333 },
334 [ C(OP_PREFETCH) ] = {
335 [ C(RESULT_ACCESS) ] = 0x0,
336 [ C(RESULT_MISS) ] = 0x0,
337 },
338 },
339 [ C(LL ) ] = {
340 [ C(OP_READ) ] = {
341 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
342 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
343 },
344 [ C(OP_WRITE) ] = {
345 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
346 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
347 },
348 [ C(OP_PREFETCH) ] = {
349 [ C(RESULT_ACCESS) ] = 0x0,
350 [ C(RESULT_MISS) ] = 0x0,
351 },
352 },
353 [ C(DTLB) ] = {
354 [ C(OP_READ) ] = {
355 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
356 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
357 },
358 [ C(OP_WRITE) ] = {
359 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
360 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
361 },
362 [ C(OP_PREFETCH) ] = {
363 [ C(RESULT_ACCESS) ] = 0x0,
364 [ C(RESULT_MISS) ] = 0x0,
365 },
366 },
367 [ C(ITLB) ] = {
368 [ C(OP_READ) ] = {
369 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
370 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
371 },
372 [ C(OP_WRITE) ] = {
373 [ C(RESULT_ACCESS) ] = -1,
374 [ C(RESULT_MISS) ] = -1,
375 },
376 [ C(OP_PREFETCH) ] = {
377 [ C(RESULT_ACCESS) ] = -1,
378 [ C(RESULT_MISS) ] = -1,
379 },
380 },
381 [ C(BPU ) ] = {
382 [ C(OP_READ) ] = {
383 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
384 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
385 },
386 [ C(OP_WRITE) ] = {
387 [ C(RESULT_ACCESS) ] = -1,
388 [ C(RESULT_MISS) ] = -1,
389 },
390 [ C(OP_PREFETCH) ] = {
391 [ C(RESULT_ACCESS) ] = -1,
392 [ C(RESULT_MISS) ] = -1,
393 },
394 },
395 [ C(NODE) ] = {
396 [ C(OP_READ) ] = {
397 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
398 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
399 },
400 [ C(OP_WRITE) ] = {
401 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
402 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
403 },
404 [ C(OP_PREFETCH) ] = {
405 [ C(RESULT_ACCESS) ] = 0x0,
406 [ C(RESULT_MISS) ] = 0x0,
407 },
408 },
409};
410
411static __initconst const u64 skl_hw_cache_extra_regs
412 [PERF_COUNT_HW_CACHE_MAX]
413 [PERF_COUNT_HW_CACHE_OP_MAX]
414 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
415{
416 [ C(LL ) ] = {
417 [ C(OP_READ) ] = {
418 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
419 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
420 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
421 SKL_L3_MISS|SKL_ANY_SNOOP|
422 SKL_SUPPLIER_NONE,
423 },
424 [ C(OP_WRITE) ] = {
425 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
426 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
427 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
428 SKL_L3_MISS|SKL_ANY_SNOOP|
429 SKL_SUPPLIER_NONE,
430 },
431 [ C(OP_PREFETCH) ] = {
432 [ C(RESULT_ACCESS) ] = 0x0,
433 [ C(RESULT_MISS) ] = 0x0,
434 },
435 },
436 [ C(NODE) ] = {
437 [ C(OP_READ) ] = {
438 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
439 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
440 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
441 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
442 },
443 [ C(OP_WRITE) ] = {
444 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
445 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
446 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
447 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
448 },
449 [ C(OP_PREFETCH) ] = {
450 [ C(RESULT_ACCESS) ] = 0x0,
451 [ C(RESULT_MISS) ] = 0x0,
452 },
453 },
454};
455
74e6543f
YZ		 456#define SNB_DMND_DATA_RD (1ULL << 0)
457#define SNB_DMND_RFO (1ULL << 1)
458#define SNB_DMND_IFETCH (1ULL << 2)
459#define SNB_DMND_WB (1ULL << 3)
460#define SNB_PF_DATA_RD (1ULL << 4)
461#define SNB_PF_RFO (1ULL << 5)
462#define SNB_PF_IFETCH (1ULL << 6)
463#define SNB_LLC_DATA_RD (1ULL << 7)
464#define SNB_LLC_RFO (1ULL << 8)
465#define SNB_LLC_IFETCH (1ULL << 9)
466#define SNB_BUS_LOCKS (1ULL << 10)
467#define SNB_STRM_ST (1ULL << 11)
468#define SNB_OTHER (1ULL << 15)
469#define SNB_RESP_ANY (1ULL << 16)
470#define SNB_NO_SUPP (1ULL << 17)
471#define SNB_LLC_HITM (1ULL << 18)
472#define SNB_LLC_HITE (1ULL << 19)
473#define SNB_LLC_HITS (1ULL << 20)
474#define SNB_LLC_HITF (1ULL << 21)
475#define SNB_LOCAL (1ULL << 22)
476#define SNB_REMOTE (0xffULL << 23)
477#define SNB_SNP_NONE (1ULL << 31)
478#define SNB_SNP_NOT_NEEDED (1ULL << 32)
479#define SNB_SNP_MISS (1ULL << 33)
480#define SNB_NO_FWD (1ULL << 34)
481#define SNB_SNP_FWD (1ULL << 35)
482#define SNB_HITM (1ULL << 36)
483#define SNB_NON_DRAM (1ULL << 37)
484
485#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
486#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
487#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
488
489#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
490 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
491 SNB_HITM)
492
493#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
494#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
495
496#define SNB_L3_ACCESS SNB_RESP_ANY
497#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
498
499static __initconst const u64 snb_hw_cache_extra_regs
500 [PERF_COUNT_HW_CACHE_MAX]
501 [PERF_COUNT_HW_CACHE_OP_MAX]
502 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
503{
504 [ C(LL ) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
507 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
511 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
515 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
516 },
517 },
518 [ C(NODE) ] = {
519 [ C(OP_READ) ] = {
520 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
521 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
522 },
523 [ C(OP_WRITE) ] = {
524 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
525 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
529 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
530 },
531 },
532};
533
b06b3d49
LM		 534static __initconst const u64 snb_hw_cache_event_ids
535 [PERF_COUNT_HW_CACHE_MAX]
536 [PERF_COUNT_HW_CACHE_OP_MAX]
537 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
538{
539 [ C(L1D) ] = {
540 [ C(OP_READ) ] = {
541 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
542 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
543 },
544 [ C(OP_WRITE) ] = {
545 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
546 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
547 },
548 [ C(OP_PREFETCH) ] = {
549 [ C(RESULT_ACCESS) ] = 0x0,
550 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
551 },
552 },
553 [ C(L1I ) ] = {
554 [ C(OP_READ) ] = {
555 [ C(RESULT_ACCESS) ] = 0x0,
556 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
557 },
558 [ C(OP_WRITE) ] = {
559 [ C(RESULT_ACCESS) ] = -1,
560 [ C(RESULT_MISS) ] = -1,
561 },
562 [ C(OP_PREFETCH) ] = {
563 [ C(RESULT_ACCESS) ] = 0x0,
564 [ C(RESULT_MISS) ] = 0x0,
565 },
566 },
567 [ C(LL ) ] = {
b06b3d49 568 [ C(OP_READ) ] = {
63b6a675 569 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 570 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 571 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
572 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 573 },
574 [ C(OP_WRITE) ] = {
63b6a675 575 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 576 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 577 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
578 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 579 },
580 [ C(OP_PREFETCH) ] = {
63b6a675 581 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 582 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 583 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
584 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 585 },
586 },
587 [ C(DTLB) ] = {
588 [ C(OP_READ) ] = {
589 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
590 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
591 },
592 [ C(OP_WRITE) ] = {
593 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
594 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
595 },
596 [ C(OP_PREFETCH) ] = {
597 [ C(RESULT_ACCESS) ] = 0x0,
598 [ C(RESULT_MISS) ] = 0x0,
599 },
600 },
601 [ C(ITLB) ] = {
602 [ C(OP_READ) ] = {
603 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
604 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
605 },
606 [ C(OP_WRITE) ] = {
607 [ C(RESULT_ACCESS) ] = -1,
608 [ C(RESULT_MISS) ] = -1,
609 },
610 [ C(OP_PREFETCH) ] = {
611 [ C(RESULT_ACCESS) ] = -1,
612 [ C(RESULT_MISS) ] = -1,
613 },
614 },
615 [ C(BPU ) ] = {
616 [ C(OP_READ) ] = {
617 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
618 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
619 },
620 [ C(OP_WRITE) ] = {
621 [ C(RESULT_ACCESS) ] = -1,
622 [ C(RESULT_MISS) ] = -1,
623 },
624 [ C(OP_PREFETCH) ] = {
625 [ C(RESULT_ACCESS) ] = -1,
626 [ C(RESULT_MISS) ] = -1,
627 },
628 },
89d6c0b5
PZ		 629 [ C(NODE) ] = {
630 [ C(OP_READ) ] = {
74e6543f
YZ		 631 [ C(RESULT_ACCESS) ] = 0x01b7,
632 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 633 },
634 [ C(OP_WRITE) ] = {
74e6543f
YZ		 635 [ C(RESULT_ACCESS) ] = 0x01b7,
636 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 637 },
638 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 639 [ C(RESULT_ACCESS) ] = 0x01b7,
640 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 641 },
642 },
643
b06b3d49
LM		 644};
645
0f1b5ca2
AK		 646/*
647 * Notes on the events:
648 * - data reads do not include code reads (comparable to earlier tables)
649 * - data counts include speculative execution (except L1 write, dtlb, bpu)
650 * - remote node access includes remote memory, remote cache, remote mmio.
651 * - prefetches are not included in the counts because they are not
652 * reliably counted.
653 */
654
655#define HSW_DEMAND_DATA_RD BIT_ULL(0)
656#define HSW_DEMAND_RFO BIT_ULL(1)
657#define HSW_ANY_RESPONSE BIT_ULL(16)
658#define HSW_SUPPLIER_NONE BIT_ULL(17)
659#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
660#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
661#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
662#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
663#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
664 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
665 HSW_L3_MISS_REMOTE_HOP2P)
666#define HSW_SNOOP_NONE BIT_ULL(31)
667#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
668#define HSW_SNOOP_MISS BIT_ULL(33)
669#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
670#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
671#define HSW_SNOOP_HITM BIT_ULL(36)
672#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
673#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
674 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
675 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
676 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
677#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
678#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
679#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
680#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
681 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
682#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
683
91f1b705
AK		 684#define BDW_L3_MISS_LOCAL BIT(26)
685#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
686 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
687 HSW_L3_MISS_REMOTE_HOP2P)
688
689
0f1b5ca2
AK		 690static __initconst const u64 hsw_hw_cache_event_ids
691 [PERF_COUNT_HW_CACHE_MAX]
692 [PERF_COUNT_HW_CACHE_OP_MAX]
693 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
694{
695 [ C(L1D ) ] = {
696 [ C(OP_READ) ] = {
697 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
698 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
699 },
700 [ C(OP_WRITE) ] = {
701 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
702 [ C(RESULT_MISS) ] = 0x0,
703 },
704 [ C(OP_PREFETCH) ] = {
705 [ C(RESULT_ACCESS) ] = 0x0,
706 [ C(RESULT_MISS) ] = 0x0,
707 },
708 },
709 [ C(L1I ) ] = {
710 [ C(OP_READ) ] = {
711 [ C(RESULT_ACCESS) ] = 0x0,
712 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
713 },
714 [ C(OP_WRITE) ] = {
715 [ C(RESULT_ACCESS) ] = -1,
716 [ C(RESULT_MISS) ] = -1,
717 },
718 [ C(OP_PREFETCH) ] = {
719 [ C(RESULT_ACCESS) ] = 0x0,
720 [ C(RESULT_MISS) ] = 0x0,
721 },
722 },
723 [ C(LL ) ] = {
724 [ C(OP_READ) ] = {
725 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
726 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
727 },
728 [ C(OP_WRITE) ] = {
729 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
730 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
731 },
732 [ C(OP_PREFETCH) ] = {
733 [ C(RESULT_ACCESS) ] = 0x0,
734 [ C(RESULT_MISS) ] = 0x0,
735 },
736 },
737 [ C(DTLB) ] = {
738 [ C(OP_READ) ] = {
739 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
740 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
741 },
742 [ C(OP_WRITE) ] = {
743 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
744 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
745 },
746 [ C(OP_PREFETCH) ] = {
747 [ C(RESULT_ACCESS) ] = 0x0,
748 [ C(RESULT_MISS) ] = 0x0,
749 },
750 },
751 [ C(ITLB) ] = {
752 [ C(OP_READ) ] = {
753 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
754 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
755 },
756 [ C(OP_WRITE) ] = {
757 [ C(RESULT_ACCESS) ] = -1,
758 [ C(RESULT_MISS) ] = -1,
759 },
760 [ C(OP_PREFETCH) ] = {
761 [ C(RESULT_ACCESS) ] = -1,
762 [ C(RESULT_MISS) ] = -1,
763 },
764 },
765 [ C(BPU ) ] = {
766 [ C(OP_READ) ] = {
767 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
768 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
769 },
770 [ C(OP_WRITE) ] = {
771 [ C(RESULT_ACCESS) ] = -1,
772 [ C(RESULT_MISS) ] = -1,
773 },
774 [ C(OP_PREFETCH) ] = {
775 [ C(RESULT_ACCESS) ] = -1,
776 [ C(RESULT_MISS) ] = -1,
777 },
778 },
779 [ C(NODE) ] = {
780 [ C(OP_READ) ] = {
781 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
782 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
783 },
784 [ C(OP_WRITE) ] = {
785 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
786 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
787 },
788 [ C(OP_PREFETCH) ] = {
789 [ C(RESULT_ACCESS) ] = 0x0,
790 [ C(RESULT_MISS) ] = 0x0,
791 },
792 },
793};
794
795static __initconst const u64 hsw_hw_cache_extra_regs
796 [PERF_COUNT_HW_CACHE_MAX]
797 [PERF_COUNT_HW_CACHE_OP_MAX]
798 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
799{
800 [ C(LL ) ] = {
801 [ C(OP_READ) ] = {
802 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
803 HSW_LLC_ACCESS,
804 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
805 HSW_L3_MISS|HSW_ANY_SNOOP,
806 },
807 [ C(OP_WRITE) ] = {
808 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
809 HSW_LLC_ACCESS,
810 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
811 HSW_L3_MISS|HSW_ANY_SNOOP,
812 },
813 [ C(OP_PREFETCH) ] = {
814 [ C(RESULT_ACCESS) ] = 0x0,
815 [ C(RESULT_MISS) ] = 0x0,
816 },
817 },
818 [ C(NODE) ] = {
819 [ C(OP_READ) ] = {
820 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
821 HSW_L3_MISS_LOCAL_DRAM|
822 HSW_SNOOP_DRAM,
823 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
824 HSW_L3_MISS_REMOTE|
825 HSW_SNOOP_DRAM,
826 },
827 [ C(OP_WRITE) ] = {
828 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
829 HSW_L3_MISS_LOCAL_DRAM|
830 HSW_SNOOP_DRAM,
831 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
832 HSW_L3_MISS_REMOTE|
833 HSW_SNOOP_DRAM,
834 },
835 [ C(OP_PREFETCH) ] = {
836 [ C(RESULT_ACCESS) ] = 0x0,
837 [ C(RESULT_MISS) ] = 0x0,
838 },
839 },
840};
841
caaa8be3 842static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 843 [PERF_COUNT_HW_CACHE_MAX]
844 [PERF_COUNT_HW_CACHE_OP_MAX]
845 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
846{
847 [ C(L1D) ] = {
848 [ C(OP_READ) ] = {
849 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
850 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
851 },
852 [ C(OP_WRITE) ] = {
853 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
854 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
855 },
856 [ C(OP_PREFETCH) ] = {
857 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
858 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
859 },
860 },
861 [ C(L1I ) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
864 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
865 },
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = -1,
868 [ C(RESULT_MISS) ] = -1,
869 },
870 [ C(OP_PREFETCH) ] = {
871 [ C(RESULT_ACCESS) ] = 0x0,
872 [ C(RESULT_MISS) ] = 0x0,
873 },
874 },
875 [ C(LL ) ] = {
876 [ C(OP_READ) ] = {
63b6a675 877 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 878 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 879 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
880 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 881 },
e994d7d2
AK		 882 /*
883 * Use RFO, not WRITEBACK, because a write miss would typically occur
884 * on RFO.
885 */
f22f54f4 886 [ C(OP_WRITE) ] = {
63b6a675
PZ		 887 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
888 [ C(RESULT_ACCESS) ] = 0x01b7,
889 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 890 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 891 },
892 [ C(OP_PREFETCH) ] = {
63b6a675 893 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 894 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 895 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
896 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 897 },
898 },
899 [ C(DTLB) ] = {
900 [ C(OP_READ) ] = {
901 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
902 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
903 },
904 [ C(OP_WRITE) ] = {
905 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
906 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
907 },
908 [ C(OP_PREFETCH) ] = {
909 [ C(RESULT_ACCESS) ] = 0x0,
910 [ C(RESULT_MISS) ] = 0x0,
911 },
912 },
913 [ C(ITLB) ] = {
914 [ C(OP_READ) ] = {
915 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
916 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
917 },
918 [ C(OP_WRITE) ] = {
919 [ C(RESULT_ACCESS) ] = -1,
920 [ C(RESULT_MISS) ] = -1,
921 },
922 [ C(OP_PREFETCH) ] = {
923 [ C(RESULT_ACCESS) ] = -1,
924 [ C(RESULT_MISS) ] = -1,
925 },
926 },
927 [ C(BPU ) ] = {
928 [ C(OP_READ) ] = {
929 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
930 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
931 },
932 [ C(OP_WRITE) ] = {
933 [ C(RESULT_ACCESS) ] = -1,
934 [ C(RESULT_MISS) ] = -1,
935 },
936 [ C(OP_PREFETCH) ] = {
937 [ C(RESULT_ACCESS) ] = -1,
938 [ C(RESULT_MISS) ] = -1,
939 },
940 },
89d6c0b5
PZ		 941 [ C(NODE) ] = {
942 [ C(OP_READ) ] = {
943 [ C(RESULT_ACCESS) ] = 0x01b7,
944 [ C(RESULT_MISS) ] = 0x01b7,
945 },
946 [ C(OP_WRITE) ] = {
947 [ C(RESULT_ACCESS) ] = 0x01b7,
948 [ C(RESULT_MISS) ] = 0x01b7,
949 },
950 [ C(OP_PREFETCH) ] = {
951 [ C(RESULT_ACCESS) ] = 0x01b7,
952 [ C(RESULT_MISS) ] = 0x01b7,
953 },
954 },
f22f54f4
PZ		 955};
956
e994d7d2 957/*
63b6a675
PZ		 958 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
959 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 960 */
961
63b6a675
PZ		 962#define NHM_DMND_DATA_RD (1 << 0)
963#define NHM_DMND_RFO (1 << 1)
964#define NHM_DMND_IFETCH (1 << 2)
965#define NHM_DMND_WB (1 << 3)
966#define NHM_PF_DATA_RD (1 << 4)
967#define NHM_PF_DATA_RFO (1 << 5)
968#define NHM_PF_IFETCH (1 << 6)
969#define NHM_OFFCORE_OTHER (1 << 7)
970#define NHM_UNCORE_HIT (1 << 8)
971#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
972#define NHM_OTHER_CORE_HITM (1 << 10)
973 /* reserved */
974#define NHM_REMOTE_CACHE_FWD (1 << 12)
975#define NHM_REMOTE_DRAM (1 << 13)
976#define NHM_LOCAL_DRAM (1 << 14)
977#define NHM_NON_DRAM (1 << 15)
978
87e24f4b
PZ		 979#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
980#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 981
982#define NHM_DMND_READ (NHM_DMND_DATA_RD)
983#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
984#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
985
986#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 987#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 988#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 989
990static __initconst const u64 nehalem_hw_cache_extra_regs
991 [PERF_COUNT_HW_CACHE_MAX]
992 [PERF_COUNT_HW_CACHE_OP_MAX]
993 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
994{
995 [ C(LL ) ] = {
996 [ C(OP_READ) ] = {
63b6a675
PZ		 997 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
998 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 999 },
1000 [ C(OP_WRITE) ] = {
63b6a675
PZ		 1001 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1002 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 1003 },
1004 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 1005 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1006 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 1007 },
89d6c0b5
PZ		 1008 },
1009 [ C(NODE) ] = {
1010 [ C(OP_READ) ] = {
87e24f4b
PZ		 1011 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1012 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 1013 },
1014 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 1015 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1016 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 1017 },
1018 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 1019 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1020 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 1021 },
1022 },
e994d7d2
AK		 1023};
1024
caaa8be3 1025static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 1026 [PERF_COUNT_HW_CACHE_MAX]
1027 [PERF_COUNT_HW_CACHE_OP_MAX]
1028 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1029{
1030 [ C(L1D) ] = {
1031 [ C(OP_READ) ] = {
f4929bd3
PZ		 1032 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1033 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 1034 },
1035 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 1036 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1037 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 1038 },
1039 [ C(OP_PREFETCH) ] = {
1040 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1041 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1042 },
1043 },
1044 [ C(L1I ) ] = {
1045 [ C(OP_READ) ] = {
1046 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1047 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1048 },
1049 [ C(OP_WRITE) ] = {
1050 [ C(RESULT_ACCESS) ] = -1,
1051 [ C(RESULT_MISS) ] = -1,
1052 },
1053 [ C(OP_PREFETCH) ] = {
1054 [ C(RESULT_ACCESS) ] = 0x0,
1055 [ C(RESULT_MISS) ] = 0x0,
1056 },
1057 },
1058 [ C(LL ) ] = {
1059 [ C(OP_READ) ] = {
e994d7d2
AK		 1060 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1061 [ C(RESULT_ACCESS) ] = 0x01b7,
1062 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1063 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 1064 },
e994d7d2
AK		 1065 /*
1066 * Use RFO, not WRITEBACK, because a write miss would typically occur
1067 * on RFO.
1068 */
f22f54f4 1069 [ C(OP_WRITE) ] = {
e994d7d2
AK		 1070 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1071 [ C(RESULT_ACCESS) ] = 0x01b7,
1072 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1073 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1074 },
1075 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 1076 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1077 [ C(RESULT_ACCESS) ] = 0x01b7,
1078 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1079 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1080 },
1081 },
1082 [ C(DTLB) ] = {
1083 [ C(OP_READ) ] = {
1084 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1085 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1086 },
1087 [ C(OP_WRITE) ] = {
1088 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1089 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1090 },
1091 [ C(OP_PREFETCH) ] = {
1092 [ C(RESULT_ACCESS) ] = 0x0,
1093 [ C(RESULT_MISS) ] = 0x0,
1094 },
1095 },
1096 [ C(ITLB) ] = {
1097 [ C(OP_READ) ] = {
1098 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1099 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1100 },
1101 [ C(OP_WRITE) ] = {
1102 [ C(RESULT_ACCESS) ] = -1,
1103 [ C(RESULT_MISS) ] = -1,
1104 },
1105 [ C(OP_PREFETCH) ] = {
1106 [ C(RESULT_ACCESS) ] = -1,
1107 [ C(RESULT_MISS) ] = -1,
1108 },
1109 },
1110 [ C(BPU ) ] = {
1111 [ C(OP_READ) ] = {
1112 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1113 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1114 },
1115 [ C(OP_WRITE) ] = {
1116 [ C(RESULT_ACCESS) ] = -1,
1117 [ C(RESULT_MISS) ] = -1,
1118 },
1119 [ C(OP_PREFETCH) ] = {
1120 [ C(RESULT_ACCESS) ] = -1,
1121 [ C(RESULT_MISS) ] = -1,
1122 },
1123 },
89d6c0b5
PZ		 1124 [ C(NODE) ] = {
1125 [ C(OP_READ) ] = {
1126 [ C(RESULT_ACCESS) ] = 0x01b7,
1127 [ C(RESULT_MISS) ] = 0x01b7,
1128 },
1129 [ C(OP_WRITE) ] = {
1130 [ C(RESULT_ACCESS) ] = 0x01b7,
1131 [ C(RESULT_MISS) ] = 0x01b7,
1132 },
1133 [ C(OP_PREFETCH) ] = {
1134 [ C(RESULT_ACCESS) ] = 0x01b7,
1135 [ C(RESULT_MISS) ] = 0x01b7,
1136 },
1137 },
f22f54f4
PZ		 1138};
1139
caaa8be3 1140static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 1141 [PERF_COUNT_HW_CACHE_MAX]
1142 [PERF_COUNT_HW_CACHE_OP_MAX]
1143 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1144{
1145 [ C(L1D) ] = {
1146 [ C(OP_READ) ] = {
1147 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1148 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1149 },
1150 [ C(OP_WRITE) ] = {
1151 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1152 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1153 },
1154 [ C(OP_PREFETCH) ] = {
1155 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1156 [ C(RESULT_MISS) ] = 0,
1157 },
1158 },
1159 [ C(L1I ) ] = {
1160 [ C(OP_READ) ] = {
1161 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1162 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1163 },
1164 [ C(OP_WRITE) ] = {
1165 [ C(RESULT_ACCESS) ] = -1,
1166 [ C(RESULT_MISS) ] = -1,
1167 },
1168 [ C(OP_PREFETCH) ] = {
1169 [ C(RESULT_ACCESS) ] = 0,
1170 [ C(RESULT_MISS) ] = 0,
1171 },
1172 },
1173 [ C(LL ) ] = {
1174 [ C(OP_READ) ] = {
1175 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1176 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1177 },
1178 [ C(OP_WRITE) ] = {
1179 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1180 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1181 },
1182 [ C(OP_PREFETCH) ] = {
1183 [ C(RESULT_ACCESS) ] = 0,
1184 [ C(RESULT_MISS) ] = 0,
1185 },
1186 },
1187 [ C(DTLB) ] = {
1188 [ C(OP_READ) ] = {
1189 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1190 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1191 },
1192 [ C(OP_WRITE) ] = {
1193 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1194 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1195 },
1196 [ C(OP_PREFETCH) ] = {
1197 [ C(RESULT_ACCESS) ] = 0,
1198 [ C(RESULT_MISS) ] = 0,
1199 },
1200 },
1201 [ C(ITLB) ] = {
1202 [ C(OP_READ) ] = {
1203 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1204 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1205 },
1206 [ C(OP_WRITE) ] = {
1207 [ C(RESULT_ACCESS) ] = -1,
1208 [ C(RESULT_MISS) ] = -1,
1209 },
1210 [ C(OP_PREFETCH) ] = {
1211 [ C(RESULT_ACCESS) ] = -1,
1212 [ C(RESULT_MISS) ] = -1,
1213 },
1214 },
1215 [ C(BPU ) ] = {
1216 [ C(OP_READ) ] = {
1217 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1218 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1219 },
1220 [ C(OP_WRITE) ] = {
1221 [ C(RESULT_ACCESS) ] = -1,
1222 [ C(RESULT_MISS) ] = -1,
1223 },
1224 [ C(OP_PREFETCH) ] = {
1225 [ C(RESULT_ACCESS) ] = -1,
1226 [ C(RESULT_MISS) ] = -1,
1227 },
1228 },
1229};
1230
caaa8be3 1231static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1232 [PERF_COUNT_HW_CACHE_MAX]
1233 [PERF_COUNT_HW_CACHE_OP_MAX]
1234 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1235{
1236 [ C(L1D) ] = {
1237 [ C(OP_READ) ] = {
1238 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1239 [ C(RESULT_MISS) ] = 0,
1240 },
1241 [ C(OP_WRITE) ] = {
1242 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1243 [ C(RESULT_MISS) ] = 0,
1244 },
1245 [ C(OP_PREFETCH) ] = {
1246 [ C(RESULT_ACCESS) ] = 0x0,
1247 [ C(RESULT_MISS) ] = 0,
1248 },
1249 },
1250 [ C(L1I ) ] = {
1251 [ C(OP_READ) ] = {
1252 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1253 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1254 },
1255 [ C(OP_WRITE) ] = {
1256 [ C(RESULT_ACCESS) ] = -1,
1257 [ C(RESULT_MISS) ] = -1,
1258 },
1259 [ C(OP_PREFETCH) ] = {
1260 [ C(RESULT_ACCESS) ] = 0,
1261 [ C(RESULT_MISS) ] = 0,
1262 },
1263 },
1264 [ C(LL ) ] = {
1265 [ C(OP_READ) ] = {
1266 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1267 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1268 },
1269 [ C(OP_WRITE) ] = {
1270 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1271 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1272 },
1273 [ C(OP_PREFETCH) ] = {
1274 [ C(RESULT_ACCESS) ] = 0,
1275 [ C(RESULT_MISS) ] = 0,
1276 },
1277 },
1278 [ C(DTLB) ] = {
1279 [ C(OP_READ) ] = {
1280 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1281 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1282 },
1283 [ C(OP_WRITE) ] = {
1284 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1285 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1286 },
1287 [ C(OP_PREFETCH) ] = {
1288 [ C(RESULT_ACCESS) ] = 0,
1289 [ C(RESULT_MISS) ] = 0,
1290 },
1291 },
1292 [ C(ITLB) ] = {
1293 [ C(OP_READ) ] = {
1294 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1295 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1296 },
1297 [ C(OP_WRITE) ] = {
1298 [ C(RESULT_ACCESS) ] = -1,
1299 [ C(RESULT_MISS) ] = -1,
1300 },
1301 [ C(OP_PREFETCH) ] = {
1302 [ C(RESULT_ACCESS) ] = -1,
1303 [ C(RESULT_MISS) ] = -1,
1304 },
1305 },
1306 [ C(BPU ) ] = {
1307 [ C(OP_READ) ] = {
1308 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1309 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1310 },
1311 [ C(OP_WRITE) ] = {
1312 [ C(RESULT_ACCESS) ] = -1,
1313 [ C(RESULT_MISS) ] = -1,
1314 },
1315 [ C(OP_PREFETCH) ] = {
1316 [ C(RESULT_ACCESS) ] = -1,
1317 [ C(RESULT_MISS) ] = -1,
1318 },
1319 },
1320};
1321
1fa64180
YZ		 1322static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1323{
1324 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1 1325 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
ae3f011f 1326 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1fa64180
YZ		 1327 EVENT_EXTRA_END
1328};
1329
1330#define SLM_DMND_READ SNB_DMND_DATA_RD
1331#define SLM_DMND_WRITE SNB_DMND_RFO
1332#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1333
1334#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1335#define SLM_LLC_ACCESS SNB_RESP_ANY
1336#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1337
1338static __initconst const u64 slm_hw_cache_extra_regs
1339 [PERF_COUNT_HW_CACHE_MAX]
1340 [PERF_COUNT_HW_CACHE_OP_MAX]
1341 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1342{
1343 [ C(LL ) ] = {
1344 [ C(OP_READ) ] = {
1345 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1346 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1347 },
1348 [ C(OP_WRITE) ] = {
1349 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1350 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1351 },
1352 [ C(OP_PREFETCH) ] = {
1353 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1354 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1355 },
1356 },
1357};
1358
1359static __initconst const u64 slm_hw_cache_event_ids
1360 [PERF_COUNT_HW_CACHE_MAX]
1361 [PERF_COUNT_HW_CACHE_OP_MAX]
1362 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1363{
1364 [ C(L1D) ] = {
1365 [ C(OP_READ) ] = {
1366 [ C(RESULT_ACCESS) ] = 0,
1367 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1368 },
1369 [ C(OP_WRITE) ] = {
1370 [ C(RESULT_ACCESS) ] = 0,
1371 [ C(RESULT_MISS) ] = 0,
1372 },
1373 [ C(OP_PREFETCH) ] = {
1374 [ C(RESULT_ACCESS) ] = 0,
1375 [ C(RESULT_MISS) ] = 0,
1376 },
1377 },
1378 [ C(L1I ) ] = {
1379 [ C(OP_READ) ] = {
1380 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1381 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1382 },
1383 [ C(OP_WRITE) ] = {
1384 [ C(RESULT_ACCESS) ] = -1,
1385 [ C(RESULT_MISS) ] = -1,
1386 },
1387 [ C(OP_PREFETCH) ] = {
1388 [ C(RESULT_ACCESS) ] = 0,
1389 [ C(RESULT_MISS) ] = 0,
1390 },
1391 },
1392 [ C(LL ) ] = {
1393 [ C(OP_READ) ] = {
1394 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1395 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1396 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1397 },
1398 [ C(OP_WRITE) ] = {
1399 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1400 [ C(RESULT_ACCESS) ] = 0x01b7,
1401 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1402 [ C(RESULT_MISS) ] = 0x01b7,
1403 },
1404 [ C(OP_PREFETCH) ] = {
1405 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1406 [ C(RESULT_ACCESS) ] = 0x01b7,
1407 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1408 [ C(RESULT_MISS) ] = 0x01b7,
1409 },
1410 },
1411 [ C(DTLB) ] = {
1412 [ C(OP_READ) ] = {
1413 [ C(RESULT_ACCESS) ] = 0,
1414 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1415 },
1416 [ C(OP_WRITE) ] = {
1417 [ C(RESULT_ACCESS) ] = 0,
1418 [ C(RESULT_MISS) ] = 0,
1419 },
1420 [ C(OP_PREFETCH) ] = {
1421 [ C(RESULT_ACCESS) ] = 0,
1422 [ C(RESULT_MISS) ] = 0,
1423 },
1424 },
1425 [ C(ITLB) ] = {
1426 [ C(OP_READ) ] = {
1427 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1428 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1429 },
1430 [ C(OP_WRITE) ] = {
1431 [ C(RESULT_ACCESS) ] = -1,
1432 [ C(RESULT_MISS) ] = -1,
1433 },
1434 [ C(OP_PREFETCH) ] = {
1435 [ C(RESULT_ACCESS) ] = -1,
1436 [ C(RESULT_MISS) ] = -1,
1437 },
1438 },
1439 [ C(BPU ) ] = {
1440 [ C(OP_READ) ] = {
1441 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1442 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1443 },
1444 [ C(OP_WRITE) ] = {
1445 [ C(RESULT_ACCESS) ] = -1,
1446 [ C(RESULT_MISS) ] = -1,
1447 },
1448 [ C(OP_PREFETCH) ] = {
1449 [ C(RESULT_ACCESS) ] = -1,
1450 [ C(RESULT_MISS) ] = -1,
1451 },
1452 },
1453};
1454
1a78d937
AK		 1455/*
1456 * Use from PMIs where the LBRs are already disabled.
1457 */
1458static void __intel_pmu_disable_all(void)
f22f54f4 1459{
89cbc767 1460 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1461
1462 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1463
15c7ad51 1464 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1465 intel_pmu_disable_bts();
8062382c
AS		 1466 else
1467 intel_bts_disable_local();
ca037701
PZ		 1468
1469 intel_pmu_pebs_disable_all();
1a78d937
AK		 1470}
1471
1472static void intel_pmu_disable_all(void)
1473{
1474 __intel_pmu_disable_all();
caff2bef 1475 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1476}
1477
1a78d937 1478static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1479{
89cbc767 1480 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1481
d329527e 1482 intel_pmu_pebs_enable_all();
1a78d937 1483 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1484 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1485 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1486
15c7ad51 1487 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1488 struct perf_event *event =
15c7ad51 1489 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1490
1491 if (WARN_ON_ONCE(!event))
1492 return;
1493
1494 intel_pmu_enable_bts(event->hw.config);
8062382c
AS		 1495 } else
1496 intel_bts_enable_local();
f22f54f4
PZ		 1497}
1498
1a78d937
AK		 1499static void intel_pmu_enable_all(int added)
1500{
1501 __intel_pmu_enable_all(added, false);
1502}
1503
11164cd4
PZ		 1504/*
1505 * Workaround for:
1506 * Intel Errata AAK100 (model 26)
1507 * Intel Errata AAP53 (model 30)
40b91cd1 1508 * Intel Errata BD53 (model 44)
11164cd4 1509 *
351af072
ZY		 1510 * The official story:
1511 * These chips need to be 'reset' when adding counters by programming the
1512 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1513 * in sequence on the same PMC or on different PMCs.
1514 *
1515 * In practise it appears some of these events do in fact count, and
1516 * we need to programm all 4 events.
11164cd4 1517 */
351af072 1518static void intel_pmu_nhm_workaround(void)
11164cd4 1519{
89cbc767 1520 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1521 static const unsigned long nhm_magic[4] = {
1522 0x4300B5,
1523 0x4300D2,
1524 0x4300B1,
1525 0x4300B1
1526 };
1527 struct perf_event *event;
1528 int i;
11164cd4 1529
351af072
ZY		 1530 /*
1531 * The Errata requires below steps:
1532 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1533 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1534 * the corresponding PMCx;
1535 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1536 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1537 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1538 */
11164cd4 1539
351af072
ZY		 1540 /*
1541 * The real steps we choose are a little different from above.
1542 * A) To reduce MSR operations, we don't run step 1) as they
1543 * are already cleared before this function is called;
1544 * B) Call x86_perf_event_update to save PMCx before configuring
1545 * PERFEVTSELx with magic number;
1546 * C) With step 5), we do clear only when the PERFEVTSELx is
1547 * not used currently.
1548 * D) Call x86_perf_event_set_period to restore PMCx;
1549 */
11164cd4 1550
351af072
ZY		 1551 /* We always operate 4 pairs of PERF Counters */
1552 for (i = 0; i < 4; i++) {
1553 event = cpuc->events[i];
1554 if (event)
1555 x86_perf_event_update(event);
1556 }
11164cd4 1557
351af072
ZY		 1558 for (i = 0; i < 4; i++) {
1559 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1560 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1561 }
1562
1563 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1564 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1565
351af072
ZY		 1566 for (i = 0; i < 4; i++) {
1567 event = cpuc->events[i];
1568
1569 if (event) {
1570 x86_perf_event_set_period(event);
31fa58af 1571 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1572 ARCH_PERFMON_EVENTSEL_ENABLE);
1573 } else
1574 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1575 }
351af072
ZY		 1576}
1577
1578static void intel_pmu_nhm_enable_all(int added)
1579{
1580 if (added)
1581 intel_pmu_nhm_workaround();
11164cd4
PZ		 1582 intel_pmu_enable_all(added);
1583}
1584
f22f54f4
PZ		 1585static inline u64 intel_pmu_get_status(void)
1586{
1587 u64 status;
1588
1589 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1590
1591 return status;
1592}
1593
1594static inline void intel_pmu_ack_status(u64 ack)
1595{
1596 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1597}
1598
ca037701 1599static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1600{
15c7ad51 1601 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1602 u64 ctrl_val, mask;
1603
1604 mask = 0xfULL << (idx * 4);
1605
1606 rdmsrl(hwc->config_base, ctrl_val);
1607 ctrl_val &= ~mask;
7645a24c 1608 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1609}
1610
2b9e344d
PZ		 1611static inline bool event_is_checkpointed(struct perf_event *event)
1612{
1613 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1614}
1615
ca037701 1616static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1617{
aff3d91a 1618 struct hw_perf_event *hwc = &event->hw;
89cbc767 1619 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1620
15c7ad51 1621 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1622 intel_pmu_disable_bts();
1623 intel_pmu_drain_bts_buffer();
1624 return;
1625 }
1626
144d31e6
GN		 1627 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1628 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1629 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1630
60ce0fbd
SE		 1631 /*
1632 * must disable before any actual event
1633 * because any event may be combined with LBR
1634 */
a46a2300 1635 if (needs_branch_stack(event))
60ce0fbd
SE		 1636 intel_pmu_lbr_disable(event);
1637
f22f54f4 1638 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1639 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1640 return;
1641 }
1642
aff3d91a 1643 x86_pmu_disable_event(event);
ca037701 1644
ab608344 1645 if (unlikely(event->attr.precise_ip))
ef21f683 1646 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1647}
1648
ca037701 1649static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1650{
15c7ad51 1651 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1652 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1653
1654 /*
1655 * Enable IRQ generation (0x8),
1656 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1657 * if requested:
1658 */
1659 bits = 0x8ULL;
1660 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1661 bits |= 0x2;
1662 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1663 bits |= 0x1;
1664
1665 /*
1666 * ANY bit is supported in v3 and up
1667 */
1668 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1669 bits |= 0x4;
1670
1671 bits <<= (idx * 4);
1672 mask = 0xfULL << (idx * 4);
1673
1674 rdmsrl(hwc->config_base, ctrl_val);
1675 ctrl_val &= ~mask;
1676 ctrl_val |= bits;
7645a24c 1677 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1678}
1679
aff3d91a 1680static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1681{
aff3d91a 1682 struct hw_perf_event *hwc = &event->hw;
89cbc767 1683 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1684
15c7ad51 1685 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1686 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1687 return;
1688
1689 intel_pmu_enable_bts(hwc->config);
1690 return;
1691 }
60ce0fbd
SE		 1692 /*
1693 * must enabled before any actual event
1694 * because any event may be combined with LBR
1695 */
a46a2300 1696 if (needs_branch_stack(event))
60ce0fbd 1697 intel_pmu_lbr_enable(event);
f22f54f4 1698
144d31e6
GN		 1699 if (event->attr.exclude_host)
1700 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1701 if (event->attr.exclude_guest)
1702 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1703
2b9e344d
PZ		 1704 if (unlikely(event_is_checkpointed(event)))
1705 cpuc->intel_cp_status |= (1ull << hwc->idx);
1706
f22f54f4 1707 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1708 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1709 return;
1710 }
1711
ab608344 1712 if (unlikely(event->attr.precise_ip))
ef21f683 1713 intel_pmu_pebs_enable(event);
ca037701 1714
31fa58af 1715 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1716}
1717
1718/*
1719 * Save and restart an expired event. Called by NMI contexts,
1720 * so it has to be careful about preempting normal event ops:
1721 */
de0428a7 1722int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1723{
cc2ad4ba 1724 x86_perf_event_update(event);
2dbf0116
AK		 1725 /*
1726 * For a checkpointed counter always reset back to 0. This
1727 * avoids a situation where the counter overflows, aborts the
1728 * transaction and is then set back to shortly before the
1729 * overflow, and overflows and aborts again.
1730 */
1731 if (unlikely(event_is_checkpointed(event))) {
1732 /* No race with NMIs because the counter should not be armed */
1733 wrmsrl(event->hw.event_base, 0);
1734 local64_set(&event->hw.prev_count, 0);
1735 }
cc2ad4ba 1736 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1737}
1738
1739static void intel_pmu_reset(void)
1740{
0a3aee0d 1741 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1742 unsigned long flags;
1743 int idx;
1744
948b1bb8 1745 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1746 return;
1747
1748 local_irq_save(flags);
1749
c767a54b 1750 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1751
948b1bb8 1752 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1753 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1754 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1755 }
948b1bb8 1756 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1757 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1758
f22f54f4
PZ		 1759 if (ds)
1760 ds->bts_index = ds->bts_buffer_base;
1761
8882edf7
AK		 1762 /* Ack all overflows and disable fixed counters */
1763 if (x86_pmu.version >= 2) {
1764 intel_pmu_ack_status(intel_pmu_get_status());
1765 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1766 }
1767
1768 /* Reset LBRs and LBR freezing */
1769 if (x86_pmu.lbr_nr) {
1770 update_debugctlmsr(get_debugctlmsr() &
1771 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
1772 }
1773
f22f54f4
PZ		 1774 local_irq_restore(flags);
1775}
1776
1777/*
1778 * This handler is triggered by the local APIC, so the APIC IRQ handling
1779 * rules apply:
1780 */
1781static int intel_pmu_handle_irq(struct pt_regs *regs)
1782{
1783 struct perf_sample_data data;
1784 struct cpu_hw_events *cpuc;
1785 int bit, loops;
2e556b5b 1786 u64 status;
b0b2072d 1787 int handled;
f22f54f4 1788
89cbc767 1789 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1790
2bce5dac 1791 /*
72db5596
AK		 1792 * No known reason to not always do late ACK,
1793 * but just in case do it opt-in.
2bce5dac 1794 */
72db5596
AK		 1795 if (!x86_pmu.late_ack)
1796 apic_write(APIC_LVTPC, APIC_DM_NMI);
1a78d937 1797 __intel_pmu_disable_all();
b0b2072d 1798 handled = intel_pmu_drain_bts_buffer();
8062382c 1799 handled += intel_bts_interrupt();
f22f54f4 1800 status = intel_pmu_get_status();
a3ef2229
MM		 1801 if (!status)
1802 goto done;
f22f54f4
PZ		 1803
1804 loops = 0;
1805again:
0f29e573 1806 intel_pmu_lbr_read();
2e556b5b 1807 intel_pmu_ack_status(status);
f22f54f4 1808 if (++loops > 100) {
ae0def05
DH		 1809 static bool warned = false;
1810 if (!warned) {
1811 WARN(1, "perfevents: irq loop stuck!\n");
1812 perf_event_print_debug();
1813 warned = true;
1814 }
f22f54f4 1815 intel_pmu_reset();
3fb2b8dd 1816 goto done;
f22f54f4
PZ		 1817 }
1818
1819 inc_irq_stat(apic_perf_irqs);
ca037701 1820
caff2bef 1821
b292d7a1 1822 /*
d8020bee
AK		 1823 * Ignore a range of extra bits in status that do not indicate
1824 * overflow by themselves.
b292d7a1 1825 */
d8020bee
AK		 1826 status &= ~(GLOBAL_STATUS_COND_CHG |
1827 GLOBAL_STATUS_ASIF |
1828 GLOBAL_STATUS_LBRS_FROZEN);
1829 if (!status)
1830 goto done;
b292d7a1 1831
ca037701
PZ		 1832 /*
1833 * PEBS overflow sets bit 62 in the global status register
1834 */
de725dec
PZ		 1835 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1836 handled++;
ca037701 1837 x86_pmu.drain_pebs(regs);
de725dec 1838 }
ca037701 1839
52ca9ced
AS		 1840 /*
1841 * Intel PT
1842 */
1843 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
1844 handled++;
1845 intel_pt_interrupt();
1846 }
1847
2dbf0116 1848 /*
2b9e344d
PZ		 1849 * Checkpointed counters can lead to 'spurious' PMIs because the
1850 * rollback caused by the PMI will have cleared the overflow status
1851 * bit. Therefore always force probe these counters.
2dbf0116 1852 */
2b9e344d 1853 status |= cpuc->intel_cp_status;
2dbf0116 1854
984b3f57 1855 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1856 struct perf_event *event = cpuc->events[bit];
1857
de725dec
PZ		 1858 handled++;
1859
f22f54f4
PZ		 1860 if (!test_bit(bit, cpuc->active_mask))
1861 continue;
1862
1863 if (!intel_pmu_save_and_restart(event))
1864 continue;
1865
fd0d000b 1866 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1867
60ce0fbd
SE		 1868 if (has_branch_stack(event))
1869 data.br_stack = &cpuc->lbr_stack;
1870
a8b0ca17 1871 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1872 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1873 }
1874
f22f54f4
PZ		 1875 /*
1876 * Repeat if there is more work to be done:
1877 */
1878 status = intel_pmu_get_status();
1879 if (status)
1880 goto again;
1881
3fb2b8dd 1882done:
1a78d937 1883 __intel_pmu_enable_all(0, true);
72db5596
AK		 1884 /*
1885 * Only unmask the NMI after the overflow counters
1886 * have been reset. This avoids spurious NMIs on
1887 * Haswell CPUs.
1888 */
1889 if (x86_pmu.late_ack)
1890 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1891 return handled;
f22f54f4
PZ		 1892}
1893
f22f54f4 1894static struct event_constraint *
ca037701 1895intel_bts_constraints(struct perf_event *event)
f22f54f4 1896{
ca037701
PZ		 1897 struct hw_perf_event *hwc = &event->hw;
1898 unsigned int hw_event, bts_event;
f22f54f4 1899
18a073a3
PZ		 1900 if (event->attr.freq)
1901 return NULL;
1902
ca037701
PZ		 1903 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1904 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1905
ca037701 1906 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1907 return &bts_constraint;
ca037701 1908
f22f54f4
PZ		 1909 return NULL;
1910}
1911
ae3f011f 1912static int intel_alt_er(int idx, u64 config)
b79e8941 1913{
ae3f011f 1914 int alt_idx;
9a5e3fb5 1915 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 1916 return idx;
b79e8941 1917
5a425294 1918 if (idx == EXTRA_REG_RSP_0)
ae3f011f 1919 alt_idx = EXTRA_REG_RSP_1;
5a425294
PZ		 1920
1921 if (idx == EXTRA_REG_RSP_1)
ae3f011f 1922 alt_idx = EXTRA_REG_RSP_0;
5a425294 1923
ae3f011f
KL		 1924 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
1925 return idx;
1926
1927 return alt_idx;
5a425294
PZ		 1928}
1929
1930static void intel_fixup_er(struct perf_event *event, int idx)
1931{
1932 event->hw.extra_reg.idx = idx;
1933
1934 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1935 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1936 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1937 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1938 } else if (idx == EXTRA_REG_RSP_1) {
1939 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1940 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1941 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1942 }
b79e8941
PZ		 1943}
1944
efc9f05d
SE		 1945/*
1946 * manage allocation of shared extra msr for certain events
1947 *
1948 * sharing can be:
1949 * per-cpu: to be shared between the various events on a single PMU
1950 * per-core: per-cpu + shared by HT threads
1951 */
a7e3ed1e 1952static struct event_constraint *
efc9f05d 1953__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1954 struct perf_event *event,
1955 struct hw_perf_event_extra *reg)
a7e3ed1e 1956{
efc9f05d 1957 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1958 struct er_account *era;
cd8a38d3 1959 unsigned long flags;
5a425294 1960 int idx = reg->idx;
a7e3ed1e 1961
5a425294
PZ		 1962 /*
1963 * reg->alloc can be set due to existing state, so for fake cpuc we
1964 * need to ignore this, otherwise we might fail to allocate proper fake
1965 * state for this extra reg constraint. Also see the comment below.
1966 */
1967 if (reg->alloc && !cpuc->is_fake)
b36817e8 1968 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1969
b79e8941 1970again:
5a425294 1971 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1972 /*
1973 * we use spin_lock_irqsave() to avoid lockdep issues when
1974 * passing a fake cpuc
1975 */
1976 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1977
1978 if (!atomic_read(&era->ref) || era->config == reg->config) {
1979
5a425294
PZ		 1980 /*
1981 * If its a fake cpuc -- as per validate_{group,event}() we
1982 * shouldn't touch event state and we can avoid doing so
1983 * since both will only call get_event_constraints() once
1984 * on each event, this avoids the need for reg->alloc.
1985 *
1986 * Not doing the ER fixup will only result in era->reg being
1987 * wrong, but since we won't actually try and program hardware
1988 * this isn't a problem either.
1989 */
1990 if (!cpuc->is_fake) {
1991 if (idx != reg->idx)
1992 intel_fixup_er(event, idx);
1993
1994 /*
1995 * x86_schedule_events() can call get_event_constraints()
1996 * multiple times on events in the case of incremental
1997 * scheduling(). reg->alloc ensures we only do the ER
1998 * allocation once.
1999 */
2000 reg->alloc = 1;
2001 }
2002
efc9f05d
SE		 2003 /* lock in msr value */
2004 era->config = reg->config;
2005 era->reg = reg->reg;
2006
2007 /* one more user */
2008 atomic_inc(&era->ref);
2009
a7e3ed1e 2010 /*
b36817e8
SE		 2011 * need to call x86_get_event_constraint()
2012 * to check if associated event has constraints
a7e3ed1e 2013 */
b36817e8 2014 c = NULL;
5a425294 2015 } else {
ae3f011f 2016 idx = intel_alt_er(idx, reg->config);
5a425294
PZ		 2017 if (idx != reg->idx) {
2018 raw_spin_unlock_irqrestore(&era->lock, flags);
2019 goto again;
2020 }
a7e3ed1e 2021 }
cd8a38d3 2022 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 2023
efc9f05d
SE		 2024 return c;
2025}
2026
2027static void
2028__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2029 struct hw_perf_event_extra *reg)
2030{
2031 struct er_account *era;
2032
2033 /*
5a425294
PZ		 2034 * Only put constraint if extra reg was actually allocated. Also takes
2035 * care of event which do not use an extra shared reg.
2036 *
2037 * Also, if this is a fake cpuc we shouldn't touch any event state
2038 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2039 * either since it'll be thrown out.
efc9f05d 2040 */
5a425294 2041 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 2042 return;
2043
2044 era = &cpuc->shared_regs->regs[reg->idx];
2045
2046 /* one fewer user */
2047 atomic_dec(&era->ref);
2048
2049 /* allocate again next time */
2050 reg->alloc = 0;
2051}
2052
2053static struct event_constraint *
2054intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2055 struct perf_event *event)
2056{
b36817e8
SE		 2057 struct event_constraint *c = NULL, *d;
2058 struct hw_perf_event_extra *xreg, *breg;
2059
2060 xreg = &event->hw.extra_reg;
2061 if (xreg->idx != EXTRA_REG_NONE) {
2062 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2063 if (c == &emptyconstraint)
2064 return c;
2065 }
2066 breg = &event->hw.branch_reg;
2067 if (breg->idx != EXTRA_REG_NONE) {
2068 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2069 if (d == &emptyconstraint) {
2070 __intel_shared_reg_put_constraints(cpuc, xreg);
2071 c = d;
2072 }
2073 }
efc9f05d 2074 return c;
a7e3ed1e
AK		 2075}
2076
de0428a7 2077struct event_constraint *
79cba822
SE		 2078x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2079 struct perf_event *event)
de0428a7
KW		 2080{
2081 struct event_constraint *c;
2082
2083 if (x86_pmu.event_constraints) {
2084 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 2085 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 2086 event->hw.flags |= c->flags;
de0428a7 2087 return c;
9fac2cf3 2088 }
de0428a7
KW		 2089 }
2090 }
2091
2092 return &unconstrained;
2093}
2094
f22f54f4 2095static struct event_constraint *
e979121b 2096__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 2097 struct perf_event *event)
f22f54f4
PZ		 2098{
2099 struct event_constraint *c;
2100
ca037701
PZ		 2101 c = intel_bts_constraints(event);
2102 if (c)
2103 return c;
2104
687805e4 2105 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 2106 if (c)
2107 return c;
2108
687805e4 2109 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 2110 if (c)
2111 return c;
2112
79cba822 2113 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 2114}
2115
e979121b
MD		 2116static void
2117intel_start_scheduling(struct cpu_hw_events *cpuc)
2118{
2119 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2120 struct intel_excl_states *xl;
e979121b 2121 int tid = cpuc->excl_thread_id;
e979121b
MD		 2122
2123 /*
2124 * nothing needed if in group validation mode
2125 */
b37609c3 2126 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 2127 return;
b37609c3 2128
e979121b
MD		 2129 /*
2130 * no exclusion needed
2131 */
17186ccd 2132 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2133 return;
2134
e979121b
MD		 2135 xl = &excl_cntrs->states[tid];
2136
2137 xl->sched_started = true;
e979121b
MD		 2138 /*
2139 * lock shared state until we are done scheduling
2140 * in stop_event_scheduling()
2141 * makes scheduling appear as a transaction
2142 */
e979121b 2143 raw_spin_lock(&excl_cntrs->lock);
e979121b
MD		 2144}
2145
0c41e756
PZ		 2146static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2147{
2148 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2149 struct event_constraint *c = cpuc->event_constraint[idx];
2150 struct intel_excl_states *xl;
2151 int tid = cpuc->excl_thread_id;
2152
2153 if (cpuc->is_fake || !is_ht_workaround_enabled())
2154 return;
2155
2156 if (WARN_ON_ONCE(!excl_cntrs))
2157 return;
2158
2159 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2160 return;
2161
2162 xl = &excl_cntrs->states[tid];
2163
2164 lockdep_assert_held(&excl_cntrs->lock);
2165
1fe684e3 2166 if (c->flags & PERF_X86_EVENT_EXCL)
43ef205b 2167 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1fe684e3 2168 else
43ef205b 2169 xl->state[cntr] = INTEL_EXCL_SHARED;
0c41e756
PZ		 2170}
2171
e979121b
MD		 2172static void
2173intel_stop_scheduling(struct cpu_hw_events *cpuc)
2174{
2175 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2176 struct intel_excl_states *xl;
e979121b 2177 int tid = cpuc->excl_thread_id;
e979121b
MD		 2178
2179 /*
2180 * nothing needed if in group validation mode
2181 */
b37609c3 2182 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 2183 return;
2184 /*
2185 * no exclusion needed
2186 */
17186ccd 2187 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2188 return;
2189
e979121b
MD		 2190 xl = &excl_cntrs->states[tid];
2191
e979121b
MD		 2192 xl->sched_started = false;
2193 /*
2194 * release shared state lock (acquired in intel_start_scheduling())
2195 */
2196 raw_spin_unlock(&excl_cntrs->lock);
2197}
2198
2199static struct event_constraint *
2200intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2201 int idx, struct event_constraint *c)
2202{
e979121b 2203 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2204 struct intel_excl_states *xlo;
e979121b 2205 int tid = cpuc->excl_thread_id;
1c565833 2206 int is_excl, i;
e979121b
MD		 2207
2208 /*
2209 * validating a group does not require
2210 * enforcing cross-thread exclusion
2211 */
b37609c3
SE		 2212 if (cpuc->is_fake || !is_ht_workaround_enabled())
2213 return c;
2214
2215 /*
2216 * no exclusion needed
2217 */
17186ccd 2218 if (WARN_ON_ONCE(!excl_cntrs))
e979121b 2219 return c;
e979121b 2220
e979121b
MD		 2221 /*
2222 * because we modify the constraint, we need
2223 * to make a copy. Static constraints come
2224 * from static const tables.
2225 *
2226 * only needed when constraint has not yet
2227 * been cloned (marked dynamic)
2228 */
2229 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
aaf932e8 2230 struct event_constraint *cx;
e979121b 2231
e979121b
MD		 2232 /*
2233 * grab pre-allocated constraint entry
2234 */
2235 cx = &cpuc->constraint_list[idx];
2236
2237 /*
2238 * initialize dynamic constraint
2239 * with static constraint
2240 */
aaf932e8 2241 *cx = *c;
e979121b
MD		 2242
2243 /*
2244 * mark constraint as dynamic, so we
2245 * can free it later on
2246 */
2247 cx->flags |= PERF_X86_EVENT_DYNAMIC;
aaf932e8 2248 c = cx;
e979121b
MD		 2249 }
2250
2251 /*
2252 * From here on, the constraint is dynamic.
2253 * Either it was just allocated above, or it
2254 * was allocated during a earlier invocation
2255 * of this function
2256 */
2257
1c565833
PZ		 2258 /*
2259 * state of sibling HT
2260 */
2261 xlo = &excl_cntrs->states[tid ^ 1];
2262
2263 /*
2264 * event requires exclusive counter access
2265 * across HT threads
2266 */
2267 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2268 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2269 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2270 if (!cpuc->n_excl++)
2271 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2272 }
2273
e979121b
MD		 2274 /*
2275 * Modify static constraint with current dynamic
2276 * state of thread
2277 *
2278 * EXCLUSIVE: sibling counter measuring exclusive event
2279 * SHARED : sibling counter measuring non-exclusive event
2280 * UNUSED : sibling counter unused
2281 */
aaf932e8 2282 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
e979121b
MD		 2283 /*
2284 * exclusive event in sibling counter
2285 * our corresponding counter cannot be used
2286 * regardless of our event
2287 */
1c565833 2288 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
aaf932e8 2289 __clear_bit(i, c->idxmsk);
e979121b
MD		 2290 /*
2291 * if measuring an exclusive event, sibling
2292 * measuring non-exclusive, then counter cannot
2293 * be used
2294 */
1c565833 2295 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
aaf932e8 2296 __clear_bit(i, c->idxmsk);
e979121b
MD		 2297 }
2298
2299 /*
2300 * recompute actual bit weight for scheduling algorithm
2301 */
aaf932e8 2302 c->weight = hweight64(c->idxmsk64);
e979121b
MD		 2303
2304 /*
2305 * if we return an empty mask, then switch
2306 * back to static empty constraint to avoid
2307 * the cost of freeing later on
2308 */
aaf932e8
PZ		 2309 if (c->weight == 0)
2310 c = &emptyconstraint;
e979121b 2311
aaf932e8 2312 return c;
e979121b
MD		 2313}
2314
2315static struct event_constraint *
2316intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2317 struct perf_event *event)
2318{
ebfb4988 2319 struct event_constraint *c1 = NULL;
a90738c2 2320 struct event_constraint *c2;
e979121b 2321
ebfb4988
PZ		 2322 if (idx >= 0) /* fake does < 0 */
2323 c1 = cpuc->event_constraint[idx];
2324
e979121b
MD		 2325 /*
2326 * first time only
2327 * - static constraint: no change across incremental scheduling calls
2328 * - dynamic constraint: handled by intel_get_excl_constraints()
2329 */
a90738c2
SE		 2330 c2 = __intel_get_event_constraints(cpuc, idx, event);
2331 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2332 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2333 c1->weight = c2->weight;
2334 c2 = c1;
2335 }
e979121b
MD		 2336
2337 if (cpuc->excl_cntrs)
a90738c2 2338 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2339
a90738c2 2340 return c2;
e979121b
MD		 2341}
2342
2343static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2344 struct perf_event *event)
2345{
2346 struct hw_perf_event *hwc = &event->hw;
2347 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
e979121b 2348 int tid = cpuc->excl_thread_id;
1c565833 2349 struct intel_excl_states *xl;
e979121b
MD		 2350
2351 /*
2352 * nothing needed if in group validation mode
2353 */
2354 if (cpuc->is_fake)
2355 return;
2356
17186ccd 2357 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2358 return;
2359
cc1790cf
PZ		 2360 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2361 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2362 if (!--cpuc->n_excl)
2363 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2364 }
e979121b
MD		 2365
2366 /*
ba040653
PZ		 2367 * If event was actually assigned, then mark the counter state as
2368 * unused now.
e979121b 2369 */
ba040653
PZ		 2370 if (hwc->idx >= 0) {
2371 xl = &excl_cntrs->states[tid];
2372
2373 /*
2374 * put_constraint may be called from x86_schedule_events()
2375 * which already has the lock held so here make locking
2376 * conditional.
2377 */
2378 if (!xl->sched_started)
2379 raw_spin_lock(&excl_cntrs->lock);
e979121b 2380
1c565833 2381 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
e979121b 2382
ba040653
PZ		 2383 if (!xl->sched_started)
2384 raw_spin_unlock(&excl_cntrs->lock);
2385 }
e979121b
MD		 2386}
2387
efc9f05d
SE		 2388static void
2389intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2390 struct perf_event *event)
2391{
efc9f05d 2392 struct hw_perf_event_extra *reg;
a7e3ed1e 2393
efc9f05d
SE		 2394 reg = &event->hw.extra_reg;
2395 if (reg->idx != EXTRA_REG_NONE)
2396 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2397
2398 reg = &event->hw.branch_reg;
2399 if (reg->idx != EXTRA_REG_NONE)
2400 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2401}
a7e3ed1e 2402
efc9f05d
SE		 2403static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2404 struct perf_event *event)
2405{
2406 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2407
2408 /*
2409 * is PMU has exclusive counter restrictions, then
2410 * all events are subject to and must call the
2411 * put_excl_constraints() routine
2412 */
b371b594 2413 if (cpuc->excl_cntrs)
e979121b 2414 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2415}
2416
0780c927 2417static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2418{
0780c927 2419 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2420 /*
2421 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2422 * (0x003c) so that we can use it with PEBS.
2423 *
2424 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2425 * PEBS capable. However we can use INST_RETIRED.ANY_P
2426 * (0x00c0), which is a PEBS capable event, to get the same
2427 * count.
2428 *
2429 * INST_RETIRED.ANY_P counts the number of cycles that retires
2430 * CNTMASK instructions. By setting CNTMASK to a value (16)
2431 * larger than the maximum number of instructions that can be
2432 * retired per cycle (4) and then inverting the condition, we
2433 * count all cycles that retire 16 or less instructions, which
2434 * is every cycle.
2435 *
2436 * Thereby we gain a PEBS capable cycle counter.
2437 */
f9b4eeb8
PZ		 2438 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2439
0780c927
PZ		 2440 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2441 event->hw.config = alt_config;
2442 }
2443}
2444
2445static void intel_pebs_aliases_snb(struct perf_event *event)
2446{
2447 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2448 /*
2449 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2450 * (0x003c) so that we can use it with PEBS.
2451 *
2452 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2453 * PEBS capable. However we can use UOPS_RETIRED.ALL
2454 * (0x01c2), which is a PEBS capable event, to get the same
2455 * count.
2456 *
2457 * UOPS_RETIRED.ALL counts the number of cycles that retires
2458 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2459 * larger than the maximum number of micro-ops that can be
2460 * retired per cycle (4) and then inverting the condition, we
2461 * count all cycles that retire 16 or less micro-ops, which
2462 * is every cycle.
2463 *
2464 * Thereby we gain a PEBS capable cycle counter.
2465 */
2466 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2467
2468 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2469 event->hw.config = alt_config;
2470 }
0780c927
PZ		 2471}
2472
a7b58d21
AK		 2473static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2474{
2475 unsigned long flags = x86_pmu.free_running_flags;
2476
2477 if (event->attr.use_clockid)
2478 flags &= ~PERF_SAMPLE_TIME;
2479 return flags;
2480}
2481
0780c927
PZ		 2482static int intel_pmu_hw_config(struct perf_event *event)
2483{
2484 int ret = x86_pmu_hw_config(event);
2485
2486 if (ret)
2487 return ret;
2488
851559e3 2489 if (event->attr.precise_ip) {
3569c0d7 2490 if (!event->attr.freq) {
851559e3 2491 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
a7b58d21
AK		 2492 if (!(event->attr.sample_type &
2493 ~intel_pmu_free_running_flags(event)))
3569c0d7
YZ		 2494 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2495 }
851559e3
YZ		 2496 if (x86_pmu.pebs_aliases)
2497 x86_pmu.pebs_aliases(event);
2498 }
7639dae0 2499
a46a2300 2500 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2501 ret = intel_pmu_setup_lbr_filter(event);
2502 if (ret)
2503 return ret;
48070342
AS		 2504
2505 /*
2506 * BTS is set up earlier in this path, so don't account twice
2507 */
2508 if (!intel_pmu_has_bts(event)) {
2509 /* disallow lbr if conflicting events are present */
2510 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2511 return -EBUSY;
2512
2513 event->destroy = hw_perf_lbr_event_destroy;
2514 }
60ce0fbd
SE		 2515 }
2516
b4cdc5c2
PZ		 2517 if (event->attr.type != PERF_TYPE_RAW)
2518 return 0;
2519
2520 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2521 return 0;
2522
2523 if (x86_pmu.version < 3)
2524 return -EINVAL;
2525
2526 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2527 return -EACCES;
2528
2529 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2530
2531 return 0;
2532}
2533
144d31e6
GN		 2534struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2535{
2536 if (x86_pmu.guest_get_msrs)
2537 return x86_pmu.guest_get_msrs(nr);
2538 *nr = 0;
2539 return NULL;
2540}
2541EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2542
2543static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2544{
89cbc767 2545 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2546 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2547
2548 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2549 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2550 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2551 /*
2552 * If PMU counter has PEBS enabled it is not enough to disable counter
2553 * on a guest entry since PEBS memory write can overshoot guest entry
2554 * and corrupt guest memory. Disabling PEBS solves the problem.
2555 */
2556 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2557 arr[1].host = cpuc->pebs_enabled;
2558 arr[1].guest = 0;
144d31e6 2559
26a4f3c0 2560 *nr = 2;
144d31e6
GN		 2561 return arr;
2562}
2563
2564static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2565{
89cbc767 2566 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2567 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2568 int idx;
2569
2570 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2571 struct perf_event *event = cpuc->events[idx];
2572
2573 arr[idx].msr = x86_pmu_config_addr(idx);
2574 arr[idx].host = arr[idx].guest = 0;
2575
2576 if (!test_bit(idx, cpuc->active_mask))
2577 continue;
2578
2579 arr[idx].host = arr[idx].guest =
2580 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2581
2582 if (event->attr.exclude_host)
2583 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2584 else if (event->attr.exclude_guest)
2585 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2586 }
2587
2588 *nr = x86_pmu.num_counters;
2589 return arr;
2590}
2591
2592static void core_pmu_enable_event(struct perf_event *event)
2593{
2594 if (!event->attr.exclude_host)
2595 x86_pmu_enable_event(event);
2596}
2597
2598static void core_pmu_enable_all(int added)
2599{
89cbc767 2600 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2601 int idx;
2602
2603 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2604 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2605
2606 if (!test_bit(idx, cpuc->active_mask) ||
2607 cpuc->events[idx]->attr.exclude_host)
2608 continue;
2609
2610 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2611 }
2612}
2613
3a632cb2
AK		 2614static int hsw_hw_config(struct perf_event *event)
2615{
2616 int ret = intel_pmu_hw_config(event);
2617
2618 if (ret)
2619 return ret;
2620 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2621 return 0;
2622 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2623
2624 /*
2625 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2626 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2627 * this combination.
2628 */
2629 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2630 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2631 event->attr.precise_ip > 0))
2632 return -EOPNOTSUPP;
2633
2dbf0116
AK		 2634 if (event_is_checkpointed(event)) {
2635 /*
2636 * Sampling of checkpointed events can cause situations where
2637 * the CPU constantly aborts because of a overflow, which is
2638 * then checkpointed back and ignored. Forbid checkpointing
2639 * for sampling.
2640 *
2641 * But still allow a long sampling period, so that perf stat
2642 * from KVM works.
2643 */
2644 if (event->attr.sample_period > 0 &&
2645 event->attr.sample_period < 0x7fffffff)
2646 return -EOPNOTSUPP;
2647 }
3a632cb2
AK		 2648 return 0;
2649}
2650
2651static struct event_constraint counter2_constraint =
2652 EVENT_CONSTRAINT(0, 0x4, 0);
2653
2654static struct event_constraint *
79cba822
SE		 2655hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2656 struct perf_event *event)
3a632cb2 2657{
79cba822
SE		 2658 struct event_constraint *c;
2659
2660 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2661
2662 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2663 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2664 if (c->idxmsk64 & (1U << 2))
2665 return &counter2_constraint;
2666 return &emptyconstraint;
2667 }
2668
2669 return c;
2670}
2671
294fe0f5
AK		 2672/*
2673 * Broadwell:
2674 *
2675 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
2676 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
2677 * the two to enforce a minimum period of 128 (the smallest value that has bits
2678 * 0-5 cleared and >= 100).
2679 *
2680 * Because of how the code in x86_perf_event_set_period() works, the truncation
2681 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
2682 * to make up for the 'lost' events due to carrying the 'error' in period_left.
2683 *
2684 * Therefore the effective (average) period matches the requested period,
2685 * despite coarser hardware granularity.
2686 */
2687static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
2688{
2689 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
2690 X86_CONFIG(.event=0xc0, .umask=0x01)) {
2691 if (left < 128)
2692 left = 128;
2693 left &= ~0x3fu;
2694 }
2695 return left;
2696}
2697
641cc938
JO		 2698PMU_FORMAT_ATTR(event, "config:0-7" );
2699PMU_FORMAT_ATTR(umask, "config:8-15" );
2700PMU_FORMAT_ATTR(edge, "config:18" );
2701PMU_FORMAT_ATTR(pc, "config:19" );
2702PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
2703PMU_FORMAT_ATTR(inv, "config:23" );
2704PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 2705PMU_FORMAT_ATTR(in_tx, "config:32");
2706PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 2707
2708static struct attribute *intel_arch_formats_attr[] = {
2709 &format_attr_event.attr,
2710 &format_attr_umask.attr,
2711 &format_attr_edge.attr,
2712 &format_attr_pc.attr,
2713 &format_attr_inv.attr,
2714 &format_attr_cmask.attr,
2715 NULL,
2716};
2717
0bf79d44
JO		 2718ssize_t intel_event_sysfs_show(char *page, u64 config)
2719{
2720 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
2721
2722 return x86_event_sysfs_show(page, config, event);
2723}
2724
de0428a7 2725struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 2726{
2727 struct intel_shared_regs *regs;
2728 int i;
2729
2730 regs = kzalloc_node(sizeof(struct intel_shared_regs),
2731 GFP_KERNEL, cpu_to_node(cpu));
2732 if (regs) {
2733 /*
2734 * initialize the locks to keep lockdep happy
2735 */
2736 for (i = 0; i < EXTRA_REG_MAX; i++)
2737 raw_spin_lock_init(&regs->regs[i].lock);
2738
2739 regs->core_id = -1;
2740 }
2741 return regs;
2742}
2743
6f6539ca
MD		 2744static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
2745{
2746 struct intel_excl_cntrs *c;
6f6539ca
MD		 2747
2748 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
2749 GFP_KERNEL, cpu_to_node(cpu));
2750 if (c) {
2751 raw_spin_lock_init(&c->lock);
6f6539ca
MD		 2752 c->core_id = -1;
2753 }
2754 return c;
2755}
2756
a7e3ed1e
AK		 2757static int intel_pmu_cpu_prepare(int cpu)
2758{
2759 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2760
6f6539ca
MD		 2761 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
2762 cpuc->shared_regs = allocate_shared_regs(cpu);
2763 if (!cpuc->shared_regs)
dbc72b7a 2764 goto err;
6f6539ca 2765 }
69092624 2766
6f6539ca
MD		 2767 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
2768 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
2769
2770 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
2771 if (!cpuc->constraint_list)
dbc72b7a 2772 goto err_shared_regs;
6f6539ca
MD		 2773
2774 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
dbc72b7a
PZ		 2775 if (!cpuc->excl_cntrs)
2776 goto err_constraint_list;
2777
6f6539ca
MD		 2778 cpuc->excl_thread_id = 0;
2779 }
a7e3ed1e 2780
a7e3ed1e 2781 return NOTIFY_OK;
dbc72b7a
PZ		 2782
2783err_constraint_list:
2784 kfree(cpuc->constraint_list);
2785 cpuc->constraint_list = NULL;
2786
2787err_shared_regs:
2788 kfree(cpuc->shared_regs);
2789 cpuc->shared_regs = NULL;
2790
2791err:
2792 return NOTIFY_BAD;
a7e3ed1e
AK		 2793}
2794
74846d35
PZ		 2795static void intel_pmu_cpu_starting(int cpu)
2796{
a7e3ed1e
AK		 2797 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2798 int core_id = topology_core_id(cpu);
2799 int i;
2800
69092624
LM		 2801 init_debug_store_on_cpu(cpu);
2802 /*
2803 * Deal with CPUs that don't clear their LBRs on power-up.
2804 */
2805 intel_pmu_lbr_reset();
2806
b36817e8
SE		 2807 cpuc->lbr_sel = NULL;
2808
2809 if (!cpuc->shared_regs)
69092624
LM		 2810 return;
2811
9a5e3fb5 2812 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
90413464
SE		 2813 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED];
2814
06931e62 2815 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
b36817e8 2816 struct intel_shared_regs *pc;
a7e3ed1e 2817
b36817e8
SE		 2818 pc = per_cpu(cpu_hw_events, i).shared_regs;
2819 if (pc && pc->core_id == core_id) {
90413464 2820 *onln = cpuc->shared_regs;
b36817e8
SE		 2821 cpuc->shared_regs = pc;
2822 break;
2823 }
a7e3ed1e 2824 }
b36817e8
SE		 2825 cpuc->shared_regs->core_id = core_id;
2826 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 2827 }
2828
b36817e8
SE		 2829 if (x86_pmu.lbr_sel_map)
2830 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 2831
2832 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
06931e62 2833 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6f6539ca
MD		 2834 struct intel_excl_cntrs *c;
2835
2836 c = per_cpu(cpu_hw_events, i).excl_cntrs;
2837 if (c && c->core_id == core_id) {
2838 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
2839 cpuc->excl_cntrs = c;
2840 cpuc->excl_thread_id = 1;
2841 break;
2842 }
2843 }
2844 cpuc->excl_cntrs->core_id = core_id;
2845 cpuc->excl_cntrs->refcnt++;
2846 }
74846d35
PZ		 2847}
2848
b37609c3 2849static void free_excl_cntrs(int cpu)
74846d35 2850{
a7e3ed1e 2851 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 2852 struct intel_excl_cntrs *c;
a7e3ed1e 2853
6f6539ca
MD		 2854 c = cpuc->excl_cntrs;
2855 if (c) {
2856 if (c->core_id == -1 || --c->refcnt == 0)
2857 kfree(c);
2858 cpuc->excl_cntrs = NULL;
2859 kfree(cpuc->constraint_list);
2860 cpuc->constraint_list = NULL;
2861 }
b37609c3 2862}
a7e3ed1e 2863
b37609c3
SE		 2864static void intel_pmu_cpu_dying(int cpu)
2865{
2866 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2867 struct intel_shared_regs *pc;
2868
2869 pc = cpuc->shared_regs;
2870 if (pc) {
2871 if (pc->core_id == -1 || --pc->refcnt == 0)
2872 kfree(pc);
2873 cpuc->shared_regs = NULL;
e979121b
MD		 2874 }
2875
b37609c3
SE		 2876 free_excl_cntrs(cpu);
2877
74846d35
PZ		 2878 fini_debug_store_on_cpu(cpu);
2879}
2880
9c964efa
YZ		 2881static void intel_pmu_sched_task(struct perf_event_context *ctx,
2882 bool sched_in)
2883{
2884 if (x86_pmu.pebs_active)
2885 intel_pmu_pebs_sched_task(ctx, sched_in);
2886 if (x86_pmu.lbr_nr)
2887 intel_pmu_lbr_sched_task(ctx, sched_in);
2888}
2889
641cc938
JO		 2890PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
2891
a63fcab4
SE		 2892PMU_FORMAT_ATTR(ldlat, "config1:0-15");
2893
641cc938
JO		 2894static struct attribute *intel_arch3_formats_attr[] = {
2895 &format_attr_event.attr,
2896 &format_attr_umask.attr,
2897 &format_attr_edge.attr,
2898 &format_attr_pc.attr,
2899 &format_attr_any.attr,
2900 &format_attr_inv.attr,
2901 &format_attr_cmask.attr,
3a632cb2
AK		 2902 &format_attr_in_tx.attr,
2903 &format_attr_in_tx_cp.attr,
641cc938
JO		 2904
2905 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 2906 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 2907 NULL,
2908};
2909
3b6e0421
JO		 2910static __initconst const struct x86_pmu core_pmu = {
2911 .name = "core",
2912 .handle_irq = x86_pmu_handle_irq,
2913 .disable_all = x86_pmu_disable_all,
2914 .enable_all = core_pmu_enable_all,
2915 .enable = core_pmu_enable_event,
2916 .disable = x86_pmu_disable_event,
2917 .hw_config = x86_pmu_hw_config,
2918 .schedule_events = x86_schedule_events,
2919 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2920 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2921 .event_map = intel_pmu_event_map,
2922 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2923 .apic = 1,
a7b58d21
AK		 2924 .free_running_flags = PEBS_FREERUNNING_FLAGS,
2925
3b6e0421
JO		 2926 /*
2927 * Intel PMCs cannot be accessed sanely above 32-bit width,
2928 * so we install an artificial 1<<31 period regardless of
2929 * the generic event period:
2930 */
2931 .max_period = (1ULL<<31) - 1,
2932 .get_event_constraints = intel_get_event_constraints,
2933 .put_event_constraints = intel_put_event_constraints,
2934 .event_constraints = intel_core_event_constraints,
2935 .guest_get_msrs = core_guest_get_msrs,
2936 .format_attrs = intel_arch_formats_attr,
2937 .events_sysfs_show = intel_event_sysfs_show,
2938
2939 /*
2940 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
2941 * together with PMU version 1 and thus be using core_pmu with
2942 * shared_regs. We need following callbacks here to allocate
2943 * it properly.
2944 */
2945 .cpu_prepare = intel_pmu_cpu_prepare,
2946 .cpu_starting = intel_pmu_cpu_starting,
2947 .cpu_dying = intel_pmu_cpu_dying,
2948};
2949
caaa8be3 2950static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 2951 .name = "Intel",
2952 .handle_irq = intel_pmu_handle_irq,
2953 .disable_all = intel_pmu_disable_all,
2954 .enable_all = intel_pmu_enable_all,
2955 .enable = intel_pmu_enable_event,
2956 .disable = intel_pmu_disable_event,
b4cdc5c2 2957 .hw_config = intel_pmu_hw_config,
a072738e 2958 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 2959 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
2960 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
2961 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 2962 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
2963 .apic = 1,
a7b58d21 2964 .free_running_flags = PEBS_FREERUNNING_FLAGS,
f22f54f4
PZ		 2965 /*
2966 * Intel PMCs cannot be accessed sanely above 32 bit width,
2967 * so we install an artificial 1<<31 period regardless of
2968 * the generic event period:
2969 */
2970 .max_period = (1ULL << 31) - 1,
3f6da390 2971 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 2972 .put_event_constraints = intel_put_event_constraints,
0780c927 2973 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 2974
641cc938 2975 .format_attrs = intel_arch3_formats_attr,
0bf79d44 2976 .events_sysfs_show = intel_event_sysfs_show,
641cc938 2977
a7e3ed1e 2978 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 2979 .cpu_starting = intel_pmu_cpu_starting,
2980 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 2981 .guest_get_msrs = intel_guest_get_msrs,
9c964efa 2982 .sched_task = intel_pmu_sched_task,
f22f54f4
PZ		 2983};
2984
c1d6f42f 2985static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 2986{
2987 /*
2988 * PEBS is unreliable due to:
2989 *
2990 * AJ67 - PEBS may experience CPL leaks
2991 * AJ68 - PEBS PMI may be delayed by one event
2992 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
2993 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
2994 *
2995 * AJ67 could be worked around by restricting the OS/USR flags.
2996 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
2997 *
2998 * AJ106 could possibly be worked around by not allowing LBR
2999 * usage from PEBS, including the fixup.
3000 * AJ68 could possibly be worked around by always programming
ec75a716 3001 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 3002 *
3003 * But taken together it might just make sense to not enable PEBS on
3004 * these chips.
3005 */
c767a54b 3006 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 3007 x86_pmu.pebs = 0;
3008 x86_pmu.pebs_constraints = NULL;
3009}
3010
c93dc84c
PZ		 3011static int intel_snb_pebs_broken(int cpu)
3012{
3013 u32 rev = UINT_MAX; /* default to broken for unknown models */
3014
3015 switch (cpu_data(cpu).x86_model) {
3016 case 42: /* SNB */
3017 rev = 0x28;
3018 break;
3019
3020 case 45: /* SNB-EP */
3021 switch (cpu_data(cpu).x86_mask) {
3022 case 6: rev = 0x618; break;
3023 case 7: rev = 0x70c; break;
3024 }
3025 }
3026
3027 return (cpu_data(cpu).microcode < rev);
3028}
3029
3030static void intel_snb_check_microcode(void)
3031{
3032 int pebs_broken = 0;
3033 int cpu;
3034
3035 get_online_cpus();
3036 for_each_online_cpu(cpu) {
3037 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3038 break;
3039 }
3040 put_online_cpus();
3041
3042 if (pebs_broken == x86_pmu.pebs_broken)
3043 return;
3044
3045 /*
3046 * Serialized by the microcode lock..
3047 */
3048 if (x86_pmu.pebs_broken) {
3049 pr_info("PEBS enabled due to microcode update\n");
3050 x86_pmu.pebs_broken = 0;
3051 } else {
3052 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3053 x86_pmu.pebs_broken = 1;
3054 }
3055}
3056
338b522c
KL		 3057/*
3058 * Under certain circumstances, access certain MSR may cause #GP.
3059 * The function tests if the input MSR can be safely accessed.
3060 */
3061static bool check_msr(unsigned long msr, u64 mask)
3062{
3063 u64 val_old, val_new, val_tmp;
3064
3065 /*
3066 * Read the current value, change it and read it back to see if it
3067 * matches, this is needed to detect certain hardware emulators
3068 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3069 */
3070 if (rdmsrl_safe(msr, &val_old))
3071 return false;
3072
3073 /*
3074 * Only change the bits which can be updated by wrmsrl.
3075 */
3076 val_tmp = val_old ^ mask;
3077 if (wrmsrl_safe(msr, val_tmp) ||
3078 rdmsrl_safe(msr, &val_new))
3079 return false;
3080
3081 if (val_new != val_tmp)
3082 return false;
3083
3084 /* Here it's sure that the MSR can be safely accessed.
3085 * Restore the old value and return.
3086 */
3087 wrmsrl(msr, val_old);
3088
3089 return true;
3090}
3091
c1d6f42f 3092static __init void intel_sandybridge_quirk(void)
6a600a8b 3093{
c93dc84c
PZ		 3094 x86_pmu.check_microcode = intel_snb_check_microcode;
3095 intel_snb_check_microcode();
6a600a8b
PZ		 3096}
3097
c1d6f42f
PZ		 3098static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3099 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3100 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3101 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3102 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3103 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3104 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3105 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 3106};
3107
c1d6f42f
PZ		 3108static __init void intel_arch_events_quirk(void)
3109{
3110 int bit;
3111
3112 /* disable event that reported as not presend by cpuid */
3113 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3114 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 3115 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3116 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 3117 }
3118}
3119
3120static __init void intel_nehalem_quirk(void)
3121{
3122 union cpuid10_ebx ebx;
3123
3124 ebx.full = x86_pmu.events_maskl;
3125 if (ebx.split.no_branch_misses_retired) {
3126 /*
3127 * Erratum AAJ80 detected, we work it around by using
3128 * the BR_MISP_EXEC.ANY event. This will over-count
3129 * branch-misses, but it's still much better than the
3130 * architectural event which is often completely bogus:
3131 */
3132 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3133 ebx.split.no_branch_misses_retired = 0;
3134 x86_pmu.events_maskl = ebx.full;
c767a54b 3135 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 3136 }
3137}
3138
93fcf72c
MD		 3139/*
3140 * enable software workaround for errata:
3141 * SNB: BJ122
3142 * IVB: BV98
3143 * HSW: HSD29
3144 *
3145 * Only needed when HT is enabled. However detecting
b37609c3
SE		 3146 * if HT is enabled is difficult (model specific). So instead,
3147 * we enable the workaround in the early boot, and verify if
3148 * it is needed in a later initcall phase once we have valid
3149 * topology information to check if HT is actually enabled
93fcf72c
MD		 3150 */
3151static __init void intel_ht_bug(void)
3152{
b37609c3 3153 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c 3154
93fcf72c 3155 x86_pmu.start_scheduling = intel_start_scheduling;
0c41e756 3156 x86_pmu.commit_scheduling = intel_commit_scheduling;
93fcf72c 3157 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 3158}
3159
7f2ee91f
IM		 3160EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3161EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 3162
4b2c4f1f 3163/* Haswell special events */
7f2ee91f
IM		 3164EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3165EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3166EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3167EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3168EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3169EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3170EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3171EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3172EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3173EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3174EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3175EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 3176
f9134f36 3177static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 3178 EVENT_PTR(tx_start),
3179 EVENT_PTR(tx_commit),
3180 EVENT_PTR(tx_abort),
3181 EVENT_PTR(tx_capacity),
3182 EVENT_PTR(tx_conflict),
3183 EVENT_PTR(el_start),
3184 EVENT_PTR(el_commit),
3185 EVENT_PTR(el_abort),
3186 EVENT_PTR(el_capacity),
3187 EVENT_PTR(el_conflict),
3188 EVENT_PTR(cycles_t),
3189 EVENT_PTR(cycles_ct),
f9134f36
AK		 3190 EVENT_PTR(mem_ld_hsw),
3191 EVENT_PTR(mem_st_hsw),
3192 NULL
3193};
3194
de0428a7 3195__init int intel_pmu_init(void)
f22f54f4
PZ		 3196{
3197 union cpuid10_edx edx;
3198 union cpuid10_eax eax;
ffb871bc 3199 union cpuid10_ebx ebx;
a1eac7ac 3200 struct event_constraint *c;
f22f54f4 3201 unsigned int unused;
338b522c
KL		 3202 struct extra_reg *er;
3203 int version, i;
f22f54f4
PZ		 3204
3205 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 3206 switch (boot_cpu_data.x86) {
3207 case 0x6:
3208 return p6_pmu_init();
e717bf4e
VW		 3209 case 0xb:
3210 return knc_pmu_init();
a072738e
CG		 3211 case 0xf:
3212 return p4_pmu_init();
3213 }
f22f54f4 3214 return -ENODEV;
f22f54f4
PZ		 3215 }
3216
3217 /*
3218 * Check whether the Architectural PerfMon supports
3219 * Branch Misses Retired hw_event or not.
3220 */
ffb871bc
GN		 3221 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3222 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 3223 return -ENODEV;
3224
3225 version = eax.split.version_id;
3226 if (version < 2)
3227 x86_pmu = core_pmu;
3228 else
3229 x86_pmu = intel_pmu;
3230
3231 x86_pmu.version = version;
948b1bb8
RR		 3232 x86_pmu.num_counters = eax.split.num_counters;
3233 x86_pmu.cntval_bits = eax.split.bit_width;
3234 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 3235
c1d6f42f
PZ		 3236 x86_pmu.events_maskl = ebx.full;
3237 x86_pmu.events_mask_len = eax.split.mask_length;
3238
70ab7003
AK		 3239 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3240
f22f54f4
PZ		 3241 /*
3242 * Quirk: v2 perfmon does not report fixed-purpose events, so
3243 * assume at least 3 events:
3244 */
3245 if (version > 1)
948b1bb8 3246 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 3247
c9b08884 3248 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 3249 u64 capabilities;
3250
3251 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3252 x86_pmu.intel_cap.capabilities = capabilities;
3253 }
3254
ca037701
PZ		 3255 intel_ds_init();
3256
c1d6f42f
PZ		 3257 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3258
f22f54f4
PZ		 3259 /*
3260 * Install the hw-cache-events table:
3261 */
3262 switch (boot_cpu_data.x86_model) {
0f7c29ce 3263 case 14: /* 65nm Core "Yonah" */
f22f54f4
PZ		 3264 pr_cont("Core events, ");
3265 break;
3266
0f7c29ce 3267 case 15: /* 65nm Core2 "Merom" */
c1d6f42f 3268 x86_add_quirk(intel_clovertown_quirk);
0f7c29ce
PZ		 3269 case 22: /* 65nm Core2 "Merom-L" */
3270 case 23: /* 45nm Core2 "Penryn" */
3271 case 29: /* 45nm Core2 "Dunnington (MP) */
f22f54f4
PZ		 3272 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3273 sizeof(hw_cache_event_ids));
3274
caff2bef
PZ		 3275 intel_pmu_lbr_init_core();
3276
f22f54f4 3277 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3278 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3279 pr_cont("Core2 events, ");
3280 break;
3281
0f7c29ce
PZ		 3282 case 30: /* 45nm Nehalem */
3283 case 26: /* 45nm Nehalem-EP */
3284 case 46: /* 45nm Nehalem-EX */
f22f54f4
PZ		 3285 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3286 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3287 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3288 sizeof(hw_cache_extra_regs));
f22f54f4 3289
caff2bef
PZ		 3290 intel_pmu_lbr_init_nhm();
3291
f22f54f4 3292 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3293 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3294 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3295 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3296
f20093ee
SE		 3297 x86_pmu.cpu_events = nhm_events_attrs;
3298
91fc4cc0 3299 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3300 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3301 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3302 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3303 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3304 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3305
c1d6f42f 3306 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3307
11164cd4 3308 pr_cont("Nehalem events, ");
f22f54f4 3309 break;
caff2bef 3310
0f7c29ce
PZ		 3311 case 28: /* 45nm Atom "Pineview" */
3312 case 38: /* 45nm Atom "Lincroft" */
3313 case 39: /* 32nm Atom "Penwell" */
3314 case 53: /* 32nm Atom "Cloverview" */
3315 case 54: /* 32nm Atom "Cedarview" */
f22f54f4
PZ		 3316 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3317 sizeof(hw_cache_event_ids));
3318
caff2bef
PZ		 3319 intel_pmu_lbr_init_atom();
3320
f22f54f4 3321 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3322 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 3323 pr_cont("Atom events, ");
3324 break;
3325
0f7c29ce 3326 case 55: /* 22nm Atom "Silvermont" */
ef454cae 3327 case 76: /* 14nm Atom "Airmont" */
0f7c29ce 3328 case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
1fa64180
YZ		 3329 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3330 sizeof(hw_cache_event_ids));
3331 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3332 sizeof(hw_cache_extra_regs));
3333
3334 intel_pmu_lbr_init_atom();
3335
3336 x86_pmu.event_constraints = intel_slm_event_constraints;
3337 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3338 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3339 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
1fa64180
YZ		 3340 pr_cont("Silvermont events, ");
3341 break;
3342
0f7c29ce
PZ		 3343 case 37: /* 32nm Westmere */
3344 case 44: /* 32nm Westmere-EP */
3345 case 47: /* 32nm Westmere-EX */
f22f54f4
PZ		 3346 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3347 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3348 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3349 sizeof(hw_cache_extra_regs));
f22f54f4 3350
caff2bef
PZ		 3351 intel_pmu_lbr_init_nhm();
3352
f22f54f4 3353 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3354 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3355 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3356 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3357 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3358
f20093ee
SE		 3359 x86_pmu.cpu_events = nhm_events_attrs;
3360
30112039 3361 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3362 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3363 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3364 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3365 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3366 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3367
f22f54f4
PZ		 3368 pr_cont("Westmere events, ");
3369 break;
b622d644 3370
0f7c29ce
PZ		 3371 case 42: /* 32nm SandyBridge */
3372 case 45: /* 32nm SandyBridge-E/EN/EP */
47a8863d 3373 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3374 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3375 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3376 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3377 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3378 sizeof(hw_cache_extra_regs));
b06b3d49 3379
c5cc2cd9 3380 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3381
3382 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3383 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3384 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3385 if (boot_cpu_data.x86_model == 45)
3386 x86_pmu.extra_regs = intel_snbep_extra_regs;
3387 else
3388 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3389
3390
ee89cbc2 3391 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3392 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3393 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3394
f20093ee
SE		 3395 x86_pmu.cpu_events = snb_events_attrs;
3396
e04d1b23 3397 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3398 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3399 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3400 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3401 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3402 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3403
b06b3d49
LM		 3404 pr_cont("SandyBridge events, ");
3405 break;
0f7c29ce
PZ		 3406
3407 case 58: /* 22nm IvyBridge */
3408 case 62: /* 22nm IvyBridge-EP/EX */
93fcf72c 3409 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3410 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3411 sizeof(hw_cache_event_ids));
1996388e
VW		 3412 /* dTLB-load-misses on IVB is different than SNB */
3413 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3414
20a36e39
SE		 3415 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3416 sizeof(hw_cache_extra_regs));
3417
3418 intel_pmu_lbr_init_snb();
3419
69943182 3420 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 3421 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
3422 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 3423 if (boot_cpu_data.x86_model == 62)
3424 x86_pmu.extra_regs = intel_snbep_extra_regs;
3425 else
3426 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3427 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3428 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3429 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3430
f20093ee
SE		 3431 x86_pmu.cpu_events = snb_events_attrs;
3432
20a36e39
SE		 3433 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3434 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3435 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3436
3437 pr_cont("IvyBridge events, ");
3438 break;
3439
b06b3d49 3440
d86c8eaf
AK		 3441 case 60: /* 22nm Haswell Core */
3442 case 63: /* 22nm Haswell Server */
3443 case 69: /* 22nm Haswell ULT */
3444 case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
93fcf72c 3445 x86_add_quirk(intel_ht_bug);
72db5596 3446 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3447 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3448 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3449
e9d7f7cd 3450 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3451
3452 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3453 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3454 x86_pmu.extra_regs = intel_snbep_extra_regs;
3044318f 3455 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2 3456 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3457 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3458 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3459
3460 x86_pmu.hw_config = hsw_hw_config;
3461 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3462 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3463 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3464 pr_cont("Haswell events, ");
3465 break;
3466
91f1b705
AK		 3467 case 61: /* 14nm Broadwell Core-M */
3468 case 86: /* 14nm Broadwell Xeon D */
4b36f1a4
AK		 3469 case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
3470 case 79: /* 14nm Broadwell Server */
91f1b705
AK		 3471 x86_pmu.late_ack = true;
3472 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3473 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3474
3475 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3476 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3477 BDW_L3_MISS|HSW_SNOOP_DRAM;
3478 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3479 HSW_SNOOP_DRAM;
3480 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3481 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3482 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3483 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3484
78d504bc 3485 intel_pmu_lbr_init_hsw();
91f1b705
AK		 3486
3487 x86_pmu.event_constraints = intel_bdw_event_constraints;
3488 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3489 x86_pmu.extra_regs = intel_snbep_extra_regs;
3490 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3491 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3492 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3493 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3494
3495 x86_pmu.hw_config = hsw_hw_config;
3496 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3497 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3498 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3499 pr_cont("Broadwell events, ");
3500 break;
3501
9a92e16f
AK		 3502 case 78: /* 14nm Skylake Mobile */
3503 case 94: /* 14nm Skylake Desktop */
3504 x86_pmu.late_ack = true;
3505 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3506 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3507 intel_pmu_lbr_init_skl();
3508
3509 x86_pmu.event_constraints = intel_skl_event_constraints;
3510 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3511 x86_pmu.extra_regs = intel_skl_extra_regs;
3512 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3513 /* all extra regs are per-cpu when HT is on */
3514 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3515 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3516
3517 x86_pmu.hw_config = hsw_hw_config;
3518 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3519 x86_pmu.cpu_events = hsw_events_attrs;
3520 WARN_ON(!x86_pmu.format_attrs);
3521 x86_pmu.cpu_events = hsw_events_attrs;
3522 pr_cont("Skylake events, ");
3523 break;
3524
f22f54f4 3525 default:
0af3ac1f
AK		 3526 switch (x86_pmu.version) {
3527 case 1:
3528 x86_pmu.event_constraints = intel_v1_event_constraints;
3529 pr_cont("generic architected perfmon v1, ");
3530 break;
3531 default:
3532 /*
3533 * default constraints for v2 and up
3534 */
3535 x86_pmu.event_constraints = intel_gen_event_constraints;
3536 pr_cont("generic architected perfmon, ");
3537 break;
3538 }
f22f54f4 3539 }
ffb871bc 3540
a1eac7ac
RR		 3541 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3542 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3543 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3544 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3545 }
3546 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3547
3548 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3549 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3550 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3551 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3552 }
3553
3554 x86_pmu.intel_ctrl |=
3555 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3556
3557 if (x86_pmu.event_constraints) {
3558 /*
3559 * event on fixed counter2 (REF_CYCLES) only works on this
3560 * counter, so do not extend mask to generic counters
3561 */
3562 for_each_event_constraint(c, x86_pmu.event_constraints) {
2c33645d
PI		 3563 if (c->cmask == FIXED_EVENT_FLAGS
3564 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3565 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac 3566 }
2c33645d
PI		 3567 c->idxmsk64 &=
3568 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
3569 c->weight = hweight64(c->idxmsk64);
a1eac7ac
RR		 3570 }
3571 }
3572
338b522c
KL		 3573 /*
3574 * Access LBR MSR may cause #GP under certain circumstances.
3575 * E.g. KVM doesn't support LBR MSR
3576 * Check all LBT MSR here.
3577 * Disable LBR access if any LBR MSRs can not be accessed.
3578 */
3579 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
3580 x86_pmu.lbr_nr = 0;
3581 for (i = 0; i < x86_pmu.lbr_nr; i++) {
3582 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
3583 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
3584 x86_pmu.lbr_nr = 0;
3585 }
3586
3587 /*
3588 * Access extra MSR may cause #GP under certain circumstances.
3589 * E.g. KVM doesn't support offcore event
3590 * Check all extra_regs here.
3591 */
3592 if (x86_pmu.extra_regs) {
3593 for (er = x86_pmu.extra_regs; er->msr; er++) {
8c4fe709 3594 er->extra_msr_access = check_msr(er->msr, 0x11UL);
338b522c
KL		 3595 /* Disable LBR select mapping */
3596 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
3597 x86_pmu.lbr_sel_map = NULL;
3598 }
3599 }
3600
069e0c3c
AK		 3601 /* Support full width counters using alternative MSR range */
3602 if (x86_pmu.intel_cap.full_width_write) {
3603 x86_pmu.max_period = x86_pmu.cntval_mask;
3604 x86_pmu.perfctr = MSR_IA32_PMC0;
3605 pr_cont("full-width counters, ");
3606 }
3607
f22f54f4
PZ		 3608 return 0;
3609}
b37609c3
SE		 3610
3611/*
3612 * HT bug: phase 2 init
3613 * Called once we have valid topology information to check
3614 * whether or not HT is enabled
3615 * If HT is off, then we disable the workaround
3616 */
3617static __init int fixup_ht_bug(void)
3618{
3619 int cpu = smp_processor_id();
3620 int w, c;
3621 /*
3622 * problem not present on this CPU model, nothing to do
3623 */
3624 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
3625 return 0;
3626
06931e62 3627 w = cpumask_weight(topology_sibling_cpumask(cpu));
b37609c3
SE		 3628 if (w > 1) {
3629 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
3630 return 0;
3631 }
3632
ec6a9066 3633 if (lockup_detector_suspend() != 0) {
999bbe49
UO		 3634 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
3635 return 0;
3636 }
b37609c3
SE		 3637
3638 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
3639
b37609c3 3640 x86_pmu.start_scheduling = NULL;
0c41e756 3641 x86_pmu.commit_scheduling = NULL;
b37609c3
SE		 3642 x86_pmu.stop_scheduling = NULL;
3643
ec6a9066 3644 lockup_detector_resume();
b37609c3
SE		 3645
3646 get_online_cpus();
3647
3648 for_each_online_cpu(c) {
3649 free_excl_cntrs(c);
3650 }
3651
3652 put_online_cpus();
3653 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
3654 return 0;
3655}
3656subsys_initcall(fixup_ht_bug)
Linux 6.x block layer and io_uring tree(s)