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perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X
[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
53ad0447
YZ		 84 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
85 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 86 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 87 EVENT_EXTRA_END
88};
89
5c543e3c 90static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 91{
b622d644
PZ		 92 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
93 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 94 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 95 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
96 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
97 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 98 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 99 EVENT_CONSTRAINT_END
100};
101
5c543e3c 102static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 103{
104 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
105 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 106 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 107 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
108 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
110 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 111 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 112 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
113 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 114 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
115 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
b06b3d49
LM		 116 EVENT_CONSTRAINT_END
117};
118
69943182
SE		 119static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
120{
121 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
122 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
123 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
124 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
125 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
126 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
127 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
128 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
129 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
132 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
741a698f
PZ		 133 /*
134 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
135 * siblings; disable these events because they can corrupt unrelated
136 * counters.
137 */
138 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
139 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
141 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
69943182
SE		 142 EVENT_CONSTRAINT_END
143};
144
5c543e3c 145static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 146{
53ad0447
YZ		 147 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
148 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
149 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 150 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 151 EVENT_EXTRA_END
152};
153
0af3ac1f
AK		 154static struct event_constraint intel_v1_event_constraints[] __read_mostly =
155{
156 EVENT_CONSTRAINT_END
157};
158
5c543e3c 159static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 160{
b622d644
PZ		 161 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
162 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 163 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 164 EVENT_CONSTRAINT_END
165};
166
ee89cbc2 167static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 168 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
169 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
170 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 171 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 172 EVENT_EXTRA_END
173};
174
175static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 176 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
177 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
178 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 179 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 180 EVENT_EXTRA_END
181};
182
f20093ee
SE		 183EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
184EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
9ad64c0f 185EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 186
187struct attribute *nhm_events_attrs[] = {
188 EVENT_PTR(mem_ld_nhm),
189 NULL,
190};
191
192struct attribute *snb_events_attrs[] = {
193 EVENT_PTR(mem_ld_snb),
9ad64c0f 194 EVENT_PTR(mem_st_snb),
f20093ee
SE		 195 NULL,
196};
197
3a632cb2
AK		 198static struct event_constraint intel_hsw_event_constraints[] = {
199 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
200 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
201 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
202 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
203 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
204 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
205 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
206 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
207 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
208 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
209 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
210 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
211 EVENT_CONSTRAINT_END
212};
213
f22f54f4
PZ		 214static u64 intel_pmu_event_map(int hw_event)
215{
216 return intel_perfmon_event_map[hw_event];
217}
218
74e6543f
YZ		 219#define SNB_DMND_DATA_RD (1ULL << 0)
220#define SNB_DMND_RFO (1ULL << 1)
221#define SNB_DMND_IFETCH (1ULL << 2)
222#define SNB_DMND_WB (1ULL << 3)
223#define SNB_PF_DATA_RD (1ULL << 4)
224#define SNB_PF_RFO (1ULL << 5)
225#define SNB_PF_IFETCH (1ULL << 6)
226#define SNB_LLC_DATA_RD (1ULL << 7)
227#define SNB_LLC_RFO (1ULL << 8)
228#define SNB_LLC_IFETCH (1ULL << 9)
229#define SNB_BUS_LOCKS (1ULL << 10)
230#define SNB_STRM_ST (1ULL << 11)
231#define SNB_OTHER (1ULL << 15)
232#define SNB_RESP_ANY (1ULL << 16)
233#define SNB_NO_SUPP (1ULL << 17)
234#define SNB_LLC_HITM (1ULL << 18)
235#define SNB_LLC_HITE (1ULL << 19)
236#define SNB_LLC_HITS (1ULL << 20)
237#define SNB_LLC_HITF (1ULL << 21)
238#define SNB_LOCAL (1ULL << 22)
239#define SNB_REMOTE (0xffULL << 23)
240#define SNB_SNP_NONE (1ULL << 31)
241#define SNB_SNP_NOT_NEEDED (1ULL << 32)
242#define SNB_SNP_MISS (1ULL << 33)
243#define SNB_NO_FWD (1ULL << 34)
244#define SNB_SNP_FWD (1ULL << 35)
245#define SNB_HITM (1ULL << 36)
246#define SNB_NON_DRAM (1ULL << 37)
247
248#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
249#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
250#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
251
252#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
253 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
254 SNB_HITM)
255
256#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
257#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
258
259#define SNB_L3_ACCESS SNB_RESP_ANY
260#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
261
262static __initconst const u64 snb_hw_cache_extra_regs
263 [PERF_COUNT_HW_CACHE_MAX]
264 [PERF_COUNT_HW_CACHE_OP_MAX]
265 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
266{
267 [ C(LL ) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
270 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
271 },
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
274 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
275 },
276 [ C(OP_PREFETCH) ] = {
277 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
278 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
279 },
280 },
281 [ C(NODE) ] = {
282 [ C(OP_READ) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
284 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
285 },
286 [ C(OP_WRITE) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
288 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
289 },
290 [ C(OP_PREFETCH) ] = {
291 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
292 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
293 },
294 },
295};
296
b06b3d49
LM		 297static __initconst const u64 snb_hw_cache_event_ids
298 [PERF_COUNT_HW_CACHE_MAX]
299 [PERF_COUNT_HW_CACHE_OP_MAX]
300 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
301{
302 [ C(L1D) ] = {
303 [ C(OP_READ) ] = {
304 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
305 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
306 },
307 [ C(OP_WRITE) ] = {
308 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
309 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
310 },
311 [ C(OP_PREFETCH) ] = {
312 [ C(RESULT_ACCESS) ] = 0x0,
313 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
314 },
315 },
316 [ C(L1I ) ] = {
317 [ C(OP_READ) ] = {
318 [ C(RESULT_ACCESS) ] = 0x0,
319 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
320 },
321 [ C(OP_WRITE) ] = {
322 [ C(RESULT_ACCESS) ] = -1,
323 [ C(RESULT_MISS) ] = -1,
324 },
325 [ C(OP_PREFETCH) ] = {
326 [ C(RESULT_ACCESS) ] = 0x0,
327 [ C(RESULT_MISS) ] = 0x0,
328 },
329 },
330 [ C(LL ) ] = {
b06b3d49 331 [ C(OP_READ) ] = {
63b6a675 332 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 333 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 334 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
335 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 336 },
337 [ C(OP_WRITE) ] = {
63b6a675 338 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 339 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 340 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
341 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 342 },
343 [ C(OP_PREFETCH) ] = {
63b6a675 344 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 345 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 346 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
347 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 348 },
349 },
350 [ C(DTLB) ] = {
351 [ C(OP_READ) ] = {
352 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
353 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
354 },
355 [ C(OP_WRITE) ] = {
356 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
357 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
358 },
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = 0x0,
361 [ C(RESULT_MISS) ] = 0x0,
362 },
363 },
364 [ C(ITLB) ] = {
365 [ C(OP_READ) ] = {
366 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
367 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
368 },
369 [ C(OP_WRITE) ] = {
370 [ C(RESULT_ACCESS) ] = -1,
371 [ C(RESULT_MISS) ] = -1,
372 },
373 [ C(OP_PREFETCH) ] = {
374 [ C(RESULT_ACCESS) ] = -1,
375 [ C(RESULT_MISS) ] = -1,
376 },
377 },
378 [ C(BPU ) ] = {
379 [ C(OP_READ) ] = {
380 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
381 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
382 },
383 [ C(OP_WRITE) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 [ C(OP_PREFETCH) ] = {
388 [ C(RESULT_ACCESS) ] = -1,
389 [ C(RESULT_MISS) ] = -1,
390 },
391 },
89d6c0b5
PZ		 392 [ C(NODE) ] = {
393 [ C(OP_READ) ] = {
74e6543f
YZ		 394 [ C(RESULT_ACCESS) ] = 0x01b7,
395 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 396 },
397 [ C(OP_WRITE) ] = {
74e6543f
YZ		 398 [ C(RESULT_ACCESS) ] = 0x01b7,
399 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 400 },
401 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 402 [ C(RESULT_ACCESS) ] = 0x01b7,
403 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 404 },
405 },
406
b06b3d49
LM		 407};
408
caaa8be3 409static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 410 [PERF_COUNT_HW_CACHE_MAX]
411 [PERF_COUNT_HW_CACHE_OP_MAX]
412 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
413{
414 [ C(L1D) ] = {
415 [ C(OP_READ) ] = {
416 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
417 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
418 },
419 [ C(OP_WRITE) ] = {
420 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
421 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
422 },
423 [ C(OP_PREFETCH) ] = {
424 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
425 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
426 },
427 },
428 [ C(L1I ) ] = {
429 [ C(OP_READ) ] = {
430 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
431 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
432 },
433 [ C(OP_WRITE) ] = {
434 [ C(RESULT_ACCESS) ] = -1,
435 [ C(RESULT_MISS) ] = -1,
436 },
437 [ C(OP_PREFETCH) ] = {
438 [ C(RESULT_ACCESS) ] = 0x0,
439 [ C(RESULT_MISS) ] = 0x0,
440 },
441 },
442 [ C(LL ) ] = {
443 [ C(OP_READ) ] = {
63b6a675 444 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 445 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 446 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
447 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 448 },
e994d7d2
AK		 449 /*
450 * Use RFO, not WRITEBACK, because a write miss would typically occur
451 * on RFO.
452 */
f22f54f4 453 [ C(OP_WRITE) ] = {
63b6a675
PZ		 454 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
455 [ C(RESULT_ACCESS) ] = 0x01b7,
456 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 457 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 458 },
459 [ C(OP_PREFETCH) ] = {
63b6a675 460 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 461 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 462 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
463 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 464 },
465 },
466 [ C(DTLB) ] = {
467 [ C(OP_READ) ] = {
468 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
469 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
470 },
471 [ C(OP_WRITE) ] = {
472 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
473 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
474 },
475 [ C(OP_PREFETCH) ] = {
476 [ C(RESULT_ACCESS) ] = 0x0,
477 [ C(RESULT_MISS) ] = 0x0,
478 },
479 },
480 [ C(ITLB) ] = {
481 [ C(OP_READ) ] = {
482 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
483 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
484 },
485 [ C(OP_WRITE) ] = {
486 [ C(RESULT_ACCESS) ] = -1,
487 [ C(RESULT_MISS) ] = -1,
488 },
489 [ C(OP_PREFETCH) ] = {
490 [ C(RESULT_ACCESS) ] = -1,
491 [ C(RESULT_MISS) ] = -1,
492 },
493 },
494 [ C(BPU ) ] = {
495 [ C(OP_READ) ] = {
496 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
497 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
498 },
499 [ C(OP_WRITE) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 [ C(OP_PREFETCH) ] = {
504 [ C(RESULT_ACCESS) ] = -1,
505 [ C(RESULT_MISS) ] = -1,
506 },
507 },
89d6c0b5
PZ		 508 [ C(NODE) ] = {
509 [ C(OP_READ) ] = {
510 [ C(RESULT_ACCESS) ] = 0x01b7,
511 [ C(RESULT_MISS) ] = 0x01b7,
512 },
513 [ C(OP_WRITE) ] = {
514 [ C(RESULT_ACCESS) ] = 0x01b7,
515 [ C(RESULT_MISS) ] = 0x01b7,
516 },
517 [ C(OP_PREFETCH) ] = {
518 [ C(RESULT_ACCESS) ] = 0x01b7,
519 [ C(RESULT_MISS) ] = 0x01b7,
520 },
521 },
f22f54f4
PZ		 522};
523
e994d7d2 524/*
63b6a675
PZ		 525 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
526 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 527 */
528
63b6a675
PZ		 529#define NHM_DMND_DATA_RD (1 << 0)
530#define NHM_DMND_RFO (1 << 1)
531#define NHM_DMND_IFETCH (1 << 2)
532#define NHM_DMND_WB (1 << 3)
533#define NHM_PF_DATA_RD (1 << 4)
534#define NHM_PF_DATA_RFO (1 << 5)
535#define NHM_PF_IFETCH (1 << 6)
536#define NHM_OFFCORE_OTHER (1 << 7)
537#define NHM_UNCORE_HIT (1 << 8)
538#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
539#define NHM_OTHER_CORE_HITM (1 << 10)
540 /* reserved */
541#define NHM_REMOTE_CACHE_FWD (1 << 12)
542#define NHM_REMOTE_DRAM (1 << 13)
543#define NHM_LOCAL_DRAM (1 << 14)
544#define NHM_NON_DRAM (1 << 15)
545
87e24f4b
PZ		 546#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
547#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 548
549#define NHM_DMND_READ (NHM_DMND_DATA_RD)
550#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
551#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
552
553#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 554#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 555#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 556
557static __initconst const u64 nehalem_hw_cache_extra_regs
558 [PERF_COUNT_HW_CACHE_MAX]
559 [PERF_COUNT_HW_CACHE_OP_MAX]
560 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
561{
562 [ C(LL ) ] = {
563 [ C(OP_READ) ] = {
63b6a675
PZ		 564 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
565 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 566 },
567 [ C(OP_WRITE) ] = {
63b6a675
PZ		 568 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
569 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 570 },
571 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 572 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
573 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 574 },
89d6c0b5
PZ		 575 },
576 [ C(NODE) ] = {
577 [ C(OP_READ) ] = {
87e24f4b
PZ		 578 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
579 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 580 },
581 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 582 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
583 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 584 },
585 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 586 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
587 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 588 },
589 },
e994d7d2
AK		 590};
591
caaa8be3 592static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 593 [PERF_COUNT_HW_CACHE_MAX]
594 [PERF_COUNT_HW_CACHE_OP_MAX]
595 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
596{
597 [ C(L1D) ] = {
598 [ C(OP_READ) ] = {
f4929bd3
PZ		 599 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
600 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 601 },
602 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 603 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
604 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 605 },
606 [ C(OP_PREFETCH) ] = {
607 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
608 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
609 },
610 },
611 [ C(L1I ) ] = {
612 [ C(OP_READ) ] = {
613 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
614 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
615 },
616 [ C(OP_WRITE) ] = {
617 [ C(RESULT_ACCESS) ] = -1,
618 [ C(RESULT_MISS) ] = -1,
619 },
620 [ C(OP_PREFETCH) ] = {
621 [ C(RESULT_ACCESS) ] = 0x0,
622 [ C(RESULT_MISS) ] = 0x0,
623 },
624 },
625 [ C(LL ) ] = {
626 [ C(OP_READ) ] = {
e994d7d2
AK		 627 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
628 [ C(RESULT_ACCESS) ] = 0x01b7,
629 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
630 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 631 },
e994d7d2
AK		 632 /*
633 * Use RFO, not WRITEBACK, because a write miss would typically occur
634 * on RFO.
635 */
f22f54f4 636 [ C(OP_WRITE) ] = {
e994d7d2
AK		 637 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
638 [ C(RESULT_ACCESS) ] = 0x01b7,
639 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
640 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 641 },
642 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 643 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
644 [ C(RESULT_ACCESS) ] = 0x01b7,
645 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
646 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 647 },
648 },
649 [ C(DTLB) ] = {
650 [ C(OP_READ) ] = {
651 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
652 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
653 },
654 [ C(OP_WRITE) ] = {
655 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
656 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
657 },
658 [ C(OP_PREFETCH) ] = {
659 [ C(RESULT_ACCESS) ] = 0x0,
660 [ C(RESULT_MISS) ] = 0x0,
661 },
662 },
663 [ C(ITLB) ] = {
664 [ C(OP_READ) ] = {
665 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
666 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
667 },
668 [ C(OP_WRITE) ] = {
669 [ C(RESULT_ACCESS) ] = -1,
670 [ C(RESULT_MISS) ] = -1,
671 },
672 [ C(OP_PREFETCH) ] = {
673 [ C(RESULT_ACCESS) ] = -1,
674 [ C(RESULT_MISS) ] = -1,
675 },
676 },
677 [ C(BPU ) ] = {
678 [ C(OP_READ) ] = {
679 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
680 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
681 },
682 [ C(OP_WRITE) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 [ C(OP_PREFETCH) ] = {
687 [ C(RESULT_ACCESS) ] = -1,
688 [ C(RESULT_MISS) ] = -1,
689 },
690 },
89d6c0b5
PZ		 691 [ C(NODE) ] = {
692 [ C(OP_READ) ] = {
693 [ C(RESULT_ACCESS) ] = 0x01b7,
694 [ C(RESULT_MISS) ] = 0x01b7,
695 },
696 [ C(OP_WRITE) ] = {
697 [ C(RESULT_ACCESS) ] = 0x01b7,
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 [ C(OP_PREFETCH) ] = {
701 [ C(RESULT_ACCESS) ] = 0x01b7,
702 [ C(RESULT_MISS) ] = 0x01b7,
703 },
704 },
f22f54f4
PZ		 705};
706
caaa8be3 707static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 708 [PERF_COUNT_HW_CACHE_MAX]
709 [PERF_COUNT_HW_CACHE_OP_MAX]
710 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
711{
712 [ C(L1D) ] = {
713 [ C(OP_READ) ] = {
714 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
715 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
716 },
717 [ C(OP_WRITE) ] = {
718 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
719 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
720 },
721 [ C(OP_PREFETCH) ] = {
722 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
723 [ C(RESULT_MISS) ] = 0,
724 },
725 },
726 [ C(L1I ) ] = {
727 [ C(OP_READ) ] = {
728 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
729 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
730 },
731 [ C(OP_WRITE) ] = {
732 [ C(RESULT_ACCESS) ] = -1,
733 [ C(RESULT_MISS) ] = -1,
734 },
735 [ C(OP_PREFETCH) ] = {
736 [ C(RESULT_ACCESS) ] = 0,
737 [ C(RESULT_MISS) ] = 0,
738 },
739 },
740 [ C(LL ) ] = {
741 [ C(OP_READ) ] = {
742 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
743 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
744 },
745 [ C(OP_WRITE) ] = {
746 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
747 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
748 },
749 [ C(OP_PREFETCH) ] = {
750 [ C(RESULT_ACCESS) ] = 0,
751 [ C(RESULT_MISS) ] = 0,
752 },
753 },
754 [ C(DTLB) ] = {
755 [ C(OP_READ) ] = {
756 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
757 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
758 },
759 [ C(OP_WRITE) ] = {
760 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
761 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
762 },
763 [ C(OP_PREFETCH) ] = {
764 [ C(RESULT_ACCESS) ] = 0,
765 [ C(RESULT_MISS) ] = 0,
766 },
767 },
768 [ C(ITLB) ] = {
769 [ C(OP_READ) ] = {
770 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
771 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
772 },
773 [ C(OP_WRITE) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 [ C(OP_PREFETCH) ] = {
778 [ C(RESULT_ACCESS) ] = -1,
779 [ C(RESULT_MISS) ] = -1,
780 },
781 },
782 [ C(BPU ) ] = {
783 [ C(OP_READ) ] = {
784 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
785 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
786 },
787 [ C(OP_WRITE) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 [ C(OP_PREFETCH) ] = {
792 [ C(RESULT_ACCESS) ] = -1,
793 [ C(RESULT_MISS) ] = -1,
794 },
795 },
796};
797
caaa8be3 798static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 799 [PERF_COUNT_HW_CACHE_MAX]
800 [PERF_COUNT_HW_CACHE_OP_MAX]
801 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
802{
803 [ C(L1D) ] = {
804 [ C(OP_READ) ] = {
805 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
806 [ C(RESULT_MISS) ] = 0,
807 },
808 [ C(OP_WRITE) ] = {
809 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
810 [ C(RESULT_MISS) ] = 0,
811 },
812 [ C(OP_PREFETCH) ] = {
813 [ C(RESULT_ACCESS) ] = 0x0,
814 [ C(RESULT_MISS) ] = 0,
815 },
816 },
817 [ C(L1I ) ] = {
818 [ C(OP_READ) ] = {
819 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
820 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
821 },
822 [ C(OP_WRITE) ] = {
823 [ C(RESULT_ACCESS) ] = -1,
824 [ C(RESULT_MISS) ] = -1,
825 },
826 [ C(OP_PREFETCH) ] = {
827 [ C(RESULT_ACCESS) ] = 0,
828 [ C(RESULT_MISS) ] = 0,
829 },
830 },
831 [ C(LL ) ] = {
832 [ C(OP_READ) ] = {
833 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
834 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
835 },
836 [ C(OP_WRITE) ] = {
837 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
838 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
839 },
840 [ C(OP_PREFETCH) ] = {
841 [ C(RESULT_ACCESS) ] = 0,
842 [ C(RESULT_MISS) ] = 0,
843 },
844 },
845 [ C(DTLB) ] = {
846 [ C(OP_READ) ] = {
847 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
848 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
849 },
850 [ C(OP_WRITE) ] = {
851 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
852 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
853 },
854 [ C(OP_PREFETCH) ] = {
855 [ C(RESULT_ACCESS) ] = 0,
856 [ C(RESULT_MISS) ] = 0,
857 },
858 },
859 [ C(ITLB) ] = {
860 [ C(OP_READ) ] = {
861 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
862 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
863 },
864 [ C(OP_WRITE) ] = {
865 [ C(RESULT_ACCESS) ] = -1,
866 [ C(RESULT_MISS) ] = -1,
867 },
868 [ C(OP_PREFETCH) ] = {
869 [ C(RESULT_ACCESS) ] = -1,
870 [ C(RESULT_MISS) ] = -1,
871 },
872 },
873 [ C(BPU ) ] = {
874 [ C(OP_READ) ] = {
875 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
876 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
877 },
878 [ C(OP_WRITE) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 [ C(OP_PREFETCH) ] = {
883 [ C(RESULT_ACCESS) ] = -1,
884 [ C(RESULT_MISS) ] = -1,
885 },
886 },
887};
888
60ce0fbd
SE		 889static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
890{
891 /* user explicitly requested branch sampling */
892 if (has_branch_stack(event))
893 return true;
894
895 /* implicit branch sampling to correct PEBS skid */
3044318f
AK		 896 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
897 x86_pmu.intel_cap.pebs_format < 2)
60ce0fbd
SE		 898 return true;
899
900 return false;
901}
902
f22f54f4
PZ		 903static void intel_pmu_disable_all(void)
904{
905 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
906
907 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
908
15c7ad51 909 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 910 intel_pmu_disable_bts();
ca037701
PZ		 911
912 intel_pmu_pebs_disable_all();
caff2bef 913 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 914}
915
11164cd4 916static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 917{
918 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
919
d329527e
PZ		 920 intel_pmu_pebs_enable_all();
921 intel_pmu_lbr_enable_all();
144d31e6
GN		 922 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
923 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 924
15c7ad51 925 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 926 struct perf_event *event =
15c7ad51 927 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 928
929 if (WARN_ON_ONCE(!event))
930 return;
931
932 intel_pmu_enable_bts(event->hw.config);
933 }
934}
935
11164cd4
PZ		 936/*
937 * Workaround for:
938 * Intel Errata AAK100 (model 26)
939 * Intel Errata AAP53 (model 30)
40b91cd1 940 * Intel Errata BD53 (model 44)
11164cd4 941 *
351af072
ZY		 942 * The official story:
943 * These chips need to be 'reset' when adding counters by programming the
944 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
945 * in sequence on the same PMC or on different PMCs.
946 *
947 * In practise it appears some of these events do in fact count, and
948 * we need to programm all 4 events.
11164cd4 949 */
351af072 950static void intel_pmu_nhm_workaround(void)
11164cd4 951{
351af072
ZY		 952 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
953 static const unsigned long nhm_magic[4] = {
954 0x4300B5,
955 0x4300D2,
956 0x4300B1,
957 0x4300B1
958 };
959 struct perf_event *event;
960 int i;
11164cd4 961
351af072
ZY		 962 /*
963 * The Errata requires below steps:
964 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
965 * 2) Configure 4 PERFEVTSELx with the magic events and clear
966 * the corresponding PMCx;
967 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
968 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
969 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
970 */
11164cd4 971
351af072
ZY		 972 /*
973 * The real steps we choose are a little different from above.
974 * A) To reduce MSR operations, we don't run step 1) as they
975 * are already cleared before this function is called;
976 * B) Call x86_perf_event_update to save PMCx before configuring
977 * PERFEVTSELx with magic number;
978 * C) With step 5), we do clear only when the PERFEVTSELx is
979 * not used currently.
980 * D) Call x86_perf_event_set_period to restore PMCx;
981 */
11164cd4 982
351af072
ZY		 983 /* We always operate 4 pairs of PERF Counters */
984 for (i = 0; i < 4; i++) {
985 event = cpuc->events[i];
986 if (event)
987 x86_perf_event_update(event);
988 }
11164cd4 989
351af072
ZY		 990 for (i = 0; i < 4; i++) {
991 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
992 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
993 }
994
995 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
996 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 997
351af072
ZY		 998 for (i = 0; i < 4; i++) {
999 event = cpuc->events[i];
1000
1001 if (event) {
1002 x86_perf_event_set_period(event);
31fa58af 1003 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1004 ARCH_PERFMON_EVENTSEL_ENABLE);
1005 } else
1006 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1007 }
351af072
ZY		 1008}
1009
1010static void intel_pmu_nhm_enable_all(int added)
1011{
1012 if (added)
1013 intel_pmu_nhm_workaround();
11164cd4
PZ		 1014 intel_pmu_enable_all(added);
1015}
1016
f22f54f4
PZ		 1017static inline u64 intel_pmu_get_status(void)
1018{
1019 u64 status;
1020
1021 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1022
1023 return status;
1024}
1025
1026static inline void intel_pmu_ack_status(u64 ack)
1027{
1028 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1029}
1030
ca037701 1031static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1032{
15c7ad51 1033 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1034 u64 ctrl_val, mask;
1035
1036 mask = 0xfULL << (idx * 4);
1037
1038 rdmsrl(hwc->config_base, ctrl_val);
1039 ctrl_val &= ~mask;
7645a24c 1040 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1041}
1042
ca037701 1043static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1044{
aff3d91a 1045 struct hw_perf_event *hwc = &event->hw;
144d31e6 1046 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1047
15c7ad51 1048 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1049 intel_pmu_disable_bts();
1050 intel_pmu_drain_bts_buffer();
1051 return;
1052 }
1053
144d31e6
GN		 1054 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1055 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1056
60ce0fbd
SE		 1057 /*
1058 * must disable before any actual event
1059 * because any event may be combined with LBR
1060 */
1061 if (intel_pmu_needs_lbr_smpl(event))
1062 intel_pmu_lbr_disable(event);
1063
f22f54f4 1064 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1065 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1066 return;
1067 }
1068
aff3d91a 1069 x86_pmu_disable_event(event);
ca037701 1070
ab608344 1071 if (unlikely(event->attr.precise_ip))
ef21f683 1072 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1073}
1074
ca037701 1075static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1076{
15c7ad51 1077 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1078 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1079
1080 /*
1081 * Enable IRQ generation (0x8),
1082 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1083 * if requested:
1084 */
1085 bits = 0x8ULL;
1086 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1087 bits |= 0x2;
1088 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1089 bits |= 0x1;
1090
1091 /*
1092 * ANY bit is supported in v3 and up
1093 */
1094 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1095 bits |= 0x4;
1096
1097 bits <<= (idx * 4);
1098 mask = 0xfULL << (idx * 4);
1099
1100 rdmsrl(hwc->config_base, ctrl_val);
1101 ctrl_val &= ~mask;
1102 ctrl_val |= bits;
7645a24c 1103 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1104}
1105
aff3d91a 1106static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1107{
aff3d91a 1108 struct hw_perf_event *hwc = &event->hw;
144d31e6 1109 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1110
15c7ad51 1111 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1112 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1113 return;
1114
1115 intel_pmu_enable_bts(hwc->config);
1116 return;
1117 }
60ce0fbd
SE		 1118 /*
1119 * must enabled before any actual event
1120 * because any event may be combined with LBR
1121 */
1122 if (intel_pmu_needs_lbr_smpl(event))
1123 intel_pmu_lbr_enable(event);
f22f54f4 1124
144d31e6
GN		 1125 if (event->attr.exclude_host)
1126 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1127 if (event->attr.exclude_guest)
1128 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1129
f22f54f4 1130 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1131 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1132 return;
1133 }
1134
ab608344 1135 if (unlikely(event->attr.precise_ip))
ef21f683 1136 intel_pmu_pebs_enable(event);
ca037701 1137
31fa58af 1138 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1139}
1140
1141/*
1142 * Save and restart an expired event. Called by NMI contexts,
1143 * so it has to be careful about preempting normal event ops:
1144 */
de0428a7 1145int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1146{
cc2ad4ba
PZ		 1147 x86_perf_event_update(event);
1148 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1149}
1150
1151static void intel_pmu_reset(void)
1152{
0a3aee0d 1153 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1154 unsigned long flags;
1155 int idx;
1156
948b1bb8 1157 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1158 return;
1159
1160 local_irq_save(flags);
1161
c767a54b 1162 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1163
948b1bb8 1164 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1165 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1166 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1167 }
948b1bb8 1168 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1169 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1170
f22f54f4
PZ		 1171 if (ds)
1172 ds->bts_index = ds->bts_buffer_base;
1173
1174 local_irq_restore(flags);
1175}
1176
1177/*
1178 * This handler is triggered by the local APIC, so the APIC IRQ handling
1179 * rules apply:
1180 */
1181static int intel_pmu_handle_irq(struct pt_regs *regs)
1182{
1183 struct perf_sample_data data;
1184 struct cpu_hw_events *cpuc;
1185 int bit, loops;
2e556b5b 1186 u64 status;
b0b2072d 1187 int handled;
f22f54f4 1188
f22f54f4
PZ		 1189 cpuc = &__get_cpu_var(cpu_hw_events);
1190
2bce5dac 1191 /*
72db5596
AK		 1192 * No known reason to not always do late ACK,
1193 * but just in case do it opt-in.
2bce5dac 1194 */
72db5596
AK		 1195 if (!x86_pmu.late_ack)
1196 apic_write(APIC_LVTPC, APIC_DM_NMI);
3fb2b8dd 1197 intel_pmu_disable_all();
b0b2072d 1198 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1199 status = intel_pmu_get_status();
1200 if (!status) {
11164cd4 1201 intel_pmu_enable_all(0);
b0b2072d 1202 return handled;
f22f54f4
PZ		 1203 }
1204
1205 loops = 0;
1206again:
2e556b5b 1207 intel_pmu_ack_status(status);
f22f54f4 1208 if (++loops > 100) {
ae0def05
DH		 1209 static bool warned = false;
1210 if (!warned) {
1211 WARN(1, "perfevents: irq loop stuck!\n");
1212 perf_event_print_debug();
1213 warned = true;
1214 }
f22f54f4 1215 intel_pmu_reset();
3fb2b8dd 1216 goto done;
f22f54f4
PZ		 1217 }
1218
1219 inc_irq_stat(apic_perf_irqs);
ca037701 1220
caff2bef
PZ		 1221 intel_pmu_lbr_read();
1222
ca037701
PZ		 1223 /*
1224 * PEBS overflow sets bit 62 in the global status register
1225 */
de725dec
PZ		 1226 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1227 handled++;
ca037701 1228 x86_pmu.drain_pebs(regs);
de725dec 1229 }
ca037701 1230
984b3f57 1231 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1232 struct perf_event *event = cpuc->events[bit];
1233
de725dec
PZ		 1234 handled++;
1235
f22f54f4
PZ		 1236 if (!test_bit(bit, cpuc->active_mask))
1237 continue;
1238
1239 if (!intel_pmu_save_and_restart(event))
1240 continue;
1241
fd0d000b 1242 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1243
60ce0fbd
SE		 1244 if (has_branch_stack(event))
1245 data.br_stack = &cpuc->lbr_stack;
1246
a8b0ca17 1247 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1248 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1249 }
1250
f22f54f4
PZ		 1251 /*
1252 * Repeat if there is more work to be done:
1253 */
1254 status = intel_pmu_get_status();
1255 if (status)
1256 goto again;
1257
3fb2b8dd 1258done:
11164cd4 1259 intel_pmu_enable_all(0);
72db5596
AK		 1260 /*
1261 * Only unmask the NMI after the overflow counters
1262 * have been reset. This avoids spurious NMIs on
1263 * Haswell CPUs.
1264 */
1265 if (x86_pmu.late_ack)
1266 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 1267 return handled;
f22f54f4
PZ		 1268}
1269
f22f54f4 1270static struct event_constraint *
ca037701 1271intel_bts_constraints(struct perf_event *event)
f22f54f4 1272{
ca037701
PZ		 1273 struct hw_perf_event *hwc = &event->hw;
1274 unsigned int hw_event, bts_event;
f22f54f4 1275
18a073a3
PZ		 1276 if (event->attr.freq)
1277 return NULL;
1278
ca037701
PZ		 1279 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1280 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1281
ca037701 1282 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1283 return &bts_constraint;
ca037701 1284
f22f54f4
PZ		 1285 return NULL;
1286}
1287
5a425294 1288static int intel_alt_er(int idx)
b79e8941
PZ		 1289{
1290 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1291 return idx;
b79e8941 1292
5a425294
PZ		 1293 if (idx == EXTRA_REG_RSP_0)
1294 return EXTRA_REG_RSP_1;
1295
1296 if (idx == EXTRA_REG_RSP_1)
1297 return EXTRA_REG_RSP_0;
1298
1299 return idx;
1300}
1301
1302static void intel_fixup_er(struct perf_event *event, int idx)
1303{
1304 event->hw.extra_reg.idx = idx;
1305
1306 if (idx == EXTRA_REG_RSP_0) {
b79e8941 1307 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1308 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 1309 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1310 } else if (idx == EXTRA_REG_RSP_1) {
1311 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 1312 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 1313 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1314 }
b79e8941
PZ		 1315}
1316
efc9f05d
SE		 1317/*
1318 * manage allocation of shared extra msr for certain events
1319 *
1320 * sharing can be:
1321 * per-cpu: to be shared between the various events on a single PMU
1322 * per-core: per-cpu + shared by HT threads
1323 */
a7e3ed1e 1324static struct event_constraint *
efc9f05d 1325__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1326 struct perf_event *event,
1327 struct hw_perf_event_extra *reg)
a7e3ed1e 1328{
efc9f05d 1329 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1330 struct er_account *era;
cd8a38d3 1331 unsigned long flags;
5a425294 1332 int idx = reg->idx;
a7e3ed1e 1333
5a425294
PZ		 1334 /*
1335 * reg->alloc can be set due to existing state, so for fake cpuc we
1336 * need to ignore this, otherwise we might fail to allocate proper fake
1337 * state for this extra reg constraint. Also see the comment below.
1338 */
1339 if (reg->alloc && !cpuc->is_fake)
b36817e8 1340 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1341
b79e8941 1342again:
5a425294 1343 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1344 /*
1345 * we use spin_lock_irqsave() to avoid lockdep issues when
1346 * passing a fake cpuc
1347 */
1348 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1349
1350 if (!atomic_read(&era->ref) || era->config == reg->config) {
1351
5a425294
PZ		 1352 /*
1353 * If its a fake cpuc -- as per validate_{group,event}() we
1354 * shouldn't touch event state and we can avoid doing so
1355 * since both will only call get_event_constraints() once
1356 * on each event, this avoids the need for reg->alloc.
1357 *
1358 * Not doing the ER fixup will only result in era->reg being
1359 * wrong, but since we won't actually try and program hardware
1360 * this isn't a problem either.
1361 */
1362 if (!cpuc->is_fake) {
1363 if (idx != reg->idx)
1364 intel_fixup_er(event, idx);
1365
1366 /*
1367 * x86_schedule_events() can call get_event_constraints()
1368 * multiple times on events in the case of incremental
1369 * scheduling(). reg->alloc ensures we only do the ER
1370 * allocation once.
1371 */
1372 reg->alloc = 1;
1373 }
1374
efc9f05d
SE		 1375 /* lock in msr value */
1376 era->config = reg->config;
1377 era->reg = reg->reg;
1378
1379 /* one more user */
1380 atomic_inc(&era->ref);
1381
a7e3ed1e 1382 /*
b36817e8
SE		 1383 * need to call x86_get_event_constraint()
1384 * to check if associated event has constraints
a7e3ed1e 1385 */
b36817e8 1386 c = NULL;
5a425294
PZ		 1387 } else {
1388 idx = intel_alt_er(idx);
1389 if (idx != reg->idx) {
1390 raw_spin_unlock_irqrestore(&era->lock, flags);
1391 goto again;
1392 }
a7e3ed1e 1393 }
cd8a38d3 1394 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1395
efc9f05d
SE		 1396 return c;
1397}
1398
1399static void
1400__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1401 struct hw_perf_event_extra *reg)
1402{
1403 struct er_account *era;
1404
1405 /*
5a425294
PZ		 1406 * Only put constraint if extra reg was actually allocated. Also takes
1407 * care of event which do not use an extra shared reg.
1408 *
1409 * Also, if this is a fake cpuc we shouldn't touch any event state
1410 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1411 * either since it'll be thrown out.
efc9f05d 1412 */
5a425294 1413 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1414 return;
1415
1416 era = &cpuc->shared_regs->regs[reg->idx];
1417
1418 /* one fewer user */
1419 atomic_dec(&era->ref);
1420
1421 /* allocate again next time */
1422 reg->alloc = 0;
1423}
1424
1425static struct event_constraint *
1426intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1427 struct perf_event *event)
1428{
b36817e8
SE		 1429 struct event_constraint *c = NULL, *d;
1430 struct hw_perf_event_extra *xreg, *breg;
1431
1432 xreg = &event->hw.extra_reg;
1433 if (xreg->idx != EXTRA_REG_NONE) {
1434 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1435 if (c == &emptyconstraint)
1436 return c;
1437 }
1438 breg = &event->hw.branch_reg;
1439 if (breg->idx != EXTRA_REG_NONE) {
1440 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1441 if (d == &emptyconstraint) {
1442 __intel_shared_reg_put_constraints(cpuc, xreg);
1443 c = d;
1444 }
1445 }
efc9f05d 1446 return c;
a7e3ed1e
AK		 1447}
1448
de0428a7
KW		 1449struct event_constraint *
1450x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1451{
1452 struct event_constraint *c;
1453
1454 if (x86_pmu.event_constraints) {
1455 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 1456 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 1457 event->hw.flags |= c->flags;
de0428a7 1458 return c;
9fac2cf3 1459 }
de0428a7
KW		 1460 }
1461 }
1462
1463 return &unconstrained;
1464}
1465
f22f54f4
PZ		 1466static struct event_constraint *
1467intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1468{
1469 struct event_constraint *c;
1470
ca037701
PZ		 1471 c = intel_bts_constraints(event);
1472 if (c)
1473 return c;
1474
1475 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1476 if (c)
1477 return c;
1478
efc9f05d 1479 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1480 if (c)
1481 return c;
1482
f22f54f4
PZ		 1483 return x86_get_event_constraints(cpuc, event);
1484}
1485
efc9f05d
SE		 1486static void
1487intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1488 struct perf_event *event)
1489{
efc9f05d 1490 struct hw_perf_event_extra *reg;
a7e3ed1e 1491
efc9f05d
SE		 1492 reg = &event->hw.extra_reg;
1493 if (reg->idx != EXTRA_REG_NONE)
1494 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1495
1496 reg = &event->hw.branch_reg;
1497 if (reg->idx != EXTRA_REG_NONE)
1498 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1499}
a7e3ed1e 1500
efc9f05d
SE		 1501static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1502 struct perf_event *event)
1503{
1504 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1505}
1506
0780c927 1507static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1508{
0780c927 1509 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1510 /*
1511 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1512 * (0x003c) so that we can use it with PEBS.
1513 *
1514 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1515 * PEBS capable. However we can use INST_RETIRED.ANY_P
1516 * (0x00c0), which is a PEBS capable event, to get the same
1517 * count.
1518 *
1519 * INST_RETIRED.ANY_P counts the number of cycles that retires
1520 * CNTMASK instructions. By setting CNTMASK to a value (16)
1521 * larger than the maximum number of instructions that can be
1522 * retired per cycle (4) and then inverting the condition, we
1523 * count all cycles that retire 16 or less instructions, which
1524 * is every cycle.
1525 *
1526 * Thereby we gain a PEBS capable cycle counter.
1527 */
f9b4eeb8
PZ		 1528 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1529
0780c927
PZ		 1530 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1531 event->hw.config = alt_config;
1532 }
1533}
1534
1535static void intel_pebs_aliases_snb(struct perf_event *event)
1536{
1537 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1538 /*
1539 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1540 * (0x003c) so that we can use it with PEBS.
1541 *
1542 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1543 * PEBS capable. However we can use UOPS_RETIRED.ALL
1544 * (0x01c2), which is a PEBS capable event, to get the same
1545 * count.
1546 *
1547 * UOPS_RETIRED.ALL counts the number of cycles that retires
1548 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1549 * larger than the maximum number of micro-ops that can be
1550 * retired per cycle (4) and then inverting the condition, we
1551 * count all cycles that retire 16 or less micro-ops, which
1552 * is every cycle.
1553 *
1554 * Thereby we gain a PEBS capable cycle counter.
1555 */
1556 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1557
1558 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1559 event->hw.config = alt_config;
1560 }
0780c927
PZ		 1561}
1562
1563static int intel_pmu_hw_config(struct perf_event *event)
1564{
1565 int ret = x86_pmu_hw_config(event);
1566
1567 if (ret)
1568 return ret;
1569
1570 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1571 x86_pmu.pebs_aliases(event);
7639dae0 1572
60ce0fbd
SE		 1573 if (intel_pmu_needs_lbr_smpl(event)) {
1574 ret = intel_pmu_setup_lbr_filter(event);
1575 if (ret)
1576 return ret;
1577 }
1578
b4cdc5c2
PZ		 1579 if (event->attr.type != PERF_TYPE_RAW)
1580 return 0;
1581
1582 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1583 return 0;
1584
1585 if (x86_pmu.version < 3)
1586 return -EINVAL;
1587
1588 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1589 return -EACCES;
1590
1591 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1592
1593 return 0;
1594}
1595
144d31e6
GN		 1596struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1597{
1598 if (x86_pmu.guest_get_msrs)
1599 return x86_pmu.guest_get_msrs(nr);
1600 *nr = 0;
1601 return NULL;
1602}
1603EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1604
1605static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1606{
1607 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1608 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1609
1610 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1611 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1612 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1613 /*
1614 * If PMU counter has PEBS enabled it is not enough to disable counter
1615 * on a guest entry since PEBS memory write can overshoot guest entry
1616 * and corrupt guest memory. Disabling PEBS solves the problem.
1617 */
1618 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1619 arr[1].host = cpuc->pebs_enabled;
1620 arr[1].guest = 0;
144d31e6 1621
26a4f3c0 1622 *nr = 2;
144d31e6
GN		 1623 return arr;
1624}
1625
1626static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1627{
1628 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1629 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1630 int idx;
1631
1632 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1633 struct perf_event *event = cpuc->events[idx];
1634
1635 arr[idx].msr = x86_pmu_config_addr(idx);
1636 arr[idx].host = arr[idx].guest = 0;
1637
1638 if (!test_bit(idx, cpuc->active_mask))
1639 continue;
1640
1641 arr[idx].host = arr[idx].guest =
1642 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1643
1644 if (event->attr.exclude_host)
1645 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1646 else if (event->attr.exclude_guest)
1647 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1648 }
1649
1650 *nr = x86_pmu.num_counters;
1651 return arr;
1652}
1653
1654static void core_pmu_enable_event(struct perf_event *event)
1655{
1656 if (!event->attr.exclude_host)
1657 x86_pmu_enable_event(event);
1658}
1659
1660static void core_pmu_enable_all(int added)
1661{
1662 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1663 int idx;
1664
1665 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1666 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1667
1668 if (!test_bit(idx, cpuc->active_mask) ||
1669 cpuc->events[idx]->attr.exclude_host)
1670 continue;
1671
1672 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1673 }
1674}
1675
3a632cb2
AK		 1676static int hsw_hw_config(struct perf_event *event)
1677{
1678 int ret = intel_pmu_hw_config(event);
1679
1680 if (ret)
1681 return ret;
1682 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1683 return 0;
1684 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1685
1686 /*
1687 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1688 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1689 * this combination.
1690 */
1691 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1692 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1693 event->attr.precise_ip > 0))
1694 return -EOPNOTSUPP;
1695
1696 return 0;
1697}
1698
1699static struct event_constraint counter2_constraint =
1700 EVENT_CONSTRAINT(0, 0x4, 0);
1701
1702static struct event_constraint *
1703hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1704{
1705 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1706
1707 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1708 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1709 if (c->idxmsk64 & (1U << 2))
1710 return &counter2_constraint;
1711 return &emptyconstraint;
1712 }
1713
1714 return c;
1715}
1716
641cc938
JO		 1717PMU_FORMAT_ATTR(event, "config:0-7" );
1718PMU_FORMAT_ATTR(umask, "config:8-15" );
1719PMU_FORMAT_ATTR(edge, "config:18" );
1720PMU_FORMAT_ATTR(pc, "config:19" );
1721PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1722PMU_FORMAT_ATTR(inv, "config:23" );
1723PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 1724PMU_FORMAT_ATTR(in_tx, "config:32");
1725PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 1726
1727static struct attribute *intel_arch_formats_attr[] = {
1728 &format_attr_event.attr,
1729 &format_attr_umask.attr,
1730 &format_attr_edge.attr,
1731 &format_attr_pc.attr,
1732 &format_attr_inv.attr,
1733 &format_attr_cmask.attr,
1734 NULL,
1735};
1736
0bf79d44
JO		 1737ssize_t intel_event_sysfs_show(char *page, u64 config)
1738{
1739 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1740
1741 return x86_event_sysfs_show(page, config, event);
1742}
1743
caaa8be3 1744static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1745 .name = "core",
1746 .handle_irq = x86_pmu_handle_irq,
1747 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1748 .enable_all = core_pmu_enable_all,
1749 .enable = core_pmu_enable_event,
f22f54f4 1750 .disable = x86_pmu_disable_event,
b4cdc5c2 1751 .hw_config = x86_pmu_hw_config,
a072738e 1752 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1753 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1754 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1755 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1756 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1757 .apic = 1,
1758 /*
1759 * Intel PMCs cannot be accessed sanely above 32 bit width,
1760 * so we install an artificial 1<<31 period regardless of
1761 * the generic event period:
1762 */
1763 .max_period = (1ULL << 31) - 1,
1764 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1765 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1766 .event_constraints = intel_core_event_constraints,
144d31e6 1767 .guest_get_msrs = core_guest_get_msrs,
641cc938 1768 .format_attrs = intel_arch_formats_attr,
0bf79d44 1769 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 1770};
1771
de0428a7 1772struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1773{
1774 struct intel_shared_regs *regs;
1775 int i;
1776
1777 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1778 GFP_KERNEL, cpu_to_node(cpu));
1779 if (regs) {
1780 /*
1781 * initialize the locks to keep lockdep happy
1782 */
1783 for (i = 0; i < EXTRA_REG_MAX; i++)
1784 raw_spin_lock_init(&regs->regs[i].lock);
1785
1786 regs->core_id = -1;
1787 }
1788 return regs;
1789}
1790
a7e3ed1e
AK		 1791static int intel_pmu_cpu_prepare(int cpu)
1792{
1793 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1794
b36817e8 1795 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1796 return NOTIFY_OK;
1797
efc9f05d
SE		 1798 cpuc->shared_regs = allocate_shared_regs(cpu);
1799 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1800 return NOTIFY_BAD;
1801
a7e3ed1e
AK		 1802 return NOTIFY_OK;
1803}
1804
74846d35
PZ		 1805static void intel_pmu_cpu_starting(int cpu)
1806{
a7e3ed1e
AK		 1807 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1808 int core_id = topology_core_id(cpu);
1809 int i;
1810
69092624
LM		 1811 init_debug_store_on_cpu(cpu);
1812 /*
1813 * Deal with CPUs that don't clear their LBRs on power-up.
1814 */
1815 intel_pmu_lbr_reset();
1816
b36817e8
SE		 1817 cpuc->lbr_sel = NULL;
1818
1819 if (!cpuc->shared_regs)
69092624
LM		 1820 return;
1821
b36817e8
SE		 1822 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1823 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1824 struct intel_shared_regs *pc;
a7e3ed1e 1825
b36817e8
SE		 1826 pc = per_cpu(cpu_hw_events, i).shared_regs;
1827 if (pc && pc->core_id == core_id) {
1828 cpuc->kfree_on_online = cpuc->shared_regs;
1829 cpuc->shared_regs = pc;
1830 break;
1831 }
a7e3ed1e 1832 }
b36817e8
SE		 1833 cpuc->shared_regs->core_id = core_id;
1834 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 1835 }
1836
b36817e8
SE		 1837 if (x86_pmu.lbr_sel_map)
1838 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 1839}
1840
1841static void intel_pmu_cpu_dying(int cpu)
1842{
a7e3ed1e 1843 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1844 struct intel_shared_regs *pc;
a7e3ed1e 1845
efc9f05d 1846 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1847 if (pc) {
1848 if (pc->core_id == -1 || --pc->refcnt == 0)
1849 kfree(pc);
efc9f05d 1850 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1851 }
1852
74846d35
PZ		 1853 fini_debug_store_on_cpu(cpu);
1854}
1855
d010b332
SE		 1856static void intel_pmu_flush_branch_stack(void)
1857{
1858 /*
1859 * Intel LBR does not tag entries with the
1860 * PID of the current task, then we need to
1861 * flush it on ctxsw
1862 * For now, we simply reset it
1863 */
1864 if (x86_pmu.lbr_nr)
1865 intel_pmu_lbr_reset();
1866}
1867
641cc938
JO		 1868PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1869
a63fcab4
SE		 1870PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1871
641cc938
JO		 1872static struct attribute *intel_arch3_formats_attr[] = {
1873 &format_attr_event.attr,
1874 &format_attr_umask.attr,
1875 &format_attr_edge.attr,
1876 &format_attr_pc.attr,
1877 &format_attr_any.attr,
1878 &format_attr_inv.attr,
1879 &format_attr_cmask.attr,
3a632cb2
AK		 1880 &format_attr_in_tx.attr,
1881 &format_attr_in_tx_cp.attr,
641cc938
JO		 1882
1883 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 1884 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 1885 NULL,
1886};
1887
caaa8be3 1888static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1889 .name = "Intel",
1890 .handle_irq = intel_pmu_handle_irq,
1891 .disable_all = intel_pmu_disable_all,
1892 .enable_all = intel_pmu_enable_all,
1893 .enable = intel_pmu_enable_event,
1894 .disable = intel_pmu_disable_event,
b4cdc5c2 1895 .hw_config = intel_pmu_hw_config,
a072738e 1896 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1897 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1898 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1899 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1900 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1901 .apic = 1,
1902 /*
1903 * Intel PMCs cannot be accessed sanely above 32 bit width,
1904 * so we install an artificial 1<<31 period regardless of
1905 * the generic event period:
1906 */
1907 .max_period = (1ULL << 31) - 1,
3f6da390 1908 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1909 .put_event_constraints = intel_put_event_constraints,
0780c927 1910 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 1911
641cc938 1912 .format_attrs = intel_arch3_formats_attr,
0bf79d44 1913 .events_sysfs_show = intel_event_sysfs_show,
641cc938 1914
a7e3ed1e 1915 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1916 .cpu_starting = intel_pmu_cpu_starting,
1917 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1918 .guest_get_msrs = intel_guest_get_msrs,
d010b332 1919 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 1920};
1921
c1d6f42f 1922static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1923{
1924 /*
1925 * PEBS is unreliable due to:
1926 *
1927 * AJ67 - PEBS may experience CPL leaks
1928 * AJ68 - PEBS PMI may be delayed by one event
1929 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1930 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1931 *
1932 * AJ67 could be worked around by restricting the OS/USR flags.
1933 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1934 *
1935 * AJ106 could possibly be worked around by not allowing LBR
1936 * usage from PEBS, including the fixup.
1937 * AJ68 could possibly be worked around by always programming
ec75a716 1938 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1939 *
1940 * But taken together it might just make sense to not enable PEBS on
1941 * these chips.
1942 */
c767a54b 1943 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 1944 x86_pmu.pebs = 0;
1945 x86_pmu.pebs_constraints = NULL;
1946}
1947
c93dc84c
PZ		 1948static int intel_snb_pebs_broken(int cpu)
1949{
1950 u32 rev = UINT_MAX; /* default to broken for unknown models */
1951
1952 switch (cpu_data(cpu).x86_model) {
1953 case 42: /* SNB */
1954 rev = 0x28;
1955 break;
1956
1957 case 45: /* SNB-EP */
1958 switch (cpu_data(cpu).x86_mask) {
1959 case 6: rev = 0x618; break;
1960 case 7: rev = 0x70c; break;
1961 }
1962 }
1963
1964 return (cpu_data(cpu).microcode < rev);
1965}
1966
1967static void intel_snb_check_microcode(void)
1968{
1969 int pebs_broken = 0;
1970 int cpu;
1971
1972 get_online_cpus();
1973 for_each_online_cpu(cpu) {
1974 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1975 break;
1976 }
1977 put_online_cpus();
1978
1979 if (pebs_broken == x86_pmu.pebs_broken)
1980 return;
1981
1982 /*
1983 * Serialized by the microcode lock..
1984 */
1985 if (x86_pmu.pebs_broken) {
1986 pr_info("PEBS enabled due to microcode update\n");
1987 x86_pmu.pebs_broken = 0;
1988 } else {
1989 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1990 x86_pmu.pebs_broken = 1;
1991 }
1992}
1993
c1d6f42f 1994static __init void intel_sandybridge_quirk(void)
6a600a8b 1995{
c93dc84c
PZ		 1996 x86_pmu.check_microcode = intel_snb_check_microcode;
1997 intel_snb_check_microcode();
6a600a8b
PZ		 1998}
1999
c1d6f42f
PZ		 2000static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
2001 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
2002 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
2003 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
2004 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
2005 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2006 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2007 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2008};
2009
c1d6f42f
PZ		 2010static __init void intel_arch_events_quirk(void)
2011{
2012 int bit;
2013
2014 /* disable event that reported as not presend by cpuid */
2015 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2016 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2017 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2018 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2019 }
2020}
2021
2022static __init void intel_nehalem_quirk(void)
2023{
2024 union cpuid10_ebx ebx;
2025
2026 ebx.full = x86_pmu.events_maskl;
2027 if (ebx.split.no_branch_misses_retired) {
2028 /*
2029 * Erratum AAJ80 detected, we work it around by using
2030 * the BR_MISP_EXEC.ANY event. This will over-count
2031 * branch-misses, but it's still much better than the
2032 * architectural event which is often completely bogus:
2033 */
2034 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2035 ebx.split.no_branch_misses_retired = 0;
2036 x86_pmu.events_maskl = ebx.full;
c767a54b 2037 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2038 }
2039}
2040
f9134f36
AK		 2041EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
2042EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
2043
2044static struct attribute *hsw_events_attrs[] = {
2045 EVENT_PTR(mem_ld_hsw),
2046 EVENT_PTR(mem_st_hsw),
2047 NULL
2048};
2049
de0428a7 2050__init int intel_pmu_init(void)
f22f54f4
PZ		 2051{
2052 union cpuid10_edx edx;
2053 union cpuid10_eax eax;
ffb871bc 2054 union cpuid10_ebx ebx;
a1eac7ac 2055 struct event_constraint *c;
f22f54f4 2056 unsigned int unused;
f22f54f4
PZ		 2057 int version;
2058
2059 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2060 switch (boot_cpu_data.x86) {
2061 case 0x6:
2062 return p6_pmu_init();
e717bf4e
VW		 2063 case 0xb:
2064 return knc_pmu_init();
a072738e
CG		 2065 case 0xf:
2066 return p4_pmu_init();
2067 }
f22f54f4 2068 return -ENODEV;
f22f54f4
PZ		 2069 }
2070
2071 /*
2072 * Check whether the Architectural PerfMon supports
2073 * Branch Misses Retired hw_event or not.
2074 */
ffb871bc
GN		 2075 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2076 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2077 return -ENODEV;
2078
2079 version = eax.split.version_id;
2080 if (version < 2)
2081 x86_pmu = core_pmu;
2082 else
2083 x86_pmu = intel_pmu;
2084
2085 x86_pmu.version = version;
948b1bb8
RR		 2086 x86_pmu.num_counters = eax.split.num_counters;
2087 x86_pmu.cntval_bits = eax.split.bit_width;
2088 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2089
c1d6f42f
PZ		 2090 x86_pmu.events_maskl = ebx.full;
2091 x86_pmu.events_mask_len = eax.split.mask_length;
2092
70ab7003
AK		 2093 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2094
f22f54f4
PZ		 2095 /*
2096 * Quirk: v2 perfmon does not report fixed-purpose events, so
2097 * assume at least 3 events:
2098 */
2099 if (version > 1)
948b1bb8 2100 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2101
8db909a7
PZ		 2102 /*
2103 * v2 and above have a perf capabilities MSR
2104 */
2105 if (version > 1) {
2106 u64 capabilities;
2107
2108 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2109 x86_pmu.intel_cap.capabilities = capabilities;
2110 }
2111
ca037701
PZ		 2112 intel_ds_init();
2113
c1d6f42f
PZ		 2114 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2115
f22f54f4
PZ		 2116 /*
2117 * Install the hw-cache-events table:
2118 */
2119 switch (boot_cpu_data.x86_model) {
2120 case 14: /* 65 nm core solo/duo, "Yonah" */
2121 pr_cont("Core events, ");
2122 break;
2123
2124 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 2125 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 2126 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2127 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2128 case 29: /* six-core 45 nm xeon "Dunnington" */
2129 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2130 sizeof(hw_cache_event_ids));
2131
caff2bef
PZ		 2132 intel_pmu_lbr_init_core();
2133
f22f54f4 2134 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2135 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2136 pr_cont("Core2 events, ");
2137 break;
2138
2139 case 26: /* 45 nm nehalem, "Bloomfield" */
2140 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 2141 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 2142 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2143 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2144 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2145 sizeof(hw_cache_extra_regs));
f22f54f4 2146
caff2bef
PZ		 2147 intel_pmu_lbr_init_nhm();
2148
f22f54f4 2149 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2150 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2151 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2152 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2153
f20093ee
SE		 2154 x86_pmu.cpu_events = nhm_events_attrs;
2155
91fc4cc0 2156 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2157 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2158 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2159 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2160 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2161 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2162
c1d6f42f 2163 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2164
11164cd4 2165 pr_cont("Nehalem events, ");
f22f54f4 2166 break;
caff2bef 2167
b622d644 2168 case 28: /* Atom */
0927b482
SL		 2169 case 38: /* Lincroft */
2170 case 39: /* Penwell */
2171 case 53: /* Cloverview */
2172 case 54: /* Cedarview */
f22f54f4
PZ		 2173 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2174 sizeof(hw_cache_event_ids));
2175
caff2bef
PZ		 2176 intel_pmu_lbr_init_atom();
2177
f22f54f4 2178 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2179 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2180 pr_cont("Atom events, ");
2181 break;
2182
2183 case 37: /* 32 nm nehalem, "Clarkdale" */
2184 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2185 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2186 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2187 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2188 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2189 sizeof(hw_cache_extra_regs));
f22f54f4 2190
caff2bef
PZ		 2191 intel_pmu_lbr_init_nhm();
2192
f22f54f4 2193 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2194 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2195 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2196 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2197 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2198
f20093ee
SE		 2199 x86_pmu.cpu_events = nhm_events_attrs;
2200
30112039 2201 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2202 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2203 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2204 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2205 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2206 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2207
f22f54f4
PZ		 2208 pr_cont("Westmere events, ");
2209 break;
b622d644 2210
b06b3d49 2211 case 42: /* SandyBridge */
a34668f6 2212 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2213 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2214 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2215 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2216 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2217 sizeof(hw_cache_extra_regs));
b06b3d49 2218
c5cc2cd9 2219 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2220
2221 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2222 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2223 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2224 if (boot_cpu_data.x86_model == 45)
2225 x86_pmu.extra_regs = intel_snbep_extra_regs;
2226 else
2227 x86_pmu.extra_regs = intel_snb_extra_regs;
ee89cbc2 2228 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2229 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2230 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2231
f20093ee
SE		 2232 x86_pmu.cpu_events = snb_events_attrs;
2233
e04d1b23 2234 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2235 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2236 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2237 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2238 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2239 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2240
b06b3d49
LM		 2241 pr_cont("SandyBridge events, ");
2242 break;
20a36e39 2243 case 58: /* IvyBridge */
923d8697 2244 case 62: /* IvyBridge EP */
20a36e39
SE		 2245 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2246 sizeof(hw_cache_event_ids));
2247 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2248 sizeof(hw_cache_extra_regs));
2249
2250 intel_pmu_lbr_init_snb();
2251
69943182 2252 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2253 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2254 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2255 if (boot_cpu_data.x86_model == 62)
2256 x86_pmu.extra_regs = intel_snbep_extra_regs;
2257 else
2258 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39
SE		 2259 /* all extra regs are per-cpu when HT is on */
2260 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2261 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2262
f20093ee
SE		 2263 x86_pmu.cpu_events = snb_events_attrs;
2264
20a36e39
SE		 2265 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2266 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2267 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2268
2269 pr_cont("IvyBridge events, ");
2270 break;
2271
b06b3d49 2272
3a632cb2
AK		 2273 case 60: /* Haswell Client */
2274 case 70:
2275 case 71:
2276 case 63:
0499bd86 2277 case 69:
72db5596 2278 x86_pmu.late_ack = true;
3a632cb2
AK		 2279 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2280 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2281
2282 intel_pmu_lbr_init_snb();
2283
2284 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 2285 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
3a632cb2 2286 x86_pmu.extra_regs = intel_snb_extra_regs;
3044318f 2287 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
3a632cb2
AK		 2288 /* all extra regs are per-cpu when HT is on */
2289 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2290 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2291
2292 x86_pmu.hw_config = hsw_hw_config;
2293 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 2294 x86_pmu.cpu_events = hsw_events_attrs;
3a632cb2
AK		 2295 pr_cont("Haswell events, ");
2296 break;
2297
f22f54f4 2298 default:
0af3ac1f
AK		 2299 switch (x86_pmu.version) {
2300 case 1:
2301 x86_pmu.event_constraints = intel_v1_event_constraints;
2302 pr_cont("generic architected perfmon v1, ");
2303 break;
2304 default:
2305 /*
2306 * default constraints for v2 and up
2307 */
2308 x86_pmu.event_constraints = intel_gen_event_constraints;
2309 pr_cont("generic architected perfmon, ");
2310 break;
2311 }
f22f54f4 2312 }
ffb871bc 2313
a1eac7ac
RR		 2314 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2315 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2316 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2317 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2318 }
2319 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2320
2321 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2322 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2323 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2324 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2325 }
2326
2327 x86_pmu.intel_ctrl |=
2328 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2329
2330 if (x86_pmu.event_constraints) {
2331 /*
2332 * event on fixed counter2 (REF_CYCLES) only works on this
2333 * counter, so do not extend mask to generic counters
2334 */
2335 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 2336 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 2337 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2338 continue;
2339 }
2340
2341 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2342 c->weight += x86_pmu.num_counters;
2343 }
2344 }
2345
069e0c3c
AK		 2346 /* Support full width counters using alternative MSR range */
2347 if (x86_pmu.intel_cap.full_width_write) {
2348 x86_pmu.max_period = x86_pmu.cntval_mask;
2349 x86_pmu.perfctr = MSR_IA32_PMC0;
2350 pr_cont("full-width counters, ");
2351 }
2352
f22f54f4
PZ		 2353 return 0;
2354}
Linux 6.x block layer and io_uring tree(s)