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f22f54f4 PZ |
1 | #ifdef CONFIG_CPU_SUP_INTEL |
2 | ||
3 | /* | |
b622d644 | 4 | * Intel PerfMon, used on Core and later. |
f22f54f4 PZ |
5 | */ |
6 | static const u64 intel_perfmon_event_map[] = | |
7 | { | |
8 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, | |
9 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
10 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
11 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
12 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
13 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
14 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
15 | }; | |
16 | ||
17 | static struct event_constraint intel_core_event_constraints[] = | |
18 | { | |
19 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
20 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
21 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
22 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
23 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
24 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ | |
25 | EVENT_CONSTRAINT_END | |
26 | }; | |
27 | ||
28 | static struct event_constraint intel_core2_event_constraints[] = | |
29 | { | |
b622d644 PZ |
30 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
31 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
32 | /* | |
33 | * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event | |
34 | * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed | |
35 | * ratio between these counters. | |
36 | */ | |
37 | /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */ | |
f22f54f4 PZ |
38 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
39 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
40 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
41 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
42 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
43 | INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ | |
44 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
45 | INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ | |
b622d644 | 46 | INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ |
f22f54f4 PZ |
47 | INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ |
48 | EVENT_CONSTRAINT_END | |
49 | }; | |
50 | ||
51 | static struct event_constraint intel_nehalem_event_constraints[] = | |
52 | { | |
b622d644 PZ |
53 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
54 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
55 | /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */ | |
f22f54f4 PZ |
56 | INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ |
57 | INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ | |
58 | INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ | |
59 | INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ | |
60 | INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ | |
61 | INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ | |
62 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ | |
63 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
64 | EVENT_CONSTRAINT_END | |
65 | }; | |
66 | ||
67 | static struct event_constraint intel_westmere_event_constraints[] = | |
68 | { | |
b622d644 PZ |
69 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
70 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
71 | /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */ | |
f22f54f4 PZ |
72 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
73 | INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ | |
74 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
75 | EVENT_CONSTRAINT_END | |
76 | }; | |
77 | ||
78 | static struct event_constraint intel_gen_event_constraints[] = | |
79 | { | |
b622d644 PZ |
80 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
81 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
82 | /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */ | |
f22f54f4 PZ |
83 | EVENT_CONSTRAINT_END |
84 | }; | |
85 | ||
86 | static u64 intel_pmu_event_map(int hw_event) | |
87 | { | |
88 | return intel_perfmon_event_map[hw_event]; | |
89 | } | |
90 | ||
91 | static __initconst u64 westmere_hw_cache_event_ids | |
92 | [PERF_COUNT_HW_CACHE_MAX] | |
93 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
94 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
95 | { | |
96 | [ C(L1D) ] = { | |
97 | [ C(OP_READ) ] = { | |
98 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
99 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
100 | }, | |
101 | [ C(OP_WRITE) ] = { | |
102 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
103 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
104 | }, | |
105 | [ C(OP_PREFETCH) ] = { | |
106 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
107 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
108 | }, | |
109 | }, | |
110 | [ C(L1I ) ] = { | |
111 | [ C(OP_READ) ] = { | |
112 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
113 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
114 | }, | |
115 | [ C(OP_WRITE) ] = { | |
116 | [ C(RESULT_ACCESS) ] = -1, | |
117 | [ C(RESULT_MISS) ] = -1, | |
118 | }, | |
119 | [ C(OP_PREFETCH) ] = { | |
120 | [ C(RESULT_ACCESS) ] = 0x0, | |
121 | [ C(RESULT_MISS) ] = 0x0, | |
122 | }, | |
123 | }, | |
124 | [ C(LL ) ] = { | |
125 | [ C(OP_READ) ] = { | |
126 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ | |
127 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ | |
128 | }, | |
129 | [ C(OP_WRITE) ] = { | |
130 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ | |
131 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ | |
132 | }, | |
133 | [ C(OP_PREFETCH) ] = { | |
134 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ | |
135 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ | |
136 | }, | |
137 | }, | |
138 | [ C(DTLB) ] = { | |
139 | [ C(OP_READ) ] = { | |
140 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
141 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
142 | }, | |
143 | [ C(OP_WRITE) ] = { | |
144 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
145 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
146 | }, | |
147 | [ C(OP_PREFETCH) ] = { | |
148 | [ C(RESULT_ACCESS) ] = 0x0, | |
149 | [ C(RESULT_MISS) ] = 0x0, | |
150 | }, | |
151 | }, | |
152 | [ C(ITLB) ] = { | |
153 | [ C(OP_READ) ] = { | |
154 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
155 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ | |
156 | }, | |
157 | [ C(OP_WRITE) ] = { | |
158 | [ C(RESULT_ACCESS) ] = -1, | |
159 | [ C(RESULT_MISS) ] = -1, | |
160 | }, | |
161 | [ C(OP_PREFETCH) ] = { | |
162 | [ C(RESULT_ACCESS) ] = -1, | |
163 | [ C(RESULT_MISS) ] = -1, | |
164 | }, | |
165 | }, | |
166 | [ C(BPU ) ] = { | |
167 | [ C(OP_READ) ] = { | |
168 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
169 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
170 | }, | |
171 | [ C(OP_WRITE) ] = { | |
172 | [ C(RESULT_ACCESS) ] = -1, | |
173 | [ C(RESULT_MISS) ] = -1, | |
174 | }, | |
175 | [ C(OP_PREFETCH) ] = { | |
176 | [ C(RESULT_ACCESS) ] = -1, | |
177 | [ C(RESULT_MISS) ] = -1, | |
178 | }, | |
179 | }, | |
180 | }; | |
181 | ||
182 | static __initconst u64 nehalem_hw_cache_event_ids | |
183 | [PERF_COUNT_HW_CACHE_MAX] | |
184 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
185 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
186 | { | |
187 | [ C(L1D) ] = { | |
188 | [ C(OP_READ) ] = { | |
189 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
190 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
191 | }, | |
192 | [ C(OP_WRITE) ] = { | |
193 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
194 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
195 | }, | |
196 | [ C(OP_PREFETCH) ] = { | |
197 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
198 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
199 | }, | |
200 | }, | |
201 | [ C(L1I ) ] = { | |
202 | [ C(OP_READ) ] = { | |
203 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
204 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
205 | }, | |
206 | [ C(OP_WRITE) ] = { | |
207 | [ C(RESULT_ACCESS) ] = -1, | |
208 | [ C(RESULT_MISS) ] = -1, | |
209 | }, | |
210 | [ C(OP_PREFETCH) ] = { | |
211 | [ C(RESULT_ACCESS) ] = 0x0, | |
212 | [ C(RESULT_MISS) ] = 0x0, | |
213 | }, | |
214 | }, | |
215 | [ C(LL ) ] = { | |
216 | [ C(OP_READ) ] = { | |
217 | [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS */ | |
218 | [ C(RESULT_MISS) ] = 0x0224, /* L2_RQSTS.LD_MISS */ | |
219 | }, | |
220 | [ C(OP_WRITE) ] = { | |
221 | [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS */ | |
222 | [ C(RESULT_MISS) ] = 0x0824, /* L2_RQSTS.RFO_MISS */ | |
223 | }, | |
224 | [ C(OP_PREFETCH) ] = { | |
225 | [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference */ | |
226 | [ C(RESULT_MISS) ] = 0x412e, /* LLC Misses */ | |
227 | }, | |
228 | }, | |
229 | [ C(DTLB) ] = { | |
230 | [ C(OP_READ) ] = { | |
231 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
232 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
233 | }, | |
234 | [ C(OP_WRITE) ] = { | |
235 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
236 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
237 | }, | |
238 | [ C(OP_PREFETCH) ] = { | |
239 | [ C(RESULT_ACCESS) ] = 0x0, | |
240 | [ C(RESULT_MISS) ] = 0x0, | |
241 | }, | |
242 | }, | |
243 | [ C(ITLB) ] = { | |
244 | [ C(OP_READ) ] = { | |
245 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
246 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ | |
247 | }, | |
248 | [ C(OP_WRITE) ] = { | |
249 | [ C(RESULT_ACCESS) ] = -1, | |
250 | [ C(RESULT_MISS) ] = -1, | |
251 | }, | |
252 | [ C(OP_PREFETCH) ] = { | |
253 | [ C(RESULT_ACCESS) ] = -1, | |
254 | [ C(RESULT_MISS) ] = -1, | |
255 | }, | |
256 | }, | |
257 | [ C(BPU ) ] = { | |
258 | [ C(OP_READ) ] = { | |
259 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
260 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
261 | }, | |
262 | [ C(OP_WRITE) ] = { | |
263 | [ C(RESULT_ACCESS) ] = -1, | |
264 | [ C(RESULT_MISS) ] = -1, | |
265 | }, | |
266 | [ C(OP_PREFETCH) ] = { | |
267 | [ C(RESULT_ACCESS) ] = -1, | |
268 | [ C(RESULT_MISS) ] = -1, | |
269 | }, | |
270 | }, | |
271 | }; | |
272 | ||
273 | static __initconst u64 core2_hw_cache_event_ids | |
274 | [PERF_COUNT_HW_CACHE_MAX] | |
275 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
276 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
277 | { | |
278 | [ C(L1D) ] = { | |
279 | [ C(OP_READ) ] = { | |
280 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
281 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
282 | }, | |
283 | [ C(OP_WRITE) ] = { | |
284 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
285 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
286 | }, | |
287 | [ C(OP_PREFETCH) ] = { | |
288 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
289 | [ C(RESULT_MISS) ] = 0, | |
290 | }, | |
291 | }, | |
292 | [ C(L1I ) ] = { | |
293 | [ C(OP_READ) ] = { | |
294 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
295 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
296 | }, | |
297 | [ C(OP_WRITE) ] = { | |
298 | [ C(RESULT_ACCESS) ] = -1, | |
299 | [ C(RESULT_MISS) ] = -1, | |
300 | }, | |
301 | [ C(OP_PREFETCH) ] = { | |
302 | [ C(RESULT_ACCESS) ] = 0, | |
303 | [ C(RESULT_MISS) ] = 0, | |
304 | }, | |
305 | }, | |
306 | [ C(LL ) ] = { | |
307 | [ C(OP_READ) ] = { | |
308 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
309 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
310 | }, | |
311 | [ C(OP_WRITE) ] = { | |
312 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
313 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
314 | }, | |
315 | [ C(OP_PREFETCH) ] = { | |
316 | [ C(RESULT_ACCESS) ] = 0, | |
317 | [ C(RESULT_MISS) ] = 0, | |
318 | }, | |
319 | }, | |
320 | [ C(DTLB) ] = { | |
321 | [ C(OP_READ) ] = { | |
322 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
323 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
324 | }, | |
325 | [ C(OP_WRITE) ] = { | |
326 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
327 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
328 | }, | |
329 | [ C(OP_PREFETCH) ] = { | |
330 | [ C(RESULT_ACCESS) ] = 0, | |
331 | [ C(RESULT_MISS) ] = 0, | |
332 | }, | |
333 | }, | |
334 | [ C(ITLB) ] = { | |
335 | [ C(OP_READ) ] = { | |
336 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
337 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
338 | }, | |
339 | [ C(OP_WRITE) ] = { | |
340 | [ C(RESULT_ACCESS) ] = -1, | |
341 | [ C(RESULT_MISS) ] = -1, | |
342 | }, | |
343 | [ C(OP_PREFETCH) ] = { | |
344 | [ C(RESULT_ACCESS) ] = -1, | |
345 | [ C(RESULT_MISS) ] = -1, | |
346 | }, | |
347 | }, | |
348 | [ C(BPU ) ] = { | |
349 | [ C(OP_READ) ] = { | |
350 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
351 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
352 | }, | |
353 | [ C(OP_WRITE) ] = { | |
354 | [ C(RESULT_ACCESS) ] = -1, | |
355 | [ C(RESULT_MISS) ] = -1, | |
356 | }, | |
357 | [ C(OP_PREFETCH) ] = { | |
358 | [ C(RESULT_ACCESS) ] = -1, | |
359 | [ C(RESULT_MISS) ] = -1, | |
360 | }, | |
361 | }, | |
362 | }; | |
363 | ||
364 | static __initconst u64 atom_hw_cache_event_ids | |
365 | [PERF_COUNT_HW_CACHE_MAX] | |
366 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
367 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
368 | { | |
369 | [ C(L1D) ] = { | |
370 | [ C(OP_READ) ] = { | |
371 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
372 | [ C(RESULT_MISS) ] = 0, | |
373 | }, | |
374 | [ C(OP_WRITE) ] = { | |
375 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ | |
376 | [ C(RESULT_MISS) ] = 0, | |
377 | }, | |
378 | [ C(OP_PREFETCH) ] = { | |
379 | [ C(RESULT_ACCESS) ] = 0x0, | |
380 | [ C(RESULT_MISS) ] = 0, | |
381 | }, | |
382 | }, | |
383 | [ C(L1I ) ] = { | |
384 | [ C(OP_READ) ] = { | |
385 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
386 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
387 | }, | |
388 | [ C(OP_WRITE) ] = { | |
389 | [ C(RESULT_ACCESS) ] = -1, | |
390 | [ C(RESULT_MISS) ] = -1, | |
391 | }, | |
392 | [ C(OP_PREFETCH) ] = { | |
393 | [ C(RESULT_ACCESS) ] = 0, | |
394 | [ C(RESULT_MISS) ] = 0, | |
395 | }, | |
396 | }, | |
397 | [ C(LL ) ] = { | |
398 | [ C(OP_READ) ] = { | |
399 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
400 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
401 | }, | |
402 | [ C(OP_WRITE) ] = { | |
403 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
404 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
405 | }, | |
406 | [ C(OP_PREFETCH) ] = { | |
407 | [ C(RESULT_ACCESS) ] = 0, | |
408 | [ C(RESULT_MISS) ] = 0, | |
409 | }, | |
410 | }, | |
411 | [ C(DTLB) ] = { | |
412 | [ C(OP_READ) ] = { | |
413 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ | |
414 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ | |
415 | }, | |
416 | [ C(OP_WRITE) ] = { | |
417 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ | |
418 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ | |
419 | }, | |
420 | [ C(OP_PREFETCH) ] = { | |
421 | [ C(RESULT_ACCESS) ] = 0, | |
422 | [ C(RESULT_MISS) ] = 0, | |
423 | }, | |
424 | }, | |
425 | [ C(ITLB) ] = { | |
426 | [ C(OP_READ) ] = { | |
427 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
428 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
429 | }, | |
430 | [ C(OP_WRITE) ] = { | |
431 | [ C(RESULT_ACCESS) ] = -1, | |
432 | [ C(RESULT_MISS) ] = -1, | |
433 | }, | |
434 | [ C(OP_PREFETCH) ] = { | |
435 | [ C(RESULT_ACCESS) ] = -1, | |
436 | [ C(RESULT_MISS) ] = -1, | |
437 | }, | |
438 | }, | |
439 | [ C(BPU ) ] = { | |
440 | [ C(OP_READ) ] = { | |
441 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
442 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
443 | }, | |
444 | [ C(OP_WRITE) ] = { | |
445 | [ C(RESULT_ACCESS) ] = -1, | |
446 | [ C(RESULT_MISS) ] = -1, | |
447 | }, | |
448 | [ C(OP_PREFETCH) ] = { | |
449 | [ C(RESULT_ACCESS) ] = -1, | |
450 | [ C(RESULT_MISS) ] = -1, | |
451 | }, | |
452 | }, | |
453 | }; | |
454 | ||
455 | static u64 intel_pmu_raw_event(u64 hw_event) | |
456 | { | |
457 | #define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL | |
458 | #define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL | |
459 | #define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL | |
460 | #define CORE_EVNTSEL_INV_MASK 0x00800000ULL | |
461 | #define CORE_EVNTSEL_REG_MASK 0xFF000000ULL | |
462 | ||
463 | #define CORE_EVNTSEL_MASK \ | |
464 | (INTEL_ARCH_EVTSEL_MASK | \ | |
465 | INTEL_ARCH_UNIT_MASK | \ | |
466 | INTEL_ARCH_EDGE_MASK | \ | |
467 | INTEL_ARCH_INV_MASK | \ | |
468 | INTEL_ARCH_CNT_MASK) | |
469 | ||
470 | return hw_event & CORE_EVNTSEL_MASK; | |
471 | } | |
472 | ||
f22f54f4 PZ |
473 | static void intel_pmu_disable_all(void) |
474 | { | |
475 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
476 | ||
477 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
478 | ||
479 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) | |
480 | intel_pmu_disable_bts(); | |
ca037701 PZ |
481 | |
482 | intel_pmu_pebs_disable_all(); | |
caff2bef | 483 | intel_pmu_lbr_disable_all(); |
f22f54f4 PZ |
484 | } |
485 | ||
486 | static void intel_pmu_enable_all(void) | |
487 | { | |
488 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
489 | ||
490 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); | |
491 | ||
492 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { | |
493 | struct perf_event *event = | |
494 | cpuc->events[X86_PMC_IDX_FIXED_BTS]; | |
495 | ||
496 | if (WARN_ON_ONCE(!event)) | |
497 | return; | |
498 | ||
499 | intel_pmu_enable_bts(event->hw.config); | |
500 | } | |
ca037701 PZ |
501 | |
502 | intel_pmu_pebs_enable_all(); | |
caff2bef | 503 | intel_pmu_lbr_enable_all(); |
f22f54f4 PZ |
504 | } |
505 | ||
506 | static inline u64 intel_pmu_get_status(void) | |
507 | { | |
508 | u64 status; | |
509 | ||
510 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
511 | ||
512 | return status; | |
513 | } | |
514 | ||
515 | static inline void intel_pmu_ack_status(u64 ack) | |
516 | { | |
517 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
518 | } | |
519 | ||
ca037701 | 520 | static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 521 | { |
aff3d91a | 522 | int idx = hwc->idx - X86_PMC_IDX_FIXED; |
f22f54f4 PZ |
523 | u64 ctrl_val, mask; |
524 | ||
525 | mask = 0xfULL << (idx * 4); | |
526 | ||
527 | rdmsrl(hwc->config_base, ctrl_val); | |
528 | ctrl_val &= ~mask; | |
529 | (void)checking_wrmsrl(hwc->config_base, ctrl_val); | |
530 | } | |
531 | ||
ca037701 | 532 | static void intel_pmu_disable_event(struct perf_event *event) |
f22f54f4 | 533 | { |
aff3d91a PZ |
534 | struct hw_perf_event *hwc = &event->hw; |
535 | ||
536 | if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { | |
f22f54f4 PZ |
537 | intel_pmu_disable_bts(); |
538 | intel_pmu_drain_bts_buffer(); | |
539 | return; | |
540 | } | |
541 | ||
542 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { | |
aff3d91a | 543 | intel_pmu_disable_fixed(hwc); |
f22f54f4 PZ |
544 | return; |
545 | } | |
546 | ||
aff3d91a | 547 | x86_pmu_disable_event(event); |
ca037701 PZ |
548 | |
549 | if (unlikely(event->attr.precise)) | |
ef21f683 | 550 | intel_pmu_pebs_disable(event); |
f22f54f4 PZ |
551 | } |
552 | ||
ca037701 | 553 | static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 554 | { |
aff3d91a | 555 | int idx = hwc->idx - X86_PMC_IDX_FIXED; |
f22f54f4 PZ |
556 | u64 ctrl_val, bits, mask; |
557 | int err; | |
558 | ||
559 | /* | |
560 | * Enable IRQ generation (0x8), | |
561 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
562 | * if requested: | |
563 | */ | |
564 | bits = 0x8ULL; | |
565 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
566 | bits |= 0x2; | |
567 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
568 | bits |= 0x1; | |
569 | ||
570 | /* | |
571 | * ANY bit is supported in v3 and up | |
572 | */ | |
573 | if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) | |
574 | bits |= 0x4; | |
575 | ||
576 | bits <<= (idx * 4); | |
577 | mask = 0xfULL << (idx * 4); | |
578 | ||
579 | rdmsrl(hwc->config_base, ctrl_val); | |
580 | ctrl_val &= ~mask; | |
581 | ctrl_val |= bits; | |
582 | err = checking_wrmsrl(hwc->config_base, ctrl_val); | |
583 | } | |
584 | ||
aff3d91a | 585 | static void intel_pmu_enable_event(struct perf_event *event) |
f22f54f4 | 586 | { |
aff3d91a PZ |
587 | struct hw_perf_event *hwc = &event->hw; |
588 | ||
589 | if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { | |
f22f54f4 PZ |
590 | if (!__get_cpu_var(cpu_hw_events).enabled) |
591 | return; | |
592 | ||
593 | intel_pmu_enable_bts(hwc->config); | |
594 | return; | |
595 | } | |
596 | ||
597 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { | |
aff3d91a | 598 | intel_pmu_enable_fixed(hwc); |
f22f54f4 PZ |
599 | return; |
600 | } | |
601 | ||
ca037701 | 602 | if (unlikely(event->attr.precise)) |
ef21f683 | 603 | intel_pmu_pebs_enable(event); |
ca037701 | 604 | |
aff3d91a | 605 | __x86_pmu_enable_event(hwc); |
f22f54f4 PZ |
606 | } |
607 | ||
608 | /* | |
609 | * Save and restart an expired event. Called by NMI contexts, | |
610 | * so it has to be careful about preempting normal event ops: | |
611 | */ | |
612 | static int intel_pmu_save_and_restart(struct perf_event *event) | |
613 | { | |
cc2ad4ba PZ |
614 | x86_perf_event_update(event); |
615 | return x86_perf_event_set_period(event); | |
f22f54f4 PZ |
616 | } |
617 | ||
618 | static void intel_pmu_reset(void) | |
619 | { | |
620 | struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds; | |
621 | unsigned long flags; | |
622 | int idx; | |
623 | ||
624 | if (!x86_pmu.num_events) | |
625 | return; | |
626 | ||
627 | local_irq_save(flags); | |
628 | ||
629 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | |
630 | ||
631 | for (idx = 0; idx < x86_pmu.num_events; idx++) { | |
632 | checking_wrmsrl(x86_pmu.eventsel + idx, 0ull); | |
633 | checking_wrmsrl(x86_pmu.perfctr + idx, 0ull); | |
634 | } | |
635 | for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) { | |
636 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | |
637 | } | |
638 | if (ds) | |
639 | ds->bts_index = ds->bts_buffer_base; | |
640 | ||
641 | local_irq_restore(flags); | |
642 | } | |
643 | ||
644 | /* | |
645 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
646 | * rules apply: | |
647 | */ | |
648 | static int intel_pmu_handle_irq(struct pt_regs *regs) | |
649 | { | |
650 | struct perf_sample_data data; | |
651 | struct cpu_hw_events *cpuc; | |
652 | int bit, loops; | |
653 | u64 ack, status; | |
654 | ||
dc1d628a | 655 | perf_sample_data_init(&data, 0); |
f22f54f4 PZ |
656 | |
657 | cpuc = &__get_cpu_var(cpu_hw_events); | |
658 | ||
3fb2b8dd | 659 | intel_pmu_disable_all(); |
f22f54f4 PZ |
660 | intel_pmu_drain_bts_buffer(); |
661 | status = intel_pmu_get_status(); | |
662 | if (!status) { | |
3fb2b8dd | 663 | intel_pmu_enable_all(); |
f22f54f4 PZ |
664 | return 0; |
665 | } | |
666 | ||
667 | loops = 0; | |
668 | again: | |
669 | if (++loops > 100) { | |
670 | WARN_ONCE(1, "perfevents: irq loop stuck!\n"); | |
671 | perf_event_print_debug(); | |
672 | intel_pmu_reset(); | |
3fb2b8dd | 673 | goto done; |
f22f54f4 PZ |
674 | } |
675 | ||
676 | inc_irq_stat(apic_perf_irqs); | |
677 | ack = status; | |
ca037701 | 678 | |
caff2bef PZ |
679 | intel_pmu_lbr_read(); |
680 | ||
ca037701 PZ |
681 | /* |
682 | * PEBS overflow sets bit 62 in the global status register | |
683 | */ | |
684 | if (__test_and_clear_bit(62, (unsigned long *)&status)) | |
685 | x86_pmu.drain_pebs(regs); | |
686 | ||
984b3f57 | 687 | for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
f22f54f4 PZ |
688 | struct perf_event *event = cpuc->events[bit]; |
689 | ||
f22f54f4 PZ |
690 | if (!test_bit(bit, cpuc->active_mask)) |
691 | continue; | |
692 | ||
693 | if (!intel_pmu_save_and_restart(event)) | |
694 | continue; | |
695 | ||
696 | data.period = event->hw.last_period; | |
697 | ||
698 | if (perf_event_overflow(event, 1, &data, regs)) | |
71e2d282 | 699 | x86_pmu_stop(event); |
f22f54f4 PZ |
700 | } |
701 | ||
702 | intel_pmu_ack_status(ack); | |
703 | ||
704 | /* | |
705 | * Repeat if there is more work to be done: | |
706 | */ | |
707 | status = intel_pmu_get_status(); | |
708 | if (status) | |
709 | goto again; | |
710 | ||
3fb2b8dd PZ |
711 | done: |
712 | intel_pmu_enable_all(); | |
f22f54f4 PZ |
713 | return 1; |
714 | } | |
715 | ||
f22f54f4 | 716 | static struct event_constraint * |
ca037701 | 717 | intel_bts_constraints(struct perf_event *event) |
f22f54f4 | 718 | { |
ca037701 PZ |
719 | struct hw_perf_event *hwc = &event->hw; |
720 | unsigned int hw_event, bts_event; | |
f22f54f4 | 721 | |
ca037701 PZ |
722 | hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; |
723 | bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); | |
f22f54f4 | 724 | |
ca037701 | 725 | if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) |
f22f54f4 | 726 | return &bts_constraint; |
ca037701 | 727 | |
f22f54f4 PZ |
728 | return NULL; |
729 | } | |
730 | ||
731 | static struct event_constraint * | |
732 | intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) | |
733 | { | |
734 | struct event_constraint *c; | |
735 | ||
ca037701 PZ |
736 | c = intel_bts_constraints(event); |
737 | if (c) | |
738 | return c; | |
739 | ||
740 | c = intel_pebs_constraints(event); | |
f22f54f4 PZ |
741 | if (c) |
742 | return c; | |
743 | ||
744 | return x86_get_event_constraints(cpuc, event); | |
745 | } | |
746 | ||
747 | static __initconst struct x86_pmu core_pmu = { | |
748 | .name = "core", | |
749 | .handle_irq = x86_pmu_handle_irq, | |
750 | .disable_all = x86_pmu_disable_all, | |
751 | .enable_all = x86_pmu_enable_all, | |
752 | .enable = x86_pmu_enable_event, | |
753 | .disable = x86_pmu_disable_event, | |
754 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, | |
755 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
756 | .event_map = intel_pmu_event_map, | |
757 | .raw_event = intel_pmu_raw_event, | |
758 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), | |
759 | .apic = 1, | |
760 | /* | |
761 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
762 | * so we install an artificial 1<<31 period regardless of | |
763 | * the generic event period: | |
764 | */ | |
765 | .max_period = (1ULL << 31) - 1, | |
766 | .get_event_constraints = intel_get_event_constraints, | |
767 | .event_constraints = intel_core_event_constraints, | |
768 | }; | |
769 | ||
770 | static __initconst struct x86_pmu intel_pmu = { | |
771 | .name = "Intel", | |
772 | .handle_irq = intel_pmu_handle_irq, | |
773 | .disable_all = intel_pmu_disable_all, | |
774 | .enable_all = intel_pmu_enable_all, | |
775 | .enable = intel_pmu_enable_event, | |
776 | .disable = intel_pmu_disable_event, | |
777 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, | |
778 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
779 | .event_map = intel_pmu_event_map, | |
780 | .raw_event = intel_pmu_raw_event, | |
781 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), | |
782 | .apic = 1, | |
783 | /* | |
784 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
785 | * so we install an artificial 1<<31 period regardless of | |
786 | * the generic event period: | |
787 | */ | |
788 | .max_period = (1ULL << 31) - 1, | |
3f6da390 PZ |
789 | .get_event_constraints = intel_get_event_constraints, |
790 | ||
791 | .cpu_starting = init_debug_store_on_cpu, | |
792 | .cpu_dying = fini_debug_store_on_cpu, | |
f22f54f4 PZ |
793 | }; |
794 | ||
795 | static __init int intel_pmu_init(void) | |
796 | { | |
797 | union cpuid10_edx edx; | |
798 | union cpuid10_eax eax; | |
799 | unsigned int unused; | |
800 | unsigned int ebx; | |
801 | int version; | |
802 | ||
803 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { | |
804 | /* check for P6 processor family */ | |
805 | if (boot_cpu_data.x86 == 6) { | |
806 | return p6_pmu_init(); | |
807 | } else { | |
808 | return -ENODEV; | |
809 | } | |
810 | } | |
811 | ||
812 | /* | |
813 | * Check whether the Architectural PerfMon supports | |
814 | * Branch Misses Retired hw_event or not. | |
815 | */ | |
816 | cpuid(10, &eax.full, &ebx, &unused, &edx.full); | |
817 | if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED) | |
818 | return -ENODEV; | |
819 | ||
820 | version = eax.split.version_id; | |
821 | if (version < 2) | |
822 | x86_pmu = core_pmu; | |
823 | else | |
824 | x86_pmu = intel_pmu; | |
825 | ||
826 | x86_pmu.version = version; | |
827 | x86_pmu.num_events = eax.split.num_events; | |
828 | x86_pmu.event_bits = eax.split.bit_width; | |
829 | x86_pmu.event_mask = (1ULL << eax.split.bit_width) - 1; | |
830 | ||
831 | /* | |
832 | * Quirk: v2 perfmon does not report fixed-purpose events, so | |
833 | * assume at least 3 events: | |
834 | */ | |
835 | if (version > 1) | |
836 | x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3); | |
837 | ||
8db909a7 PZ |
838 | /* |
839 | * v2 and above have a perf capabilities MSR | |
840 | */ | |
841 | if (version > 1) { | |
842 | u64 capabilities; | |
843 | ||
844 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); | |
845 | x86_pmu.intel_cap.capabilities = capabilities; | |
846 | } | |
847 | ||
ca037701 PZ |
848 | intel_ds_init(); |
849 | ||
f22f54f4 PZ |
850 | /* |
851 | * Install the hw-cache-events table: | |
852 | */ | |
853 | switch (boot_cpu_data.x86_model) { | |
854 | case 14: /* 65 nm core solo/duo, "Yonah" */ | |
855 | pr_cont("Core events, "); | |
856 | break; | |
857 | ||
858 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ | |
859 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ | |
860 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
861 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
862 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, | |
863 | sizeof(hw_cache_event_ids)); | |
864 | ||
caff2bef PZ |
865 | intel_pmu_lbr_init_core(); |
866 | ||
f22f54f4 PZ |
867 | x86_pmu.event_constraints = intel_core2_event_constraints; |
868 | pr_cont("Core2 events, "); | |
869 | break; | |
870 | ||
871 | case 26: /* 45 nm nehalem, "Bloomfield" */ | |
872 | case 30: /* 45 nm nehalem, "Lynnfield" */ | |
873 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, | |
874 | sizeof(hw_cache_event_ids)); | |
875 | ||
caff2bef PZ |
876 | intel_pmu_lbr_init_nhm(); |
877 | ||
f22f54f4 PZ |
878 | x86_pmu.event_constraints = intel_nehalem_event_constraints; |
879 | pr_cont("Nehalem/Corei7 events, "); | |
880 | break; | |
caff2bef | 881 | |
b622d644 | 882 | case 28: /* Atom */ |
f22f54f4 PZ |
883 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
884 | sizeof(hw_cache_event_ids)); | |
885 | ||
caff2bef PZ |
886 | intel_pmu_lbr_init_atom(); |
887 | ||
f22f54f4 PZ |
888 | x86_pmu.event_constraints = intel_gen_event_constraints; |
889 | pr_cont("Atom events, "); | |
890 | break; | |
891 | ||
892 | case 37: /* 32 nm nehalem, "Clarkdale" */ | |
893 | case 44: /* 32 nm nehalem, "Gulftown" */ | |
894 | memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, | |
895 | sizeof(hw_cache_event_ids)); | |
896 | ||
caff2bef PZ |
897 | intel_pmu_lbr_init_nhm(); |
898 | ||
f22f54f4 PZ |
899 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
900 | pr_cont("Westmere events, "); | |
901 | break; | |
b622d644 | 902 | |
f22f54f4 PZ |
903 | default: |
904 | /* | |
905 | * default constraints for v2 and up | |
906 | */ | |
907 | x86_pmu.event_constraints = intel_gen_event_constraints; | |
908 | pr_cont("generic architected perfmon, "); | |
909 | } | |
910 | return 0; | |
911 | } | |
912 | ||
913 | #else /* CONFIG_CPU_SUP_INTEL */ | |
914 | ||
915 | static int intel_pmu_init(void) | |
916 | { | |
917 | return 0; | |
918 | } | |
919 | ||
920 | #endif /* CONFIG_CPU_SUP_INTEL */ |