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perf/x86/intel: Add simple Haswell PMU support
[linux-2.6-block.git] / arch / x86 / kernel / cpu / perf_event_intel.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
de0428a7 15
3a632cb2 16#include <asm/cpufeature.h>
de0428a7
KW		 17#include <asm/hardirq.h>
18#include <asm/apic.h>
19
20#include "perf_event.h"
a7e3ed1e 21
f22f54f4 22/*
b622d644 23 * Intel PerfMon, used on Core and later.
f22f54f4 24 */
ec75a716 25static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 26{
c3b7cdf1
PE		 27 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
28 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
29 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
30 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
31 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
32 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
33 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
34 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 35};
36
5c543e3c 37static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 38{
39 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
40 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
41 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
42 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
43 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
44 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
45 EVENT_CONSTRAINT_END
46};
47
5c543e3c 48static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 49{
b622d644
PZ		 50 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
51 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 52 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 53 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
54 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
55 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
56 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
57 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
58 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
59 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
60 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 61 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 62 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
63 EVENT_CONSTRAINT_END
64};
65
5c543e3c 66static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 67{
b622d644
PZ		 68 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
69 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 70 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 71 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
72 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
73 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
74 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
75 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
76 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
77 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
78 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
79 EVENT_CONSTRAINT_END
80};
81
5c543e3c 82static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 83{
efc9f05d 84 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 85 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 86 EVENT_EXTRA_END
87};
88
5c543e3c 89static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 90{
b622d644
PZ		 91 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
92 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 93 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 94 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
95 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
96 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 97 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 98 EVENT_CONSTRAINT_END
99};
100
5c543e3c 101static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 102{
103 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
104 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 105 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 106 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
107 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
108 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
109 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 110 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 111 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
112 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 113 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
b06b3d49
LM		 115 EVENT_CONSTRAINT_END
116};
117
69943182
SE		 118static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
119{
120 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
121 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
122 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
123 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
124 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
125 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
126 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
127 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
128 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
129 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
130 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
131 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
741a698f
PZ		 132 /*
133 * Errata BV98 -- MEM_*_RETIRED events can leak between counters of SMT
134 * siblings; disable these events because they can corrupt unrelated
135 * counters.
136 */
137 INTEL_EVENT_CONSTRAINT(0xd0, 0x0), /* MEM_UOPS_RETIRED.* */
138 INTEL_EVENT_CONSTRAINT(0xd1, 0x0), /* MEM_LOAD_UOPS_RETIRED.* */
139 INTEL_EVENT_CONSTRAINT(0xd2, 0x0), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
140 INTEL_EVENT_CONSTRAINT(0xd3, 0x0), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
69943182
SE		 141 EVENT_CONSTRAINT_END
142};
143
5c543e3c 144static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 145{
efc9f05d
SE		 146 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
147 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 148 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 149 EVENT_EXTRA_END
150};
151
0af3ac1f
AK		 152static struct event_constraint intel_v1_event_constraints[] __read_mostly =
153{
154 EVENT_CONSTRAINT_END
155};
156
5c543e3c 157static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 158{
b622d644
PZ		 159 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
160 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 161 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 162 EVENT_CONSTRAINT_END
163};
164
ee89cbc2 165static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
f1923820
SE		 166 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
167 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 168 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 169 EVENT_EXTRA_END
170};
171
172static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
173 INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
174 INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 175 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 176 EVENT_EXTRA_END
177};
178
f20093ee
SE		 179EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
180EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
9ad64c0f 181EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee
SE		 182
183struct attribute *nhm_events_attrs[] = {
184 EVENT_PTR(mem_ld_nhm),
185 NULL,
186};
187
188struct attribute *snb_events_attrs[] = {
189 EVENT_PTR(mem_ld_snb),
9ad64c0f 190 EVENT_PTR(mem_st_snb),
f20093ee
SE		 191 NULL,
192};
193
3a632cb2
AK		 194static struct event_constraint intel_hsw_event_constraints[] = {
195 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
196 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
197 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
198 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
199 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
200 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
201 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
202 INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
203 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
204 INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
205 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
206 INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
207 EVENT_CONSTRAINT_END
208};
209
f22f54f4
PZ		 210static u64 intel_pmu_event_map(int hw_event)
211{
212 return intel_perfmon_event_map[hw_event];
213}
214
74e6543f
YZ		 215#define SNB_DMND_DATA_RD (1ULL << 0)
216#define SNB_DMND_RFO (1ULL << 1)
217#define SNB_DMND_IFETCH (1ULL << 2)
218#define SNB_DMND_WB (1ULL << 3)
219#define SNB_PF_DATA_RD (1ULL << 4)
220#define SNB_PF_RFO (1ULL << 5)
221#define SNB_PF_IFETCH (1ULL << 6)
222#define SNB_LLC_DATA_RD (1ULL << 7)
223#define SNB_LLC_RFO (1ULL << 8)
224#define SNB_LLC_IFETCH (1ULL << 9)
225#define SNB_BUS_LOCKS (1ULL << 10)
226#define SNB_STRM_ST (1ULL << 11)
227#define SNB_OTHER (1ULL << 15)
228#define SNB_RESP_ANY (1ULL << 16)
229#define SNB_NO_SUPP (1ULL << 17)
230#define SNB_LLC_HITM (1ULL << 18)
231#define SNB_LLC_HITE (1ULL << 19)
232#define SNB_LLC_HITS (1ULL << 20)
233#define SNB_LLC_HITF (1ULL << 21)
234#define SNB_LOCAL (1ULL << 22)
235#define SNB_REMOTE (0xffULL << 23)
236#define SNB_SNP_NONE (1ULL << 31)
237#define SNB_SNP_NOT_NEEDED (1ULL << 32)
238#define SNB_SNP_MISS (1ULL << 33)
239#define SNB_NO_FWD (1ULL << 34)
240#define SNB_SNP_FWD (1ULL << 35)
241#define SNB_HITM (1ULL << 36)
242#define SNB_NON_DRAM (1ULL << 37)
243
244#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
245#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
246#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
247
248#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
249 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
250 SNB_HITM)
251
252#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
253#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
254
255#define SNB_L3_ACCESS SNB_RESP_ANY
256#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
257
258static __initconst const u64 snb_hw_cache_extra_regs
259 [PERF_COUNT_HW_CACHE_MAX]
260 [PERF_COUNT_HW_CACHE_OP_MAX]
261 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
262{
263 [ C(LL ) ] = {
264 [ C(OP_READ) ] = {
265 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
266 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
267 },
268 [ C(OP_WRITE) ] = {
269 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
270 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
271 },
272 [ C(OP_PREFETCH) ] = {
273 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
274 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
275 },
276 },
277 [ C(NODE) ] = {
278 [ C(OP_READ) ] = {
279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
281 },
282 [ C(OP_WRITE) ] = {
283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
285 },
286 [ C(OP_PREFETCH) ] = {
287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
289 },
290 },
291};
292
b06b3d49
LM		 293static __initconst const u64 snb_hw_cache_event_ids
294 [PERF_COUNT_HW_CACHE_MAX]
295 [PERF_COUNT_HW_CACHE_OP_MAX]
296 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
297{
298 [ C(L1D) ] = {
299 [ C(OP_READ) ] = {
300 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
301 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
302 },
303 [ C(OP_WRITE) ] = {
304 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
305 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
306 },
307 [ C(OP_PREFETCH) ] = {
308 [ C(RESULT_ACCESS) ] = 0x0,
309 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
310 },
311 },
312 [ C(L1I ) ] = {
313 [ C(OP_READ) ] = {
314 [ C(RESULT_ACCESS) ] = 0x0,
315 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
316 },
317 [ C(OP_WRITE) ] = {
318 [ C(RESULT_ACCESS) ] = -1,
319 [ C(RESULT_MISS) ] = -1,
320 },
321 [ C(OP_PREFETCH) ] = {
322 [ C(RESULT_ACCESS) ] = 0x0,
323 [ C(RESULT_MISS) ] = 0x0,
324 },
325 },
326 [ C(LL ) ] = {
b06b3d49 327 [ C(OP_READ) ] = {
63b6a675 328 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 329 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 330 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
331 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 332 },
333 [ C(OP_WRITE) ] = {
63b6a675 334 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 335 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 336 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
337 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 338 },
339 [ C(OP_PREFETCH) ] = {
63b6a675 340 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 341 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 342 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
343 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 344 },
345 },
346 [ C(DTLB) ] = {
347 [ C(OP_READ) ] = {
348 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
349 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
350 },
351 [ C(OP_WRITE) ] = {
352 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
353 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
354 },
355 [ C(OP_PREFETCH) ] = {
356 [ C(RESULT_ACCESS) ] = 0x0,
357 [ C(RESULT_MISS) ] = 0x0,
358 },
359 },
360 [ C(ITLB) ] = {
361 [ C(OP_READ) ] = {
362 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
363 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
364 },
365 [ C(OP_WRITE) ] = {
366 [ C(RESULT_ACCESS) ] = -1,
367 [ C(RESULT_MISS) ] = -1,
368 },
369 [ C(OP_PREFETCH) ] = {
370 [ C(RESULT_ACCESS) ] = -1,
371 [ C(RESULT_MISS) ] = -1,
372 },
373 },
374 [ C(BPU ) ] = {
375 [ C(OP_READ) ] = {
376 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
377 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
378 },
379 [ C(OP_WRITE) ] = {
380 [ C(RESULT_ACCESS) ] = -1,
381 [ C(RESULT_MISS) ] = -1,
382 },
383 [ C(OP_PREFETCH) ] = {
384 [ C(RESULT_ACCESS) ] = -1,
385 [ C(RESULT_MISS) ] = -1,
386 },
387 },
89d6c0b5
PZ		 388 [ C(NODE) ] = {
389 [ C(OP_READ) ] = {
74e6543f
YZ		 390 [ C(RESULT_ACCESS) ] = 0x01b7,
391 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 392 },
393 [ C(OP_WRITE) ] = {
74e6543f
YZ		 394 [ C(RESULT_ACCESS) ] = 0x01b7,
395 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 396 },
397 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 398 [ C(RESULT_ACCESS) ] = 0x01b7,
399 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 400 },
401 },
402
b06b3d49
LM		 403};
404
caaa8be3 405static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 406 [PERF_COUNT_HW_CACHE_MAX]
407 [PERF_COUNT_HW_CACHE_OP_MAX]
408 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
409{
410 [ C(L1D) ] = {
411 [ C(OP_READ) ] = {
412 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
413 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
414 },
415 [ C(OP_WRITE) ] = {
416 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
417 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
418 },
419 [ C(OP_PREFETCH) ] = {
420 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
421 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
422 },
423 },
424 [ C(L1I ) ] = {
425 [ C(OP_READ) ] = {
426 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
427 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
428 },
429 [ C(OP_WRITE) ] = {
430 [ C(RESULT_ACCESS) ] = -1,
431 [ C(RESULT_MISS) ] = -1,
432 },
433 [ C(OP_PREFETCH) ] = {
434 [ C(RESULT_ACCESS) ] = 0x0,
435 [ C(RESULT_MISS) ] = 0x0,
436 },
437 },
438 [ C(LL ) ] = {
439 [ C(OP_READ) ] = {
63b6a675 440 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 441 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 442 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
443 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 444 },
e994d7d2
AK		 445 /*
446 * Use RFO, not WRITEBACK, because a write miss would typically occur
447 * on RFO.
448 */
f22f54f4 449 [ C(OP_WRITE) ] = {
63b6a675
PZ		 450 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
451 [ C(RESULT_ACCESS) ] = 0x01b7,
452 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 453 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 454 },
455 [ C(OP_PREFETCH) ] = {
63b6a675 456 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 457 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 458 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
459 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 460 },
461 },
462 [ C(DTLB) ] = {
463 [ C(OP_READ) ] = {
464 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
465 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
466 },
467 [ C(OP_WRITE) ] = {
468 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
469 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
470 },
471 [ C(OP_PREFETCH) ] = {
472 [ C(RESULT_ACCESS) ] = 0x0,
473 [ C(RESULT_MISS) ] = 0x0,
474 },
475 },
476 [ C(ITLB) ] = {
477 [ C(OP_READ) ] = {
478 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
479 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = -1,
483 [ C(RESULT_MISS) ] = -1,
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = -1,
487 [ C(RESULT_MISS) ] = -1,
488 },
489 },
490 [ C(BPU ) ] = {
491 [ C(OP_READ) ] = {
492 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
493 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = -1,
497 [ C(RESULT_MISS) ] = -1,
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = -1,
501 [ C(RESULT_MISS) ] = -1,
502 },
503 },
89d6c0b5
PZ		 504 [ C(NODE) ] = {
505 [ C(OP_READ) ] = {
506 [ C(RESULT_ACCESS) ] = 0x01b7,
507 [ C(RESULT_MISS) ] = 0x01b7,
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = 0x01b7,
511 [ C(RESULT_MISS) ] = 0x01b7,
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = 0x01b7,
515 [ C(RESULT_MISS) ] = 0x01b7,
516 },
517 },
f22f54f4
PZ		 518};
519
e994d7d2 520/*
63b6a675
PZ		 521 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
522 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 523 */
524
63b6a675
PZ		 525#define NHM_DMND_DATA_RD (1 << 0)
526#define NHM_DMND_RFO (1 << 1)
527#define NHM_DMND_IFETCH (1 << 2)
528#define NHM_DMND_WB (1 << 3)
529#define NHM_PF_DATA_RD (1 << 4)
530#define NHM_PF_DATA_RFO (1 << 5)
531#define NHM_PF_IFETCH (1 << 6)
532#define NHM_OFFCORE_OTHER (1 << 7)
533#define NHM_UNCORE_HIT (1 << 8)
534#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
535#define NHM_OTHER_CORE_HITM (1 << 10)
536 /* reserved */
537#define NHM_REMOTE_CACHE_FWD (1 << 12)
538#define NHM_REMOTE_DRAM (1 << 13)
539#define NHM_LOCAL_DRAM (1 << 14)
540#define NHM_NON_DRAM (1 << 15)
541
87e24f4b
PZ		 542#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
543#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 544
545#define NHM_DMND_READ (NHM_DMND_DATA_RD)
546#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
547#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
548
549#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 550#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 551#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 552
553static __initconst const u64 nehalem_hw_cache_extra_regs
554 [PERF_COUNT_HW_CACHE_MAX]
555 [PERF_COUNT_HW_CACHE_OP_MAX]
556 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
557{
558 [ C(LL ) ] = {
559 [ C(OP_READ) ] = {
63b6a675
PZ		 560 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
561 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 562 },
563 [ C(OP_WRITE) ] = {
63b6a675
PZ		 564 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
565 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 566 },
567 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 568 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
569 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 570 },
89d6c0b5
PZ		 571 },
572 [ C(NODE) ] = {
573 [ C(OP_READ) ] = {
87e24f4b
PZ		 574 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
575 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 576 },
577 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 578 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
579 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 580 },
581 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 582 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
583 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 584 },
585 },
e994d7d2
AK		 586};
587
caaa8be3 588static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 589 [PERF_COUNT_HW_CACHE_MAX]
590 [PERF_COUNT_HW_CACHE_OP_MAX]
591 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
592{
593 [ C(L1D) ] = {
594 [ C(OP_READ) ] = {
f4929bd3
PZ		 595 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
596 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 597 },
598 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 599 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
600 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 601 },
602 [ C(OP_PREFETCH) ] = {
603 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
604 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
605 },
606 },
607 [ C(L1I ) ] = {
608 [ C(OP_READ) ] = {
609 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
610 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
611 },
612 [ C(OP_WRITE) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
615 },
616 [ C(OP_PREFETCH) ] = {
617 [ C(RESULT_ACCESS) ] = 0x0,
618 [ C(RESULT_MISS) ] = 0x0,
619 },
620 },
621 [ C(LL ) ] = {
622 [ C(OP_READ) ] = {
e994d7d2
AK		 623 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
624 [ C(RESULT_ACCESS) ] = 0x01b7,
625 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
626 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 627 },
e994d7d2
AK		 628 /*
629 * Use RFO, not WRITEBACK, because a write miss would typically occur
630 * on RFO.
631 */
f22f54f4 632 [ C(OP_WRITE) ] = {
e994d7d2
AK		 633 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
634 [ C(RESULT_ACCESS) ] = 0x01b7,
635 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
636 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 637 },
638 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 639 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
640 [ C(RESULT_ACCESS) ] = 0x01b7,
641 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
642 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 643 },
644 },
645 [ C(DTLB) ] = {
646 [ C(OP_READ) ] = {
647 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
648 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
649 },
650 [ C(OP_WRITE) ] = {
651 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
652 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
653 },
654 [ C(OP_PREFETCH) ] = {
655 [ C(RESULT_ACCESS) ] = 0x0,
656 [ C(RESULT_MISS) ] = 0x0,
657 },
658 },
659 [ C(ITLB) ] = {
660 [ C(OP_READ) ] = {
661 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
662 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
663 },
664 [ C(OP_WRITE) ] = {
665 [ C(RESULT_ACCESS) ] = -1,
666 [ C(RESULT_MISS) ] = -1,
667 },
668 [ C(OP_PREFETCH) ] = {
669 [ C(RESULT_ACCESS) ] = -1,
670 [ C(RESULT_MISS) ] = -1,
671 },
672 },
673 [ C(BPU ) ] = {
674 [ C(OP_READ) ] = {
675 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
676 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
677 },
678 [ C(OP_WRITE) ] = {
679 [ C(RESULT_ACCESS) ] = -1,
680 [ C(RESULT_MISS) ] = -1,
681 },
682 [ C(OP_PREFETCH) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 },
89d6c0b5
PZ		 687 [ C(NODE) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = 0x01b7,
690 [ C(RESULT_MISS) ] = 0x01b7,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = 0x01b7,
694 [ C(RESULT_MISS) ] = 0x01b7,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = 0x01b7,
698 [ C(RESULT_MISS) ] = 0x01b7,
699 },
700 },
f22f54f4
PZ		 701};
702
caaa8be3 703static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 704 [PERF_COUNT_HW_CACHE_MAX]
705 [PERF_COUNT_HW_CACHE_OP_MAX]
706 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
707{
708 [ C(L1D) ] = {
709 [ C(OP_READ) ] = {
710 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
711 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
712 },
713 [ C(OP_WRITE) ] = {
714 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
715 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
716 },
717 [ C(OP_PREFETCH) ] = {
718 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
719 [ C(RESULT_MISS) ] = 0,
720 },
721 },
722 [ C(L1I ) ] = {
723 [ C(OP_READ) ] = {
724 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
725 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
726 },
727 [ C(OP_WRITE) ] = {
728 [ C(RESULT_ACCESS) ] = -1,
729 [ C(RESULT_MISS) ] = -1,
730 },
731 [ C(OP_PREFETCH) ] = {
732 [ C(RESULT_ACCESS) ] = 0,
733 [ C(RESULT_MISS) ] = 0,
734 },
735 },
736 [ C(LL ) ] = {
737 [ C(OP_READ) ] = {
738 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
739 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
740 },
741 [ C(OP_WRITE) ] = {
742 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
743 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
744 },
745 [ C(OP_PREFETCH) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = 0,
748 },
749 },
750 [ C(DTLB) ] = {
751 [ C(OP_READ) ] = {
752 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
753 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
754 },
755 [ C(OP_WRITE) ] = {
756 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
757 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
758 },
759 [ C(OP_PREFETCH) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = 0,
762 },
763 },
764 [ C(ITLB) ] = {
765 [ C(OP_READ) ] = {
766 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
767 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
768 },
769 [ C(OP_WRITE) ] = {
770 [ C(RESULT_ACCESS) ] = -1,
771 [ C(RESULT_MISS) ] = -1,
772 },
773 [ C(OP_PREFETCH) ] = {
774 [ C(RESULT_ACCESS) ] = -1,
775 [ C(RESULT_MISS) ] = -1,
776 },
777 },
778 [ C(BPU ) ] = {
779 [ C(OP_READ) ] = {
780 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
781 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
782 },
783 [ C(OP_WRITE) ] = {
784 [ C(RESULT_ACCESS) ] = -1,
785 [ C(RESULT_MISS) ] = -1,
786 },
787 [ C(OP_PREFETCH) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
790 },
791 },
792};
793
caaa8be3 794static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 795 [PERF_COUNT_HW_CACHE_MAX]
796 [PERF_COUNT_HW_CACHE_OP_MAX]
797 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
798{
799 [ C(L1D) ] = {
800 [ C(OP_READ) ] = {
801 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
802 [ C(RESULT_MISS) ] = 0,
803 },
804 [ C(OP_WRITE) ] = {
805 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
806 [ C(RESULT_MISS) ] = 0,
807 },
808 [ C(OP_PREFETCH) ] = {
809 [ C(RESULT_ACCESS) ] = 0x0,
810 [ C(RESULT_MISS) ] = 0,
811 },
812 },
813 [ C(L1I ) ] = {
814 [ C(OP_READ) ] = {
815 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
816 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
817 },
818 [ C(OP_WRITE) ] = {
819 [ C(RESULT_ACCESS) ] = -1,
820 [ C(RESULT_MISS) ] = -1,
821 },
822 [ C(OP_PREFETCH) ] = {
823 [ C(RESULT_ACCESS) ] = 0,
824 [ C(RESULT_MISS) ] = 0,
825 },
826 },
827 [ C(LL ) ] = {
828 [ C(OP_READ) ] = {
829 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
830 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
831 },
832 [ C(OP_WRITE) ] = {
833 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
834 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
835 },
836 [ C(OP_PREFETCH) ] = {
837 [ C(RESULT_ACCESS) ] = 0,
838 [ C(RESULT_MISS) ] = 0,
839 },
840 },
841 [ C(DTLB) ] = {
842 [ C(OP_READ) ] = {
843 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
844 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
845 },
846 [ C(OP_WRITE) ] = {
847 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
848 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
849 },
850 [ C(OP_PREFETCH) ] = {
851 [ C(RESULT_ACCESS) ] = 0,
852 [ C(RESULT_MISS) ] = 0,
853 },
854 },
855 [ C(ITLB) ] = {
856 [ C(OP_READ) ] = {
857 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
858 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
859 },
860 [ C(OP_WRITE) ] = {
861 [ C(RESULT_ACCESS) ] = -1,
862 [ C(RESULT_MISS) ] = -1,
863 },
864 [ C(OP_PREFETCH) ] = {
865 [ C(RESULT_ACCESS) ] = -1,
866 [ C(RESULT_MISS) ] = -1,
867 },
868 },
869 [ C(BPU ) ] = {
870 [ C(OP_READ) ] = {
871 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
872 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
873 },
874 [ C(OP_WRITE) ] = {
875 [ C(RESULT_ACCESS) ] = -1,
876 [ C(RESULT_MISS) ] = -1,
877 },
878 [ C(OP_PREFETCH) ] = {
879 [ C(RESULT_ACCESS) ] = -1,
880 [ C(RESULT_MISS) ] = -1,
881 },
882 },
883};
884
60ce0fbd
SE		 885static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
886{
887 /* user explicitly requested branch sampling */
888 if (has_branch_stack(event))
889 return true;
890
891 /* implicit branch sampling to correct PEBS skid */
892 if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
893 return true;
894
895 return false;
896}
897
f22f54f4
PZ		 898static void intel_pmu_disable_all(void)
899{
900 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
901
902 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
903
15c7ad51 904 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 905 intel_pmu_disable_bts();
ca037701
PZ		 906
907 intel_pmu_pebs_disable_all();
caff2bef 908 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 909}
910
11164cd4 911static void intel_pmu_enable_all(int added)
f22f54f4
PZ		 912{
913 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
914
d329527e
PZ		 915 intel_pmu_pebs_enable_all();
916 intel_pmu_lbr_enable_all();
144d31e6
GN		 917 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
918 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 919
15c7ad51 920 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 921 struct perf_event *event =
15c7ad51 922 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 923
924 if (WARN_ON_ONCE(!event))
925 return;
926
927 intel_pmu_enable_bts(event->hw.config);
928 }
929}
930
11164cd4
PZ		 931/*
932 * Workaround for:
933 * Intel Errata AAK100 (model 26)
934 * Intel Errata AAP53 (model 30)
40b91cd1 935 * Intel Errata BD53 (model 44)
11164cd4 936 *
351af072
ZY		 937 * The official story:
938 * These chips need to be 'reset' when adding counters by programming the
939 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
940 * in sequence on the same PMC or on different PMCs.
941 *
942 * In practise it appears some of these events do in fact count, and
943 * we need to programm all 4 events.
11164cd4 944 */
351af072 945static void intel_pmu_nhm_workaround(void)
11164cd4 946{
351af072
ZY		 947 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
948 static const unsigned long nhm_magic[4] = {
949 0x4300B5,
950 0x4300D2,
951 0x4300B1,
952 0x4300B1
953 };
954 struct perf_event *event;
955 int i;
11164cd4 956
351af072
ZY		 957 /*
958 * The Errata requires below steps:
959 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
960 * 2) Configure 4 PERFEVTSELx with the magic events and clear
961 * the corresponding PMCx;
962 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
963 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
964 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
965 */
11164cd4 966
351af072
ZY		 967 /*
968 * The real steps we choose are a little different from above.
969 * A) To reduce MSR operations, we don't run step 1) as they
970 * are already cleared before this function is called;
971 * B) Call x86_perf_event_update to save PMCx before configuring
972 * PERFEVTSELx with magic number;
973 * C) With step 5), we do clear only when the PERFEVTSELx is
974 * not used currently.
975 * D) Call x86_perf_event_set_period to restore PMCx;
976 */
11164cd4 977
351af072
ZY		 978 /* We always operate 4 pairs of PERF Counters */
979 for (i = 0; i < 4; i++) {
980 event = cpuc->events[i];
981 if (event)
982 x86_perf_event_update(event);
983 }
11164cd4 984
351af072
ZY		 985 for (i = 0; i < 4; i++) {
986 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
987 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
988 }
989
990 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
991 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 992
351af072
ZY		 993 for (i = 0; i < 4; i++) {
994 event = cpuc->events[i];
995
996 if (event) {
997 x86_perf_event_set_period(event);
31fa58af 998 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 999 ARCH_PERFMON_EVENTSEL_ENABLE);
1000 } else
1001 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1002 }
351af072
ZY		 1003}
1004
1005static void intel_pmu_nhm_enable_all(int added)
1006{
1007 if (added)
1008 intel_pmu_nhm_workaround();
11164cd4
PZ		 1009 intel_pmu_enable_all(added);
1010}
1011
f22f54f4
PZ		 1012static inline u64 intel_pmu_get_status(void)
1013{
1014 u64 status;
1015
1016 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1017
1018 return status;
1019}
1020
1021static inline void intel_pmu_ack_status(u64 ack)
1022{
1023 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1024}
1025
ca037701 1026static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1027{
15c7ad51 1028 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1029 u64 ctrl_val, mask;
1030
1031 mask = 0xfULL << (idx * 4);
1032
1033 rdmsrl(hwc->config_base, ctrl_val);
1034 ctrl_val &= ~mask;
7645a24c 1035 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1036}
1037
ca037701 1038static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1039{
aff3d91a 1040 struct hw_perf_event *hwc = &event->hw;
144d31e6 1041 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1042
15c7ad51 1043 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1044 intel_pmu_disable_bts();
1045 intel_pmu_drain_bts_buffer();
1046 return;
1047 }
1048
144d31e6
GN		 1049 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1050 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
1051
60ce0fbd
SE		 1052 /*
1053 * must disable before any actual event
1054 * because any event may be combined with LBR
1055 */
1056 if (intel_pmu_needs_lbr_smpl(event))
1057 intel_pmu_lbr_disable(event);
1058
f22f54f4 1059 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1060 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1061 return;
1062 }
1063
aff3d91a 1064 x86_pmu_disable_event(event);
ca037701 1065
ab608344 1066 if (unlikely(event->attr.precise_ip))
ef21f683 1067 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1068}
1069
ca037701 1070static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1071{
15c7ad51 1072 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1073 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1074
1075 /*
1076 * Enable IRQ generation (0x8),
1077 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1078 * if requested:
1079 */
1080 bits = 0x8ULL;
1081 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1082 bits |= 0x2;
1083 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1084 bits |= 0x1;
1085
1086 /*
1087 * ANY bit is supported in v3 and up
1088 */
1089 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1090 bits |= 0x4;
1091
1092 bits <<= (idx * 4);
1093 mask = 0xfULL << (idx * 4);
1094
1095 rdmsrl(hwc->config_base, ctrl_val);
1096 ctrl_val &= ~mask;
1097 ctrl_val |= bits;
7645a24c 1098 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1099}
1100
aff3d91a 1101static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1102{
aff3d91a 1103 struct hw_perf_event *hwc = &event->hw;
144d31e6 1104 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
aff3d91a 1105
15c7ad51 1106 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1107 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1108 return;
1109
1110 intel_pmu_enable_bts(hwc->config);
1111 return;
1112 }
60ce0fbd
SE		 1113 /*
1114 * must enabled before any actual event
1115 * because any event may be combined with LBR
1116 */
1117 if (intel_pmu_needs_lbr_smpl(event))
1118 intel_pmu_lbr_enable(event);
f22f54f4 1119
144d31e6
GN		 1120 if (event->attr.exclude_host)
1121 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1122 if (event->attr.exclude_guest)
1123 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1124
f22f54f4 1125 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1126 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1127 return;
1128 }
1129
ab608344 1130 if (unlikely(event->attr.precise_ip))
ef21f683 1131 intel_pmu_pebs_enable(event);
ca037701 1132
31fa58af 1133 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1134}
1135
1136/*
1137 * Save and restart an expired event. Called by NMI contexts,
1138 * so it has to be careful about preempting normal event ops:
1139 */
de0428a7 1140int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 1141{
cc2ad4ba
PZ		 1142 x86_perf_event_update(event);
1143 return x86_perf_event_set_period(event);
f22f54f4
PZ		 1144}
1145
1146static void intel_pmu_reset(void)
1147{
0a3aee0d 1148 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 1149 unsigned long flags;
1150 int idx;
1151
948b1bb8 1152 if (!x86_pmu.num_counters)
f22f54f4
PZ		 1153 return;
1154
1155 local_irq_save(flags);
1156
c767a54b 1157 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 1158
948b1bb8 1159 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 1160 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
1161 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 1162 }
948b1bb8 1163 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 1164 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 1165
f22f54f4
PZ		 1166 if (ds)
1167 ds->bts_index = ds->bts_buffer_base;
1168
1169 local_irq_restore(flags);
1170}
1171
1172/*
1173 * This handler is triggered by the local APIC, so the APIC IRQ handling
1174 * rules apply:
1175 */
1176static int intel_pmu_handle_irq(struct pt_regs *regs)
1177{
1178 struct perf_sample_data data;
1179 struct cpu_hw_events *cpuc;
1180 int bit, loops;
2e556b5b 1181 u64 status;
b0b2072d 1182 int handled;
f22f54f4 1183
f22f54f4
PZ		 1184 cpuc = &__get_cpu_var(cpu_hw_events);
1185
2bce5dac
DZ		 1186 /*
1187 * Some chipsets need to unmask the LVTPC in a particular spot
1188 * inside the nmi handler. As a result, the unmasking was pushed
1189 * into all the nmi handlers.
1190 *
1191 * This handler doesn't seem to have any issues with the unmasking
1192 * so it was left at the top.
1193 */
1194 apic_write(APIC_LVTPC, APIC_DM_NMI);
1195
3fb2b8dd 1196 intel_pmu_disable_all();
b0b2072d 1197 handled = intel_pmu_drain_bts_buffer();
f22f54f4
PZ		 1198 status = intel_pmu_get_status();
1199 if (!status) {
11164cd4 1200 intel_pmu_enable_all(0);
b0b2072d 1201 return handled;
f22f54f4
PZ		 1202 }
1203
1204 loops = 0;
1205again:
2e556b5b 1206 intel_pmu_ack_status(status);
f22f54f4 1207 if (++loops > 100) {
ae0def05
DH		 1208 static bool warned = false;
1209 if (!warned) {
1210 WARN(1, "perfevents: irq loop stuck!\n");
1211 perf_event_print_debug();
1212 warned = true;
1213 }
f22f54f4 1214 intel_pmu_reset();
3fb2b8dd 1215 goto done;
f22f54f4
PZ		 1216 }
1217
1218 inc_irq_stat(apic_perf_irqs);
ca037701 1219
caff2bef
PZ		 1220 intel_pmu_lbr_read();
1221
ca037701
PZ		 1222 /*
1223 * PEBS overflow sets bit 62 in the global status register
1224 */
de725dec
PZ		 1225 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
1226 handled++;
ca037701 1227 x86_pmu.drain_pebs(regs);
de725dec 1228 }
ca037701 1229
984b3f57 1230 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 1231 struct perf_event *event = cpuc->events[bit];
1232
de725dec
PZ		 1233 handled++;
1234
f22f54f4
PZ		 1235 if (!test_bit(bit, cpuc->active_mask))
1236 continue;
1237
1238 if (!intel_pmu_save_and_restart(event))
1239 continue;
1240
fd0d000b 1241 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 1242
60ce0fbd
SE		 1243 if (has_branch_stack(event))
1244 data.br_stack = &cpuc->lbr_stack;
1245
a8b0ca17 1246 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 1247 x86_pmu_stop(event, 0);
f22f54f4
PZ		 1248 }
1249
f22f54f4
PZ		 1250 /*
1251 * Repeat if there is more work to be done:
1252 */
1253 status = intel_pmu_get_status();
1254 if (status)
1255 goto again;
1256
3fb2b8dd 1257done:
11164cd4 1258 intel_pmu_enable_all(0);
de725dec 1259 return handled;
f22f54f4
PZ		 1260}
1261
f22f54f4 1262static struct event_constraint *
ca037701 1263intel_bts_constraints(struct perf_event *event)
f22f54f4 1264{
ca037701
PZ		 1265 struct hw_perf_event *hwc = &event->hw;
1266 unsigned int hw_event, bts_event;
f22f54f4 1267
18a073a3
PZ		 1268 if (event->attr.freq)
1269 return NULL;
1270
ca037701
PZ		 1271 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
1272 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 1273
ca037701 1274 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 1275 return &bts_constraint;
ca037701 1276
f22f54f4
PZ		 1277 return NULL;
1278}
1279
5a425294 1280static int intel_alt_er(int idx)
b79e8941
PZ		 1281{
1282 if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
5a425294 1283 return idx;
b79e8941 1284
5a425294
PZ		 1285 if (idx == EXTRA_REG_RSP_0)
1286 return EXTRA_REG_RSP_1;
1287
1288 if (idx == EXTRA_REG_RSP_1)
1289 return EXTRA_REG_RSP_0;
1290
1291 return idx;
1292}
1293
1294static void intel_fixup_er(struct perf_event *event, int idx)
1295{
1296 event->hw.extra_reg.idx = idx;
1297
1298 if (idx == EXTRA_REG_RSP_0) {
b79e8941
PZ		 1299 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1300 event->hw.config |= 0x01b7;
b79e8941 1301 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 1302 } else if (idx == EXTRA_REG_RSP_1) {
1303 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
1304 event->hw.config |= 0x01bb;
1305 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 1306 }
b79e8941
PZ		 1307}
1308
efc9f05d
SE		 1309/*
1310 * manage allocation of shared extra msr for certain events
1311 *
1312 * sharing can be:
1313 * per-cpu: to be shared between the various events on a single PMU
1314 * per-core: per-cpu + shared by HT threads
1315 */
a7e3ed1e 1316static struct event_constraint *
efc9f05d 1317__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 1318 struct perf_event *event,
1319 struct hw_perf_event_extra *reg)
a7e3ed1e 1320{
efc9f05d 1321 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 1322 struct er_account *era;
cd8a38d3 1323 unsigned long flags;
5a425294 1324 int idx = reg->idx;
a7e3ed1e 1325
5a425294
PZ		 1326 /*
1327 * reg->alloc can be set due to existing state, so for fake cpuc we
1328 * need to ignore this, otherwise we might fail to allocate proper fake
1329 * state for this extra reg constraint. Also see the comment below.
1330 */
1331 if (reg->alloc && !cpuc->is_fake)
b36817e8 1332 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 1333
b79e8941 1334again:
5a425294 1335 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 1336 /*
1337 * we use spin_lock_irqsave() to avoid lockdep issues when
1338 * passing a fake cpuc
1339 */
1340 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 1341
1342 if (!atomic_read(&era->ref) || era->config == reg->config) {
1343
5a425294
PZ		 1344 /*
1345 * If its a fake cpuc -- as per validate_{group,event}() we
1346 * shouldn't touch event state and we can avoid doing so
1347 * since both will only call get_event_constraints() once
1348 * on each event, this avoids the need for reg->alloc.
1349 *
1350 * Not doing the ER fixup will only result in era->reg being
1351 * wrong, but since we won't actually try and program hardware
1352 * this isn't a problem either.
1353 */
1354 if (!cpuc->is_fake) {
1355 if (idx != reg->idx)
1356 intel_fixup_er(event, idx);
1357
1358 /*
1359 * x86_schedule_events() can call get_event_constraints()
1360 * multiple times on events in the case of incremental
1361 * scheduling(). reg->alloc ensures we only do the ER
1362 * allocation once.
1363 */
1364 reg->alloc = 1;
1365 }
1366
efc9f05d
SE		 1367 /* lock in msr value */
1368 era->config = reg->config;
1369 era->reg = reg->reg;
1370
1371 /* one more user */
1372 atomic_inc(&era->ref);
1373
a7e3ed1e 1374 /*
b36817e8
SE		 1375 * need to call x86_get_event_constraint()
1376 * to check if associated event has constraints
a7e3ed1e 1377 */
b36817e8 1378 c = NULL;
5a425294
PZ		 1379 } else {
1380 idx = intel_alt_er(idx);
1381 if (idx != reg->idx) {
1382 raw_spin_unlock_irqrestore(&era->lock, flags);
1383 goto again;
1384 }
a7e3ed1e 1385 }
cd8a38d3 1386 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 1387
efc9f05d
SE		 1388 return c;
1389}
1390
1391static void
1392__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
1393 struct hw_perf_event_extra *reg)
1394{
1395 struct er_account *era;
1396
1397 /*
5a425294
PZ		 1398 * Only put constraint if extra reg was actually allocated. Also takes
1399 * care of event which do not use an extra shared reg.
1400 *
1401 * Also, if this is a fake cpuc we shouldn't touch any event state
1402 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
1403 * either since it'll be thrown out.
efc9f05d 1404 */
5a425294 1405 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 1406 return;
1407
1408 era = &cpuc->shared_regs->regs[reg->idx];
1409
1410 /* one fewer user */
1411 atomic_dec(&era->ref);
1412
1413 /* allocate again next time */
1414 reg->alloc = 0;
1415}
1416
1417static struct event_constraint *
1418intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
1419 struct perf_event *event)
1420{
b36817e8
SE		 1421 struct event_constraint *c = NULL, *d;
1422 struct hw_perf_event_extra *xreg, *breg;
1423
1424 xreg = &event->hw.extra_reg;
1425 if (xreg->idx != EXTRA_REG_NONE) {
1426 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
1427 if (c == &emptyconstraint)
1428 return c;
1429 }
1430 breg = &event->hw.branch_reg;
1431 if (breg->idx != EXTRA_REG_NONE) {
1432 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
1433 if (d == &emptyconstraint) {
1434 __intel_shared_reg_put_constraints(cpuc, xreg);
1435 c = d;
1436 }
1437 }
efc9f05d 1438 return c;
a7e3ed1e
AK		 1439}
1440
de0428a7
KW		 1441struct event_constraint *
1442x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1443{
1444 struct event_constraint *c;
1445
1446 if (x86_pmu.event_constraints) {
1447 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3
SE		 1448 if ((event->hw.config & c->cmask) == c->code) {
1449 /* hw.flags zeroed at initialization */
1450 event->hw.flags |= c->flags;
de0428a7 1451 return c;
9fac2cf3 1452 }
de0428a7
KW		 1453 }
1454 }
1455
1456 return &unconstrained;
1457}
1458
f22f54f4
PZ		 1459static struct event_constraint *
1460intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1461{
1462 struct event_constraint *c;
1463
ca037701
PZ		 1464 c = intel_bts_constraints(event);
1465 if (c)
1466 return c;
1467
1468 c = intel_pebs_constraints(event);
f22f54f4
PZ		 1469 if (c)
1470 return c;
1471
efc9f05d 1472 c = intel_shared_regs_constraints(cpuc, event);
a7e3ed1e
AK		 1473 if (c)
1474 return c;
1475
f22f54f4
PZ		 1476 return x86_get_event_constraints(cpuc, event);
1477}
1478
efc9f05d
SE		 1479static void
1480intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 1481 struct perf_event *event)
1482{
efc9f05d 1483 struct hw_perf_event_extra *reg;
a7e3ed1e 1484
efc9f05d
SE		 1485 reg = &event->hw.extra_reg;
1486 if (reg->idx != EXTRA_REG_NONE)
1487 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 1488
1489 reg = &event->hw.branch_reg;
1490 if (reg->idx != EXTRA_REG_NONE)
1491 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 1492}
a7e3ed1e 1493
efc9f05d
SE		 1494static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
1495 struct perf_event *event)
1496{
9fac2cf3 1497 event->hw.flags = 0;
efc9f05d 1498 intel_put_shared_regs_event_constraints(cpuc, event);
a7e3ed1e
AK		 1499}
1500
0780c927 1501static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 1502{
0780c927 1503 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 1504 /*
1505 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1506 * (0x003c) so that we can use it with PEBS.
1507 *
1508 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1509 * PEBS capable. However we can use INST_RETIRED.ANY_P
1510 * (0x00c0), which is a PEBS capable event, to get the same
1511 * count.
1512 *
1513 * INST_RETIRED.ANY_P counts the number of cycles that retires
1514 * CNTMASK instructions. By setting CNTMASK to a value (16)
1515 * larger than the maximum number of instructions that can be
1516 * retired per cycle (4) and then inverting the condition, we
1517 * count all cycles that retire 16 or less instructions, which
1518 * is every cycle.
1519 *
1520 * Thereby we gain a PEBS capable cycle counter.
1521 */
f9b4eeb8
PZ		 1522 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
1523
0780c927
PZ		 1524 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1525 event->hw.config = alt_config;
1526 }
1527}
1528
1529static void intel_pebs_aliases_snb(struct perf_event *event)
1530{
1531 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
1532 /*
1533 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
1534 * (0x003c) so that we can use it with PEBS.
1535 *
1536 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
1537 * PEBS capable. However we can use UOPS_RETIRED.ALL
1538 * (0x01c2), which is a PEBS capable event, to get the same
1539 * count.
1540 *
1541 * UOPS_RETIRED.ALL counts the number of cycles that retires
1542 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
1543 * larger than the maximum number of micro-ops that can be
1544 * retired per cycle (4) and then inverting the condition, we
1545 * count all cycles that retire 16 or less micro-ops, which
1546 * is every cycle.
1547 *
1548 * Thereby we gain a PEBS capable cycle counter.
1549 */
1550 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 1551
1552 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
1553 event->hw.config = alt_config;
1554 }
0780c927
PZ		 1555}
1556
1557static int intel_pmu_hw_config(struct perf_event *event)
1558{
1559 int ret = x86_pmu_hw_config(event);
1560
1561 if (ret)
1562 return ret;
1563
1564 if (event->attr.precise_ip && x86_pmu.pebs_aliases)
1565 x86_pmu.pebs_aliases(event);
7639dae0 1566
60ce0fbd
SE		 1567 if (intel_pmu_needs_lbr_smpl(event)) {
1568 ret = intel_pmu_setup_lbr_filter(event);
1569 if (ret)
1570 return ret;
1571 }
1572
b4cdc5c2
PZ		 1573 if (event->attr.type != PERF_TYPE_RAW)
1574 return 0;
1575
1576 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
1577 return 0;
1578
1579 if (x86_pmu.version < 3)
1580 return -EINVAL;
1581
1582 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
1583 return -EACCES;
1584
1585 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
1586
1587 return 0;
1588}
1589
144d31e6
GN		 1590struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
1591{
1592 if (x86_pmu.guest_get_msrs)
1593 return x86_pmu.guest_get_msrs(nr);
1594 *nr = 0;
1595 return NULL;
1596}
1597EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
1598
1599static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
1600{
1601 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1602 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1603
1604 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
1605 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
1606 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 1607 /*
1608 * If PMU counter has PEBS enabled it is not enough to disable counter
1609 * on a guest entry since PEBS memory write can overshoot guest entry
1610 * and corrupt guest memory. Disabling PEBS solves the problem.
1611 */
1612 arr[1].msr = MSR_IA32_PEBS_ENABLE;
1613 arr[1].host = cpuc->pebs_enabled;
1614 arr[1].guest = 0;
144d31e6 1615
26a4f3c0 1616 *nr = 2;
144d31e6
GN		 1617 return arr;
1618}
1619
1620static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
1621{
1622 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1623 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
1624 int idx;
1625
1626 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1627 struct perf_event *event = cpuc->events[idx];
1628
1629 arr[idx].msr = x86_pmu_config_addr(idx);
1630 arr[idx].host = arr[idx].guest = 0;
1631
1632 if (!test_bit(idx, cpuc->active_mask))
1633 continue;
1634
1635 arr[idx].host = arr[idx].guest =
1636 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
1637
1638 if (event->attr.exclude_host)
1639 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1640 else if (event->attr.exclude_guest)
1641 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
1642 }
1643
1644 *nr = x86_pmu.num_counters;
1645 return arr;
1646}
1647
1648static void core_pmu_enable_event(struct perf_event *event)
1649{
1650 if (!event->attr.exclude_host)
1651 x86_pmu_enable_event(event);
1652}
1653
1654static void core_pmu_enable_all(int added)
1655{
1656 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1657 int idx;
1658
1659 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1660 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
1661
1662 if (!test_bit(idx, cpuc->active_mask) ||
1663 cpuc->events[idx]->attr.exclude_host)
1664 continue;
1665
1666 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
1667 }
1668}
1669
3a632cb2
AK		 1670static int hsw_hw_config(struct perf_event *event)
1671{
1672 int ret = intel_pmu_hw_config(event);
1673
1674 if (ret)
1675 return ret;
1676 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
1677 return 0;
1678 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
1679
1680 /*
1681 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
1682 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
1683 * this combination.
1684 */
1685 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
1686 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
1687 event->attr.precise_ip > 0))
1688 return -EOPNOTSUPP;
1689
1690 return 0;
1691}
1692
1693static struct event_constraint counter2_constraint =
1694 EVENT_CONSTRAINT(0, 0x4, 0);
1695
1696static struct event_constraint *
1697hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1698{
1699 struct event_constraint *c = intel_get_event_constraints(cpuc, event);
1700
1701 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
1702 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
1703 if (c->idxmsk64 & (1U << 2))
1704 return &counter2_constraint;
1705 return &emptyconstraint;
1706 }
1707
1708 return c;
1709}
1710
641cc938
JO		 1711PMU_FORMAT_ATTR(event, "config:0-7" );
1712PMU_FORMAT_ATTR(umask, "config:8-15" );
1713PMU_FORMAT_ATTR(edge, "config:18" );
1714PMU_FORMAT_ATTR(pc, "config:19" );
1715PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
1716PMU_FORMAT_ATTR(inv, "config:23" );
1717PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 1718PMU_FORMAT_ATTR(in_tx, "config:32");
1719PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 1720
1721static struct attribute *intel_arch_formats_attr[] = {
1722 &format_attr_event.attr,
1723 &format_attr_umask.attr,
1724 &format_attr_edge.attr,
1725 &format_attr_pc.attr,
1726 &format_attr_inv.attr,
1727 &format_attr_cmask.attr,
1728 NULL,
1729};
1730
0bf79d44
JO		 1731ssize_t intel_event_sysfs_show(char *page, u64 config)
1732{
1733 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
1734
1735 return x86_event_sysfs_show(page, config, event);
1736}
1737
caaa8be3 1738static __initconst const struct x86_pmu core_pmu = {
f22f54f4
PZ		 1739 .name = "core",
1740 .handle_irq = x86_pmu_handle_irq,
1741 .disable_all = x86_pmu_disable_all,
144d31e6
GN		 1742 .enable_all = core_pmu_enable_all,
1743 .enable = core_pmu_enable_event,
f22f54f4 1744 .disable = x86_pmu_disable_event,
b4cdc5c2 1745 .hw_config = x86_pmu_hw_config,
a072738e 1746 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1747 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1748 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1749 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1750 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1751 .apic = 1,
1752 /*
1753 * Intel PMCs cannot be accessed sanely above 32 bit width,
1754 * so we install an artificial 1<<31 period regardless of
1755 * the generic event period:
1756 */
1757 .max_period = (1ULL << 31) - 1,
1758 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1759 .put_event_constraints = intel_put_event_constraints,
f22f54f4 1760 .event_constraints = intel_core_event_constraints,
144d31e6 1761 .guest_get_msrs = core_guest_get_msrs,
641cc938 1762 .format_attrs = intel_arch_formats_attr,
0bf79d44 1763 .events_sysfs_show = intel_event_sysfs_show,
f22f54f4
PZ		 1764};
1765
de0428a7 1766struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 1767{
1768 struct intel_shared_regs *regs;
1769 int i;
1770
1771 regs = kzalloc_node(sizeof(struct intel_shared_regs),
1772 GFP_KERNEL, cpu_to_node(cpu));
1773 if (regs) {
1774 /*
1775 * initialize the locks to keep lockdep happy
1776 */
1777 for (i = 0; i < EXTRA_REG_MAX; i++)
1778 raw_spin_lock_init(&regs->regs[i].lock);
1779
1780 regs->core_id = -1;
1781 }
1782 return regs;
1783}
1784
a7e3ed1e
AK		 1785static int intel_pmu_cpu_prepare(int cpu)
1786{
1787 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1788
b36817e8 1789 if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map))
69092624
LM		 1790 return NOTIFY_OK;
1791
efc9f05d
SE		 1792 cpuc->shared_regs = allocate_shared_regs(cpu);
1793 if (!cpuc->shared_regs)
a7e3ed1e
AK		 1794 return NOTIFY_BAD;
1795
a7e3ed1e
AK		 1796 return NOTIFY_OK;
1797}
1798
74846d35
PZ		 1799static void intel_pmu_cpu_starting(int cpu)
1800{
a7e3ed1e
AK		 1801 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1802 int core_id = topology_core_id(cpu);
1803 int i;
1804
69092624
LM		 1805 init_debug_store_on_cpu(cpu);
1806 /*
1807 * Deal with CPUs that don't clear their LBRs on power-up.
1808 */
1809 intel_pmu_lbr_reset();
1810
b36817e8
SE		 1811 cpuc->lbr_sel = NULL;
1812
1813 if (!cpuc->shared_regs)
69092624
LM		 1814 return;
1815
b36817e8
SE		 1816 if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) {
1817 for_each_cpu(i, topology_thread_cpumask(cpu)) {
1818 struct intel_shared_regs *pc;
a7e3ed1e 1819
b36817e8
SE		 1820 pc = per_cpu(cpu_hw_events, i).shared_regs;
1821 if (pc && pc->core_id == core_id) {
1822 cpuc->kfree_on_online = cpuc->shared_regs;
1823 cpuc->shared_regs = pc;
1824 break;
1825 }
a7e3ed1e 1826 }
b36817e8
SE		 1827 cpuc->shared_regs->core_id = core_id;
1828 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 1829 }
1830
b36817e8
SE		 1831 if (x86_pmu.lbr_sel_map)
1832 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
74846d35
PZ		 1833}
1834
1835static void intel_pmu_cpu_dying(int cpu)
1836{
a7e3ed1e 1837 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
efc9f05d 1838 struct intel_shared_regs *pc;
a7e3ed1e 1839
efc9f05d 1840 pc = cpuc->shared_regs;
a7e3ed1e
AK		 1841 if (pc) {
1842 if (pc->core_id == -1 || --pc->refcnt == 0)
1843 kfree(pc);
efc9f05d 1844 cpuc->shared_regs = NULL;
a7e3ed1e
AK		 1845 }
1846
74846d35
PZ		 1847 fini_debug_store_on_cpu(cpu);
1848}
1849
d010b332
SE		 1850static void intel_pmu_flush_branch_stack(void)
1851{
1852 /*
1853 * Intel LBR does not tag entries with the
1854 * PID of the current task, then we need to
1855 * flush it on ctxsw
1856 * For now, we simply reset it
1857 */
1858 if (x86_pmu.lbr_nr)
1859 intel_pmu_lbr_reset();
1860}
1861
641cc938
JO		 1862PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
1863
a63fcab4
SE		 1864PMU_FORMAT_ATTR(ldlat, "config1:0-15");
1865
641cc938
JO		 1866static struct attribute *intel_arch3_formats_attr[] = {
1867 &format_attr_event.attr,
1868 &format_attr_umask.attr,
1869 &format_attr_edge.attr,
1870 &format_attr_pc.attr,
1871 &format_attr_any.attr,
1872 &format_attr_inv.attr,
1873 &format_attr_cmask.attr,
3a632cb2
AK		 1874 &format_attr_in_tx.attr,
1875 &format_attr_in_tx_cp.attr,
641cc938
JO		 1876
1877 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 1878 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 1879 NULL,
1880};
1881
caaa8be3 1882static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 1883 .name = "Intel",
1884 .handle_irq = intel_pmu_handle_irq,
1885 .disable_all = intel_pmu_disable_all,
1886 .enable_all = intel_pmu_enable_all,
1887 .enable = intel_pmu_enable_event,
1888 .disable = intel_pmu_disable_event,
b4cdc5c2 1889 .hw_config = intel_pmu_hw_config,
a072738e 1890 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 1891 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
1892 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
1893 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 1894 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
1895 .apic = 1,
1896 /*
1897 * Intel PMCs cannot be accessed sanely above 32 bit width,
1898 * so we install an artificial 1<<31 period regardless of
1899 * the generic event period:
1900 */
1901 .max_period = (1ULL << 31) - 1,
3f6da390 1902 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 1903 .put_event_constraints = intel_put_event_constraints,
0780c927 1904 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 1905
641cc938 1906 .format_attrs = intel_arch3_formats_attr,
0bf79d44 1907 .events_sysfs_show = intel_event_sysfs_show,
641cc938 1908
a7e3ed1e 1909 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 1910 .cpu_starting = intel_pmu_cpu_starting,
1911 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 1912 .guest_get_msrs = intel_guest_get_msrs,
d010b332 1913 .flush_branch_stack = intel_pmu_flush_branch_stack,
f22f54f4
PZ		 1914};
1915
c1d6f42f 1916static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 1917{
1918 /*
1919 * PEBS is unreliable due to:
1920 *
1921 * AJ67 - PEBS may experience CPL leaks
1922 * AJ68 - PEBS PMI may be delayed by one event
1923 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
1924 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
1925 *
1926 * AJ67 could be worked around by restricting the OS/USR flags.
1927 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
1928 *
1929 * AJ106 could possibly be worked around by not allowing LBR
1930 * usage from PEBS, including the fixup.
1931 * AJ68 could possibly be worked around by always programming
ec75a716 1932 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 1933 *
1934 * But taken together it might just make sense to not enable PEBS on
1935 * these chips.
1936 */
c767a54b 1937 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 1938 x86_pmu.pebs = 0;
1939 x86_pmu.pebs_constraints = NULL;
1940}
1941
c93dc84c
PZ		 1942static int intel_snb_pebs_broken(int cpu)
1943{
1944 u32 rev = UINT_MAX; /* default to broken for unknown models */
1945
1946 switch (cpu_data(cpu).x86_model) {
1947 case 42: /* SNB */
1948 rev = 0x28;
1949 break;
1950
1951 case 45: /* SNB-EP */
1952 switch (cpu_data(cpu).x86_mask) {
1953 case 6: rev = 0x618; break;
1954 case 7: rev = 0x70c; break;
1955 }
1956 }
1957
1958 return (cpu_data(cpu).microcode < rev);
1959}
1960
1961static void intel_snb_check_microcode(void)
1962{
1963 int pebs_broken = 0;
1964 int cpu;
1965
1966 get_online_cpus();
1967 for_each_online_cpu(cpu) {
1968 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
1969 break;
1970 }
1971 put_online_cpus();
1972
1973 if (pebs_broken == x86_pmu.pebs_broken)
1974 return;
1975
1976 /*
1977 * Serialized by the microcode lock..
1978 */
1979 if (x86_pmu.pebs_broken) {
1980 pr_info("PEBS enabled due to microcode update\n");
1981 x86_pmu.pebs_broken = 0;
1982 } else {
1983 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
1984 x86_pmu.pebs_broken = 1;
1985 }
1986}
1987
c1d6f42f 1988static __init void intel_sandybridge_quirk(void)
6a600a8b 1989{
c93dc84c
PZ		 1990 x86_pmu.check_microcode = intel_snb_check_microcode;
1991 intel_snb_check_microcode();
6a600a8b
PZ		 1992}
1993
c1d6f42f
PZ		 1994static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
1995 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
1996 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
1997 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
1998 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
1999 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
2000 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
2001 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 2002};
2003
c1d6f42f
PZ		 2004static __init void intel_arch_events_quirk(void)
2005{
2006 int bit;
2007
2008 /* disable event that reported as not presend by cpuid */
2009 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
2010 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 2011 pr_warn("CPUID marked event: \'%s\' unavailable\n",
2012 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 2013 }
2014}
2015
2016static __init void intel_nehalem_quirk(void)
2017{
2018 union cpuid10_ebx ebx;
2019
2020 ebx.full = x86_pmu.events_maskl;
2021 if (ebx.split.no_branch_misses_retired) {
2022 /*
2023 * Erratum AAJ80 detected, we work it around by using
2024 * the BR_MISP_EXEC.ANY event. This will over-count
2025 * branch-misses, but it's still much better than the
2026 * architectural event which is often completely bogus:
2027 */
2028 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
2029 ebx.split.no_branch_misses_retired = 0;
2030 x86_pmu.events_maskl = ebx.full;
c767a54b 2031 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 2032 }
2033}
2034
de0428a7 2035__init int intel_pmu_init(void)
f22f54f4
PZ		 2036{
2037 union cpuid10_edx edx;
2038 union cpuid10_eax eax;
ffb871bc 2039 union cpuid10_ebx ebx;
a1eac7ac 2040 struct event_constraint *c;
f22f54f4 2041 unsigned int unused;
f22f54f4
PZ		 2042 int version;
2043
2044 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 2045 switch (boot_cpu_data.x86) {
2046 case 0x6:
2047 return p6_pmu_init();
e717bf4e
VW		 2048 case 0xb:
2049 return knc_pmu_init();
a072738e
CG		 2050 case 0xf:
2051 return p4_pmu_init();
2052 }
f22f54f4 2053 return -ENODEV;
f22f54f4
PZ		 2054 }
2055
2056 /*
2057 * Check whether the Architectural PerfMon supports
2058 * Branch Misses Retired hw_event or not.
2059 */
ffb871bc
GN		 2060 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
2061 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 2062 return -ENODEV;
2063
2064 version = eax.split.version_id;
2065 if (version < 2)
2066 x86_pmu = core_pmu;
2067 else
2068 x86_pmu = intel_pmu;
2069
2070 x86_pmu.version = version;
948b1bb8
RR		 2071 x86_pmu.num_counters = eax.split.num_counters;
2072 x86_pmu.cntval_bits = eax.split.bit_width;
2073 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 2074
c1d6f42f
PZ		 2075 x86_pmu.events_maskl = ebx.full;
2076 x86_pmu.events_mask_len = eax.split.mask_length;
2077
70ab7003
AK		 2078 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
2079
f22f54f4
PZ		 2080 /*
2081 * Quirk: v2 perfmon does not report fixed-purpose events, so
2082 * assume at least 3 events:
2083 */
2084 if (version > 1)
948b1bb8 2085 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
f22f54f4 2086
8db909a7
PZ		 2087 /*
2088 * v2 and above have a perf capabilities MSR
2089 */
2090 if (version > 1) {
2091 u64 capabilities;
2092
2093 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
2094 x86_pmu.intel_cap.capabilities = capabilities;
2095 }
2096
ca037701
PZ		 2097 intel_ds_init();
2098
c1d6f42f
PZ		 2099 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
2100
f22f54f4
PZ		 2101 /*
2102 * Install the hw-cache-events table:
2103 */
2104 switch (boot_cpu_data.x86_model) {
2105 case 14: /* 65 nm core solo/duo, "Yonah" */
2106 pr_cont("Core events, ");
2107 break;
2108
2109 case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
c1d6f42f 2110 x86_add_quirk(intel_clovertown_quirk);
f22f54f4
PZ		 2111 case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2112 case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2113 case 29: /* six-core 45 nm xeon "Dunnington" */
2114 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2115 sizeof(hw_cache_event_ids));
2116
caff2bef
PZ		 2117 intel_pmu_lbr_init_core();
2118
f22f54f4 2119 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 2120 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 2121 pr_cont("Core2 events, ");
2122 break;
2123
2124 case 26: /* 45 nm nehalem, "Bloomfield" */
2125 case 30: /* 45 nm nehalem, "Lynnfield" */
134fbadf 2126 case 46: /* 45 nm nehalem-ex, "Beckton" */
f22f54f4
PZ		 2127 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2128 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2129 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2130 sizeof(hw_cache_extra_regs));
f22f54f4 2131
caff2bef
PZ		 2132 intel_pmu_lbr_init_nhm();
2133
f22f54f4 2134 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 2135 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 2136 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 2137 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 2138
f20093ee
SE		 2139 x86_pmu.cpu_events = nhm_events_attrs;
2140
91fc4cc0 2141 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2142 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2143 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 2144 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2145 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2146 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 2147
c1d6f42f 2148 x86_add_quirk(intel_nehalem_quirk);
ec75a716 2149
11164cd4 2150 pr_cont("Nehalem events, ");
f22f54f4 2151 break;
caff2bef 2152
b622d644 2153 case 28: /* Atom */
0927b482
SL		 2154 case 38: /* Lincroft */
2155 case 39: /* Penwell */
2156 case 53: /* Cloverview */
2157 case 54: /* Cedarview */
f22f54f4
PZ		 2158 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2159 sizeof(hw_cache_event_ids));
2160
caff2bef
PZ		 2161 intel_pmu_lbr_init_atom();
2162
f22f54f4 2163 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 2164 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
f22f54f4
PZ		 2165 pr_cont("Atom events, ");
2166 break;
2167
2168 case 37: /* 32 nm nehalem, "Clarkdale" */
2169 case 44: /* 32 nm nehalem, "Gulftown" */
b2508e82 2170 case 47: /* 32 nm Xeon E7 */
f22f54f4
PZ		 2171 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
2172 sizeof(hw_cache_event_ids));
e994d7d2
AK		 2173 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
2174 sizeof(hw_cache_extra_regs));
f22f54f4 2175
caff2bef
PZ		 2176 intel_pmu_lbr_init_nhm();
2177
f22f54f4 2178 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 2179 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 2180 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 2181 x86_pmu.extra_regs = intel_westmere_extra_regs;
b79e8941 2182 x86_pmu.er_flags |= ERF_HAS_RSP_1;
30112039 2183
f20093ee
SE		 2184 x86_pmu.cpu_events = nhm_events_attrs;
2185
30112039 2186 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 2187 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2188 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 2189 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 2190 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2191 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 2192
f22f54f4
PZ		 2193 pr_cont("Westmere events, ");
2194 break;
b622d644 2195
b06b3d49 2196 case 42: /* SandyBridge */
a34668f6 2197 case 45: /* SandyBridge, "Romely-EP" */
47a8863d 2198 x86_add_quirk(intel_sandybridge_quirk);
b06b3d49
LM		 2199 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2200 sizeof(hw_cache_event_ids));
74e6543f
YZ		 2201 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2202 sizeof(hw_cache_extra_regs));
b06b3d49 2203
c5cc2cd9 2204 intel_pmu_lbr_init_snb();
b06b3d49
LM		 2205
2206 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 2207 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 2208 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2209 if (boot_cpu_data.x86_model == 45)
2210 x86_pmu.extra_regs = intel_snbep_extra_regs;
2211 else
2212 x86_pmu.extra_regs = intel_snb_extra_regs;
ee89cbc2 2213 /* all extra regs are per-cpu when HT is on */
b79e8941
PZ		 2214 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2215 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
e04d1b23 2216
f20093ee
SE		 2217 x86_pmu.cpu_events = snb_events_attrs;
2218
e04d1b23 2219 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 2220 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2221 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2222 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 2223 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
2224 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 2225
b06b3d49
LM		 2226 pr_cont("SandyBridge events, ");
2227 break;
20a36e39 2228 case 58: /* IvyBridge */
923d8697 2229 case 62: /* IvyBridge EP */
20a36e39
SE		 2230 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
2231 sizeof(hw_cache_event_ids));
2232 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
2233 sizeof(hw_cache_extra_regs));
2234
2235 intel_pmu_lbr_init_snb();
2236
69943182 2237 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39
SE		 2238 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
2239 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
f1923820
SE		 2240 if (boot_cpu_data.x86_model == 62)
2241 x86_pmu.extra_regs = intel_snbep_extra_regs;
2242 else
2243 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39
SE		 2244 /* all extra regs are per-cpu when HT is on */
2245 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2246 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2247
f20093ee
SE		 2248 x86_pmu.cpu_events = snb_events_attrs;
2249
20a36e39
SE		 2250 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
2251 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
2252 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
2253
2254 pr_cont("IvyBridge events, ");
2255 break;
2256
b06b3d49 2257
3a632cb2
AK		 2258 case 60: /* Haswell Client */
2259 case 70:
2260 case 71:
2261 case 63:
2262 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
2263 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
2264
2265 intel_pmu_lbr_init_snb();
2266
2267 x86_pmu.event_constraints = intel_hsw_event_constraints;
2268
2269 x86_pmu.extra_regs = intel_snb_extra_regs;
2270 /* all extra regs are per-cpu when HT is on */
2271 x86_pmu.er_flags |= ERF_HAS_RSP_1;
2272 x86_pmu.er_flags |= ERF_NO_HT_SHARING;
2273
2274 x86_pmu.hw_config = hsw_hw_config;
2275 x86_pmu.get_event_constraints = hsw_get_event_constraints;
2276 pr_cont("Haswell events, ");
2277 break;
2278
f22f54f4 2279 default:
0af3ac1f
AK		 2280 switch (x86_pmu.version) {
2281 case 1:
2282 x86_pmu.event_constraints = intel_v1_event_constraints;
2283 pr_cont("generic architected perfmon v1, ");
2284 break;
2285 default:
2286 /*
2287 * default constraints for v2 and up
2288 */
2289 x86_pmu.event_constraints = intel_gen_event_constraints;
2290 pr_cont("generic architected perfmon, ");
2291 break;
2292 }
f22f54f4 2293 }
ffb871bc 2294
a1eac7ac
RR		 2295 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
2296 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2297 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
2298 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
2299 }
2300 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
2301
2302 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
2303 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2304 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
2305 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
2306 }
2307
2308 x86_pmu.intel_ctrl |=
2309 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
2310
2311 if (x86_pmu.event_constraints) {
2312 /*
2313 * event on fixed counter2 (REF_CYCLES) only works on this
2314 * counter, so do not extend mask to generic counters
2315 */
2316 for_each_event_constraint(c, x86_pmu.event_constraints) {
3a632cb2 2317 if (c->cmask != FIXED_EVENT_FLAGS
a1eac7ac
RR		 2318 || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
2319 continue;
2320 }
2321
2322 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
2323 c->weight += x86_pmu.num_counters;
2324 }
2325 }
2326
f22f54f4
PZ		 2327 return 0;
2328}
Linux 6.x block layer and io_uring tree(s)