Commit | Line | Data |
---|---|---|
a7e3ed1e | 1 | /* |
efc9f05d SE |
2 | * Per core/cpu state |
3 | * | |
4 | * Used to coordinate shared registers between HT threads or | |
5 | * among events on a single PMU. | |
a7e3ed1e | 6 | */ |
de0428a7 | 7 | |
c767a54b JP |
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
9 | ||
de0428a7 KW |
10 | #include <linux/stddef.h> |
11 | #include <linux/types.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/slab.h> | |
69c60c88 | 14 | #include <linux/export.h> |
de0428a7 KW |
15 | |
16 | #include <asm/hardirq.h> | |
17 | #include <asm/apic.h> | |
18 | ||
19 | #include "perf_event.h" | |
a7e3ed1e | 20 | |
f22f54f4 | 21 | /* |
b622d644 | 22 | * Intel PerfMon, used on Core and later. |
f22f54f4 | 23 | */ |
ec75a716 | 24 | static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = |
f22f54f4 | 25 | { |
c3b7cdf1 PE |
26 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
27 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | |
28 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | |
29 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | |
30 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | |
31 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | |
32 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | |
33 | [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ | |
f22f54f4 PZ |
34 | }; |
35 | ||
5c543e3c | 36 | static struct event_constraint intel_core_event_constraints[] __read_mostly = |
f22f54f4 PZ |
37 | { |
38 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
39 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
40 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
41 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
42 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
43 | INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */ | |
44 | EVENT_CONSTRAINT_END | |
45 | }; | |
46 | ||
5c543e3c | 47 | static struct event_constraint intel_core2_event_constraints[] __read_mostly = |
f22f54f4 | 48 | { |
b622d644 PZ |
49 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
50 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 51 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
52 | INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */ |
53 | INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */ | |
54 | INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */ | |
55 | INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */ | |
56 | INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */ | |
57 | INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */ | |
58 | INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */ | |
59 | INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */ | |
b622d644 | 60 | INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */ |
f22f54f4 PZ |
61 | INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */ |
62 | EVENT_CONSTRAINT_END | |
63 | }; | |
64 | ||
5c543e3c | 65 | static struct event_constraint intel_nehalem_event_constraints[] __read_mostly = |
f22f54f4 | 66 | { |
b622d644 PZ |
67 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
68 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 69 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
70 | INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */ |
71 | INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */ | |
72 | INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */ | |
73 | INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */ | |
74 | INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */ | |
75 | INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */ | |
76 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ | |
77 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
78 | EVENT_CONSTRAINT_END | |
79 | }; | |
80 | ||
5c543e3c | 81 | static struct extra_reg intel_nehalem_extra_regs[] __read_mostly = |
a7e3ed1e | 82 | { |
efc9f05d | 83 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), |
a7e3ed1e AK |
84 | EVENT_EXTRA_END |
85 | }; | |
86 | ||
5c543e3c | 87 | static struct event_constraint intel_westmere_event_constraints[] __read_mostly = |
f22f54f4 | 88 | { |
b622d644 PZ |
89 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
90 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 91 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
92 | INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */ |
93 | INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */ | |
94 | INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */ | |
d1100770 | 95 | INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */ |
f22f54f4 PZ |
96 | EVENT_CONSTRAINT_END |
97 | }; | |
98 | ||
5c543e3c | 99 | static struct event_constraint intel_snb_event_constraints[] __read_mostly = |
b06b3d49 LM |
100 | { |
101 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ | |
102 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 103 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
b06b3d49 | 104 | INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */ |
b06b3d49 LM |
105 | INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ |
106 | INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */ | |
107 | EVENT_CONSTRAINT_END | |
108 | }; | |
109 | ||
5c543e3c | 110 | static struct extra_reg intel_westmere_extra_regs[] __read_mostly = |
a7e3ed1e | 111 | { |
efc9f05d SE |
112 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0), |
113 | INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1), | |
a7e3ed1e AK |
114 | EVENT_EXTRA_END |
115 | }; | |
116 | ||
0af3ac1f AK |
117 | static struct event_constraint intel_v1_event_constraints[] __read_mostly = |
118 | { | |
119 | EVENT_CONSTRAINT_END | |
120 | }; | |
121 | ||
5c543e3c | 122 | static struct event_constraint intel_gen_event_constraints[] __read_mostly = |
f22f54f4 | 123 | { |
b622d644 PZ |
124 | FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */ |
125 | FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ | |
cd09c0c4 | 126 | FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ |
f22f54f4 PZ |
127 | EVENT_CONSTRAINT_END |
128 | }; | |
129 | ||
ee89cbc2 SE |
130 | static struct extra_reg intel_snb_extra_regs[] __read_mostly = { |
131 | INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0), | |
132 | INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1), | |
133 | EVENT_EXTRA_END | |
134 | }; | |
135 | ||
f22f54f4 PZ |
136 | static u64 intel_pmu_event_map(int hw_event) |
137 | { | |
138 | return intel_perfmon_event_map[hw_event]; | |
139 | } | |
140 | ||
b06b3d49 LM |
141 | static __initconst const u64 snb_hw_cache_event_ids |
142 | [PERF_COUNT_HW_CACHE_MAX] | |
143 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
144 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
145 | { | |
146 | [ C(L1D) ] = { | |
147 | [ C(OP_READ) ] = { | |
148 | [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */ | |
149 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */ | |
150 | }, | |
151 | [ C(OP_WRITE) ] = { | |
152 | [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */ | |
153 | [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */ | |
154 | }, | |
155 | [ C(OP_PREFETCH) ] = { | |
156 | [ C(RESULT_ACCESS) ] = 0x0, | |
157 | [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */ | |
158 | }, | |
159 | }, | |
160 | [ C(L1I ) ] = { | |
161 | [ C(OP_READ) ] = { | |
162 | [ C(RESULT_ACCESS) ] = 0x0, | |
163 | [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */ | |
164 | }, | |
165 | [ C(OP_WRITE) ] = { | |
166 | [ C(RESULT_ACCESS) ] = -1, | |
167 | [ C(RESULT_MISS) ] = -1, | |
168 | }, | |
169 | [ C(OP_PREFETCH) ] = { | |
170 | [ C(RESULT_ACCESS) ] = 0x0, | |
171 | [ C(RESULT_MISS) ] = 0x0, | |
172 | }, | |
173 | }, | |
174 | [ C(LL ) ] = { | |
b06b3d49 | 175 | [ C(OP_READ) ] = { |
63b6a675 | 176 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
b06b3d49 | 177 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
178 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
179 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
180 | }, |
181 | [ C(OP_WRITE) ] = { | |
63b6a675 | 182 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
b06b3d49 | 183 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
184 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ |
185 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
186 | }, |
187 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 188 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
b06b3d49 | 189 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
190 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
191 | [ C(RESULT_MISS) ] = 0x01b7, | |
b06b3d49 LM |
192 | }, |
193 | }, | |
194 | [ C(DTLB) ] = { | |
195 | [ C(OP_READ) ] = { | |
196 | [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */ | |
197 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */ | |
198 | }, | |
199 | [ C(OP_WRITE) ] = { | |
200 | [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */ | |
201 | [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */ | |
202 | }, | |
203 | [ C(OP_PREFETCH) ] = { | |
204 | [ C(RESULT_ACCESS) ] = 0x0, | |
205 | [ C(RESULT_MISS) ] = 0x0, | |
206 | }, | |
207 | }, | |
208 | [ C(ITLB) ] = { | |
209 | [ C(OP_READ) ] = { | |
210 | [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */ | |
211 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */ | |
212 | }, | |
213 | [ C(OP_WRITE) ] = { | |
214 | [ C(RESULT_ACCESS) ] = -1, | |
215 | [ C(RESULT_MISS) ] = -1, | |
216 | }, | |
217 | [ C(OP_PREFETCH) ] = { | |
218 | [ C(RESULT_ACCESS) ] = -1, | |
219 | [ C(RESULT_MISS) ] = -1, | |
220 | }, | |
221 | }, | |
222 | [ C(BPU ) ] = { | |
223 | [ C(OP_READ) ] = { | |
224 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
225 | [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */ | |
226 | }, | |
227 | [ C(OP_WRITE) ] = { | |
228 | [ C(RESULT_ACCESS) ] = -1, | |
229 | [ C(RESULT_MISS) ] = -1, | |
230 | }, | |
231 | [ C(OP_PREFETCH) ] = { | |
232 | [ C(RESULT_ACCESS) ] = -1, | |
233 | [ C(RESULT_MISS) ] = -1, | |
234 | }, | |
235 | }, | |
89d6c0b5 PZ |
236 | [ C(NODE) ] = { |
237 | [ C(OP_READ) ] = { | |
238 | [ C(RESULT_ACCESS) ] = -1, | |
239 | [ C(RESULT_MISS) ] = -1, | |
240 | }, | |
241 | [ C(OP_WRITE) ] = { | |
242 | [ C(RESULT_ACCESS) ] = -1, | |
243 | [ C(RESULT_MISS) ] = -1, | |
244 | }, | |
245 | [ C(OP_PREFETCH) ] = { | |
246 | [ C(RESULT_ACCESS) ] = -1, | |
247 | [ C(RESULT_MISS) ] = -1, | |
248 | }, | |
249 | }, | |
250 | ||
b06b3d49 LM |
251 | }; |
252 | ||
caaa8be3 | 253 | static __initconst const u64 westmere_hw_cache_event_ids |
f22f54f4 PZ |
254 | [PERF_COUNT_HW_CACHE_MAX] |
255 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
256 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
257 | { | |
258 | [ C(L1D) ] = { | |
259 | [ C(OP_READ) ] = { | |
260 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
261 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
262 | }, | |
263 | [ C(OP_WRITE) ] = { | |
264 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
265 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
266 | }, | |
267 | [ C(OP_PREFETCH) ] = { | |
268 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
269 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
270 | }, | |
271 | }, | |
272 | [ C(L1I ) ] = { | |
273 | [ C(OP_READ) ] = { | |
274 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
275 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
276 | }, | |
277 | [ C(OP_WRITE) ] = { | |
278 | [ C(RESULT_ACCESS) ] = -1, | |
279 | [ C(RESULT_MISS) ] = -1, | |
280 | }, | |
281 | [ C(OP_PREFETCH) ] = { | |
282 | [ C(RESULT_ACCESS) ] = 0x0, | |
283 | [ C(RESULT_MISS) ] = 0x0, | |
284 | }, | |
285 | }, | |
286 | [ C(LL ) ] = { | |
287 | [ C(OP_READ) ] = { | |
63b6a675 | 288 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
e994d7d2 | 289 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
290 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ |
291 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 292 | }, |
e994d7d2 AK |
293 | /* |
294 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
295 | * on RFO. | |
296 | */ | |
f22f54f4 | 297 | [ C(OP_WRITE) ] = { |
63b6a675 PZ |
298 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
299 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
300 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
e994d7d2 | 301 | [ C(RESULT_MISS) ] = 0x01b7, |
f22f54f4 PZ |
302 | }, |
303 | [ C(OP_PREFETCH) ] = { | |
63b6a675 | 304 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
e994d7d2 | 305 | [ C(RESULT_ACCESS) ] = 0x01b7, |
63b6a675 PZ |
306 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ |
307 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
308 | }, |
309 | }, | |
310 | [ C(DTLB) ] = { | |
311 | [ C(OP_READ) ] = { | |
312 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ | |
313 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
314 | }, | |
315 | [ C(OP_WRITE) ] = { | |
316 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ | |
317 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
318 | }, | |
319 | [ C(OP_PREFETCH) ] = { | |
320 | [ C(RESULT_ACCESS) ] = 0x0, | |
321 | [ C(RESULT_MISS) ] = 0x0, | |
322 | }, | |
323 | }, | |
324 | [ C(ITLB) ] = { | |
325 | [ C(OP_READ) ] = { | |
326 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
327 | [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */ | |
328 | }, | |
329 | [ C(OP_WRITE) ] = { | |
330 | [ C(RESULT_ACCESS) ] = -1, | |
331 | [ C(RESULT_MISS) ] = -1, | |
332 | }, | |
333 | [ C(OP_PREFETCH) ] = { | |
334 | [ C(RESULT_ACCESS) ] = -1, | |
335 | [ C(RESULT_MISS) ] = -1, | |
336 | }, | |
337 | }, | |
338 | [ C(BPU ) ] = { | |
339 | [ C(OP_READ) ] = { | |
340 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
341 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
342 | }, | |
343 | [ C(OP_WRITE) ] = { | |
344 | [ C(RESULT_ACCESS) ] = -1, | |
345 | [ C(RESULT_MISS) ] = -1, | |
346 | }, | |
347 | [ C(OP_PREFETCH) ] = { | |
348 | [ C(RESULT_ACCESS) ] = -1, | |
349 | [ C(RESULT_MISS) ] = -1, | |
350 | }, | |
351 | }, | |
89d6c0b5 PZ |
352 | [ C(NODE) ] = { |
353 | [ C(OP_READ) ] = { | |
354 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
355 | [ C(RESULT_MISS) ] = 0x01b7, | |
356 | }, | |
357 | [ C(OP_WRITE) ] = { | |
358 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
359 | [ C(RESULT_MISS) ] = 0x01b7, | |
360 | }, | |
361 | [ C(OP_PREFETCH) ] = { | |
362 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
363 | [ C(RESULT_MISS) ] = 0x01b7, | |
364 | }, | |
365 | }, | |
f22f54f4 PZ |
366 | }; |
367 | ||
e994d7d2 | 368 | /* |
63b6a675 PZ |
369 | * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits; |
370 | * See IA32 SDM Vol 3B 30.6.1.3 | |
e994d7d2 AK |
371 | */ |
372 | ||
63b6a675 PZ |
373 | #define NHM_DMND_DATA_RD (1 << 0) |
374 | #define NHM_DMND_RFO (1 << 1) | |
375 | #define NHM_DMND_IFETCH (1 << 2) | |
376 | #define NHM_DMND_WB (1 << 3) | |
377 | #define NHM_PF_DATA_RD (1 << 4) | |
378 | #define NHM_PF_DATA_RFO (1 << 5) | |
379 | #define NHM_PF_IFETCH (1 << 6) | |
380 | #define NHM_OFFCORE_OTHER (1 << 7) | |
381 | #define NHM_UNCORE_HIT (1 << 8) | |
382 | #define NHM_OTHER_CORE_HIT_SNP (1 << 9) | |
383 | #define NHM_OTHER_CORE_HITM (1 << 10) | |
384 | /* reserved */ | |
385 | #define NHM_REMOTE_CACHE_FWD (1 << 12) | |
386 | #define NHM_REMOTE_DRAM (1 << 13) | |
387 | #define NHM_LOCAL_DRAM (1 << 14) | |
388 | #define NHM_NON_DRAM (1 << 15) | |
389 | ||
87e24f4b PZ |
390 | #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD) |
391 | #define NHM_REMOTE (NHM_REMOTE_DRAM) | |
63b6a675 PZ |
392 | |
393 | #define NHM_DMND_READ (NHM_DMND_DATA_RD) | |
394 | #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB) | |
395 | #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO) | |
396 | ||
397 | #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM) | |
87e24f4b | 398 | #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD) |
63b6a675 | 399 | #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS) |
e994d7d2 AK |
400 | |
401 | static __initconst const u64 nehalem_hw_cache_extra_regs | |
402 | [PERF_COUNT_HW_CACHE_MAX] | |
403 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
404 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
405 | { | |
406 | [ C(LL ) ] = { | |
407 | [ C(OP_READ) ] = { | |
63b6a675 PZ |
408 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS, |
409 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS, | |
e994d7d2 AK |
410 | }, |
411 | [ C(OP_WRITE) ] = { | |
63b6a675 PZ |
412 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS, |
413 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS, | |
e994d7d2 AK |
414 | }, |
415 | [ C(OP_PREFETCH) ] = { | |
63b6a675 PZ |
416 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS, |
417 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS, | |
e994d7d2 | 418 | }, |
89d6c0b5 PZ |
419 | }, |
420 | [ C(NODE) ] = { | |
421 | [ C(OP_READ) ] = { | |
87e24f4b PZ |
422 | [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE, |
423 | [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE, | |
89d6c0b5 PZ |
424 | }, |
425 | [ C(OP_WRITE) ] = { | |
87e24f4b PZ |
426 | [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE, |
427 | [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE, | |
89d6c0b5 PZ |
428 | }, |
429 | [ C(OP_PREFETCH) ] = { | |
87e24f4b PZ |
430 | [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE, |
431 | [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE, | |
89d6c0b5 PZ |
432 | }, |
433 | }, | |
e994d7d2 AK |
434 | }; |
435 | ||
caaa8be3 | 436 | static __initconst const u64 nehalem_hw_cache_event_ids |
f22f54f4 PZ |
437 | [PERF_COUNT_HW_CACHE_MAX] |
438 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
439 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
440 | { | |
441 | [ C(L1D) ] = { | |
442 | [ C(OP_READ) ] = { | |
f4929bd3 PZ |
443 | [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */ |
444 | [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */ | |
f22f54f4 PZ |
445 | }, |
446 | [ C(OP_WRITE) ] = { | |
f4929bd3 PZ |
447 | [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */ |
448 | [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */ | |
f22f54f4 PZ |
449 | }, |
450 | [ C(OP_PREFETCH) ] = { | |
451 | [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */ | |
452 | [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */ | |
453 | }, | |
454 | }, | |
455 | [ C(L1I ) ] = { | |
456 | [ C(OP_READ) ] = { | |
457 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
458 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
459 | }, | |
460 | [ C(OP_WRITE) ] = { | |
461 | [ C(RESULT_ACCESS) ] = -1, | |
462 | [ C(RESULT_MISS) ] = -1, | |
463 | }, | |
464 | [ C(OP_PREFETCH) ] = { | |
465 | [ C(RESULT_ACCESS) ] = 0x0, | |
466 | [ C(RESULT_MISS) ] = 0x0, | |
467 | }, | |
468 | }, | |
469 | [ C(LL ) ] = { | |
470 | [ C(OP_READ) ] = { | |
e994d7d2 AK |
471 | /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */ |
472 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
473 | /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */ | |
474 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 | 475 | }, |
e994d7d2 AK |
476 | /* |
477 | * Use RFO, not WRITEBACK, because a write miss would typically occur | |
478 | * on RFO. | |
479 | */ | |
f22f54f4 | 480 | [ C(OP_WRITE) ] = { |
e994d7d2 AK |
481 | /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */ |
482 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
483 | /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */ | |
484 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
485 | }, |
486 | [ C(OP_PREFETCH) ] = { | |
e994d7d2 AK |
487 | /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */ |
488 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
489 | /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */ | |
490 | [ C(RESULT_MISS) ] = 0x01b7, | |
f22f54f4 PZ |
491 | }, |
492 | }, | |
493 | [ C(DTLB) ] = { | |
494 | [ C(OP_READ) ] = { | |
495 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
496 | [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */ | |
497 | }, | |
498 | [ C(OP_WRITE) ] = { | |
499 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
500 | [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */ | |
501 | }, | |
502 | [ C(OP_PREFETCH) ] = { | |
503 | [ C(RESULT_ACCESS) ] = 0x0, | |
504 | [ C(RESULT_MISS) ] = 0x0, | |
505 | }, | |
506 | }, | |
507 | [ C(ITLB) ] = { | |
508 | [ C(OP_READ) ] = { | |
509 | [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */ | |
510 | [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */ | |
511 | }, | |
512 | [ C(OP_WRITE) ] = { | |
513 | [ C(RESULT_ACCESS) ] = -1, | |
514 | [ C(RESULT_MISS) ] = -1, | |
515 | }, | |
516 | [ C(OP_PREFETCH) ] = { | |
517 | [ C(RESULT_ACCESS) ] = -1, | |
518 | [ C(RESULT_MISS) ] = -1, | |
519 | }, | |
520 | }, | |
521 | [ C(BPU ) ] = { | |
522 | [ C(OP_READ) ] = { | |
523 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */ | |
524 | [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */ | |
525 | }, | |
526 | [ C(OP_WRITE) ] = { | |
527 | [ C(RESULT_ACCESS) ] = -1, | |
528 | [ C(RESULT_MISS) ] = -1, | |
529 | }, | |
530 | [ C(OP_PREFETCH) ] = { | |
531 | [ C(RESULT_ACCESS) ] = -1, | |
532 | [ C(RESULT_MISS) ] = -1, | |
533 | }, | |
534 | }, | |
89d6c0b5 PZ |
535 | [ C(NODE) ] = { |
536 | [ C(OP_READ) ] = { | |
537 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
538 | [ C(RESULT_MISS) ] = 0x01b7, | |
539 | }, | |
540 | [ C(OP_WRITE) ] = { | |
541 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
542 | [ C(RESULT_MISS) ] = 0x01b7, | |
543 | }, | |
544 | [ C(OP_PREFETCH) ] = { | |
545 | [ C(RESULT_ACCESS) ] = 0x01b7, | |
546 | [ C(RESULT_MISS) ] = 0x01b7, | |
547 | }, | |
548 | }, | |
f22f54f4 PZ |
549 | }; |
550 | ||
caaa8be3 | 551 | static __initconst const u64 core2_hw_cache_event_ids |
f22f54f4 PZ |
552 | [PERF_COUNT_HW_CACHE_MAX] |
553 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
554 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
555 | { | |
556 | [ C(L1D) ] = { | |
557 | [ C(OP_READ) ] = { | |
558 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */ | |
559 | [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */ | |
560 | }, | |
561 | [ C(OP_WRITE) ] = { | |
562 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */ | |
563 | [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */ | |
564 | }, | |
565 | [ C(OP_PREFETCH) ] = { | |
566 | [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */ | |
567 | [ C(RESULT_MISS) ] = 0, | |
568 | }, | |
569 | }, | |
570 | [ C(L1I ) ] = { | |
571 | [ C(OP_READ) ] = { | |
572 | [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */ | |
573 | [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */ | |
574 | }, | |
575 | [ C(OP_WRITE) ] = { | |
576 | [ C(RESULT_ACCESS) ] = -1, | |
577 | [ C(RESULT_MISS) ] = -1, | |
578 | }, | |
579 | [ C(OP_PREFETCH) ] = { | |
580 | [ C(RESULT_ACCESS) ] = 0, | |
581 | [ C(RESULT_MISS) ] = 0, | |
582 | }, | |
583 | }, | |
584 | [ C(LL ) ] = { | |
585 | [ C(OP_READ) ] = { | |
586 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
587 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
588 | }, | |
589 | [ C(OP_WRITE) ] = { | |
590 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
591 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
592 | }, | |
593 | [ C(OP_PREFETCH) ] = { | |
594 | [ C(RESULT_ACCESS) ] = 0, | |
595 | [ C(RESULT_MISS) ] = 0, | |
596 | }, | |
597 | }, | |
598 | [ C(DTLB) ] = { | |
599 | [ C(OP_READ) ] = { | |
600 | [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */ | |
601 | [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */ | |
602 | }, | |
603 | [ C(OP_WRITE) ] = { | |
604 | [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */ | |
605 | [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */ | |
606 | }, | |
607 | [ C(OP_PREFETCH) ] = { | |
608 | [ C(RESULT_ACCESS) ] = 0, | |
609 | [ C(RESULT_MISS) ] = 0, | |
610 | }, | |
611 | }, | |
612 | [ C(ITLB) ] = { | |
613 | [ C(OP_READ) ] = { | |
614 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
615 | [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */ | |
616 | }, | |
617 | [ C(OP_WRITE) ] = { | |
618 | [ C(RESULT_ACCESS) ] = -1, | |
619 | [ C(RESULT_MISS) ] = -1, | |
620 | }, | |
621 | [ C(OP_PREFETCH) ] = { | |
622 | [ C(RESULT_ACCESS) ] = -1, | |
623 | [ C(RESULT_MISS) ] = -1, | |
624 | }, | |
625 | }, | |
626 | [ C(BPU ) ] = { | |
627 | [ C(OP_READ) ] = { | |
628 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
629 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
630 | }, | |
631 | [ C(OP_WRITE) ] = { | |
632 | [ C(RESULT_ACCESS) ] = -1, | |
633 | [ C(RESULT_MISS) ] = -1, | |
634 | }, | |
635 | [ C(OP_PREFETCH) ] = { | |
636 | [ C(RESULT_ACCESS) ] = -1, | |
637 | [ C(RESULT_MISS) ] = -1, | |
638 | }, | |
639 | }, | |
640 | }; | |
641 | ||
caaa8be3 | 642 | static __initconst const u64 atom_hw_cache_event_ids |
f22f54f4 PZ |
643 | [PERF_COUNT_HW_CACHE_MAX] |
644 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
645 | [PERF_COUNT_HW_CACHE_RESULT_MAX] = | |
646 | { | |
647 | [ C(L1D) ] = { | |
648 | [ C(OP_READ) ] = { | |
649 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */ | |
650 | [ C(RESULT_MISS) ] = 0, | |
651 | }, | |
652 | [ C(OP_WRITE) ] = { | |
653 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */ | |
654 | [ C(RESULT_MISS) ] = 0, | |
655 | }, | |
656 | [ C(OP_PREFETCH) ] = { | |
657 | [ C(RESULT_ACCESS) ] = 0x0, | |
658 | [ C(RESULT_MISS) ] = 0, | |
659 | }, | |
660 | }, | |
661 | [ C(L1I ) ] = { | |
662 | [ C(OP_READ) ] = { | |
663 | [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */ | |
664 | [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */ | |
665 | }, | |
666 | [ C(OP_WRITE) ] = { | |
667 | [ C(RESULT_ACCESS) ] = -1, | |
668 | [ C(RESULT_MISS) ] = -1, | |
669 | }, | |
670 | [ C(OP_PREFETCH) ] = { | |
671 | [ C(RESULT_ACCESS) ] = 0, | |
672 | [ C(RESULT_MISS) ] = 0, | |
673 | }, | |
674 | }, | |
675 | [ C(LL ) ] = { | |
676 | [ C(OP_READ) ] = { | |
677 | [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */ | |
678 | [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */ | |
679 | }, | |
680 | [ C(OP_WRITE) ] = { | |
681 | [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */ | |
682 | [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */ | |
683 | }, | |
684 | [ C(OP_PREFETCH) ] = { | |
685 | [ C(RESULT_ACCESS) ] = 0, | |
686 | [ C(RESULT_MISS) ] = 0, | |
687 | }, | |
688 | }, | |
689 | [ C(DTLB) ] = { | |
690 | [ C(OP_READ) ] = { | |
691 | [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */ | |
692 | [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */ | |
693 | }, | |
694 | [ C(OP_WRITE) ] = { | |
695 | [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */ | |
696 | [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */ | |
697 | }, | |
698 | [ C(OP_PREFETCH) ] = { | |
699 | [ C(RESULT_ACCESS) ] = 0, | |
700 | [ C(RESULT_MISS) ] = 0, | |
701 | }, | |
702 | }, | |
703 | [ C(ITLB) ] = { | |
704 | [ C(OP_READ) ] = { | |
705 | [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */ | |
706 | [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */ | |
707 | }, | |
708 | [ C(OP_WRITE) ] = { | |
709 | [ C(RESULT_ACCESS) ] = -1, | |
710 | [ C(RESULT_MISS) ] = -1, | |
711 | }, | |
712 | [ C(OP_PREFETCH) ] = { | |
713 | [ C(RESULT_ACCESS) ] = -1, | |
714 | [ C(RESULT_MISS) ] = -1, | |
715 | }, | |
716 | }, | |
717 | [ C(BPU ) ] = { | |
718 | [ C(OP_READ) ] = { | |
719 | [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */ | |
720 | [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */ | |
721 | }, | |
722 | [ C(OP_WRITE) ] = { | |
723 | [ C(RESULT_ACCESS) ] = -1, | |
724 | [ C(RESULT_MISS) ] = -1, | |
725 | }, | |
726 | [ C(OP_PREFETCH) ] = { | |
727 | [ C(RESULT_ACCESS) ] = -1, | |
728 | [ C(RESULT_MISS) ] = -1, | |
729 | }, | |
730 | }, | |
731 | }; | |
732 | ||
60ce0fbd SE |
733 | static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event) |
734 | { | |
735 | /* user explicitly requested branch sampling */ | |
736 | if (has_branch_stack(event)) | |
737 | return true; | |
738 | ||
739 | /* implicit branch sampling to correct PEBS skid */ | |
740 | if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1) | |
741 | return true; | |
742 | ||
743 | return false; | |
744 | } | |
745 | ||
f22f54f4 PZ |
746 | static void intel_pmu_disable_all(void) |
747 | { | |
748 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
749 | ||
750 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
751 | ||
15c7ad51 | 752 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) |
f22f54f4 | 753 | intel_pmu_disable_bts(); |
ca037701 PZ |
754 | |
755 | intel_pmu_pebs_disable_all(); | |
caff2bef | 756 | intel_pmu_lbr_disable_all(); |
f22f54f4 PZ |
757 | } |
758 | ||
11164cd4 | 759 | static void intel_pmu_enable_all(int added) |
f22f54f4 PZ |
760 | { |
761 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
762 | ||
d329527e PZ |
763 | intel_pmu_pebs_enable_all(); |
764 | intel_pmu_lbr_enable_all(); | |
144d31e6 GN |
765 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, |
766 | x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); | |
f22f54f4 | 767 | |
15c7ad51 | 768 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { |
f22f54f4 | 769 | struct perf_event *event = |
15c7ad51 | 770 | cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
f22f54f4 PZ |
771 | |
772 | if (WARN_ON_ONCE(!event)) | |
773 | return; | |
774 | ||
775 | intel_pmu_enable_bts(event->hw.config); | |
776 | } | |
777 | } | |
778 | ||
11164cd4 PZ |
779 | /* |
780 | * Workaround for: | |
781 | * Intel Errata AAK100 (model 26) | |
782 | * Intel Errata AAP53 (model 30) | |
40b91cd1 | 783 | * Intel Errata BD53 (model 44) |
11164cd4 | 784 | * |
351af072 ZY |
785 | * The official story: |
786 | * These chips need to be 'reset' when adding counters by programming the | |
787 | * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either | |
788 | * in sequence on the same PMC or on different PMCs. | |
789 | * | |
790 | * In practise it appears some of these events do in fact count, and | |
791 | * we need to programm all 4 events. | |
11164cd4 | 792 | */ |
351af072 | 793 | static void intel_pmu_nhm_workaround(void) |
11164cd4 | 794 | { |
351af072 ZY |
795 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
796 | static const unsigned long nhm_magic[4] = { | |
797 | 0x4300B5, | |
798 | 0x4300D2, | |
799 | 0x4300B1, | |
800 | 0x4300B1 | |
801 | }; | |
802 | struct perf_event *event; | |
803 | int i; | |
11164cd4 | 804 | |
351af072 ZY |
805 | /* |
806 | * The Errata requires below steps: | |
807 | * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL; | |
808 | * 2) Configure 4 PERFEVTSELx with the magic events and clear | |
809 | * the corresponding PMCx; | |
810 | * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL; | |
811 | * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL; | |
812 | * 5) Clear 4 pairs of ERFEVTSELx and PMCx; | |
813 | */ | |
11164cd4 | 814 | |
351af072 ZY |
815 | /* |
816 | * The real steps we choose are a little different from above. | |
817 | * A) To reduce MSR operations, we don't run step 1) as they | |
818 | * are already cleared before this function is called; | |
819 | * B) Call x86_perf_event_update to save PMCx before configuring | |
820 | * PERFEVTSELx with magic number; | |
821 | * C) With step 5), we do clear only when the PERFEVTSELx is | |
822 | * not used currently. | |
823 | * D) Call x86_perf_event_set_period to restore PMCx; | |
824 | */ | |
11164cd4 | 825 | |
351af072 ZY |
826 | /* We always operate 4 pairs of PERF Counters */ |
827 | for (i = 0; i < 4; i++) { | |
828 | event = cpuc->events[i]; | |
829 | if (event) | |
830 | x86_perf_event_update(event); | |
831 | } | |
11164cd4 | 832 | |
351af072 ZY |
833 | for (i = 0; i < 4; i++) { |
834 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]); | |
835 | wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0); | |
836 | } | |
837 | ||
838 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf); | |
839 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0); | |
11164cd4 | 840 | |
351af072 ZY |
841 | for (i = 0; i < 4; i++) { |
842 | event = cpuc->events[i]; | |
843 | ||
844 | if (event) { | |
845 | x86_perf_event_set_period(event); | |
31fa58af | 846 | __x86_pmu_enable_event(&event->hw, |
351af072 ZY |
847 | ARCH_PERFMON_EVENTSEL_ENABLE); |
848 | } else | |
849 | wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0); | |
11164cd4 | 850 | } |
351af072 ZY |
851 | } |
852 | ||
853 | static void intel_pmu_nhm_enable_all(int added) | |
854 | { | |
855 | if (added) | |
856 | intel_pmu_nhm_workaround(); | |
11164cd4 PZ |
857 | intel_pmu_enable_all(added); |
858 | } | |
859 | ||
f22f54f4 PZ |
860 | static inline u64 intel_pmu_get_status(void) |
861 | { | |
862 | u64 status; | |
863 | ||
864 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
865 | ||
866 | return status; | |
867 | } | |
868 | ||
869 | static inline void intel_pmu_ack_status(u64 ack) | |
870 | { | |
871 | wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack); | |
872 | } | |
873 | ||
ca037701 | 874 | static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 875 | { |
15c7ad51 | 876 | int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
f22f54f4 PZ |
877 | u64 ctrl_val, mask; |
878 | ||
879 | mask = 0xfULL << (idx * 4); | |
880 | ||
881 | rdmsrl(hwc->config_base, ctrl_val); | |
882 | ctrl_val &= ~mask; | |
7645a24c | 883 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
884 | } |
885 | ||
ca037701 | 886 | static void intel_pmu_disable_event(struct perf_event *event) |
f22f54f4 | 887 | { |
aff3d91a | 888 | struct hw_perf_event *hwc = &event->hw; |
144d31e6 | 889 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
aff3d91a | 890 | |
15c7ad51 | 891 | if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { |
f22f54f4 PZ |
892 | intel_pmu_disable_bts(); |
893 | intel_pmu_drain_bts_buffer(); | |
894 | return; | |
895 | } | |
896 | ||
144d31e6 GN |
897 | cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx); |
898 | cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx); | |
899 | ||
60ce0fbd SE |
900 | /* |
901 | * must disable before any actual event | |
902 | * because any event may be combined with LBR | |
903 | */ | |
904 | if (intel_pmu_needs_lbr_smpl(event)) | |
905 | intel_pmu_lbr_disable(event); | |
906 | ||
f22f54f4 | 907 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
aff3d91a | 908 | intel_pmu_disable_fixed(hwc); |
f22f54f4 PZ |
909 | return; |
910 | } | |
911 | ||
aff3d91a | 912 | x86_pmu_disable_event(event); |
ca037701 | 913 | |
ab608344 | 914 | if (unlikely(event->attr.precise_ip)) |
ef21f683 | 915 | intel_pmu_pebs_disable(event); |
f22f54f4 PZ |
916 | } |
917 | ||
ca037701 | 918 | static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) |
f22f54f4 | 919 | { |
15c7ad51 | 920 | int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
f22f54f4 | 921 | u64 ctrl_val, bits, mask; |
f22f54f4 PZ |
922 | |
923 | /* | |
924 | * Enable IRQ generation (0x8), | |
925 | * and enable ring-3 counting (0x2) and ring-0 counting (0x1) | |
926 | * if requested: | |
927 | */ | |
928 | bits = 0x8ULL; | |
929 | if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) | |
930 | bits |= 0x2; | |
931 | if (hwc->config & ARCH_PERFMON_EVENTSEL_OS) | |
932 | bits |= 0x1; | |
933 | ||
934 | /* | |
935 | * ANY bit is supported in v3 and up | |
936 | */ | |
937 | if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) | |
938 | bits |= 0x4; | |
939 | ||
940 | bits <<= (idx * 4); | |
941 | mask = 0xfULL << (idx * 4); | |
942 | ||
943 | rdmsrl(hwc->config_base, ctrl_val); | |
944 | ctrl_val &= ~mask; | |
945 | ctrl_val |= bits; | |
7645a24c | 946 | wrmsrl(hwc->config_base, ctrl_val); |
f22f54f4 PZ |
947 | } |
948 | ||
aff3d91a | 949 | static void intel_pmu_enable_event(struct perf_event *event) |
f22f54f4 | 950 | { |
aff3d91a | 951 | struct hw_perf_event *hwc = &event->hw; |
144d31e6 | 952 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
aff3d91a | 953 | |
15c7ad51 | 954 | if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { |
0a3aee0d | 955 | if (!__this_cpu_read(cpu_hw_events.enabled)) |
f22f54f4 PZ |
956 | return; |
957 | ||
958 | intel_pmu_enable_bts(hwc->config); | |
959 | return; | |
960 | } | |
60ce0fbd SE |
961 | /* |
962 | * must enabled before any actual event | |
963 | * because any event may be combined with LBR | |
964 | */ | |
965 | if (intel_pmu_needs_lbr_smpl(event)) | |
966 | intel_pmu_lbr_enable(event); | |
f22f54f4 | 967 | |
144d31e6 GN |
968 | if (event->attr.exclude_host) |
969 | cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx); | |
970 | if (event->attr.exclude_guest) | |
971 | cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx); | |
972 | ||
f22f54f4 | 973 | if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { |
aff3d91a | 974 | intel_pmu_enable_fixed(hwc); |
f22f54f4 PZ |
975 | return; |
976 | } | |
977 | ||
ab608344 | 978 | if (unlikely(event->attr.precise_ip)) |
ef21f683 | 979 | intel_pmu_pebs_enable(event); |
ca037701 | 980 | |
31fa58af | 981 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f22f54f4 PZ |
982 | } |
983 | ||
984 | /* | |
985 | * Save and restart an expired event. Called by NMI contexts, | |
986 | * so it has to be careful about preempting normal event ops: | |
987 | */ | |
de0428a7 | 988 | int intel_pmu_save_and_restart(struct perf_event *event) |
f22f54f4 | 989 | { |
cc2ad4ba PZ |
990 | x86_perf_event_update(event); |
991 | return x86_perf_event_set_period(event); | |
f22f54f4 PZ |
992 | } |
993 | ||
994 | static void intel_pmu_reset(void) | |
995 | { | |
0a3aee0d | 996 | struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds); |
f22f54f4 PZ |
997 | unsigned long flags; |
998 | int idx; | |
999 | ||
948b1bb8 | 1000 | if (!x86_pmu.num_counters) |
f22f54f4 PZ |
1001 | return; |
1002 | ||
1003 | local_irq_save(flags); | |
1004 | ||
c767a54b | 1005 | pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); |
f22f54f4 | 1006 | |
948b1bb8 | 1007 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
715c85b1 PA |
1008 | wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); |
1009 | wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); | |
f22f54f4 | 1010 | } |
948b1bb8 | 1011 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) |
715c85b1 | 1012 | wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
948b1bb8 | 1013 | |
f22f54f4 PZ |
1014 | if (ds) |
1015 | ds->bts_index = ds->bts_buffer_base; | |
1016 | ||
1017 | local_irq_restore(flags); | |
1018 | } | |
1019 | ||
1020 | /* | |
1021 | * This handler is triggered by the local APIC, so the APIC IRQ handling | |
1022 | * rules apply: | |
1023 | */ | |
1024 | static int intel_pmu_handle_irq(struct pt_regs *regs) | |
1025 | { | |
1026 | struct perf_sample_data data; | |
1027 | struct cpu_hw_events *cpuc; | |
1028 | int bit, loops; | |
2e556b5b | 1029 | u64 status; |
b0b2072d | 1030 | int handled; |
f22f54f4 | 1031 | |
f22f54f4 PZ |
1032 | cpuc = &__get_cpu_var(cpu_hw_events); |
1033 | ||
2bce5dac DZ |
1034 | /* |
1035 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1036 | * inside the nmi handler. As a result, the unmasking was pushed | |
1037 | * into all the nmi handlers. | |
1038 | * | |
1039 | * This handler doesn't seem to have any issues with the unmasking | |
1040 | * so it was left at the top. | |
1041 | */ | |
1042 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1043 | ||
3fb2b8dd | 1044 | intel_pmu_disable_all(); |
b0b2072d | 1045 | handled = intel_pmu_drain_bts_buffer(); |
f22f54f4 PZ |
1046 | status = intel_pmu_get_status(); |
1047 | if (!status) { | |
11164cd4 | 1048 | intel_pmu_enable_all(0); |
b0b2072d | 1049 | return handled; |
f22f54f4 PZ |
1050 | } |
1051 | ||
1052 | loops = 0; | |
1053 | again: | |
2e556b5b | 1054 | intel_pmu_ack_status(status); |
f22f54f4 PZ |
1055 | if (++loops > 100) { |
1056 | WARN_ONCE(1, "perfevents: irq loop stuck!\n"); | |
1057 | perf_event_print_debug(); | |
1058 | intel_pmu_reset(); | |
3fb2b8dd | 1059 | goto done; |
f22f54f4 PZ |
1060 | } |
1061 | ||
1062 | inc_irq_stat(apic_perf_irqs); | |
ca037701 | 1063 | |
caff2bef PZ |
1064 | intel_pmu_lbr_read(); |
1065 | ||
ca037701 PZ |
1066 | /* |
1067 | * PEBS overflow sets bit 62 in the global status register | |
1068 | */ | |
de725dec PZ |
1069 | if (__test_and_clear_bit(62, (unsigned long *)&status)) { |
1070 | handled++; | |
ca037701 | 1071 | x86_pmu.drain_pebs(regs); |
de725dec | 1072 | } |
ca037701 | 1073 | |
984b3f57 | 1074 | for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) { |
f22f54f4 PZ |
1075 | struct perf_event *event = cpuc->events[bit]; |
1076 | ||
de725dec PZ |
1077 | handled++; |
1078 | ||
f22f54f4 PZ |
1079 | if (!test_bit(bit, cpuc->active_mask)) |
1080 | continue; | |
1081 | ||
1082 | if (!intel_pmu_save_and_restart(event)) | |
1083 | continue; | |
1084 | ||
fd0d000b | 1085 | perf_sample_data_init(&data, 0, event->hw.last_period); |
f22f54f4 | 1086 | |
60ce0fbd SE |
1087 | if (has_branch_stack(event)) |
1088 | data.br_stack = &cpuc->lbr_stack; | |
1089 | ||
a8b0ca17 | 1090 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1091 | x86_pmu_stop(event, 0); |
f22f54f4 PZ |
1092 | } |
1093 | ||
f22f54f4 PZ |
1094 | /* |
1095 | * Repeat if there is more work to be done: | |
1096 | */ | |
1097 | status = intel_pmu_get_status(); | |
1098 | if (status) | |
1099 | goto again; | |
1100 | ||
3fb2b8dd | 1101 | done: |
11164cd4 | 1102 | intel_pmu_enable_all(0); |
de725dec | 1103 | return handled; |
f22f54f4 PZ |
1104 | } |
1105 | ||
f22f54f4 | 1106 | static struct event_constraint * |
ca037701 | 1107 | intel_bts_constraints(struct perf_event *event) |
f22f54f4 | 1108 | { |
ca037701 PZ |
1109 | struct hw_perf_event *hwc = &event->hw; |
1110 | unsigned int hw_event, bts_event; | |
f22f54f4 | 1111 | |
18a073a3 PZ |
1112 | if (event->attr.freq) |
1113 | return NULL; | |
1114 | ||
ca037701 PZ |
1115 | hw_event = hwc->config & INTEL_ARCH_EVENT_MASK; |
1116 | bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); | |
f22f54f4 | 1117 | |
ca037701 | 1118 | if (unlikely(hw_event == bts_event && hwc->sample_period == 1)) |
f22f54f4 | 1119 | return &bts_constraint; |
ca037701 | 1120 | |
f22f54f4 PZ |
1121 | return NULL; |
1122 | } | |
1123 | ||
5a425294 | 1124 | static int intel_alt_er(int idx) |
b79e8941 PZ |
1125 | { |
1126 | if (!(x86_pmu.er_flags & ERF_HAS_RSP_1)) | |
5a425294 | 1127 | return idx; |
b79e8941 | 1128 | |
5a425294 PZ |
1129 | if (idx == EXTRA_REG_RSP_0) |
1130 | return EXTRA_REG_RSP_1; | |
1131 | ||
1132 | if (idx == EXTRA_REG_RSP_1) | |
1133 | return EXTRA_REG_RSP_0; | |
1134 | ||
1135 | return idx; | |
1136 | } | |
1137 | ||
1138 | static void intel_fixup_er(struct perf_event *event, int idx) | |
1139 | { | |
1140 | event->hw.extra_reg.idx = idx; | |
1141 | ||
1142 | if (idx == EXTRA_REG_RSP_0) { | |
b79e8941 PZ |
1143 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; |
1144 | event->hw.config |= 0x01b7; | |
b79e8941 | 1145 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; |
5a425294 PZ |
1146 | } else if (idx == EXTRA_REG_RSP_1) { |
1147 | event->hw.config &= ~INTEL_ARCH_EVENT_MASK; | |
1148 | event->hw.config |= 0x01bb; | |
1149 | event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; | |
b79e8941 | 1150 | } |
b79e8941 PZ |
1151 | } |
1152 | ||
efc9f05d SE |
1153 | /* |
1154 | * manage allocation of shared extra msr for certain events | |
1155 | * | |
1156 | * sharing can be: | |
1157 | * per-cpu: to be shared between the various events on a single PMU | |
1158 | * per-core: per-cpu + shared by HT threads | |
1159 | */ | |
a7e3ed1e | 1160 | static struct event_constraint * |
efc9f05d | 1161 | __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc, |
b36817e8 SE |
1162 | struct perf_event *event, |
1163 | struct hw_perf_event_extra *reg) | |
a7e3ed1e | 1164 | { |
efc9f05d | 1165 | struct event_constraint *c = &emptyconstraint; |
a7e3ed1e | 1166 | struct er_account *era; |
cd8a38d3 | 1167 | unsigned long flags; |
5a425294 | 1168 | int idx = reg->idx; |
a7e3ed1e | 1169 | |
5a425294 PZ |
1170 | /* |
1171 | * reg->alloc can be set due to existing state, so for fake cpuc we | |
1172 | * need to ignore this, otherwise we might fail to allocate proper fake | |
1173 | * state for this extra reg constraint. Also see the comment below. | |
1174 | */ | |
1175 | if (reg->alloc && !cpuc->is_fake) | |
b36817e8 | 1176 | return NULL; /* call x86_get_event_constraint() */ |
a7e3ed1e | 1177 | |
b79e8941 | 1178 | again: |
5a425294 | 1179 | era = &cpuc->shared_regs->regs[idx]; |
cd8a38d3 SE |
1180 | /* |
1181 | * we use spin_lock_irqsave() to avoid lockdep issues when | |
1182 | * passing a fake cpuc | |
1183 | */ | |
1184 | raw_spin_lock_irqsave(&era->lock, flags); | |
efc9f05d SE |
1185 | |
1186 | if (!atomic_read(&era->ref) || era->config == reg->config) { | |
1187 | ||
5a425294 PZ |
1188 | /* |
1189 | * If its a fake cpuc -- as per validate_{group,event}() we | |
1190 | * shouldn't touch event state and we can avoid doing so | |
1191 | * since both will only call get_event_constraints() once | |
1192 | * on each event, this avoids the need for reg->alloc. | |
1193 | * | |
1194 | * Not doing the ER fixup will only result in era->reg being | |
1195 | * wrong, but since we won't actually try and program hardware | |
1196 | * this isn't a problem either. | |
1197 | */ | |
1198 | if (!cpuc->is_fake) { | |
1199 | if (idx != reg->idx) | |
1200 | intel_fixup_er(event, idx); | |
1201 | ||
1202 | /* | |
1203 | * x86_schedule_events() can call get_event_constraints() | |
1204 | * multiple times on events in the case of incremental | |
1205 | * scheduling(). reg->alloc ensures we only do the ER | |
1206 | * allocation once. | |
1207 | */ | |
1208 | reg->alloc = 1; | |
1209 | } | |
1210 | ||
efc9f05d SE |
1211 | /* lock in msr value */ |
1212 | era->config = reg->config; | |
1213 | era->reg = reg->reg; | |
1214 | ||
1215 | /* one more user */ | |
1216 | atomic_inc(&era->ref); | |
1217 | ||
a7e3ed1e | 1218 | /* |
b36817e8 SE |
1219 | * need to call x86_get_event_constraint() |
1220 | * to check if associated event has constraints | |
a7e3ed1e | 1221 | */ |
b36817e8 | 1222 | c = NULL; |
5a425294 PZ |
1223 | } else { |
1224 | idx = intel_alt_er(idx); | |
1225 | if (idx != reg->idx) { | |
1226 | raw_spin_unlock_irqrestore(&era->lock, flags); | |
1227 | goto again; | |
1228 | } | |
a7e3ed1e | 1229 | } |
cd8a38d3 | 1230 | raw_spin_unlock_irqrestore(&era->lock, flags); |
a7e3ed1e | 1231 | |
efc9f05d SE |
1232 | return c; |
1233 | } | |
1234 | ||
1235 | static void | |
1236 | __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc, | |
1237 | struct hw_perf_event_extra *reg) | |
1238 | { | |
1239 | struct er_account *era; | |
1240 | ||
1241 | /* | |
5a425294 PZ |
1242 | * Only put constraint if extra reg was actually allocated. Also takes |
1243 | * care of event which do not use an extra shared reg. | |
1244 | * | |
1245 | * Also, if this is a fake cpuc we shouldn't touch any event state | |
1246 | * (reg->alloc) and we don't care about leaving inconsistent cpuc state | |
1247 | * either since it'll be thrown out. | |
efc9f05d | 1248 | */ |
5a425294 | 1249 | if (!reg->alloc || cpuc->is_fake) |
efc9f05d SE |
1250 | return; |
1251 | ||
1252 | era = &cpuc->shared_regs->regs[reg->idx]; | |
1253 | ||
1254 | /* one fewer user */ | |
1255 | atomic_dec(&era->ref); | |
1256 | ||
1257 | /* allocate again next time */ | |
1258 | reg->alloc = 0; | |
1259 | } | |
1260 | ||
1261 | static struct event_constraint * | |
1262 | intel_shared_regs_constraints(struct cpu_hw_events *cpuc, | |
1263 | struct perf_event *event) | |
1264 | { | |
b36817e8 SE |
1265 | struct event_constraint *c = NULL, *d; |
1266 | struct hw_perf_event_extra *xreg, *breg; | |
1267 | ||
1268 | xreg = &event->hw.extra_reg; | |
1269 | if (xreg->idx != EXTRA_REG_NONE) { | |
1270 | c = __intel_shared_reg_get_constraints(cpuc, event, xreg); | |
1271 | if (c == &emptyconstraint) | |
1272 | return c; | |
1273 | } | |
1274 | breg = &event->hw.branch_reg; | |
1275 | if (breg->idx != EXTRA_REG_NONE) { | |
1276 | d = __intel_shared_reg_get_constraints(cpuc, event, breg); | |
1277 | if (d == &emptyconstraint) { | |
1278 | __intel_shared_reg_put_constraints(cpuc, xreg); | |
1279 | c = d; | |
1280 | } | |
1281 | } | |
efc9f05d | 1282 | return c; |
a7e3ed1e AK |
1283 | } |
1284 | ||
de0428a7 KW |
1285 | struct event_constraint * |
1286 | x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) | |
1287 | { | |
1288 | struct event_constraint *c; | |
1289 | ||
1290 | if (x86_pmu.event_constraints) { | |
1291 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
1292 | if ((event->hw.config & c->cmask) == c->code) | |
1293 | return c; | |
1294 | } | |
1295 | } | |
1296 | ||
1297 | return &unconstrained; | |
1298 | } | |
1299 | ||
f22f54f4 PZ |
1300 | static struct event_constraint * |
1301 | intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event) | |
1302 | { | |
1303 | struct event_constraint *c; | |
1304 | ||
ca037701 PZ |
1305 | c = intel_bts_constraints(event); |
1306 | if (c) | |
1307 | return c; | |
1308 | ||
1309 | c = intel_pebs_constraints(event); | |
f22f54f4 PZ |
1310 | if (c) |
1311 | return c; | |
1312 | ||
efc9f05d | 1313 | c = intel_shared_regs_constraints(cpuc, event); |
a7e3ed1e AK |
1314 | if (c) |
1315 | return c; | |
1316 | ||
f22f54f4 PZ |
1317 | return x86_get_event_constraints(cpuc, event); |
1318 | } | |
1319 | ||
efc9f05d SE |
1320 | static void |
1321 | intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc, | |
a7e3ed1e AK |
1322 | struct perf_event *event) |
1323 | { | |
efc9f05d | 1324 | struct hw_perf_event_extra *reg; |
a7e3ed1e | 1325 | |
efc9f05d SE |
1326 | reg = &event->hw.extra_reg; |
1327 | if (reg->idx != EXTRA_REG_NONE) | |
1328 | __intel_shared_reg_put_constraints(cpuc, reg); | |
b36817e8 SE |
1329 | |
1330 | reg = &event->hw.branch_reg; | |
1331 | if (reg->idx != EXTRA_REG_NONE) | |
1332 | __intel_shared_reg_put_constraints(cpuc, reg); | |
efc9f05d | 1333 | } |
a7e3ed1e | 1334 | |
efc9f05d SE |
1335 | static void intel_put_event_constraints(struct cpu_hw_events *cpuc, |
1336 | struct perf_event *event) | |
1337 | { | |
1338 | intel_put_shared_regs_event_constraints(cpuc, event); | |
a7e3ed1e AK |
1339 | } |
1340 | ||
0780c927 | 1341 | static void intel_pebs_aliases_core2(struct perf_event *event) |
b4cdc5c2 | 1342 | { |
0780c927 | 1343 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { |
7639dae0 PZ |
1344 | /* |
1345 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
1346 | * (0x003c) so that we can use it with PEBS. | |
1347 | * | |
1348 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
1349 | * PEBS capable. However we can use INST_RETIRED.ANY_P | |
1350 | * (0x00c0), which is a PEBS capable event, to get the same | |
1351 | * count. | |
1352 | * | |
1353 | * INST_RETIRED.ANY_P counts the number of cycles that retires | |
1354 | * CNTMASK instructions. By setting CNTMASK to a value (16) | |
1355 | * larger than the maximum number of instructions that can be | |
1356 | * retired per cycle (4) and then inverting the condition, we | |
1357 | * count all cycles that retire 16 or less instructions, which | |
1358 | * is every cycle. | |
1359 | * | |
1360 | * Thereby we gain a PEBS capable cycle counter. | |
1361 | */ | |
f9b4eeb8 PZ |
1362 | u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); |
1363 | ||
0780c927 PZ |
1364 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); |
1365 | event->hw.config = alt_config; | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | static void intel_pebs_aliases_snb(struct perf_event *event) | |
1370 | { | |
1371 | if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) { | |
1372 | /* | |
1373 | * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P | |
1374 | * (0x003c) so that we can use it with PEBS. | |
1375 | * | |
1376 | * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't | |
1377 | * PEBS capable. However we can use UOPS_RETIRED.ALL | |
1378 | * (0x01c2), which is a PEBS capable event, to get the same | |
1379 | * count. | |
1380 | * | |
1381 | * UOPS_RETIRED.ALL counts the number of cycles that retires | |
1382 | * CNTMASK micro-ops. By setting CNTMASK to a value (16) | |
1383 | * larger than the maximum number of micro-ops that can be | |
1384 | * retired per cycle (4) and then inverting the condition, we | |
1385 | * count all cycles that retire 16 or less micro-ops, which | |
1386 | * is every cycle. | |
1387 | * | |
1388 | * Thereby we gain a PEBS capable cycle counter. | |
1389 | */ | |
1390 | u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); | |
7639dae0 PZ |
1391 | |
1392 | alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK); | |
1393 | event->hw.config = alt_config; | |
1394 | } | |
0780c927 PZ |
1395 | } |
1396 | ||
1397 | static int intel_pmu_hw_config(struct perf_event *event) | |
1398 | { | |
1399 | int ret = x86_pmu_hw_config(event); | |
1400 | ||
1401 | if (ret) | |
1402 | return ret; | |
1403 | ||
1404 | if (event->attr.precise_ip && x86_pmu.pebs_aliases) | |
1405 | x86_pmu.pebs_aliases(event); | |
7639dae0 | 1406 | |
60ce0fbd SE |
1407 | if (intel_pmu_needs_lbr_smpl(event)) { |
1408 | ret = intel_pmu_setup_lbr_filter(event); | |
1409 | if (ret) | |
1410 | return ret; | |
1411 | } | |
1412 | ||
b4cdc5c2 PZ |
1413 | if (event->attr.type != PERF_TYPE_RAW) |
1414 | return 0; | |
1415 | ||
1416 | if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY)) | |
1417 | return 0; | |
1418 | ||
1419 | if (x86_pmu.version < 3) | |
1420 | return -EINVAL; | |
1421 | ||
1422 | if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN)) | |
1423 | return -EACCES; | |
1424 | ||
1425 | event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY; | |
1426 | ||
1427 | return 0; | |
1428 | } | |
1429 | ||
144d31e6 GN |
1430 | struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) |
1431 | { | |
1432 | if (x86_pmu.guest_get_msrs) | |
1433 | return x86_pmu.guest_get_msrs(nr); | |
1434 | *nr = 0; | |
1435 | return NULL; | |
1436 | } | |
1437 | EXPORT_SYMBOL_GPL(perf_guest_get_msrs); | |
1438 | ||
1439 | static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr) | |
1440 | { | |
1441 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1442 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; | |
1443 | ||
1444 | arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL; | |
1445 | arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; | |
1446 | arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; | |
1447 | ||
1448 | *nr = 1; | |
1449 | return arr; | |
1450 | } | |
1451 | ||
1452 | static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr) | |
1453 | { | |
1454 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1455 | struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs; | |
1456 | int idx; | |
1457 | ||
1458 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1459 | struct perf_event *event = cpuc->events[idx]; | |
1460 | ||
1461 | arr[idx].msr = x86_pmu_config_addr(idx); | |
1462 | arr[idx].host = arr[idx].guest = 0; | |
1463 | ||
1464 | if (!test_bit(idx, cpuc->active_mask)) | |
1465 | continue; | |
1466 | ||
1467 | arr[idx].host = arr[idx].guest = | |
1468 | event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE; | |
1469 | ||
1470 | if (event->attr.exclude_host) | |
1471 | arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
1472 | else if (event->attr.exclude_guest) | |
1473 | arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE; | |
1474 | } | |
1475 | ||
1476 | *nr = x86_pmu.num_counters; | |
1477 | return arr; | |
1478 | } | |
1479 | ||
1480 | static void core_pmu_enable_event(struct perf_event *event) | |
1481 | { | |
1482 | if (!event->attr.exclude_host) | |
1483 | x86_pmu_enable_event(event); | |
1484 | } | |
1485 | ||
1486 | static void core_pmu_enable_all(int added) | |
1487 | { | |
1488 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1489 | int idx; | |
1490 | ||
1491 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | |
1492 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; | |
1493 | ||
1494 | if (!test_bit(idx, cpuc->active_mask) || | |
1495 | cpuc->events[idx]->attr.exclude_host) | |
1496 | continue; | |
1497 | ||
1498 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); | |
1499 | } | |
1500 | } | |
1501 | ||
641cc938 JO |
1502 | PMU_FORMAT_ATTR(event, "config:0-7" ); |
1503 | PMU_FORMAT_ATTR(umask, "config:8-15" ); | |
1504 | PMU_FORMAT_ATTR(edge, "config:18" ); | |
1505 | PMU_FORMAT_ATTR(pc, "config:19" ); | |
1506 | PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */ | |
1507 | PMU_FORMAT_ATTR(inv, "config:23" ); | |
1508 | PMU_FORMAT_ATTR(cmask, "config:24-31" ); | |
1509 | ||
1510 | static struct attribute *intel_arch_formats_attr[] = { | |
1511 | &format_attr_event.attr, | |
1512 | &format_attr_umask.attr, | |
1513 | &format_attr_edge.attr, | |
1514 | &format_attr_pc.attr, | |
1515 | &format_attr_inv.attr, | |
1516 | &format_attr_cmask.attr, | |
1517 | NULL, | |
1518 | }; | |
1519 | ||
caaa8be3 | 1520 | static __initconst const struct x86_pmu core_pmu = { |
f22f54f4 PZ |
1521 | .name = "core", |
1522 | .handle_irq = x86_pmu_handle_irq, | |
1523 | .disable_all = x86_pmu_disable_all, | |
144d31e6 GN |
1524 | .enable_all = core_pmu_enable_all, |
1525 | .enable = core_pmu_enable_event, | |
f22f54f4 | 1526 | .disable = x86_pmu_disable_event, |
b4cdc5c2 | 1527 | .hw_config = x86_pmu_hw_config, |
a072738e | 1528 | .schedule_events = x86_schedule_events, |
f22f54f4 PZ |
1529 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1530 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
1531 | .event_map = intel_pmu_event_map, | |
f22f54f4 PZ |
1532 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
1533 | .apic = 1, | |
1534 | /* | |
1535 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1536 | * so we install an artificial 1<<31 period regardless of | |
1537 | * the generic event period: | |
1538 | */ | |
1539 | .max_period = (1ULL << 31) - 1, | |
1540 | .get_event_constraints = intel_get_event_constraints, | |
a7e3ed1e | 1541 | .put_event_constraints = intel_put_event_constraints, |
f22f54f4 | 1542 | .event_constraints = intel_core_event_constraints, |
144d31e6 | 1543 | .guest_get_msrs = core_guest_get_msrs, |
641cc938 | 1544 | .format_attrs = intel_arch_formats_attr, |
f22f54f4 PZ |
1545 | }; |
1546 | ||
de0428a7 | 1547 | struct intel_shared_regs *allocate_shared_regs(int cpu) |
efc9f05d SE |
1548 | { |
1549 | struct intel_shared_regs *regs; | |
1550 | int i; | |
1551 | ||
1552 | regs = kzalloc_node(sizeof(struct intel_shared_regs), | |
1553 | GFP_KERNEL, cpu_to_node(cpu)); | |
1554 | if (regs) { | |
1555 | /* | |
1556 | * initialize the locks to keep lockdep happy | |
1557 | */ | |
1558 | for (i = 0; i < EXTRA_REG_MAX; i++) | |
1559 | raw_spin_lock_init(®s->regs[i].lock); | |
1560 | ||
1561 | regs->core_id = -1; | |
1562 | } | |
1563 | return regs; | |
1564 | } | |
1565 | ||
a7e3ed1e AK |
1566 | static int intel_pmu_cpu_prepare(int cpu) |
1567 | { | |
1568 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1569 | ||
b36817e8 | 1570 | if (!(x86_pmu.extra_regs || x86_pmu.lbr_sel_map)) |
69092624 LM |
1571 | return NOTIFY_OK; |
1572 | ||
efc9f05d SE |
1573 | cpuc->shared_regs = allocate_shared_regs(cpu); |
1574 | if (!cpuc->shared_regs) | |
a7e3ed1e AK |
1575 | return NOTIFY_BAD; |
1576 | ||
a7e3ed1e AK |
1577 | return NOTIFY_OK; |
1578 | } | |
1579 | ||
74846d35 PZ |
1580 | static void intel_pmu_cpu_starting(int cpu) |
1581 | { | |
a7e3ed1e AK |
1582 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
1583 | int core_id = topology_core_id(cpu); | |
1584 | int i; | |
1585 | ||
69092624 LM |
1586 | init_debug_store_on_cpu(cpu); |
1587 | /* | |
1588 | * Deal with CPUs that don't clear their LBRs on power-up. | |
1589 | */ | |
1590 | intel_pmu_lbr_reset(); | |
1591 | ||
b36817e8 SE |
1592 | cpuc->lbr_sel = NULL; |
1593 | ||
1594 | if (!cpuc->shared_regs) | |
69092624 LM |
1595 | return; |
1596 | ||
b36817e8 SE |
1597 | if (!(x86_pmu.er_flags & ERF_NO_HT_SHARING)) { |
1598 | for_each_cpu(i, topology_thread_cpumask(cpu)) { | |
1599 | struct intel_shared_regs *pc; | |
a7e3ed1e | 1600 | |
b36817e8 SE |
1601 | pc = per_cpu(cpu_hw_events, i).shared_regs; |
1602 | if (pc && pc->core_id == core_id) { | |
1603 | cpuc->kfree_on_online = cpuc->shared_regs; | |
1604 | cpuc->shared_regs = pc; | |
1605 | break; | |
1606 | } | |
a7e3ed1e | 1607 | } |
b36817e8 SE |
1608 | cpuc->shared_regs->core_id = core_id; |
1609 | cpuc->shared_regs->refcnt++; | |
a7e3ed1e AK |
1610 | } |
1611 | ||
b36817e8 SE |
1612 | if (x86_pmu.lbr_sel_map) |
1613 | cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR]; | |
74846d35 PZ |
1614 | } |
1615 | ||
1616 | static void intel_pmu_cpu_dying(int cpu) | |
1617 | { | |
a7e3ed1e | 1618 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
efc9f05d | 1619 | struct intel_shared_regs *pc; |
a7e3ed1e | 1620 | |
efc9f05d | 1621 | pc = cpuc->shared_regs; |
a7e3ed1e AK |
1622 | if (pc) { |
1623 | if (pc->core_id == -1 || --pc->refcnt == 0) | |
1624 | kfree(pc); | |
efc9f05d | 1625 | cpuc->shared_regs = NULL; |
a7e3ed1e AK |
1626 | } |
1627 | ||
74846d35 PZ |
1628 | fini_debug_store_on_cpu(cpu); |
1629 | } | |
1630 | ||
d010b332 SE |
1631 | static void intel_pmu_flush_branch_stack(void) |
1632 | { | |
1633 | /* | |
1634 | * Intel LBR does not tag entries with the | |
1635 | * PID of the current task, then we need to | |
1636 | * flush it on ctxsw | |
1637 | * For now, we simply reset it | |
1638 | */ | |
1639 | if (x86_pmu.lbr_nr) | |
1640 | intel_pmu_lbr_reset(); | |
1641 | } | |
1642 | ||
641cc938 JO |
1643 | PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); |
1644 | ||
1645 | static struct attribute *intel_arch3_formats_attr[] = { | |
1646 | &format_attr_event.attr, | |
1647 | &format_attr_umask.attr, | |
1648 | &format_attr_edge.attr, | |
1649 | &format_attr_pc.attr, | |
1650 | &format_attr_any.attr, | |
1651 | &format_attr_inv.attr, | |
1652 | &format_attr_cmask.attr, | |
1653 | ||
1654 | &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */ | |
1655 | NULL, | |
1656 | }; | |
1657 | ||
caaa8be3 | 1658 | static __initconst const struct x86_pmu intel_pmu = { |
f22f54f4 PZ |
1659 | .name = "Intel", |
1660 | .handle_irq = intel_pmu_handle_irq, | |
1661 | .disable_all = intel_pmu_disable_all, | |
1662 | .enable_all = intel_pmu_enable_all, | |
1663 | .enable = intel_pmu_enable_event, | |
1664 | .disable = intel_pmu_disable_event, | |
b4cdc5c2 | 1665 | .hw_config = intel_pmu_hw_config, |
a072738e | 1666 | .schedule_events = x86_schedule_events, |
f22f54f4 PZ |
1667 | .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, |
1668 | .perfctr = MSR_ARCH_PERFMON_PERFCTR0, | |
1669 | .event_map = intel_pmu_event_map, | |
f22f54f4 PZ |
1670 | .max_events = ARRAY_SIZE(intel_perfmon_event_map), |
1671 | .apic = 1, | |
1672 | /* | |
1673 | * Intel PMCs cannot be accessed sanely above 32 bit width, | |
1674 | * so we install an artificial 1<<31 period regardless of | |
1675 | * the generic event period: | |
1676 | */ | |
1677 | .max_period = (1ULL << 31) - 1, | |
3f6da390 | 1678 | .get_event_constraints = intel_get_event_constraints, |
a7e3ed1e | 1679 | .put_event_constraints = intel_put_event_constraints, |
0780c927 | 1680 | .pebs_aliases = intel_pebs_aliases_core2, |
3f6da390 | 1681 | |
641cc938 JO |
1682 | .format_attrs = intel_arch3_formats_attr, |
1683 | ||
a7e3ed1e | 1684 | .cpu_prepare = intel_pmu_cpu_prepare, |
74846d35 PZ |
1685 | .cpu_starting = intel_pmu_cpu_starting, |
1686 | .cpu_dying = intel_pmu_cpu_dying, | |
144d31e6 | 1687 | .guest_get_msrs = intel_guest_get_msrs, |
d010b332 | 1688 | .flush_branch_stack = intel_pmu_flush_branch_stack, |
f22f54f4 PZ |
1689 | }; |
1690 | ||
c1d6f42f | 1691 | static __init void intel_clovertown_quirk(void) |
3c44780b PZ |
1692 | { |
1693 | /* | |
1694 | * PEBS is unreliable due to: | |
1695 | * | |
1696 | * AJ67 - PEBS may experience CPL leaks | |
1697 | * AJ68 - PEBS PMI may be delayed by one event | |
1698 | * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12] | |
1699 | * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS | |
1700 | * | |
1701 | * AJ67 could be worked around by restricting the OS/USR flags. | |
1702 | * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI. | |
1703 | * | |
1704 | * AJ106 could possibly be worked around by not allowing LBR | |
1705 | * usage from PEBS, including the fixup. | |
1706 | * AJ68 could possibly be worked around by always programming | |
ec75a716 | 1707 | * a pebs_event_reset[0] value and coping with the lost events. |
3c44780b PZ |
1708 | * |
1709 | * But taken together it might just make sense to not enable PEBS on | |
1710 | * these chips. | |
1711 | */ | |
c767a54b | 1712 | pr_warn("PEBS disabled due to CPU errata\n"); |
3c44780b PZ |
1713 | x86_pmu.pebs = 0; |
1714 | x86_pmu.pebs_constraints = NULL; | |
1715 | } | |
1716 | ||
c93dc84c PZ |
1717 | static int intel_snb_pebs_broken(int cpu) |
1718 | { | |
1719 | u32 rev = UINT_MAX; /* default to broken for unknown models */ | |
1720 | ||
1721 | switch (cpu_data(cpu).x86_model) { | |
1722 | case 42: /* SNB */ | |
1723 | rev = 0x28; | |
1724 | break; | |
1725 | ||
1726 | case 45: /* SNB-EP */ | |
1727 | switch (cpu_data(cpu).x86_mask) { | |
1728 | case 6: rev = 0x618; break; | |
1729 | case 7: rev = 0x70c; break; | |
1730 | } | |
1731 | } | |
1732 | ||
1733 | return (cpu_data(cpu).microcode < rev); | |
1734 | } | |
1735 | ||
1736 | static void intel_snb_check_microcode(void) | |
1737 | { | |
1738 | int pebs_broken = 0; | |
1739 | int cpu; | |
1740 | ||
1741 | get_online_cpus(); | |
1742 | for_each_online_cpu(cpu) { | |
1743 | if ((pebs_broken = intel_snb_pebs_broken(cpu))) | |
1744 | break; | |
1745 | } | |
1746 | put_online_cpus(); | |
1747 | ||
1748 | if (pebs_broken == x86_pmu.pebs_broken) | |
1749 | return; | |
1750 | ||
1751 | /* | |
1752 | * Serialized by the microcode lock.. | |
1753 | */ | |
1754 | if (x86_pmu.pebs_broken) { | |
1755 | pr_info("PEBS enabled due to microcode update\n"); | |
1756 | x86_pmu.pebs_broken = 0; | |
1757 | } else { | |
1758 | pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); | |
1759 | x86_pmu.pebs_broken = 1; | |
1760 | } | |
1761 | } | |
1762 | ||
c1d6f42f | 1763 | static __init void intel_sandybridge_quirk(void) |
6a600a8b | 1764 | { |
c93dc84c PZ |
1765 | x86_pmu.check_microcode = intel_snb_check_microcode; |
1766 | intel_snb_check_microcode(); | |
6a600a8b PZ |
1767 | } |
1768 | ||
c1d6f42f PZ |
1769 | static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { |
1770 | { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" }, | |
1771 | { PERF_COUNT_HW_INSTRUCTIONS, "instructions" }, | |
1772 | { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" }, | |
1773 | { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" }, | |
1774 | { PERF_COUNT_HW_CACHE_MISSES, "cache misses" }, | |
1775 | { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" }, | |
1776 | { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" }, | |
ffb871bc GN |
1777 | }; |
1778 | ||
c1d6f42f PZ |
1779 | static __init void intel_arch_events_quirk(void) |
1780 | { | |
1781 | int bit; | |
1782 | ||
1783 | /* disable event that reported as not presend by cpuid */ | |
1784 | for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { | |
1785 | intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; | |
c767a54b JP |
1786 | pr_warn("CPUID marked event: \'%s\' unavailable\n", |
1787 | intel_arch_events_map[bit].name); | |
c1d6f42f PZ |
1788 | } |
1789 | } | |
1790 | ||
1791 | static __init void intel_nehalem_quirk(void) | |
1792 | { | |
1793 | union cpuid10_ebx ebx; | |
1794 | ||
1795 | ebx.full = x86_pmu.events_maskl; | |
1796 | if (ebx.split.no_branch_misses_retired) { | |
1797 | /* | |
1798 | * Erratum AAJ80 detected, we work it around by using | |
1799 | * the BR_MISP_EXEC.ANY event. This will over-count | |
1800 | * branch-misses, but it's still much better than the | |
1801 | * architectural event which is often completely bogus: | |
1802 | */ | |
1803 | intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; | |
1804 | ebx.split.no_branch_misses_retired = 0; | |
1805 | x86_pmu.events_maskl = ebx.full; | |
c767a54b | 1806 | pr_info("CPU erratum AAJ80 worked around\n"); |
c1d6f42f PZ |
1807 | } |
1808 | } | |
1809 | ||
de0428a7 | 1810 | __init int intel_pmu_init(void) |
f22f54f4 PZ |
1811 | { |
1812 | union cpuid10_edx edx; | |
1813 | union cpuid10_eax eax; | |
ffb871bc | 1814 | union cpuid10_ebx ebx; |
a1eac7ac | 1815 | struct event_constraint *c; |
f22f54f4 | 1816 | unsigned int unused; |
f22f54f4 PZ |
1817 | int version; |
1818 | ||
1819 | if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) { | |
a072738e CG |
1820 | switch (boot_cpu_data.x86) { |
1821 | case 0x6: | |
1822 | return p6_pmu_init(); | |
1823 | case 0xf: | |
1824 | return p4_pmu_init(); | |
1825 | } | |
f22f54f4 | 1826 | return -ENODEV; |
f22f54f4 PZ |
1827 | } |
1828 | ||
1829 | /* | |
1830 | * Check whether the Architectural PerfMon supports | |
1831 | * Branch Misses Retired hw_event or not. | |
1832 | */ | |
ffb871bc GN |
1833 | cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); |
1834 | if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) | |
f22f54f4 PZ |
1835 | return -ENODEV; |
1836 | ||
1837 | version = eax.split.version_id; | |
1838 | if (version < 2) | |
1839 | x86_pmu = core_pmu; | |
1840 | else | |
1841 | x86_pmu = intel_pmu; | |
1842 | ||
1843 | x86_pmu.version = version; | |
948b1bb8 RR |
1844 | x86_pmu.num_counters = eax.split.num_counters; |
1845 | x86_pmu.cntval_bits = eax.split.bit_width; | |
1846 | x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; | |
f22f54f4 | 1847 | |
c1d6f42f PZ |
1848 | x86_pmu.events_maskl = ebx.full; |
1849 | x86_pmu.events_mask_len = eax.split.mask_length; | |
1850 | ||
70ab7003 AK |
1851 | x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); |
1852 | ||
f22f54f4 PZ |
1853 | /* |
1854 | * Quirk: v2 perfmon does not report fixed-purpose events, so | |
1855 | * assume at least 3 events: | |
1856 | */ | |
1857 | if (version > 1) | |
948b1bb8 | 1858 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
f22f54f4 | 1859 | |
8db909a7 PZ |
1860 | /* |
1861 | * v2 and above have a perf capabilities MSR | |
1862 | */ | |
1863 | if (version > 1) { | |
1864 | u64 capabilities; | |
1865 | ||
1866 | rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); | |
1867 | x86_pmu.intel_cap.capabilities = capabilities; | |
1868 | } | |
1869 | ||
ca037701 PZ |
1870 | intel_ds_init(); |
1871 | ||
c1d6f42f PZ |
1872 | x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */ |
1873 | ||
f22f54f4 PZ |
1874 | /* |
1875 | * Install the hw-cache-events table: | |
1876 | */ | |
1877 | switch (boot_cpu_data.x86_model) { | |
1878 | case 14: /* 65 nm core solo/duo, "Yonah" */ | |
1879 | pr_cont("Core events, "); | |
1880 | break; | |
1881 | ||
1882 | case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */ | |
c1d6f42f | 1883 | x86_add_quirk(intel_clovertown_quirk); |
f22f54f4 PZ |
1884 | case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */ |
1885 | case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */ | |
1886 | case 29: /* six-core 45 nm xeon "Dunnington" */ | |
1887 | memcpy(hw_cache_event_ids, core2_hw_cache_event_ids, | |
1888 | sizeof(hw_cache_event_ids)); | |
1889 | ||
caff2bef PZ |
1890 | intel_pmu_lbr_init_core(); |
1891 | ||
f22f54f4 | 1892 | x86_pmu.event_constraints = intel_core2_event_constraints; |
17e31629 | 1893 | x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; |
f22f54f4 PZ |
1894 | pr_cont("Core2 events, "); |
1895 | break; | |
1896 | ||
1897 | case 26: /* 45 nm nehalem, "Bloomfield" */ | |
1898 | case 30: /* 45 nm nehalem, "Lynnfield" */ | |
134fbadf | 1899 | case 46: /* 45 nm nehalem-ex, "Beckton" */ |
f22f54f4 PZ |
1900 | memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids, |
1901 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
1902 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
1903 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 1904 | |
caff2bef PZ |
1905 | intel_pmu_lbr_init_nhm(); |
1906 | ||
f22f54f4 | 1907 | x86_pmu.event_constraints = intel_nehalem_event_constraints; |
17e31629 | 1908 | x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; |
11164cd4 | 1909 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
a7e3ed1e | 1910 | x86_pmu.extra_regs = intel_nehalem_extra_regs; |
ec75a716 | 1911 | |
91fc4cc0 | 1912 | /* UOPS_ISSUED.STALLED_CYCLES */ |
f9b4eeb8 PZ |
1913 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
1914 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
91fc4cc0 | 1915 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
1916 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
1917 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
94403f88 | 1918 | |
c1d6f42f | 1919 | x86_add_quirk(intel_nehalem_quirk); |
ec75a716 | 1920 | |
11164cd4 | 1921 | pr_cont("Nehalem events, "); |
f22f54f4 | 1922 | break; |
caff2bef | 1923 | |
b622d644 | 1924 | case 28: /* Atom */ |
f22f54f4 PZ |
1925 | memcpy(hw_cache_event_ids, atom_hw_cache_event_ids, |
1926 | sizeof(hw_cache_event_ids)); | |
1927 | ||
caff2bef PZ |
1928 | intel_pmu_lbr_init_atom(); |
1929 | ||
f22f54f4 | 1930 | x86_pmu.event_constraints = intel_gen_event_constraints; |
17e31629 | 1931 | x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; |
f22f54f4 PZ |
1932 | pr_cont("Atom events, "); |
1933 | break; | |
1934 | ||
1935 | case 37: /* 32 nm nehalem, "Clarkdale" */ | |
1936 | case 44: /* 32 nm nehalem, "Gulftown" */ | |
b2508e82 | 1937 | case 47: /* 32 nm Xeon E7 */ |
f22f54f4 PZ |
1938 | memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids, |
1939 | sizeof(hw_cache_event_ids)); | |
e994d7d2 AK |
1940 | memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs, |
1941 | sizeof(hw_cache_extra_regs)); | |
f22f54f4 | 1942 | |
caff2bef PZ |
1943 | intel_pmu_lbr_init_nhm(); |
1944 | ||
f22f54f4 | 1945 | x86_pmu.event_constraints = intel_westmere_event_constraints; |
40b91cd1 | 1946 | x86_pmu.enable_all = intel_pmu_nhm_enable_all; |
17e31629 | 1947 | x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; |
a7e3ed1e | 1948 | x86_pmu.extra_regs = intel_westmere_extra_regs; |
b79e8941 | 1949 | x86_pmu.er_flags |= ERF_HAS_RSP_1; |
30112039 IM |
1950 | |
1951 | /* UOPS_ISSUED.STALLED_CYCLES */ | |
f9b4eeb8 PZ |
1952 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
1953 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
30112039 | 1954 | /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ |
f9b4eeb8 PZ |
1955 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
1956 | X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); | |
30112039 | 1957 | |
f22f54f4 PZ |
1958 | pr_cont("Westmere events, "); |
1959 | break; | |
b622d644 | 1960 | |
b06b3d49 | 1961 | case 42: /* SandyBridge */ |
a34668f6 | 1962 | case 45: /* SandyBridge, "Romely-EP" */ |
47a8863d PZ |
1963 | x86_add_quirk(intel_sandybridge_quirk); |
1964 | case 58: /* IvyBridge */ | |
b06b3d49 LM |
1965 | memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, |
1966 | sizeof(hw_cache_event_ids)); | |
1967 | ||
c5cc2cd9 | 1968 | intel_pmu_lbr_init_snb(); |
b06b3d49 LM |
1969 | |
1970 | x86_pmu.event_constraints = intel_snb_event_constraints; | |
de0428a7 | 1971 | x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; |
0780c927 | 1972 | x86_pmu.pebs_aliases = intel_pebs_aliases_snb; |
ee89cbc2 SE |
1973 | x86_pmu.extra_regs = intel_snb_extra_regs; |
1974 | /* all extra regs are per-cpu when HT is on */ | |
b79e8941 PZ |
1975 | x86_pmu.er_flags |= ERF_HAS_RSP_1; |
1976 | x86_pmu.er_flags |= ERF_NO_HT_SHARING; | |
e04d1b23 LM |
1977 | |
1978 | /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */ | |
f9b4eeb8 PZ |
1979 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = |
1980 | X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 1981 | /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/ |
f9b4eeb8 PZ |
1982 | intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = |
1983 | X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); | |
e04d1b23 | 1984 | |
b06b3d49 LM |
1985 | pr_cont("SandyBridge events, "); |
1986 | break; | |
1987 | ||
f22f54f4 | 1988 | default: |
0af3ac1f AK |
1989 | switch (x86_pmu.version) { |
1990 | case 1: | |
1991 | x86_pmu.event_constraints = intel_v1_event_constraints; | |
1992 | pr_cont("generic architected perfmon v1, "); | |
1993 | break; | |
1994 | default: | |
1995 | /* | |
1996 | * default constraints for v2 and up | |
1997 | */ | |
1998 | x86_pmu.event_constraints = intel_gen_event_constraints; | |
1999 | pr_cont("generic architected perfmon, "); | |
2000 | break; | |
2001 | } | |
f22f54f4 | 2002 | } |
ffb871bc | 2003 | |
a1eac7ac RR |
2004 | if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { |
2005 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | |
2006 | x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); | |
2007 | x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; | |
2008 | } | |
2009 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
2010 | ||
2011 | if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { | |
2012 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | |
2013 | x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); | |
2014 | x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; | |
2015 | } | |
2016 | ||
2017 | x86_pmu.intel_ctrl |= | |
2018 | ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; | |
2019 | ||
2020 | if (x86_pmu.event_constraints) { | |
2021 | /* | |
2022 | * event on fixed counter2 (REF_CYCLES) only works on this | |
2023 | * counter, so do not extend mask to generic counters | |
2024 | */ | |
2025 | for_each_event_constraint(c, x86_pmu.event_constraints) { | |
2026 | if (c->cmask != X86_RAW_EVENT_MASK | |
2027 | || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) { | |
2028 | continue; | |
2029 | } | |
2030 | ||
2031 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; | |
2032 | c->weight += x86_pmu.num_counters; | |
2033 | } | |
2034 | } | |
2035 | ||
f22f54f4 PZ |
2036 | return 0; |
2037 | } |