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1da177e4 LT |
1 | /* |
2 | * Intel specific MCE features. | |
3 | * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> | |
88ccbedd AK |
4 | * Copyright (C) 2008, 2009 Intel Corporation |
5 | * Author: Andi Kleen | |
1da177e4 LT |
6 | */ |
7 | ||
8 | #include <linux/init.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/percpu.h> | |
1bf7b31e | 11 | #include <asm/apic.h> |
1da177e4 LT |
12 | #include <asm/processor.h> |
13 | #include <asm/msr.h> | |
14 | #include <asm/mce.h> | |
1da177e4 | 15 | |
88ccbedd AK |
16 | /* |
17 | * Support for Intel Correct Machine Check Interrupts. This allows | |
18 | * the CPU to raise an interrupt when a corrected machine check happened. | |
19 | * Normally we pick those up using a regular polling timer. | |
20 | * Also supports reliable discovery of shared banks. | |
21 | */ | |
22 | ||
23 | static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); | |
24 | ||
25 | /* | |
26 | * cmci_discover_lock protects against parallel discovery attempts | |
27 | * which could race against each other. | |
28 | */ | |
29 | static DEFINE_SPINLOCK(cmci_discover_lock); | |
30 | ||
31 | #define CMCI_THRESHOLD 1 | |
32 | ||
df20e2eb | 33 | static int cmci_supported(int *banks) |
88ccbedd AK |
34 | { |
35 | u64 cap; | |
36 | ||
62fdac59 HS |
37 | if (mce_cmci_disabled || mce_ignore_ce) |
38 | return 0; | |
39 | ||
88ccbedd AK |
40 | /* |
41 | * Vendor check is not strictly needed, but the initial | |
42 | * initialization is vendor keyed and this | |
43 | * makes sure none of the backdoors are entered otherwise. | |
44 | */ | |
45 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
46 | return 0; | |
47 | if (!cpu_has_apic || lapic_get_maxlvt() < 6) | |
48 | return 0; | |
49 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
50 | *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); | |
51 | return !!(cap & MCG_CMCI_P); | |
52 | } | |
53 | ||
54 | /* | |
55 | * The interrupt handler. This is called on every event. | |
56 | * Just call the poller directly to log any events. | |
57 | * This could in theory increase the threshold under high load, | |
58 | * but doesn't for now. | |
59 | */ | |
60 | static void intel_threshold_interrupt(void) | |
61 | { | |
62 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); | |
9ff36ee9 | 63 | mce_notify_irq(); |
88ccbedd AK |
64 | } |
65 | ||
66 | static void print_update(char *type, int *hdr, int num) | |
67 | { | |
68 | if (*hdr == 0) | |
69 | printk(KERN_INFO "CPU %d MCA banks", smp_processor_id()); | |
70 | *hdr = 1; | |
71 | printk(KERN_CONT " %s:%d", type, num); | |
72 | } | |
73 | ||
74 | /* | |
75 | * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks | |
76 | * on this CPU. Use the algorithm recommended in the SDM to discover shared | |
77 | * banks. | |
78 | */ | |
df20e2eb | 79 | static void cmci_discover(int banks, int boot) |
88ccbedd AK |
80 | { |
81 | unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); | |
e5299926 | 82 | unsigned long flags; |
88ccbedd AK |
83 | int hdr = 0; |
84 | int i; | |
85 | ||
e5299926 | 86 | spin_lock_irqsave(&cmci_discover_lock, flags); |
88ccbedd AK |
87 | for (i = 0; i < banks; i++) { |
88 | u64 val; | |
89 | ||
90 | if (test_bit(i, owned)) | |
91 | continue; | |
92 | ||
93 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
94 | ||
95 | /* Already owned by someone else? */ | |
96 | if (val & CMCI_EN) { | |
97 | if (test_and_clear_bit(i, owned) || boot) | |
98 | print_update("SHD", &hdr, i); | |
99 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | |
100 | continue; | |
101 | } | |
102 | ||
103 | val |= CMCI_EN | CMCI_THRESHOLD; | |
104 | wrmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
105 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
106 | ||
107 | /* Did the enable bit stick? -- the bank supports CMCI */ | |
108 | if (val & CMCI_EN) { | |
109 | if (!test_and_set_bit(i, owned) || boot) | |
110 | print_update("CMCI", &hdr, i); | |
111 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | |
112 | } else { | |
113 | WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); | |
114 | } | |
115 | } | |
e5299926 | 116 | spin_unlock_irqrestore(&cmci_discover_lock, flags); |
88ccbedd AK |
117 | if (hdr) |
118 | printk(KERN_CONT "\n"); | |
119 | } | |
120 | ||
121 | /* | |
122 | * Just in case we missed an event during initialization check | |
123 | * all the CMCI owned banks. | |
124 | */ | |
df20e2eb | 125 | void cmci_recheck(void) |
88ccbedd AK |
126 | { |
127 | unsigned long flags; | |
128 | int banks; | |
129 | ||
130 | if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks)) | |
131 | return; | |
132 | local_irq_save(flags); | |
133 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); | |
134 | local_irq_restore(flags); | |
135 | } | |
136 | ||
137 | /* | |
138 | * Disable CMCI on this CPU for all banks it owns when it goes down. | |
139 | * This allows other CPUs to claim the banks on rediscovery. | |
140 | */ | |
df20e2eb | 141 | void cmci_clear(void) |
88ccbedd | 142 | { |
e5299926 | 143 | unsigned long flags; |
88ccbedd AK |
144 | int i; |
145 | int banks; | |
146 | u64 val; | |
147 | ||
148 | if (!cmci_supported(&banks)) | |
149 | return; | |
e5299926 | 150 | spin_lock_irqsave(&cmci_discover_lock, flags); |
88ccbedd AK |
151 | for (i = 0; i < banks; i++) { |
152 | if (!test_bit(i, __get_cpu_var(mce_banks_owned))) | |
153 | continue; | |
154 | /* Disable CMCI */ | |
155 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
156 | val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); | |
157 | wrmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
158 | __clear_bit(i, __get_cpu_var(mce_banks_owned)); | |
159 | } | |
e5299926 | 160 | spin_unlock_irqrestore(&cmci_discover_lock, flags); |
88ccbedd AK |
161 | } |
162 | ||
163 | /* | |
164 | * After a CPU went down cycle through all the others and rediscover | |
165 | * Must run in process context. | |
166 | */ | |
df20e2eb | 167 | void cmci_rediscover(int dying) |
88ccbedd AK |
168 | { |
169 | int banks; | |
170 | int cpu; | |
171 | cpumask_var_t old; | |
172 | ||
173 | if (!cmci_supported(&banks)) | |
174 | return; | |
175 | if (!alloc_cpumask_var(&old, GFP_KERNEL)) | |
176 | return; | |
177 | cpumask_copy(old, ¤t->cpus_allowed); | |
178 | ||
61a021a0 | 179 | for_each_online_cpu(cpu) { |
88ccbedd AK |
180 | if (cpu == dying) |
181 | continue; | |
4f062896 | 182 | if (set_cpus_allowed_ptr(current, cpumask_of(cpu))) |
88ccbedd AK |
183 | continue; |
184 | /* Recheck banks in case CPUs don't all have the same */ | |
185 | if (cmci_supported(&banks)) | |
186 | cmci_discover(banks, 0); | |
187 | } | |
188 | ||
189 | set_cpus_allowed_ptr(current, old); | |
190 | free_cpumask_var(old); | |
191 | } | |
192 | ||
193 | /* | |
194 | * Reenable CMCI on this CPU in case a CPU down failed. | |
195 | */ | |
196 | void cmci_reenable(void) | |
197 | { | |
198 | int banks; | |
199 | if (cmci_supported(&banks)) | |
200 | cmci_discover(banks, 0); | |
201 | } | |
202 | ||
514ec49a | 203 | static void intel_init_cmci(void) |
88ccbedd AK |
204 | { |
205 | int banks; | |
206 | ||
207 | if (!cmci_supported(&banks)) | |
208 | return; | |
209 | ||
210 | mce_threshold_vector = intel_threshold_interrupt; | |
211 | cmci_discover(banks, 1); | |
212 | /* | |
213 | * For CPU #0 this runs with still disabled APIC, but that's | |
214 | * ok because only the vector is set up. We still do another | |
215 | * check for the banks later for CPU #0 just to make sure | |
216 | * to not miss any events. | |
217 | */ | |
218 | apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); | |
219 | cmci_recheck(); | |
220 | } | |
221 | ||
cc3ca220 | 222 | void mce_intel_feature_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
223 | { |
224 | intel_init_thermal(c); | |
88ccbedd | 225 | intel_init_cmci(); |
1da177e4 | 226 | } |