[linux-2.6-block.git] / arch / x86 / kernel / cpu / mcheck / mce_intel.c

/*
 * Intel specific MCE features.
 * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
 * Copyright (C) 2008, 2009 Intel Corporation
 * Author: Andi Kleen
 */

#include <linux/gfp.h>
#include <linux/interrupt.h>
#include <linux/percpu.h>
#include <linux/sched.h>
#include <linux/cpumask.h>
#include <asm/apic.h>
#include <asm/processor.h>
#include <asm/msr.h>
#include <asm/mce.h>

#include "mce-internal.h"

/*
 * Support for Intel Correct Machine Check Interrupts. This allows
 * the CPU to raise an interrupt when a corrected machine check happened.
 * Normally we pick those up using a regular polling timer.
 * Also supports reliable discovery of shared banks.
 */

/*
 * CMCI can be delivered to multiple cpus that share a machine check bank
 * so we need to designate a single cpu to process errors logged in each bank
 * in the interrupt handler (otherwise we would have many races and potential
 * double reporting of the same error).
 * Note that this can change when a cpu is offlined or brought online since
 * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
 * disables CMCI on all banks owned by the cpu and clears this bitfield. At
 * this point, cmci_rediscover() kicks in and a different cpu may end up
 * taking ownership of some of the shared MCA banks that were previously
 * owned by the offlined cpu.
 */
static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);

/*
 * CMCI storm detection backoff counter
 *
 * During storm, we reset this counter to INITIAL_CHECK_INTERVAL in case we've
 * encountered an error. If not, we decrement it by one. We signal the end of
 * the CMCI storm when it reaches 0.
 */
static DEFINE_PER_CPU(int, cmci_backoff_cnt);

/*
 * cmci_discover_lock protects against parallel discovery attempts
 * which could race against each other.
 */
static DEFINE_RAW_SPINLOCK(cmci_discover_lock);

#define CMCI_THRESHOLD		1
#define CMCI_POLL_INTERVAL	(30 * HZ)
#define CMCI_STORM_INTERVAL	(HZ)
#define CMCI_STORM_THRESHOLD	15

static DEFINE_PER_CPU(unsigned long, cmci_time_stamp);
static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt);
static DEFINE_PER_CPU(unsigned int, cmci_storm_state);

enum {
	CMCI_STORM_NONE,
	CMCI_STORM_ACTIVE,
	CMCI_STORM_SUBSIDED,
};

static atomic_t cmci_storm_on_cpus;

static int cmci_supported(int *banks)
{
	u64 cap;

	if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce)
		return 0;

	/*
	 * Vendor check is not strictly needed, but the initial
	 * initialization is vendor keyed and this
	 * makes sure none of the backdoors are entered otherwise.
	 */
	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
		return 0;
	if (!cpu_has_apic || lapic_get_maxlvt() < 6)
		return 0;
	rdmsrl(MSR_IA32_MCG_CAP, cap);
	*banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
	return !!(cap & MCG_CMCI_P);
}

static bool lmce_supported(void)
{
	u64 tmp;

	if (mca_cfg.lmce_disabled)
		return false;

	rdmsrl(MSR_IA32_MCG_CAP, tmp);

	/*
	 * LMCE depends on recovery support in the processor. Hence both
	 * MCG_SER_P and MCG_LMCE_P should be present in MCG_CAP.
	 */
	if ((tmp & (MCG_SER_P | MCG_LMCE_P)) !=
		   (MCG_SER_P | MCG_LMCE_P))
		return false;

	/*
	 * BIOS should indicate support for LMCE by setting bit 20 in
	 * IA32_FEATURE_CONTROL without which touching MCG_EXT_CTL will
	 * generate a #GP fault.
	 */
	rdmsrl(MSR_IA32_FEATURE_CONTROL, tmp);
	if ((tmp & (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE)) ==
		   (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_LMCE))
		return true;

	return false;
}

bool mce_intel_cmci_poll(void)
{
	if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
		return false;

	/*
	 * Reset the counter if we've logged an error in the last poll
	 * during the storm.
	 */
	if (machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned)))
		this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
	else
		this_cpu_dec(cmci_backoff_cnt);

	return true;
}

void mce_intel_hcpu_update(unsigned long cpu)
{
	if (per_cpu(cmci_storm_state, cpu) == CMCI_STORM_ACTIVE)
		atomic_dec(&cmci_storm_on_cpus);

	per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
}

unsigned long cmci_intel_adjust_timer(unsigned long interval)
{
	if ((this_cpu_read(cmci_backoff_cnt) > 0) &&
	    (__this_cpu_read(cmci_storm_state) == CMCI_STORM_ACTIVE)) {
		mce_notify_irq();
		return CMCI_STORM_INTERVAL;
	}

	switch (__this_cpu_read(cmci_storm_state)) {
	case CMCI_STORM_ACTIVE:

		/*
		 * We switch back to interrupt mode once the poll timer has
		 * silenced itself. That means no events recorded and the timer
		 * interval is back to our poll interval.
		 */
		__this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED);
		if (!atomic_sub_return(1, &cmci_storm_on_cpus))
			pr_notice("CMCI storm subsided: switching to interrupt mode\n");

		/* FALLTHROUGH */

	case CMCI_STORM_SUBSIDED:
		/*
		 * We wait for all CPUs to go back to SUBSIDED state. When that
		 * happens we switch back to interrupt mode.
		 */
		if (!atomic_read(&cmci_storm_on_cpus)) {
			__this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
			cmci_reenable();
			cmci_recheck();
		}
		return CMCI_POLL_INTERVAL;
	default:

		/* We have shiny weather. Let the poll do whatever it thinks. */
		return interval;
	}
}

static void cmci_storm_disable_banks(void)
{
	unsigned long flags, *owned;
	int bank;
	u64 val;

	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
	owned = this_cpu_ptr(mce_banks_owned);
	for_each_set_bit(bank, owned, MAX_NR_BANKS) {
		rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
		val &= ~MCI_CTL2_CMCI_EN;
		wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
	}
	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
}

static bool cmci_storm_detect(void)
{
	unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
	unsigned long ts = __this_cpu_read(cmci_time_stamp);
	unsigned long now = jiffies;
	int r;

	if (__this_cpu_read(cmci_storm_state) != CMCI_STORM_NONE)
		return true;

	if (time_before_eq(now, ts + CMCI_STORM_INTERVAL)) {
		cnt++;
	} else {
		cnt = 1;
		__this_cpu_write(cmci_time_stamp, now);
	}
	__this_cpu_write(cmci_storm_cnt, cnt);

	if (cnt <= CMCI_STORM_THRESHOLD)
		return false;

	cmci_storm_disable_banks();
	__this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
	r = atomic_add_return(1, &cmci_storm_on_cpus);
	mce_timer_kick(CMCI_STORM_INTERVAL);
	this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);

	if (r == 1)
		pr_notice("CMCI storm detected: switching to poll mode\n");
	return true;
}

/*
 * The interrupt handler. This is called on every event.
 * Just call the poller directly to log any events.
 * This could in theory increase the threshold under high load,
 * but doesn't for now.
 */
static void intel_threshold_interrupt(void)
{
	if (cmci_storm_detect())
		return;

	machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
}

/*
 * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
 * on this CPU. Use the algorithm recommended in the SDM to discover shared
 * banks.
 */
static void cmci_discover(int banks)
{
	unsigned long *owned = (void *)this_cpu_ptr(&mce_banks_owned);
	unsigned long flags;
	int i;
	int bios_wrong_thresh = 0;

	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
	for (i = 0; i < banks; i++) {
		u64 val;
		int bios_zero_thresh = 0;

		if (test_bit(i, owned))
			continue;

		/* Skip banks in firmware first mode */
		if (test_bit(i, mce_banks_ce_disabled))
			continue;

		rdmsrl(MSR_IA32_MCx_CTL2(i), val);

		/* Already owned by someone else? */
		if (val & MCI_CTL2_CMCI_EN) {
			clear_bit(i, owned);
			__clear_bit(i, this_cpu_ptr(mce_poll_banks));
			continue;
		}

		if (!mca_cfg.bios_cmci_threshold) {
			val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
			val |= CMCI_THRESHOLD;
		} else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {
			/*
			 * If bios_cmci_threshold boot option was specified
			 * but the threshold is zero, we'll try to initialize
			 * it to 1.
			 */
			bios_zero_thresh = 1;
			val |= CMCI_THRESHOLD;
		}

		val |= MCI_CTL2_CMCI_EN;
		wrmsrl(MSR_IA32_MCx_CTL2(i), val);
		rdmsrl(MSR_IA32_MCx_CTL2(i), val);

		/* Did the enable bit stick? -- the bank supports CMCI */
		if (val & MCI_CTL2_CMCI_EN) {
			set_bit(i, owned);
			__clear_bit(i, this_cpu_ptr(mce_poll_banks));
			/*
			 * We are able to set thresholds for some banks that
			 * had a threshold of 0. This means the BIOS has not
			 * set the thresholds properly or does not work with
			 * this boot option. Note down now and report later.
			 */
			if (mca_cfg.bios_cmci_threshold && bios_zero_thresh &&
					(val & MCI_CTL2_CMCI_THRESHOLD_MASK))
				bios_wrong_thresh = 1;
		} else {
			WARN_ON(!test_bit(i, this_cpu_ptr(mce_poll_banks)));
		}
	}
	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
	if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) {
		pr_info_once(
			"bios_cmci_threshold: Some banks do not have valid thresholds set\n");
		pr_info_once(
			"bios_cmci_threshold: Make sure your BIOS supports this boot option\n");
	}
}

/*
 * Just in case we missed an event during initialization check
 * all the CMCI owned banks.
 */
void cmci_recheck(void)
{
	unsigned long flags;
	int banks;

	if (!mce_available(raw_cpu_ptr(&cpu_info)) || !cmci_supported(&banks))
		return;

	local_irq_save(flags);
	machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
	local_irq_restore(flags);
}

/* Caller must hold the lock on cmci_discover_lock */
static void __cmci_disable_bank(int bank)
{
	u64 val;

	if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))
		return;
	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
	val &= ~MCI_CTL2_CMCI_EN;
	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
	__clear_bit(bank, this_cpu_ptr(mce_banks_owned));
}

/*
 * Disable CMCI on this CPU for all banks it owns when it goes down.
 * This allows other CPUs to claim the banks on rediscovery.
 */
void cmci_clear(void)
{
	unsigned long flags;
	int i;
	int banks;

	if (!cmci_supported(&banks))
		return;
	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
	for (i = 0; i < banks; i++)
		__cmci_disable_bank(i);
	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
}

static void cmci_rediscover_work_func(void *arg)
{
	int banks;

	/* Recheck banks in case CPUs don't all have the same */
	if (cmci_supported(&banks))
		cmci_discover(banks);
}

/* After a CPU went down cycle through all the others and rediscover */
void cmci_rediscover(void)
{
	int banks;

	if (!cmci_supported(&banks))
		return;

	on_each_cpu(cmci_rediscover_work_func, NULL, 1);
}

/*
 * Reenable CMCI on this CPU in case a CPU down failed.
 */
void cmci_reenable(void)
{
	int banks;
	if (cmci_supported(&banks))
		cmci_discover(banks);
}

void cmci_disable_bank(int bank)
{
	int banks;
	unsigned long flags;

	if (!cmci_supported(&banks))
		return;

	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
	__cmci_disable_bank(bank);
	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
}

static void intel_init_cmci(void)
{
	int banks;

	if (!cmci_supported(&banks))
		return;

	mce_threshold_vector = intel_threshold_interrupt;
	cmci_discover(banks);
	/*
	 * For CPU #0 this runs with still disabled APIC, but that's
	 * ok because only the vector is set up. We still do another
	 * check for the banks later for CPU #0 just to make sure
	 * to not miss any events.
	 */
	apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
	cmci_recheck();
}

void intel_init_lmce(void)
{
	u64 val;

	if (!lmce_supported())
		return;

	rdmsrl(MSR_IA32_MCG_EXT_CTL, val);

	if (!(val & MCG_EXT_CTL_LMCE_EN))
		wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
}

void mce_intel_feature_init(struct cpuinfo_x86 *c)
{
	intel_init_thermal(c);
	intel_init_cmci();
	intel_init_lmce();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Intel specific MCE features.
	3	* Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
88ccbedd AK	4	* Copyright (C) 2008, 2009 Intel Corporation
88ccbedd AK	5	* Author: Andi Kleen
1da177e4 LT	6	*/
1da177e4 LT	7
5a0e3ad6	8	#include <linux/gfp.h>
1da177e4 LT	9	#include <linux/interrupt.h>
1da177e4 LT	10	#include <linux/percpu.h>
d43c36dc	11	#include <linux/sched.h>
27f6c573	12	#include <linux/cpumask.h>
1bf7b31e	13	#include <asm/apic.h>
1da177e4 LT	14	#include <asm/processor.h>
	15	#include <asm/msr.h>
	16	#include <asm/mce.h>
1da177e4	17
55babd8f CG	18	#include "mce-internal.h"
55babd8f CG	19
88ccbedd AK	20	/*
	21	* Support for Intel Correct Machine Check Interrupts. This allows
	22	* the CPU to raise an interrupt when a corrected machine check happened.
	23	* Normally we pick those up using a regular polling timer.
	24	* Also supports reliable discovery of shared banks.
	25	*/
	26
0644414e NR	27	/*
	28	* CMCI can be delivered to multiple cpus that share a machine check bank
	29	* so we need to designate a single cpu to process errors logged in each bank
	30	* in the interrupt handler (otherwise we would have many races and potential
	31	* double reporting of the same error).
	32	* Note that this can change when a cpu is offlined or brought online since
	33	* some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
	34	* disables CMCI on all banks owned by the cpu and clears this bitfield. At
	35	* this point, cmci_rediscover() kicks in and a different cpu may end up
	36	* taking ownership of some of the shared MCA banks that were previously
	37	* owned by the offlined cpu.
	38	*/
88ccbedd AK	39	static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
88ccbedd AK	40
3f2f0680 BP	41	/*
	42	* CMCI storm detection backoff counter
	43	*
	44	* During storm, we reset this counter to INITIAL_CHECK_INTERVAL in case we've
	45	* encountered an error. If not, we decrement it by one. We signal the end of
	46	* the CMCI storm when it reaches 0.
	47	*/
	48	static DEFINE_PER_CPU(int, cmci_backoff_cnt);
	49
88ccbedd AK	50	/*
	51	* cmci_discover_lock protects against parallel discovery attempts
	52	* which could race against each other.
	53	*/
ed5c41d3	54	static DEFINE_RAW_SPINLOCK(cmci_discover_lock);
88ccbedd	55
55babd8f CG	56	#define CMCI_THRESHOLD 1
55babd8f CG	57	#define CMCI_POLL_INTERVAL (30 * HZ)
3f2f0680	58	#define CMCI_STORM_INTERVAL (HZ)
55babd8f CG	59	#define CMCI_STORM_THRESHOLD 15
	60
	61	static DEFINE_PER_CPU(unsigned long, cmci_time_stamp);
	62	static DEFINE_PER_CPU(unsigned int, cmci_storm_cnt);
	63	static DEFINE_PER_CPU(unsigned int, cmci_storm_state);
	64
	65	enum {
	66	CMCI_STORM_NONE,
	67	CMCI_STORM_ACTIVE,
	68	CMCI_STORM_SUBSIDED,
	69	};
	70
	71	static atomic_t cmci_storm_on_cpus;
88ccbedd	72
df20e2eb	73	static int cmci_supported(int *banks)
88ccbedd AK	74	{
	75	u64 cap;
	76
7af19e4a	77	if (mca_cfg.cmci_disabled \|\| mca_cfg.ignore_ce)
62fdac59 HS	78	return 0;
62fdac59 HS	79
88ccbedd AK	80	/*
	81	* Vendor check is not strictly needed, but the initial
	82	* initialization is vendor keyed and this
	83	* makes sure none of the backdoors are entered otherwise.
	84	*/
	85	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
	86	return 0;
	87	if (!cpu_has_apic \|\| lapic_get_maxlvt() < 6)
	88	return 0;
	89	rdmsrl(MSR_IA32_MCG_CAP, cap);
	90	*banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
	91	return !!(cap & MCG_CMCI_P);
	92	}
	93
88d53867 AR	94	static bool lmce_supported(void)
	95	{
	96	u64 tmp;
	97
	98	if (mca_cfg.lmce_disabled)
	99	return false;
	100
	101	rdmsrl(MSR_IA32_MCG_CAP, tmp);
	102
	103	/*
	104	* LMCE depends on recovery support in the processor. Hence both
	105	* MCG_SER_P and MCG_LMCE_P should be present in MCG_CAP.
	106	*/
	107	if ((tmp & (MCG_SER_P \| MCG_LMCE_P)) !=
	108	(MCG_SER_P \| MCG_LMCE_P))
	109	return false;
	110
	111	/*
	112	* BIOS should indicate support for LMCE by setting bit 20 in
	113	* IA32_FEATURE_CONTROL without which touching MCG_EXT_CTL will
	114	* generate a #GP fault.
	115	*/
	116	rdmsrl(MSR_IA32_FEATURE_CONTROL, tmp);
	117	if ((tmp & (FEATURE_CONTROL_LOCKED \| FEATURE_CONTROL_LMCE)) ==
	118	(FEATURE_CONTROL_LOCKED \| FEATURE_CONTROL_LMCE))
	119	return true;
	120
	121	return false;
	122	}
	123
3f2f0680	124	bool mce_intel_cmci_poll(void)
55babd8f CG	125	{
55babd8f CG	126	if (__this_cpu_read(cmci_storm_state) == CMCI_STORM_NONE)
3f2f0680 BP	127	return false;
	128
	129	/*
	130	* Reset the counter if we've logged an error in the last poll
	131	* during the storm.
	132	*/
	133	if (machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned)))
	134	this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
	135	else
	136	this_cpu_dec(cmci_backoff_cnt);
	137
	138	return true;
55babd8f CG	139	}
	140
	141	void mce_intel_hcpu_update(unsigned long cpu)
	142	{
	143	if (per_cpu(cmci_storm_state, cpu) == CMCI_STORM_ACTIVE)
	144	atomic_dec(&cmci_storm_on_cpus);
	145
	146	per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
	147	}
	148
3f2f0680	149	unsigned long cmci_intel_adjust_timer(unsigned long interval)
55babd8f	150	{
3f2f0680 BP	151	if ((this_cpu_read(cmci_backoff_cnt) > 0) &&
	152	(__this_cpu_read(cmci_storm_state) == CMCI_STORM_ACTIVE)) {
	153	mce_notify_irq();
	154	return CMCI_STORM_INTERVAL;
	155	}
55babd8f CG	156
	157	switch (__this_cpu_read(cmci_storm_state)) {
	158	case CMCI_STORM_ACTIVE:
3f2f0680	159
55babd8f CG	160	/*
55babd8f CG	161	* We switch back to interrupt mode once the poll timer has
3f2f0680 BP	162	* silenced itself. That means no events recorded and the timer
3f2f0680 BP	163	* interval is back to our poll interval.
55babd8f CG	164	*/
55babd8f CG	165	__this_cpu_write(cmci_storm_state, CMCI_STORM_SUBSIDED);
3f2f0680	166	if (!atomic_sub_return(1, &cmci_storm_on_cpus))
55babd8f	167	pr_notice("CMCI storm subsided: switching to interrupt mode\n");
3f2f0680	168
55babd8f CG	169	/* FALLTHROUGH */
	170
	171	case CMCI_STORM_SUBSIDED:
	172	/*
3f2f0680 BP	173	* We wait for all CPUs to go back to SUBSIDED state. When that
3f2f0680 BP	174	* happens we switch back to interrupt mode.
55babd8f CG	175	*/
	176	if (!atomic_read(&cmci_storm_on_cpus)) {
	177	__this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
	178	cmci_reenable();
	179	cmci_recheck();
	180	}
	181	return CMCI_POLL_INTERVAL;
	182	default:
3f2f0680 BP	183
3f2f0680 BP	184	/* We have shiny weather. Let the poll do whatever it thinks. */
55babd8f CG	185	return interval;
	186	}
	187	}
	188
27f6c573 CG	189	static void cmci_storm_disable_banks(void)
	190	{
	191	unsigned long flags, *owned;
	192	int bank;
	193	u64 val;
	194
ed5c41d3	195	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
89cbc767	196	owned = this_cpu_ptr(mce_banks_owned);
27f6c573 CG	197	for_each_set_bit(bank, owned, MAX_NR_BANKS) {
	198	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
	199	val &= ~MCI_CTL2_CMCI_EN;
	200	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
	201	}
ed5c41d3	202	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
27f6c573 CG	203	}
27f6c573 CG	204
55babd8f CG	205	static bool cmci_storm_detect(void)
	206	{
	207	unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
	208	unsigned long ts = __this_cpu_read(cmci_time_stamp);
	209	unsigned long now = jiffies;
	210	int r;
	211
	212	if (__this_cpu_read(cmci_storm_state) != CMCI_STORM_NONE)
	213	return true;
	214
	215	if (time_before_eq(now, ts + CMCI_STORM_INTERVAL)) {
	216	cnt++;
	217	} else {
	218	cnt = 1;
	219	__this_cpu_write(cmci_time_stamp, now);
	220	}
	221	__this_cpu_write(cmci_storm_cnt, cnt);
	222
	223	if (cnt <= CMCI_STORM_THRESHOLD)
	224	return false;
	225
27f6c573	226	cmci_storm_disable_banks();
55babd8f CG	227	__this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
55babd8f CG	228	r = atomic_add_return(1, &cmci_storm_on_cpus);
3f2f0680 BP	229	mce_timer_kick(CMCI_STORM_INTERVAL);
3f2f0680 BP	230	this_cpu_write(cmci_backoff_cnt, INITIAL_CHECK_INTERVAL);
55babd8f CG	231
	232	if (r == 1)
	233	pr_notice("CMCI storm detected: switching to poll mode\n");
	234	return true;
	235	}
	236
88ccbedd AK	237	/*
	238	* The interrupt handler. This is called on every event.
	239	* Just call the poller directly to log any events.
	240	* This could in theory increase the threshold under high load,
	241	* but doesn't for now.
	242	*/
	243	static void intel_threshold_interrupt(void)
	244	{
55babd8f CG	245	if (cmci_storm_detect())
55babd8f CG	246	return;
3f2f0680	247
89cbc767	248	machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
88ccbedd AK	249	}
88ccbedd AK	250
88ccbedd AK	251	/*
	252	* Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
	253	* on this CPU. Use the algorithm recommended in the SDM to discover shared
	254	* banks.
	255	*/
4670a300	256	static void cmci_discover(int banks)
88ccbedd	257	{
89cbc767	258	unsigned long owned = (void )this_cpu_ptr(&mce_banks_owned);
e5299926	259	unsigned long flags;
88ccbedd	260	int i;
450cc201	261	int bios_wrong_thresh = 0;
88ccbedd	262
ed5c41d3	263	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
88ccbedd AK	264	for (i = 0; i < banks; i++) {
88ccbedd AK	265	u64 val;
450cc201	266	int bios_zero_thresh = 0;
88ccbedd AK	267
	268	if (test_bit(i, owned))
	269	continue;
	270
c3d1fb56 NR	271	/* Skip banks in firmware first mode */
	272	if (test_bit(i, mce_banks_ce_disabled))
	273	continue;
	274
a2d32bcb	275	rdmsrl(MSR_IA32_MCx_CTL2(i), val);
88ccbedd AK	276
88ccbedd AK	277	/* Already owned by someone else? */
1f9a0bd4	278	if (val & MCI_CTL2_CMCI_EN) {
4670a300	279	clear_bit(i, owned);
89cbc767	280	__clear_bit(i, this_cpu_ptr(mce_poll_banks));
88ccbedd AK	281	continue;
	282	}
	283
1462594b	284	if (!mca_cfg.bios_cmci_threshold) {
450cc201 NR	285	val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
	286	val \|= CMCI_THRESHOLD;
	287	} else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {
	288	/*
	289	* If bios_cmci_threshold boot option was specified
	290	* but the threshold is zero, we'll try to initialize
	291	* it to 1.
	292	*/
	293	bios_zero_thresh = 1;
	294	val \|= CMCI_THRESHOLD;
	295	}
	296
	297	val \|= MCI_CTL2_CMCI_EN;
a2d32bcb AK	298	wrmsrl(MSR_IA32_MCx_CTL2(i), val);
a2d32bcb AK	299	rdmsrl(MSR_IA32_MCx_CTL2(i), val);
88ccbedd AK	300
88ccbedd AK	301	/* Did the enable bit stick? -- the bank supports CMCI */
1f9a0bd4	302	if (val & MCI_CTL2_CMCI_EN) {
4670a300	303	set_bit(i, owned);
89cbc767	304	__clear_bit(i, this_cpu_ptr(mce_poll_banks));
450cc201 NR	305	/*
	306	* We are able to set thresholds for some banks that
	307	* had a threshold of 0. This means the BIOS has not
	308	* set the thresholds properly or does not work with
	309	* this boot option. Note down now and report later.
	310	*/
1462594b	311	if (mca_cfg.bios_cmci_threshold && bios_zero_thresh &&
450cc201 NR	312	(val & MCI_CTL2_CMCI_THRESHOLD_MASK))
450cc201 NR	313	bios_wrong_thresh = 1;
88ccbedd	314	} else {
89cbc767	315	WARN_ON(!test_bit(i, this_cpu_ptr(mce_poll_banks)));
88ccbedd AK	316	}
88ccbedd AK	317	}
ed5c41d3	318	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
1462594b	319	if (mca_cfg.bios_cmci_threshold && bios_wrong_thresh) {
450cc201 NR	320	pr_info_once(
	321	"bios_cmci_threshold: Some banks do not have valid thresholds set\n");
	322	pr_info_once(
	323	"bios_cmci_threshold: Make sure your BIOS supports this boot option\n");
	324	}
88ccbedd AK	325	}
	326
	327	/*
	328	* Just in case we missed an event during initialization check
	329	* all the CMCI owned banks.
	330	*/
df20e2eb	331	void cmci_recheck(void)
88ccbedd AK	332	{
	333	unsigned long flags;
	334	int banks;
	335
89cbc767	336	if (!mce_available(raw_cpu_ptr(&cpu_info)) \|\| !cmci_supported(&banks))
88ccbedd	337	return;
3f2f0680	338
88ccbedd	339	local_irq_save(flags);
89cbc767	340	machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_banks_owned));
88ccbedd AK	341	local_irq_restore(flags);
	342	}
	343
c3d1fb56 NR	344	/* Caller must hold the lock on cmci_discover_lock */
	345	static void __cmci_disable_bank(int bank)
	346	{
	347	u64 val;
	348
89cbc767	349	if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))
c3d1fb56 NR	350	return;
	351	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
	352	val &= ~MCI_CTL2_CMCI_EN;
	353	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
89cbc767	354	__clear_bit(bank, this_cpu_ptr(mce_banks_owned));
c3d1fb56 NR	355	}
c3d1fb56 NR	356
88ccbedd AK	357	/*
	358	* Disable CMCI on this CPU for all banks it owns when it goes down.
	359	* This allows other CPUs to claim the banks on rediscovery.
	360	*/
df20e2eb	361	void cmci_clear(void)
88ccbedd	362	{
e5299926	363	unsigned long flags;
88ccbedd AK	364	int i;
88ccbedd AK	365	int banks;
88ccbedd AK	366
	367	if (!cmci_supported(&banks))
	368	return;
ed5c41d3	369	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
c3d1fb56 NR	370	for (i = 0; i < banks; i++)
c3d1fb56 NR	371	__cmci_disable_bank(i);
ed5c41d3	372	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
88ccbedd AK	373	}
88ccbedd AK	374
7a0c819d	375	static void cmci_rediscover_work_func(void *arg)
85b97637 TC	376	{
	377	int banks;
	378
	379	/* Recheck banks in case CPUs don't all have the same */
	380	if (cmci_supported(&banks))
	381	cmci_discover(banks);
85b97637 TC	382	}
85b97637 TC	383
7a0c819d SB	384	/* After a CPU went down cycle through all the others and rediscover */
7a0c819d SB	385	void cmci_rediscover(void)
88ccbedd	386	{
7a0c819d	387	int banks;
88ccbedd AK	388
	389	if (!cmci_supported(&banks))
	390	return;
88ccbedd	391
7a0c819d	392	on_each_cpu(cmci_rediscover_work_func, NULL, 1);
88ccbedd AK	393	}
	394
	395	/*
	396	* Reenable CMCI on this CPU in case a CPU down failed.
	397	*/
	398	void cmci_reenable(void)
	399	{
	400	int banks;
	401	if (cmci_supported(&banks))
4670a300	402	cmci_discover(banks);
88ccbedd AK	403	}
88ccbedd AK	404
c3d1fb56 NR	405	void cmci_disable_bank(int bank)
	406	{
	407	int banks;
	408	unsigned long flags;
	409
	410	if (!cmci_supported(&banks))
	411	return;
	412
ed5c41d3	413	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
c3d1fb56	414	__cmci_disable_bank(bank);
ed5c41d3	415	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
c3d1fb56 NR	416	}
c3d1fb56 NR	417
514ec49a	418	static void intel_init_cmci(void)
88ccbedd AK	419	{
	420	int banks;
	421
	422	if (!cmci_supported(&banks))
	423	return;
	424
	425	mce_threshold_vector = intel_threshold_interrupt;
4670a300	426	cmci_discover(banks);
88ccbedd AK	427	/*
	428	* For CPU #0 this runs with still disabled APIC, but that's
	429	* ok because only the vector is set up. We still do another
	430	* check for the banks later for CPU #0 just to make sure
	431	* to not miss any events.
	432	*/
	433	apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR\|APIC_DM_FIXED);
	434	cmci_recheck();
	435	}
	436
88d53867 AR	437	void intel_init_lmce(void)
	438	{
	439	u64 val;
	440
	441	if (!lmce_supported())
	442	return;
	443
	444	rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
	445
	446	if (!(val & MCG_EXT_CTL_LMCE_EN))
	447	wrmsrl(MSR_IA32_MCG_EXT_CTL, val \| MCG_EXT_CTL_LMCE_EN);
	448	}
	449
cc3ca220	450	void mce_intel_feature_init(struct cpuinfo_x86 *c)
1da177e4 LT	451	{
1da177e4 LT	452	intel_init_thermal(c);
88ccbedd	453	intel_init_cmci();
243d657e	454	intel_init_lmce();
1da177e4	455	}