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1da177e4 LT |
1 | /* |
2 | * Intel specific MCE features. | |
3 | * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca> | |
88ccbedd AK |
4 | * Copyright (C) 2008, 2009 Intel Corporation |
5 | * Author: Andi Kleen | |
1da177e4 LT |
6 | */ |
7 | ||
8 | #include <linux/init.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/percpu.h> | |
11 | #include <asm/processor.h> | |
12 | #include <asm/msr.h> | |
13 | #include <asm/mce.h> | |
1da177e4 | 14 | |
88ccbedd AK |
15 | /* |
16 | * Support for Intel Correct Machine Check Interrupts. This allows | |
17 | * the CPU to raise an interrupt when a corrected machine check happened. | |
18 | * Normally we pick those up using a regular polling timer. | |
19 | * Also supports reliable discovery of shared banks. | |
20 | */ | |
21 | ||
22 | static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); | |
23 | ||
24 | /* | |
25 | * cmci_discover_lock protects against parallel discovery attempts | |
26 | * which could race against each other. | |
27 | */ | |
28 | static DEFINE_SPINLOCK(cmci_discover_lock); | |
29 | ||
30 | #define CMCI_THRESHOLD 1 | |
31 | ||
df20e2eb | 32 | static int cmci_supported(int *banks) |
88ccbedd AK |
33 | { |
34 | u64 cap; | |
35 | ||
62fdac59 HS |
36 | if (mce_cmci_disabled || mce_ignore_ce) |
37 | return 0; | |
38 | ||
88ccbedd AK |
39 | /* |
40 | * Vendor check is not strictly needed, but the initial | |
41 | * initialization is vendor keyed and this | |
42 | * makes sure none of the backdoors are entered otherwise. | |
43 | */ | |
44 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
45 | return 0; | |
46 | if (!cpu_has_apic || lapic_get_maxlvt() < 6) | |
47 | return 0; | |
48 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
49 | *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff); | |
50 | return !!(cap & MCG_CMCI_P); | |
51 | } | |
52 | ||
53 | /* | |
54 | * The interrupt handler. This is called on every event. | |
55 | * Just call the poller directly to log any events. | |
56 | * This could in theory increase the threshold under high load, | |
57 | * but doesn't for now. | |
58 | */ | |
59 | static void intel_threshold_interrupt(void) | |
60 | { | |
61 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); | |
9ff36ee9 | 62 | mce_notify_irq(); |
88ccbedd AK |
63 | } |
64 | ||
65 | static void print_update(char *type, int *hdr, int num) | |
66 | { | |
67 | if (*hdr == 0) | |
68 | printk(KERN_INFO "CPU %d MCA banks", smp_processor_id()); | |
69 | *hdr = 1; | |
70 | printk(KERN_CONT " %s:%d", type, num); | |
71 | } | |
72 | ||
73 | /* | |
74 | * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks | |
75 | * on this CPU. Use the algorithm recommended in the SDM to discover shared | |
76 | * banks. | |
77 | */ | |
df20e2eb | 78 | static void cmci_discover(int banks, int boot) |
88ccbedd AK |
79 | { |
80 | unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned); | |
e5299926 | 81 | unsigned long flags; |
88ccbedd AK |
82 | int hdr = 0; |
83 | int i; | |
84 | ||
e5299926 | 85 | spin_lock_irqsave(&cmci_discover_lock, flags); |
88ccbedd AK |
86 | for (i = 0; i < banks; i++) { |
87 | u64 val; | |
88 | ||
89 | if (test_bit(i, owned)) | |
90 | continue; | |
91 | ||
92 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
93 | ||
94 | /* Already owned by someone else? */ | |
95 | if (val & CMCI_EN) { | |
96 | if (test_and_clear_bit(i, owned) || boot) | |
97 | print_update("SHD", &hdr, i); | |
98 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | |
99 | continue; | |
100 | } | |
101 | ||
102 | val |= CMCI_EN | CMCI_THRESHOLD; | |
103 | wrmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
104 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
105 | ||
106 | /* Did the enable bit stick? -- the bank supports CMCI */ | |
107 | if (val & CMCI_EN) { | |
108 | if (!test_and_set_bit(i, owned) || boot) | |
109 | print_update("CMCI", &hdr, i); | |
110 | __clear_bit(i, __get_cpu_var(mce_poll_banks)); | |
111 | } else { | |
112 | WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks))); | |
113 | } | |
114 | } | |
e5299926 | 115 | spin_unlock_irqrestore(&cmci_discover_lock, flags); |
88ccbedd AK |
116 | if (hdr) |
117 | printk(KERN_CONT "\n"); | |
118 | } | |
119 | ||
120 | /* | |
121 | * Just in case we missed an event during initialization check | |
122 | * all the CMCI owned banks. | |
123 | */ | |
df20e2eb | 124 | void cmci_recheck(void) |
88ccbedd AK |
125 | { |
126 | unsigned long flags; | |
127 | int banks; | |
128 | ||
129 | if (!mce_available(¤t_cpu_data) || !cmci_supported(&banks)) | |
130 | return; | |
131 | local_irq_save(flags); | |
132 | machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned)); | |
133 | local_irq_restore(flags); | |
134 | } | |
135 | ||
136 | /* | |
137 | * Disable CMCI on this CPU for all banks it owns when it goes down. | |
138 | * This allows other CPUs to claim the banks on rediscovery. | |
139 | */ | |
df20e2eb | 140 | void cmci_clear(void) |
88ccbedd | 141 | { |
e5299926 | 142 | unsigned long flags; |
88ccbedd AK |
143 | int i; |
144 | int banks; | |
145 | u64 val; | |
146 | ||
147 | if (!cmci_supported(&banks)) | |
148 | return; | |
e5299926 | 149 | spin_lock_irqsave(&cmci_discover_lock, flags); |
88ccbedd AK |
150 | for (i = 0; i < banks; i++) { |
151 | if (!test_bit(i, __get_cpu_var(mce_banks_owned))) | |
152 | continue; | |
153 | /* Disable CMCI */ | |
154 | rdmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
155 | val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK); | |
156 | wrmsrl(MSR_IA32_MC0_CTL2 + i, val); | |
157 | __clear_bit(i, __get_cpu_var(mce_banks_owned)); | |
158 | } | |
e5299926 | 159 | spin_unlock_irqrestore(&cmci_discover_lock, flags); |
88ccbedd AK |
160 | } |
161 | ||
162 | /* | |
163 | * After a CPU went down cycle through all the others and rediscover | |
164 | * Must run in process context. | |
165 | */ | |
df20e2eb | 166 | void cmci_rediscover(int dying) |
88ccbedd AK |
167 | { |
168 | int banks; | |
169 | int cpu; | |
170 | cpumask_var_t old; | |
171 | ||
172 | if (!cmci_supported(&banks)) | |
173 | return; | |
174 | if (!alloc_cpumask_var(&old, GFP_KERNEL)) | |
175 | return; | |
176 | cpumask_copy(old, ¤t->cpus_allowed); | |
177 | ||
61a021a0 | 178 | for_each_online_cpu(cpu) { |
88ccbedd AK |
179 | if (cpu == dying) |
180 | continue; | |
4f062896 | 181 | if (set_cpus_allowed_ptr(current, cpumask_of(cpu))) |
88ccbedd AK |
182 | continue; |
183 | /* Recheck banks in case CPUs don't all have the same */ | |
184 | if (cmci_supported(&banks)) | |
185 | cmci_discover(banks, 0); | |
186 | } | |
187 | ||
188 | set_cpus_allowed_ptr(current, old); | |
189 | free_cpumask_var(old); | |
190 | } | |
191 | ||
192 | /* | |
193 | * Reenable CMCI on this CPU in case a CPU down failed. | |
194 | */ | |
195 | void cmci_reenable(void) | |
196 | { | |
197 | int banks; | |
198 | if (cmci_supported(&banks)) | |
199 | cmci_discover(banks, 0); | |
200 | } | |
201 | ||
514ec49a | 202 | static void intel_init_cmci(void) |
88ccbedd AK |
203 | { |
204 | int banks; | |
205 | ||
206 | if (!cmci_supported(&banks)) | |
207 | return; | |
208 | ||
209 | mce_threshold_vector = intel_threshold_interrupt; | |
210 | cmci_discover(banks, 1); | |
211 | /* | |
212 | * For CPU #0 this runs with still disabled APIC, but that's | |
213 | * ok because only the vector is set up. We still do another | |
214 | * check for the banks later for CPU #0 just to make sure | |
215 | * to not miss any events. | |
216 | */ | |
217 | apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED); | |
218 | cmci_recheck(); | |
219 | } | |
220 | ||
cc3ca220 | 221 | void mce_intel_feature_init(struct cpuinfo_x86 *c) |
1da177e4 LT |
222 | { |
223 | intel_init_thermal(c); | |
88ccbedd | 224 | intel_init_cmci(); |
1da177e4 | 225 | } |