Commit | Line | Data |
---|---|---|
89b831ef | 1 | /* |
ea2ca36b | 2 | * (c) 2005-2016 Advanced Micro Devices, Inc. |
89b831ef JS |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
7 | * Written by Jacob Shin - AMD, Inc. | |
e6d41e8c | 8 | * Maintained by: Borislav Petkov <bp@alien8.de> |
89b831ef | 9 | * |
3490c0e4 | 10 | * All MC4_MISCi registers are shared between cores on a node. |
89b831ef | 11 | */ |
89b831ef | 12 | #include <linux/interrupt.h> |
89b831ef | 13 | #include <linux/notifier.h> |
1cb2a8e1 | 14 | #include <linux/kobject.h> |
34fa1967 | 15 | #include <linux/percpu.h> |
1cb2a8e1 IM |
16 | #include <linux/errno.h> |
17 | #include <linux/sched.h> | |
89b831ef | 18 | #include <linux/sysfs.h> |
5a0e3ad6 | 19 | #include <linux/slab.h> |
1cb2a8e1 IM |
20 | #include <linux/init.h> |
21 | #include <linux/cpu.h> | |
22 | #include <linux/smp.h> | |
23 | ||
019f34fc | 24 | #include <asm/amd_nb.h> |
89b831ef | 25 | #include <asm/apic.h> |
1cb2a8e1 | 26 | #include <asm/idle.h> |
89b831ef JS |
27 | #include <asm/mce.h> |
28 | #include <asm/msr.h> | |
24fd78a8 | 29 | #include <asm/trace/irq_vectors.h> |
89b831ef | 30 | |
60f116fc | 31 | #define NR_BLOCKS 5 |
2903ee85 JS |
32 | #define THRESHOLD_MAX 0xFFF |
33 | #define INT_TYPE_APIC 0x00020000 | |
34 | #define MASK_VALID_HI 0x80000000 | |
24ce0e96 JB |
35 | #define MASK_CNTP_HI 0x40000000 |
36 | #define MASK_LOCKED_HI 0x20000000 | |
2903ee85 JS |
37 | #define MASK_LVTOFF_HI 0x00F00000 |
38 | #define MASK_COUNT_EN_HI 0x00080000 | |
39 | #define MASK_INT_TYPE_HI 0x00060000 | |
40 | #define MASK_OVERFLOW_HI 0x00010000 | |
89b831ef | 41 | #define MASK_ERR_COUNT_HI 0x00000FFF |
95268664 JS |
42 | #define MASK_BLKPTR_LO 0xFF000000 |
43 | #define MCG_XBLK_ADDR 0xC0000400 | |
89b831ef | 44 | |
24fd78a8 AG |
45 | /* Deferred error settings */ |
46 | #define MSR_CU_DEF_ERR 0xC0000410 | |
47 | #define MASK_DEF_LVTOFF 0x000000F0 | |
48 | #define MASK_DEF_INT_TYPE 0x00000006 | |
49 | #define DEF_LVT_OFF 0x2 | |
50 | #define DEF_INT_TYPE_APIC 0x2 | |
51 | ||
f57a1f3c AG |
52 | /* Scalable MCA: */ |
53 | ||
54 | /* Threshold LVT offset is at MSR0xC0000410[15:12] */ | |
55 | #define SMCA_THR_LVT_OFF 0xF000 | |
56 | ||
336d335a BP |
57 | static const char * const th_names[] = { |
58 | "load_store", | |
59 | "insn_fetch", | |
60 | "combined_unit", | |
61 | "", | |
62 | "northbridge", | |
63 | "execution_unit", | |
64 | }; | |
65 | ||
be0aec23 AG |
66 | /* Define HWID to IP type mappings for Scalable MCA */ |
67 | struct amd_hwid amd_hwids[] = { | |
68 | [SMCA_F17H_CORE] = { "f17h_core", 0xB0 }, | |
69 | [SMCA_DF] = { "data_fabric", 0x2E }, | |
70 | [SMCA_UMC] = { "umc", 0x96 }, | |
71 | [SMCA_PB] = { "param_block", 0x5 }, | |
72 | [SMCA_PSP] = { "psp", 0xFF }, | |
73 | [SMCA_SMU] = { "smu", 0x1 }, | |
74 | }; | |
75 | EXPORT_SYMBOL_GPL(amd_hwids); | |
76 | ||
77 | const char * const amd_core_mcablock_names[] = { | |
78 | [SMCA_LS] = "load_store", | |
79 | [SMCA_IF] = "insn_fetch", | |
80 | [SMCA_L2_CACHE] = "l2_cache", | |
81 | [SMCA_DE] = "decode_unit", | |
82 | [RES] = "", | |
83 | [SMCA_EX] = "execution_unit", | |
84 | [SMCA_FP] = "floating_point", | |
85 | [SMCA_L3_CACHE] = "l3_cache", | |
86 | }; | |
87 | EXPORT_SYMBOL_GPL(amd_core_mcablock_names); | |
88 | ||
89 | const char * const amd_df_mcablock_names[] = { | |
90 | [SMCA_CS] = "coherent_slave", | |
91 | [SMCA_PIE] = "pie", | |
92 | }; | |
93 | EXPORT_SYMBOL_GPL(amd_df_mcablock_names); | |
94 | ||
bafcdd3b | 95 | static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks); |
89b831ef JS |
96 | static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */ |
97 | ||
b2762686 | 98 | static void amd_threshold_interrupt(void); |
24fd78a8 AG |
99 | static void amd_deferred_error_interrupt(void); |
100 | ||
101 | static void default_deferred_error_interrupt(void) | |
102 | { | |
103 | pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR); | |
104 | } | |
105 | void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; | |
b2762686 | 106 | |
89b831ef JS |
107 | /* |
108 | * CPU Initialization | |
109 | */ | |
110 | ||
4cd4601d | 111 | struct thresh_restart { |
1cb2a8e1 IM |
112 | struct threshold_block *b; |
113 | int reset; | |
9c37c9d8 RR |
114 | int set_lvt_off; |
115 | int lvt_off; | |
1cb2a8e1 | 116 | u16 old_limit; |
4cd4601d MT |
117 | }; |
118 | ||
c76e8164 BO |
119 | static inline bool is_shared_bank(int bank) |
120 | { | |
284b965c AG |
121 | /* |
122 | * Scalable MCA provides for only one core to have access to the MSRs of | |
123 | * a shared bank. | |
124 | */ | |
125 | if (mce_flags.smca) | |
126 | return false; | |
127 | ||
c76e8164 BO |
128 | /* Bank 4 is for northbridge reporting and is thus shared */ |
129 | return (bank == 4); | |
130 | } | |
131 | ||
2cd4c303 | 132 | static const char *bank4_names(const struct threshold_block *b) |
336d335a BP |
133 | { |
134 | switch (b->address) { | |
135 | /* MSR4_MISC0 */ | |
136 | case 0x00000413: | |
137 | return "dram"; | |
138 | ||
139 | case 0xc0000408: | |
140 | return "ht_links"; | |
141 | ||
142 | case 0xc0000409: | |
143 | return "l3_cache"; | |
144 | ||
145 | default: | |
146 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | |
147 | return ""; | |
148 | } | |
149 | }; | |
150 | ||
151 | ||
f227d430 BP |
152 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
153 | { | |
154 | /* | |
155 | * bank 4 supports APIC LVT interrupts implicitly since forever. | |
156 | */ | |
157 | if (bank == 4) | |
158 | return true; | |
159 | ||
160 | /* | |
161 | * IntP: interrupt present; if this bit is set, the thresholding | |
162 | * bank can generate APIC LVT interrupts | |
163 | */ | |
164 | return msr_high_bits & BIT(28); | |
165 | } | |
166 | ||
bbaff08d RR |
167 | static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) |
168 | { | |
169 | int msr = (hi & MASK_LVTOFF_HI) >> 20; | |
170 | ||
171 | if (apic < 0) { | |
172 | pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " | |
173 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, | |
174 | b->bank, b->block, b->address, hi, lo); | |
175 | return 0; | |
176 | } | |
177 | ||
178 | if (apic != msr) { | |
f57a1f3c AG |
179 | /* |
180 | * On SMCA CPUs, LVT offset is programmed at a different MSR, and | |
181 | * the BIOS provides the value. The original field where LVT offset | |
182 | * was set is reserved. Return early here: | |
183 | */ | |
184 | if (mce_flags.smca) | |
185 | return 0; | |
186 | ||
bbaff08d RR |
187 | pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " |
188 | "for bank %d, block %d (MSR%08X=0x%x%08x)\n", | |
189 | b->cpu, apic, b->bank, b->block, b->address, hi, lo); | |
190 | return 0; | |
191 | } | |
192 | ||
193 | return 1; | |
194 | }; | |
195 | ||
ea2ca36b | 196 | /* Reprogram MCx_MISC MSR behind this threshold bank. */ |
a6b6a14e | 197 | static void threshold_restart_bank(void *_tr) |
89b831ef | 198 | { |
4cd4601d | 199 | struct thresh_restart *tr = _tr; |
7203a049 | 200 | u32 hi, lo; |
89b831ef | 201 | |
7203a049 | 202 | rdmsr(tr->b->address, lo, hi); |
89b831ef | 203 | |
7203a049 | 204 | if (tr->b->threshold_limit < (hi & THRESHOLD_MAX)) |
4cd4601d | 205 | tr->reset = 1; /* limit cannot be lower than err count */ |
89b831ef | 206 | |
4cd4601d | 207 | if (tr->reset) { /* reset err count and overflow bit */ |
7203a049 RR |
208 | hi = |
209 | (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) | | |
4cd4601d MT |
210 | (THRESHOLD_MAX - tr->b->threshold_limit); |
211 | } else if (tr->old_limit) { /* change limit w/o reset */ | |
7203a049 | 212 | int new_count = (hi & THRESHOLD_MAX) + |
4cd4601d | 213 | (tr->old_limit - tr->b->threshold_limit); |
1cb2a8e1 | 214 | |
7203a049 | 215 | hi = (hi & ~MASK_ERR_COUNT_HI) | |
89b831ef JS |
216 | (new_count & THRESHOLD_MAX); |
217 | } | |
218 | ||
f227d430 BP |
219 | /* clear IntType */ |
220 | hi &= ~MASK_INT_TYPE_HI; | |
221 | ||
222 | if (!tr->b->interrupt_capable) | |
223 | goto done; | |
224 | ||
9c37c9d8 | 225 | if (tr->set_lvt_off) { |
bbaff08d RR |
226 | if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { |
227 | /* set new lvt offset */ | |
228 | hi &= ~MASK_LVTOFF_HI; | |
229 | hi |= tr->lvt_off << 20; | |
230 | } | |
9c37c9d8 RR |
231 | } |
232 | ||
f227d430 BP |
233 | if (tr->b->interrupt_enable) |
234 | hi |= INT_TYPE_APIC; | |
235 | ||
236 | done: | |
89b831ef | 237 | |
7203a049 RR |
238 | hi |= MASK_COUNT_EN_HI; |
239 | wrmsr(tr->b->address, lo, hi); | |
89b831ef JS |
240 | } |
241 | ||
9c37c9d8 RR |
242 | static void mce_threshold_block_init(struct threshold_block *b, int offset) |
243 | { | |
244 | struct thresh_restart tr = { | |
245 | .b = b, | |
246 | .set_lvt_off = 1, | |
247 | .lvt_off = offset, | |
248 | }; | |
249 | ||
250 | b->threshold_limit = THRESHOLD_MAX; | |
251 | threshold_restart_bank(&tr); | |
252 | }; | |
253 | ||
868c00bb | 254 | static int setup_APIC_mce_threshold(int reserved, int new) |
bbaff08d RR |
255 | { |
256 | if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR, | |
257 | APIC_EILVT_MSG_FIX, 0)) | |
258 | return new; | |
259 | ||
260 | return reserved; | |
261 | } | |
262 | ||
24fd78a8 AG |
263 | static int setup_APIC_deferred_error(int reserved, int new) |
264 | { | |
265 | if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR, | |
266 | APIC_EILVT_MSG_FIX, 0)) | |
267 | return new; | |
268 | ||
269 | return reserved; | |
270 | } | |
271 | ||
272 | static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) | |
273 | { | |
274 | u32 low = 0, high = 0; | |
275 | int def_offset = -1, def_new; | |
276 | ||
277 | if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high)) | |
278 | return; | |
279 | ||
280 | def_new = (low & MASK_DEF_LVTOFF) >> 4; | |
281 | if (!(low & MASK_DEF_LVTOFF)) { | |
282 | pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n"); | |
283 | def_new = DEF_LVT_OFF; | |
284 | low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4); | |
285 | } | |
286 | ||
287 | def_offset = setup_APIC_deferred_error(def_offset, def_new); | |
288 | if ((def_offset == def_new) && | |
289 | (deferred_error_int_vector != amd_deferred_error_interrupt)) | |
290 | deferred_error_int_vector = amd_deferred_error_interrupt; | |
291 | ||
292 | low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; | |
293 | wrmsr(MSR_CU_DEF_ERR, low, high); | |
294 | } | |
295 | ||
8dd1e17a AG |
296 | static u32 get_block_address(u32 current_addr, u32 low, u32 high, |
297 | unsigned int bank, unsigned int block) | |
298 | { | |
299 | u32 addr = 0, offset = 0; | |
300 | ||
301 | if (mce_flags.smca) { | |
302 | if (!block) { | |
303 | addr = MSR_AMD64_SMCA_MCx_MISC(bank); | |
304 | } else { | |
305 | /* | |
306 | * For SMCA enabled processors, BLKPTR field of the | |
307 | * first MISC register (MCx_MISC0) indicates presence of | |
308 | * additional MISC register set (MISC1-4). | |
309 | */ | |
310 | u32 low, high; | |
311 | ||
312 | if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high)) | |
313 | return addr; | |
314 | ||
315 | if (!(low & MCI_CONFIG_MCAX)) | |
316 | return addr; | |
317 | ||
318 | if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) && | |
319 | (low & MASK_BLKPTR_LO)) | |
320 | addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1); | |
321 | } | |
322 | return addr; | |
323 | } | |
324 | ||
325 | /* Fall back to method we used for older processors: */ | |
326 | switch (block) { | |
327 | case 0: | |
d9d73fcc | 328 | addr = msr_ops.misc(bank); |
8dd1e17a AG |
329 | break; |
330 | case 1: | |
331 | offset = ((low & MASK_BLKPTR_LO) >> 21); | |
332 | if (offset) | |
333 | addr = MCG_XBLK_ADDR + offset; | |
334 | break; | |
335 | default: | |
336 | addr = ++current_addr; | |
337 | } | |
338 | return addr; | |
339 | } | |
340 | ||
429893b1 BP |
341 | static int |
342 | prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, | |
343 | int offset, u32 misc_high) | |
344 | { | |
345 | unsigned int cpu = smp_processor_id(); | |
346 | struct threshold_block b; | |
347 | int new; | |
348 | ||
349 | if (!block) | |
350 | per_cpu(bank_map, cpu) |= (1 << bank); | |
351 | ||
352 | memset(&b, 0, sizeof(b)); | |
353 | b.cpu = cpu; | |
354 | b.bank = bank; | |
355 | b.block = block; | |
356 | b.address = addr; | |
357 | b.interrupt_capable = lvt_interrupt_supported(bank, misc_high); | |
358 | ||
359 | if (!b.interrupt_capable) | |
360 | goto done; | |
361 | ||
362 | b.interrupt_enable = 1; | |
363 | ||
364 | if (mce_flags.smca) { | |
365 | u32 smca_low, smca_high; | |
e6c8f187 AG |
366 | u32 smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); |
367 | ||
368 | if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { | |
32544f06 YG |
369 | /* |
370 | * OS is required to set the MCAX bit to acknowledge | |
371 | * that it is now using the new MSR ranges and new | |
372 | * registers under each bank. It also means that the OS | |
373 | * will configure deferred errors in the new MCx_CONFIG | |
374 | * register. If the bit is not set, uncorrectable errors | |
375 | * will cause a system panic. | |
376 | * | |
377 | * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of | |
378 | * the MSR.) | |
379 | */ | |
380 | smca_high |= BIT(0); | |
381 | ||
382 | /* | |
383 | * SMCA logs Deferred Error information in | |
384 | * MCA_DE{STAT,ADDR} registers with the option of | |
385 | * additionally logging to MCA_{STATUS,ADDR} if | |
386 | * MCA_CONFIG[LogDeferredInMcaStat] is set. | |
387 | * | |
388 | * This bit is usually set by BIOS to retain the old | |
389 | * behavior for OSes that don't use the new registers. | |
390 | * Linux supports the new registers so let's disable | |
391 | * that additional logging here. | |
392 | * | |
393 | * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in | |
394 | * the high portion of the MSR). | |
395 | */ | |
396 | smca_high &= ~BIT(2); | |
397 | ||
e6c8f187 AG |
398 | wrmsr(smca_addr, smca_low, smca_high); |
399 | } | |
429893b1 BP |
400 | |
401 | /* Gather LVT offset for thresholding: */ | |
402 | if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) | |
403 | goto out; | |
404 | ||
405 | new = (smca_low & SMCA_THR_LVT_OFF) >> 12; | |
406 | } else { | |
407 | new = (misc_high & MASK_LVTOFF_HI) >> 20; | |
408 | } | |
409 | ||
410 | offset = setup_APIC_mce_threshold(offset, new); | |
411 | ||
412 | if ((offset == new) && (mce_threshold_vector != amd_threshold_interrupt)) | |
413 | mce_threshold_vector = amd_threshold_interrupt; | |
414 | ||
415 | done: | |
416 | mce_threshold_block_init(&b, offset); | |
417 | ||
418 | out: | |
419 | return offset; | |
420 | } | |
421 | ||
95268664 | 422 | /* cpu init entry point, called from mce.c with preempt off */ |
cc3ca220 | 423 | void mce_amd_feature_init(struct cpuinfo_x86 *c) |
89b831ef | 424 | { |
95268664 | 425 | u32 low = 0, high = 0, address = 0; |
1cb2a8e1 | 426 | unsigned int bank, block; |
429893b1 | 427 | int offset = -1; |
89b831ef | 428 | |
bafcdd3b | 429 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
95268664 | 430 | for (block = 0; block < NR_BLOCKS; ++block) { |
8dd1e17a AG |
431 | address = get_block_address(address, low, high, bank, block); |
432 | if (!address) | |
433 | break; | |
95268664 JS |
434 | |
435 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 436 | break; |
95268664 | 437 | |
6dcbfe4f BP |
438 | if (!(high & MASK_VALID_HI)) |
439 | continue; | |
95268664 | 440 | |
24ce0e96 JB |
441 | if (!(high & MASK_CNTP_HI) || |
442 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
443 | continue; |
444 | ||
429893b1 | 445 | offset = prepare_threshold_block(bank, block, address, offset, high); |
95268664 | 446 | } |
89b831ef | 447 | } |
24fd78a8 AG |
448 | |
449 | if (mce_flags.succor) | |
450 | deferred_error_interrupt_enable(c); | |
89b831ef JS |
451 | } |
452 | ||
34102009 YG |
453 | static void |
454 | __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) | |
afdf344e | 455 | { |
34102009 YG |
456 | u32 msr_status = msr_ops.status(bank); |
457 | u32 msr_addr = msr_ops.addr(bank); | |
afdf344e AG |
458 | struct mce m; |
459 | u64 status; | |
460 | ||
34102009 YG |
461 | WARN_ON_ONCE(deferred_err && threshold_err); |
462 | ||
463 | if (deferred_err && mce_flags.smca) { | |
464 | msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); | |
465 | msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); | |
466 | } | |
467 | ||
468 | rdmsrl(msr_status, status); | |
469 | ||
afdf344e AG |
470 | if (!(status & MCI_STATUS_VAL)) |
471 | return; | |
472 | ||
473 | mce_setup(&m); | |
474 | ||
475 | m.status = status; | |
476 | m.bank = bank; | |
6e6e746e | 477 | |
afdf344e AG |
478 | if (threshold_err) |
479 | m.misc = misc; | |
480 | ||
6e6e746e | 481 | if (m.status & MCI_STATUS_ADDRV) |
34102009 | 482 | rdmsrl(msr_addr, m.addr); |
afdf344e | 483 | |
6e6e746e | 484 | mce_log(&m); |
34102009 YG |
485 | |
486 | wrmsrl(msr_status, 0); | |
afdf344e AG |
487 | } |
488 | ||
24fd78a8 AG |
489 | static inline void __smp_deferred_error_interrupt(void) |
490 | { | |
491 | inc_irq_stat(irq_deferred_error_count); | |
492 | deferred_error_int_vector(); | |
493 | } | |
494 | ||
495 | asmlinkage __visible void smp_deferred_error_interrupt(void) | |
496 | { | |
497 | entering_irq(); | |
498 | __smp_deferred_error_interrupt(); | |
499 | exiting_ack_irq(); | |
500 | } | |
501 | ||
502 | asmlinkage __visible void smp_trace_deferred_error_interrupt(void) | |
503 | { | |
504 | entering_irq(); | |
505 | trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR); | |
506 | __smp_deferred_error_interrupt(); | |
507 | trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR); | |
508 | exiting_ack_irq(); | |
509 | } | |
510 | ||
511 | /* APIC interrupt handler for deferred errors */ | |
512 | static void amd_deferred_error_interrupt(void) | |
513 | { | |
24fd78a8 | 514 | unsigned int bank; |
34102009 YG |
515 | u32 msr_status; |
516 | u64 status; | |
24fd78a8 AG |
517 | |
518 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
34102009 YG |
519 | msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) |
520 | : msr_ops.status(bank); | |
521 | ||
522 | rdmsrl(msr_status, status); | |
24fd78a8 AG |
523 | |
524 | if (!(status & MCI_STATUS_VAL) || | |
525 | !(status & MCI_STATUS_DEFERRED)) | |
526 | continue; | |
527 | ||
34102009 | 528 | __log_error(bank, true, false, 0); |
24fd78a8 AG |
529 | break; |
530 | } | |
531 | } | |
532 | ||
89b831ef JS |
533 | /* |
534 | * APIC Interrupt Handler | |
535 | */ | |
536 | ||
537 | /* | |
538 | * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. | |
539 | * the interrupt goes off when error_count reaches threshold_limit. | |
540 | * the handler will simply log mcelog w/ software defined bank number. | |
541 | */ | |
afdf344e | 542 | |
b2762686 | 543 | static void amd_threshold_interrupt(void) |
89b831ef | 544 | { |
1cb2a8e1 | 545 | u32 low = 0, high = 0, address = 0; |
44612a3a | 546 | int cpu = smp_processor_id(); |
95268664 | 547 | unsigned int bank, block; |
89b831ef | 548 | |
89b831ef | 549 | /* assume first bank caused it */ |
bafcdd3b | 550 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
44612a3a | 551 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
24ce0e96 | 552 | continue; |
95268664 | 553 | for (block = 0; block < NR_BLOCKS; ++block) { |
8dd1e17a AG |
554 | address = get_block_address(address, low, high, bank, block); |
555 | if (!address) | |
556 | break; | |
95268664 JS |
557 | |
558 | if (rdmsr_safe(address, &low, &high)) | |
24ce0e96 | 559 | break; |
95268664 JS |
560 | |
561 | if (!(high & MASK_VALID_HI)) { | |
562 | if (block) | |
563 | continue; | |
564 | else | |
565 | break; | |
566 | } | |
567 | ||
24ce0e96 JB |
568 | if (!(high & MASK_CNTP_HI) || |
569 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
570 | continue; |
571 | ||
1cb2a8e1 IM |
572 | /* |
573 | * Log the machine check that caused the threshold | |
574 | * event. | |
575 | */ | |
44612a3a CY |
576 | if (high & MASK_OVERFLOW_HI) |
577 | goto log; | |
89b831ef JS |
578 | } |
579 | } | |
44612a3a CY |
580 | return; |
581 | ||
582 | log: | |
34102009 | 583 | __log_error(bank, false, true, ((u64)high << 32) | low); |
89b831ef JS |
584 | } |
585 | ||
586 | /* | |
587 | * Sysfs Interface | |
588 | */ | |
589 | ||
89b831ef | 590 | struct threshold_attr { |
2903ee85 | 591 | struct attribute attr; |
1cb2a8e1 IM |
592 | ssize_t (*show) (struct threshold_block *, char *); |
593 | ssize_t (*store) (struct threshold_block *, const char *, size_t count); | |
89b831ef JS |
594 | }; |
595 | ||
1cb2a8e1 IM |
596 | #define SHOW_FIELDS(name) \ |
597 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | |
598 | { \ | |
18c20f37 | 599 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
2903ee85 | 600 | } |
89b831ef JS |
601 | SHOW_FIELDS(interrupt_enable) |
602 | SHOW_FIELDS(threshold_limit) | |
603 | ||
1cb2a8e1 | 604 | static ssize_t |
9319cec8 | 605 | store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 606 | { |
4cd4601d | 607 | struct thresh_restart tr; |
1cb2a8e1 | 608 | unsigned long new; |
1cb2a8e1 | 609 | |
f227d430 BP |
610 | if (!b->interrupt_capable) |
611 | return -EINVAL; | |
612 | ||
164109e3 | 613 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 614 | return -EINVAL; |
1cb2a8e1 | 615 | |
89b831ef JS |
616 | b->interrupt_enable = !!new; |
617 | ||
9c37c9d8 | 618 | memset(&tr, 0, sizeof(tr)); |
1cb2a8e1 | 619 | tr.b = b; |
1cb2a8e1 | 620 | |
a6b6a14e | 621 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 622 | |
9319cec8 | 623 | return size; |
89b831ef JS |
624 | } |
625 | ||
1cb2a8e1 | 626 | static ssize_t |
9319cec8 | 627 | store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) |
89b831ef | 628 | { |
4cd4601d | 629 | struct thresh_restart tr; |
1cb2a8e1 | 630 | unsigned long new; |
1cb2a8e1 | 631 | |
164109e3 | 632 | if (kstrtoul(buf, 0, &new) < 0) |
89b831ef | 633 | return -EINVAL; |
1cb2a8e1 | 634 | |
89b831ef JS |
635 | if (new > THRESHOLD_MAX) |
636 | new = THRESHOLD_MAX; | |
637 | if (new < 1) | |
638 | new = 1; | |
1cb2a8e1 | 639 | |
9c37c9d8 | 640 | memset(&tr, 0, sizeof(tr)); |
4cd4601d | 641 | tr.old_limit = b->threshold_limit; |
89b831ef | 642 | b->threshold_limit = new; |
4cd4601d | 643 | tr.b = b; |
89b831ef | 644 | |
a6b6a14e | 645 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); |
89b831ef | 646 | |
9319cec8 | 647 | return size; |
89b831ef JS |
648 | } |
649 | ||
4cd4601d MT |
650 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
651 | { | |
2c9c42fa BP |
652 | u32 lo, hi; |
653 | ||
654 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); | |
a6b6a14e | 655 | |
2c9c42fa BP |
656 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
657 | (THRESHOLD_MAX - b->threshold_limit))); | |
89b831ef JS |
658 | } |
659 | ||
6e927361 BP |
660 | static struct threshold_attr error_count = { |
661 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | |
662 | .show = show_error_count, | |
663 | }; | |
89b831ef | 664 | |
34fa1967 HS |
665 | #define RW_ATTR(val) \ |
666 | static struct threshold_attr val = { \ | |
667 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | |
668 | .show = show_## val, \ | |
669 | .store = store_## val, \ | |
89b831ef JS |
670 | }; |
671 | ||
2903ee85 JS |
672 | RW_ATTR(interrupt_enable); |
673 | RW_ATTR(threshold_limit); | |
89b831ef JS |
674 | |
675 | static struct attribute *default_attrs[] = { | |
89b831ef JS |
676 | &threshold_limit.attr, |
677 | &error_count.attr, | |
d26ecc48 BP |
678 | NULL, /* possibly interrupt_enable if supported, see below */ |
679 | NULL, | |
89b831ef JS |
680 | }; |
681 | ||
1cb2a8e1 IM |
682 | #define to_block(k) container_of(k, struct threshold_block, kobj) |
683 | #define to_attr(a) container_of(a, struct threshold_attr, attr) | |
89b831ef JS |
684 | |
685 | static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf) | |
686 | { | |
95268664 | 687 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
688 | struct threshold_attr *a = to_attr(attr); |
689 | ssize_t ret; | |
1cb2a8e1 | 690 | |
89b831ef | 691 | ret = a->show ? a->show(b, buf) : -EIO; |
1cb2a8e1 | 692 | |
89b831ef JS |
693 | return ret; |
694 | } | |
695 | ||
696 | static ssize_t store(struct kobject *kobj, struct attribute *attr, | |
697 | const char *buf, size_t count) | |
698 | { | |
95268664 | 699 | struct threshold_block *b = to_block(kobj); |
89b831ef JS |
700 | struct threshold_attr *a = to_attr(attr); |
701 | ssize_t ret; | |
1cb2a8e1 | 702 | |
89b831ef | 703 | ret = a->store ? a->store(b, buf, count) : -EIO; |
1cb2a8e1 | 704 | |
89b831ef JS |
705 | return ret; |
706 | } | |
707 | ||
52cf25d0 | 708 | static const struct sysfs_ops threshold_ops = { |
1cb2a8e1 IM |
709 | .show = show, |
710 | .store = store, | |
89b831ef JS |
711 | }; |
712 | ||
713 | static struct kobj_type threshold_ktype = { | |
1cb2a8e1 IM |
714 | .sysfs_ops = &threshold_ops, |
715 | .default_attrs = default_attrs, | |
89b831ef JS |
716 | }; |
717 | ||
148f9bb8 PG |
718 | static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank, |
719 | unsigned int block, u32 address) | |
95268664 | 720 | { |
95268664 | 721 | struct threshold_block *b = NULL; |
1cb2a8e1 IM |
722 | u32 low, high; |
723 | int err; | |
95268664 | 724 | |
bafcdd3b | 725 | if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS)) |
95268664 JS |
726 | return 0; |
727 | ||
a6b6a14e | 728 | if (rdmsr_safe_on_cpu(cpu, address, &low, &high)) |
24ce0e96 | 729 | return 0; |
95268664 JS |
730 | |
731 | if (!(high & MASK_VALID_HI)) { | |
732 | if (block) | |
733 | goto recurse; | |
734 | else | |
735 | return 0; | |
736 | } | |
737 | ||
24ce0e96 JB |
738 | if (!(high & MASK_CNTP_HI) || |
739 | (high & MASK_LOCKED_HI)) | |
95268664 JS |
740 | goto recurse; |
741 | ||
742 | b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL); | |
743 | if (!b) | |
744 | return -ENOMEM; | |
95268664 | 745 | |
1cb2a8e1 IM |
746 | b->block = block; |
747 | b->bank = bank; | |
748 | b->cpu = cpu; | |
749 | b->address = address; | |
750 | b->interrupt_enable = 0; | |
f227d430 | 751 | b->interrupt_capable = lvt_interrupt_supported(bank, high); |
1cb2a8e1 | 752 | b->threshold_limit = THRESHOLD_MAX; |
95268664 | 753 | |
d79f931f | 754 | if (b->interrupt_capable) { |
d26ecc48 | 755 | threshold_ktype.default_attrs[2] = &interrupt_enable.attr; |
d79f931f AG |
756 | b->interrupt_enable = 1; |
757 | } else { | |
d26ecc48 | 758 | threshold_ktype.default_attrs[2] = NULL; |
d79f931f | 759 | } |
d26ecc48 | 760 | |
95268664 JS |
761 | INIT_LIST_HEAD(&b->miscj); |
762 | ||
1cb2a8e1 | 763 | if (per_cpu(threshold_banks, cpu)[bank]->blocks) { |
95268664 JS |
764 | list_add(&b->miscj, |
765 | &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj); | |
1cb2a8e1 | 766 | } else { |
95268664 | 767 | per_cpu(threshold_banks, cpu)[bank]->blocks = b; |
1cb2a8e1 | 768 | } |
95268664 | 769 | |
542eb75a GKH |
770 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
771 | per_cpu(threshold_banks, cpu)[bank]->kobj, | |
336d335a | 772 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
95268664 JS |
773 | if (err) |
774 | goto out_free; | |
775 | recurse: | |
8dd1e17a AG |
776 | address = get_block_address(address, low, high, bank, ++block); |
777 | if (!address) | |
778 | return 0; | |
95268664 | 779 | |
8dd1e17a | 780 | err = allocate_threshold_blocks(cpu, bank, block, address); |
95268664 JS |
781 | if (err) |
782 | goto out_free; | |
783 | ||
213eca7f GK |
784 | if (b) |
785 | kobject_uevent(&b->kobj, KOBJ_ADD); | |
542eb75a | 786 | |
95268664 JS |
787 | return err; |
788 | ||
789 | out_free: | |
790 | if (b) { | |
38a382ae | 791 | kobject_put(&b->kobj); |
d9a5ac9e | 792 | list_del(&b->miscj); |
95268664 JS |
793 | kfree(b); |
794 | } | |
795 | return err; | |
796 | } | |
797 | ||
148f9bb8 | 798 | static int __threshold_add_blocks(struct threshold_bank *b) |
019f34fc BP |
799 | { |
800 | struct list_head *head = &b->blocks->miscj; | |
801 | struct threshold_block *pos = NULL; | |
802 | struct threshold_block *tmp = NULL; | |
803 | int err = 0; | |
804 | ||
805 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | |
806 | if (err) | |
807 | return err; | |
808 | ||
809 | list_for_each_entry_safe(pos, tmp, head, miscj) { | |
810 | ||
811 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | |
812 | if (err) { | |
813 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | |
814 | kobject_del(&pos->kobj); | |
815 | ||
816 | return err; | |
817 | } | |
818 | } | |
819 | return err; | |
820 | } | |
821 | ||
148f9bb8 | 822 | static int threshold_create_bank(unsigned int cpu, unsigned int bank) |
89b831ef | 823 | { |
d6126ef5 | 824 | struct device *dev = per_cpu(mce_device, cpu); |
019f34fc | 825 | struct amd_northbridge *nb = NULL; |
92e26e2a | 826 | struct threshold_bank *b = NULL; |
336d335a | 827 | const char *name = th_names[bank]; |
92e26e2a | 828 | int err = 0; |
95268664 | 829 | |
c76e8164 | 830 | if (is_shared_bank(bank)) { |
019f34fc | 831 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
019f34fc BP |
832 | |
833 | /* threshold descriptor already initialized on this node? */ | |
21c5e50e | 834 | if (nb && nb->bank4) { |
019f34fc BP |
835 | /* yes, use it */ |
836 | b = nb->bank4; | |
837 | err = kobject_add(b->kobj, &dev->kobj, name); | |
838 | if (err) | |
839 | goto out; | |
840 | ||
841 | per_cpu(threshold_banks, cpu)[bank] = b; | |
842 | atomic_inc(&b->cpus); | |
843 | ||
844 | err = __threshold_add_blocks(b); | |
845 | ||
846 | goto out; | |
847 | } | |
848 | } | |
849 | ||
95268664 | 850 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
89b831ef JS |
851 | if (!b) { |
852 | err = -ENOMEM; | |
853 | goto out; | |
854 | } | |
89b831ef | 855 | |
e032d807 | 856 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
92e26e2a BP |
857 | if (!b->kobj) { |
858 | err = -EINVAL; | |
a521cf20 | 859 | goto out_free; |
92e26e2a | 860 | } |
95268664 | 861 | |
89b831ef | 862 | per_cpu(threshold_banks, cpu)[bank] = b; |
95268664 | 863 | |
c76e8164 | 864 | if (is_shared_bank(bank)) { |
019f34fc BP |
865 | atomic_set(&b->cpus, 1); |
866 | ||
867 | /* nb is already initialized, see above */ | |
21c5e50e DB |
868 | if (nb) { |
869 | WARN_ON(nb->bank4); | |
870 | nb->bank4 = b; | |
871 | } | |
019f34fc BP |
872 | } |
873 | ||
4b737d78 | 874 | err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank)); |
92e26e2a BP |
875 | if (!err) |
876 | goto out; | |
95268664 | 877 | |
019f34fc | 878 | out_free: |
95268664 | 879 | kfree(b); |
019f34fc BP |
880 | |
881 | out: | |
89b831ef JS |
882 | return err; |
883 | } | |
884 | ||
885 | /* create dir/files for all valid threshold banks */ | |
148f9bb8 | 886 | static int threshold_create_device(unsigned int cpu) |
89b831ef | 887 | { |
2903ee85 | 888 | unsigned int bank; |
bafcdd3b | 889 | struct threshold_bank **bp; |
89b831ef JS |
890 | int err = 0; |
891 | ||
bafcdd3b BO |
892 | bp = kzalloc(sizeof(struct threshold_bank *) * mca_cfg.banks, |
893 | GFP_KERNEL); | |
894 | if (!bp) | |
895 | return -ENOMEM; | |
896 | ||
897 | per_cpu(threshold_banks, cpu) = bp; | |
898 | ||
899 | for (bank = 0; bank < mca_cfg.banks; ++bank) { | |
5a96f4a5 | 900 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
901 | continue; |
902 | err = threshold_create_bank(cpu, bank); | |
903 | if (err) | |
0a17941e | 904 | return err; |
89b831ef | 905 | } |
0a17941e | 906 | |
89b831ef JS |
907 | return err; |
908 | } | |
909 | ||
be6b5a35 | 910 | static void deallocate_threshold_block(unsigned int cpu, |
95268664 JS |
911 | unsigned int bank) |
912 | { | |
913 | struct threshold_block *pos = NULL; | |
914 | struct threshold_block *tmp = NULL; | |
915 | struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank]; | |
916 | ||
917 | if (!head) | |
918 | return; | |
919 | ||
920 | list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) { | |
38a382ae | 921 | kobject_put(&pos->kobj); |
95268664 JS |
922 | list_del(&pos->miscj); |
923 | kfree(pos); | |
924 | } | |
925 | ||
926 | kfree(per_cpu(threshold_banks, cpu)[bank]->blocks); | |
927 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | |
928 | } | |
929 | ||
019f34fc BP |
930 | static void __threshold_remove_blocks(struct threshold_bank *b) |
931 | { | |
932 | struct threshold_block *pos = NULL; | |
933 | struct threshold_block *tmp = NULL; | |
934 | ||
935 | kobject_del(b->kobj); | |
936 | ||
937 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | |
938 | kobject_del(&pos->kobj); | |
939 | } | |
940 | ||
be6b5a35 | 941 | static void threshold_remove_bank(unsigned int cpu, int bank) |
89b831ef | 942 | { |
019f34fc | 943 | struct amd_northbridge *nb; |
89b831ef | 944 | struct threshold_bank *b; |
89b831ef JS |
945 | |
946 | b = per_cpu(threshold_banks, cpu)[bank]; | |
947 | if (!b) | |
948 | return; | |
019f34fc | 949 | |
95268664 JS |
950 | if (!b->blocks) |
951 | goto free_out; | |
952 | ||
c76e8164 | 953 | if (is_shared_bank(bank)) { |
019f34fc BP |
954 | if (!atomic_dec_and_test(&b->cpus)) { |
955 | __threshold_remove_blocks(b); | |
956 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
957 | return; | |
958 | } else { | |
959 | /* | |
960 | * the last CPU on this node using the shared bank is | |
961 | * going away, remove that bank now. | |
962 | */ | |
963 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); | |
964 | nb->bank4 = NULL; | |
965 | } | |
966 | } | |
967 | ||
95268664 JS |
968 | deallocate_threshold_block(cpu, bank); |
969 | ||
970 | free_out: | |
8735728e | 971 | kobject_del(b->kobj); |
38a382ae | 972 | kobject_put(b->kobj); |
95268664 JS |
973 | kfree(b); |
974 | per_cpu(threshold_banks, cpu)[bank] = NULL; | |
89b831ef JS |
975 | } |
976 | ||
be6b5a35 | 977 | static void threshold_remove_device(unsigned int cpu) |
89b831ef | 978 | { |
2903ee85 | 979 | unsigned int bank; |
89b831ef | 980 | |
bafcdd3b | 981 | for (bank = 0; bank < mca_cfg.banks; ++bank) { |
5a96f4a5 | 982 | if (!(per_cpu(bank_map, cpu) & (1 << bank))) |
89b831ef JS |
983 | continue; |
984 | threshold_remove_bank(cpu, bank); | |
985 | } | |
bafcdd3b | 986 | kfree(per_cpu(threshold_banks, cpu)); |
89b831ef JS |
987 | } |
988 | ||
89b831ef | 989 | /* get notified when a cpu comes on/off */ |
148f9bb8 | 990 | static void |
1cb2a8e1 | 991 | amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu) |
89b831ef | 992 | { |
89b831ef JS |
993 | switch (action) { |
994 | case CPU_ONLINE: | |
8bb78442 | 995 | case CPU_ONLINE_FROZEN: |
89b831ef | 996 | threshold_create_device(cpu); |
89b831ef JS |
997 | break; |
998 | case CPU_DEAD: | |
8bb78442 | 999 | case CPU_DEAD_FROZEN: |
89b831ef JS |
1000 | threshold_remove_device(cpu); |
1001 | break; | |
1002 | default: | |
1003 | break; | |
1004 | } | |
89b831ef JS |
1005 | } |
1006 | ||
89b831ef JS |
1007 | static __init int threshold_init_device(void) |
1008 | { | |
2903ee85 | 1009 | unsigned lcpu = 0; |
89b831ef | 1010 | |
89b831ef JS |
1011 | /* to hit CPUs online before the notifier is up */ |
1012 | for_each_online_cpu(lcpu) { | |
fff2e89f | 1013 | int err = threshold_create_device(lcpu); |
1cb2a8e1 | 1014 | |
89b831ef | 1015 | if (err) |
fff2e89f | 1016 | return err; |
89b831ef | 1017 | } |
8735728e | 1018 | threshold_cpu_callback = amd_64_threshold_cpu_callback; |
1cb2a8e1 | 1019 | |
fff2e89f | 1020 | return 0; |
89b831ef | 1021 | } |
a8fccdb0 LJ |
1022 | /* |
1023 | * there are 3 funcs which need to be _initcalled in a logic sequence: | |
1024 | * 1. xen_late_init_mcelog | |
1025 | * 2. mcheck_init_device | |
1026 | * 3. threshold_init_device | |
1027 | * | |
1028 | * xen_late_init_mcelog must register xen_mce_chrdev_device before | |
1029 | * native mce_chrdev_device registration if running under xen platform; | |
1030 | * | |
1031 | * mcheck_init_device should be inited before threshold_init_device to | |
1032 | * initialize mce_device, otherwise a NULL ptr dereference will cause panic. | |
1033 | * | |
1034 | * so we use following _initcalls | |
1035 | * 1. device_initcall(xen_late_init_mcelog); | |
1036 | * 2. device_initcall_sync(mcheck_init_device); | |
1037 | * 3. late_initcall(threshold_init_device); | |
1038 | * | |
1039 | * when running under xen, the initcall order is 1,2,3; | |
1040 | * on baremetal, we skip 1 and we do only 2 and 3. | |
1041 | */ | |
1042 | late_initcall(threshold_init_device); |