Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
38c4c97c | 16 | #include <linux/smp_lock.h> |
e9eee03e IM |
17 | #include <linux/kobject.h> |
18 | #include <linux/kdebug.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/fs.h> | |
32 | ||
d88203d1 | 33 | #include <asm/processor.h> |
1da177e4 | 34 | #include <asm/uaccess.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
38 | #include <asm/smp.h> | |
1da177e4 | 39 | |
e9eee03e | 40 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 41 | |
553f265f AK |
42 | atomic_t mce_entry; |
43 | ||
e9eee03e | 44 | static int mce_dont_init; |
1da177e4 | 45 | |
bd78432c TH |
46 | /* |
47 | * Tolerant levels: | |
48 | * 0: always panic on uncorrected errors, log corrected errors | |
49 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
50 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
51 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
52 | */ | |
e9eee03e IM |
53 | static int tolerant = 1; |
54 | static int banks; | |
55 | static u64 *bank; | |
56 | static unsigned long notify_user; | |
57 | static int rip_msr; | |
58 | static int mce_bootlog = -1; | |
59 | static atomic_t mce_events; | |
a98f0dd3 | 60 | |
e9eee03e IM |
61 | static char trigger[128]; |
62 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 63 | |
e02e68d3 TH |
64 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
65 | ||
ee031c31 AK |
66 | /* MCA banks polled by the period polling timer for corrected events */ |
67 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
68 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
69 | }; | |
70 | ||
b5f2fa4e AK |
71 | /* Do initial initialization of a struct mce */ |
72 | void mce_setup(struct mce *m) | |
73 | { | |
74 | memset(m, 0, sizeof(struct mce)); | |
75 | m->cpu = smp_processor_id(); | |
76 | rdtscll(m->tsc); | |
77 | } | |
78 | ||
1da177e4 LT |
79 | /* |
80 | * Lockless MCE logging infrastructure. | |
81 | * This avoids deadlocks on printk locks without having to break locks. Also | |
82 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
83 | */ | |
84 | ||
231fd906 | 85 | static struct mce_log mcelog = { |
1da177e4 LT |
86 | MCE_LOG_SIGNATURE, |
87 | MCE_LOG_LEN, | |
d88203d1 | 88 | }; |
1da177e4 LT |
89 | |
90 | void mce_log(struct mce *mce) | |
91 | { | |
92 | unsigned next, entry; | |
e9eee03e | 93 | |
a98f0dd3 | 94 | atomic_inc(&mce_events); |
1da177e4 | 95 | mce->finished = 0; |
7644143c | 96 | wmb(); |
1da177e4 LT |
97 | for (;;) { |
98 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 99 | for (;;) { |
e9eee03e IM |
100 | /* |
101 | * When the buffer fills up discard new entries. | |
102 | * Assume that the earlier errors are the more | |
103 | * interesting ones: | |
104 | */ | |
673242c1 | 105 | if (entry >= MCE_LOG_LEN) { |
53756d37 | 106 | set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags); |
673242c1 AK |
107 | return; |
108 | } | |
e9eee03e | 109 | /* Old left over entry. Skip: */ |
673242c1 AK |
110 | if (mcelog.entry[entry].finished) { |
111 | entry++; | |
112 | continue; | |
113 | } | |
7644143c | 114 | break; |
1da177e4 | 115 | } |
1da177e4 LT |
116 | smp_rmb(); |
117 | next = entry + 1; | |
118 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
119 | break; | |
120 | } | |
121 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 122 | wmb(); |
1da177e4 | 123 | mcelog.entry[entry].finished = 1; |
7644143c | 124 | wmb(); |
1da177e4 | 125 | |
e02e68d3 | 126 | set_bit(0, ¬ify_user); |
1da177e4 LT |
127 | } |
128 | ||
129 | static void print_mce(struct mce *m) | |
130 | { | |
131 | printk(KERN_EMERG "\n" | |
4855170f | 132 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
133 | KERN_EMERG |
134 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
135 | m->cpu, m->mcgstatus, m->bank, m->status); | |
65ea5b03 | 136 | if (m->ip) { |
d88203d1 | 137 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 138 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 139 | m->cs, m->ip); |
1da177e4 | 140 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 141 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
142 | printk("\n"); |
143 | } | |
f6d1826d | 144 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 145 | if (m->addr) |
f6d1826d | 146 | printk("ADDR %llx ", m->addr); |
1da177e4 | 147 | if (m->misc) |
f6d1826d | 148 | printk("MISC %llx ", m->misc); |
1da177e4 | 149 | printk("\n"); |
4855170f | 150 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
151 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
152 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
153 | } |
154 | ||
155 | static void mce_panic(char *msg, struct mce *backup, unsigned long start) | |
d88203d1 | 156 | { |
1da177e4 | 157 | int i; |
e02e68d3 | 158 | |
1da177e4 LT |
159 | oops_begin(); |
160 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
161 | unsigned long tsc = mcelog.entry[i].tsc; | |
d88203d1 | 162 | |
1da177e4 LT |
163 | if (time_before(tsc, start)) |
164 | continue; | |
d88203d1 | 165 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
166 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
167 | backup = NULL; | |
168 | } | |
169 | if (backup) | |
170 | print_mce(backup); | |
e02e68d3 | 171 | panic(msg); |
d88203d1 | 172 | } |
1da177e4 | 173 | |
88ccbedd | 174 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 175 | { |
5b4408fd AK |
176 | if (mce_dont_init) |
177 | return 0; | |
3d1712c9 | 178 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
179 | } |
180 | ||
94ad8474 AK |
181 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
182 | { | |
183 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 184 | m->ip = regs->ip; |
94ad8474 AK |
185 | m->cs = regs->cs; |
186 | } else { | |
65ea5b03 | 187 | m->ip = 0; |
94ad8474 AK |
188 | m->cs = 0; |
189 | } | |
190 | if (rip_msr) { | |
191 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
192 | m->mcgstatus |= MCG_STATUS_EIPV; | |
65ea5b03 | 193 | rdmsrl(rip_msr, m->ip); |
94ad8474 AK |
194 | m->cs = 0; |
195 | } | |
196 | } | |
197 | ||
d88203d1 | 198 | /* |
b79109c3 AK |
199 | * Poll for corrected events or events that happened before reset. |
200 | * Those are just logged through /dev/mcelog. | |
201 | * | |
202 | * This is executed in standard interrupt context. | |
203 | */ | |
ee031c31 | 204 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
205 | { |
206 | struct mce m; | |
207 | int i; | |
208 | ||
209 | mce_setup(&m); | |
210 | ||
211 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | |
212 | for (i = 0; i < banks; i++) { | |
ee031c31 | 213 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
214 | continue; |
215 | ||
216 | m.misc = 0; | |
217 | m.addr = 0; | |
218 | m.bank = i; | |
219 | m.tsc = 0; | |
220 | ||
221 | barrier(); | |
222 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
223 | if (!(m.status & MCI_STATUS_VAL)) | |
224 | continue; | |
225 | ||
226 | /* | |
227 | * Uncorrected events are handled by the exception handler | |
228 | * when it is enabled. But when the exception is disabled log | |
229 | * everything. | |
230 | * | |
231 | * TBD do the same check for MCI_STATUS_EN here? | |
232 | */ | |
233 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
234 | continue; | |
235 | ||
236 | if (m.status & MCI_STATUS_MISCV) | |
237 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
238 | if (m.status & MCI_STATUS_ADDRV) | |
239 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
240 | ||
241 | if (!(flags & MCP_TIMESTAMP)) | |
242 | m.tsc = 0; | |
243 | /* | |
244 | * Don't get the IP here because it's unlikely to | |
245 | * have anything to do with the actual error location. | |
246 | */ | |
5679af4c AK |
247 | if (!(flags & MCP_DONTLOG)) { |
248 | mce_log(&m); | |
249 | add_taint(TAINT_MACHINE_CHECK); | |
250 | } | |
b79109c3 AK |
251 | |
252 | /* | |
253 | * Clear state for this bank. | |
254 | */ | |
255 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
256 | } | |
257 | ||
258 | /* | |
259 | * Don't clear MCG_STATUS here because it's only defined for | |
260 | * exceptions. | |
261 | */ | |
262 | } | |
263 | ||
264 | /* | |
265 | * The actual machine check handler. This only handles real | |
266 | * exceptions when something got corrupted coming in through int 18. | |
267 | * | |
268 | * This is executed in NMI context not subject to normal locking rules. This | |
269 | * implies that most kernel services cannot be safely used. Don't even | |
270 | * think about putting a printk in there! | |
1da177e4 | 271 | */ |
e9eee03e | 272 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
273 | { |
274 | struct mce m, panicm; | |
e9eee03e | 275 | int panicm_found = 0; |
1da177e4 LT |
276 | u64 mcestart = 0; |
277 | int i; | |
bd78432c TH |
278 | /* |
279 | * If no_way_out gets set, there is no safe way to recover from this | |
280 | * MCE. If tolerant is cranked up, we'll try anyway. | |
281 | */ | |
282 | int no_way_out = 0; | |
283 | /* | |
284 | * If kill_it gets set, there might be a way to recover from this | |
285 | * error. | |
286 | */ | |
287 | int kill_it = 0; | |
b79109c3 | 288 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 289 | |
553f265f AK |
290 | atomic_inc(&mce_entry); |
291 | ||
b79109c3 | 292 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 293 | 18, SIGKILL) == NOTIFY_STOP) |
b79109c3 AK |
294 | goto out2; |
295 | if (!banks) | |
553f265f | 296 | goto out2; |
1da177e4 | 297 | |
b5f2fa4e AK |
298 | mce_setup(&m); |
299 | ||
1da177e4 | 300 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
e9eee03e | 301 | |
bd78432c | 302 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 303 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 304 | no_way_out = 1; |
d88203d1 | 305 | |
1da177e4 LT |
306 | rdtscll(mcestart); |
307 | barrier(); | |
308 | ||
309 | for (i = 0; i < banks; i++) { | |
b79109c3 | 310 | __clear_bit(i, toclear); |
0d7482e3 | 311 | if (!bank[i]) |
1da177e4 | 312 | continue; |
d88203d1 TG |
313 | |
314 | m.misc = 0; | |
1da177e4 LT |
315 | m.addr = 0; |
316 | m.bank = i; | |
1da177e4 LT |
317 | |
318 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
319 | if ((m.status & MCI_STATUS_VAL) == 0) | |
320 | continue; | |
321 | ||
b79109c3 AK |
322 | /* |
323 | * Non uncorrected errors are handled by machine_check_poll | |
324 | * Leave them alone. | |
325 | */ | |
326 | if ((m.status & MCI_STATUS_UC) == 0) | |
327 | continue; | |
328 | ||
329 | /* | |
330 | * Set taint even when machine check was not enabled. | |
331 | */ | |
332 | add_taint(TAINT_MACHINE_CHECK); | |
333 | ||
334 | __set_bit(i, toclear); | |
335 | ||
1da177e4 | 336 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
337 | /* if PCC was set, there's no way out */ |
338 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
339 | /* | |
340 | * If this error was uncorrectable and there was | |
341 | * an overflow, we're in trouble. If no overflow, | |
342 | * we might get away with just killing a task. | |
343 | */ | |
344 | if (m.status & MCI_STATUS_UC) { | |
345 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
346 | no_way_out = 1; | |
347 | kill_it = 1; | |
348 | } | |
b79109c3 AK |
349 | } else { |
350 | /* | |
351 | * Machine check event was not enabled. Clear, but | |
352 | * ignore. | |
353 | */ | |
354 | continue; | |
1da177e4 LT |
355 | } |
356 | ||
357 | if (m.status & MCI_STATUS_MISCV) | |
358 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
359 | if (m.status & MCI_STATUS_ADDRV) | |
360 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
361 | ||
94ad8474 | 362 | mce_get_rip(&m, regs); |
b79109c3 | 363 | mce_log(&m); |
1da177e4 | 364 | |
e9eee03e IM |
365 | /* |
366 | * Did this bank cause the exception? | |
367 | * | |
368 | * Assume that the bank with uncorrectable errors did it, | |
369 | * and that there is only a single one: | |
370 | */ | |
371 | if ((m.status & MCI_STATUS_UC) && | |
372 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
373 | panicm = m; |
374 | panicm_found = 1; | |
375 | } | |
1da177e4 LT |
376 | } |
377 | ||
e9eee03e IM |
378 | /* |
379 | * If we didn't find an uncorrectable error, pick | |
380 | * the last one (shouldn't happen, just being safe). | |
381 | */ | |
1da177e4 LT |
382 | if (!panicm_found) |
383 | panicm = m; | |
bd78432c TH |
384 | |
385 | /* | |
386 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 387 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
388 | */ |
389 | if (no_way_out && tolerant < 3) | |
1da177e4 | 390 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
391 | |
392 | /* | |
393 | * If the error seems to be unrecoverable, something should be | |
394 | * done. Try to kill as little as possible. If we can kill just | |
395 | * one task, do that. If the user has set the tolerance very | |
396 | * high, don't try to do anything at all. | |
397 | */ | |
398 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
399 | int user_space = 0; |
400 | ||
bd78432c TH |
401 | /* |
402 | * If the EIPV bit is set, it means the saved IP is the | |
403 | * instruction which caused the MCE. | |
404 | */ | |
405 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 406 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
407 | |
408 | /* | |
409 | * If we know that the error was in user space, send a | |
410 | * SIGBUS. Otherwise, panic if tolerance is low. | |
411 | * | |
380851bc | 412 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
413 | * risk of deadlocking. |
414 | */ | |
415 | if (user_space) { | |
380851bc | 416 | force_sig(SIGBUS, current); |
bd78432c TH |
417 | } else if (panic_on_oops || tolerant < 2) { |
418 | mce_panic("Uncorrected machine check", | |
419 | &panicm, mcestart); | |
420 | } | |
1da177e4 LT |
421 | } |
422 | ||
e02e68d3 TH |
423 | /* notify userspace ASAP */ |
424 | set_thread_flag(TIF_MCE_NOTIFY); | |
425 | ||
bd78432c | 426 | /* the last thing we do is clear state */ |
b79109c3 AK |
427 | for (i = 0; i < banks; i++) { |
428 | if (test_bit(i, toclear)) | |
429 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
430 | } | |
1da177e4 | 431 | wrmsrl(MSR_IA32_MCG_STATUS, 0); |
553f265f AK |
432 | out2: |
433 | atomic_dec(&mce_entry); | |
1da177e4 LT |
434 | } |
435 | ||
15d5f839 DZ |
436 | #ifdef CONFIG_X86_MCE_INTEL |
437 | /*** | |
438 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 439 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
440 | * @status: Event status information |
441 | * | |
442 | * This function should be called by the thermal interrupt after the | |
443 | * event has been processed and the decision was made to log the event | |
444 | * further. | |
445 | * | |
446 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
447 | * and historically has been the register value of the | |
448 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
449 | */ | |
b5f2fa4e | 450 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
451 | { |
452 | struct mce m; | |
453 | ||
b5f2fa4e | 454 | mce_setup(&m); |
15d5f839 DZ |
455 | m.bank = MCE_THERMAL_BANK; |
456 | m.status = status; | |
15d5f839 DZ |
457 | mce_log(&m); |
458 | } | |
459 | #endif /* CONFIG_X86_MCE_INTEL */ | |
460 | ||
1da177e4 | 461 | /* |
8a336b0a TH |
462 | * Periodic polling timer for "silent" machine check errors. If the |
463 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
464 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 465 | */ |
1da177e4 | 466 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 467 | |
6298c512 | 468 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 469 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 470 | |
52d168e2 | 471 | static void mcheck_timer(unsigned long data) |
1da177e4 | 472 | { |
52d168e2 | 473 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 474 | int *n; |
52d168e2 AK |
475 | |
476 | WARN_ON(smp_processor_id() != data); | |
477 | ||
e9eee03e | 478 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
479 | machine_check_poll(MCP_TIMESTAMP, |
480 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 481 | } |
1da177e4 LT |
482 | |
483 | /* | |
e02e68d3 TH |
484 | * Alert userspace if needed. If we logged an MCE, reduce the |
485 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 486 | */ |
6298c512 | 487 | n = &__get_cpu_var(next_interval); |
e02e68d3 | 488 | if (mce_notify_user()) { |
6298c512 | 489 | *n = max(*n/2, HZ/100); |
e02e68d3 | 490 | } else { |
6298c512 | 491 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 TH |
492 | } |
493 | ||
6298c512 | 494 | t->expires = jiffies + *n; |
52d168e2 | 495 | add_timer(t); |
e02e68d3 TH |
496 | } |
497 | ||
9bd98405 AK |
498 | static void mce_do_trigger(struct work_struct *work) |
499 | { | |
500 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
501 | } | |
502 | ||
503 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
504 | ||
e02e68d3 | 505 | /* |
9bd98405 AK |
506 | * Notify the user(s) about new machine check events. |
507 | * Can be called from interrupt context, but not from machine check/NMI | |
508 | * context. | |
e02e68d3 TH |
509 | */ |
510 | int mce_notify_user(void) | |
511 | { | |
8457c84d AK |
512 | /* Not more than two messages every minute */ |
513 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
514 | ||
e02e68d3 | 515 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 516 | |
e02e68d3 | 517 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 518 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
519 | |
520 | /* | |
521 | * There is no risk of missing notifications because | |
522 | * work_pending is always cleared before the function is | |
523 | * executed. | |
524 | */ | |
525 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
526 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 527 | |
8457c84d | 528 | if (__ratelimit(&ratelimit)) |
8a336b0a | 529 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
530 | |
531 | return 1; | |
1da177e4 | 532 | } |
e02e68d3 TH |
533 | return 0; |
534 | } | |
8a336b0a | 535 | |
e9eee03e | 536 | /* see if the idle task needs to notify userspace: */ |
e02e68d3 | 537 | static int |
e9eee03e IM |
538 | mce_idle_callback(struct notifier_block *nfb, unsigned long action, |
539 | void *unused) | |
e02e68d3 TH |
540 | { |
541 | /* IDLE_END should be safe - interrupts are back on */ | |
542 | if (action == IDLE_END && test_thread_flag(TIF_MCE_NOTIFY)) | |
543 | mce_notify_user(); | |
544 | ||
545 | return NOTIFY_OK; | |
1da177e4 LT |
546 | } |
547 | ||
e02e68d3 | 548 | static struct notifier_block mce_idle_notifier = { |
e9eee03e | 549 | .notifier_call = mce_idle_callback, |
e02e68d3 | 550 | }; |
1da177e4 LT |
551 | |
552 | static __init int periodic_mcheck_init(void) | |
d88203d1 | 553 | { |
52d168e2 AK |
554 | idle_notifier_register(&mce_idle_notifier); |
555 | return 0; | |
d88203d1 | 556 | } |
1da177e4 LT |
557 | __initcall(periodic_mcheck_init); |
558 | ||
d88203d1 | 559 | /* |
1da177e4 LT |
560 | * Initialize Machine Checks for a CPU. |
561 | */ | |
0d7482e3 | 562 | static int mce_cap_init(void) |
1da177e4 | 563 | { |
0d7482e3 | 564 | unsigned b; |
e9eee03e | 565 | u64 cap; |
1da177e4 LT |
566 | |
567 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
0d7482e3 AK |
568 | b = cap & 0xff; |
569 | if (b > MAX_NR_BANKS) { | |
570 | printk(KERN_WARNING | |
571 | "MCE: Using only %u machine check banks out of %u\n", | |
572 | MAX_NR_BANKS, b); | |
573 | b = MAX_NR_BANKS; | |
574 | } | |
575 | ||
576 | /* Don't support asymmetric configurations today */ | |
577 | WARN_ON(banks != 0 && b != banks); | |
578 | banks = b; | |
579 | if (!bank) { | |
580 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
581 | if (!bank) | |
582 | return -ENOMEM; | |
583 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 584 | } |
0d7482e3 | 585 | |
94ad8474 AK |
586 | /* Use accurate RIP reporting if available. */ |
587 | if ((cap & (1<<9)) && ((cap >> 16) & 0xff) >= 9) | |
588 | rip_msr = MSR_IA32_MCG_EIP; | |
1da177e4 | 589 | |
0d7482e3 AK |
590 | return 0; |
591 | } | |
592 | ||
593 | static void mce_init(void *dummy) | |
594 | { | |
e9eee03e | 595 | mce_banks_t all_banks; |
0d7482e3 AK |
596 | u64 cap; |
597 | int i; | |
598 | ||
b79109c3 AK |
599 | /* |
600 | * Log the machine checks left over from the previous reset. | |
601 | */ | |
ee031c31 | 602 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 603 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
604 | |
605 | set_in_cr4(X86_CR4_MCE); | |
606 | ||
0d7482e3 | 607 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
608 | if (cap & MCG_CTL_P) |
609 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
610 | ||
611 | for (i = 0; i < banks; i++) { | |
0d7482e3 | 612 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 613 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 614 | } |
1da177e4 LT |
615 | } |
616 | ||
617 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 618 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 619 | { |
1da177e4 | 620 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 621 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
622 | if (c->x86 == 15 && banks > 4) { |
623 | /* | |
624 | * disable GART TBL walk error reporting, which | |
625 | * trips off incorrectly with the IOMMU & 3ware | |
626 | * & Cerberus: | |
627 | */ | |
0d7482e3 | 628 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
629 | } |
630 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
631 | /* | |
632 | * Lots of broken BIOS around that don't clear them | |
633 | * by default and leave crap in there. Don't log: | |
634 | */ | |
911f6a7b | 635 | mce_bootlog = 0; |
e9eee03e | 636 | } |
1da177e4 | 637 | } |
e583538f | 638 | |
d88203d1 | 639 | } |
1da177e4 | 640 | |
cc3ca220 | 641 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
642 | { |
643 | switch (c->x86_vendor) { | |
644 | case X86_VENDOR_INTEL: | |
645 | mce_intel_feature_init(c); | |
646 | break; | |
89b831ef JS |
647 | case X86_VENDOR_AMD: |
648 | mce_amd_feature_init(c); | |
649 | break; | |
1da177e4 LT |
650 | default: |
651 | break; | |
652 | } | |
653 | } | |
654 | ||
52d168e2 AK |
655 | static void mce_init_timer(void) |
656 | { | |
657 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 658 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 659 | |
6298c512 AK |
660 | *n = check_interval * HZ; |
661 | if (!*n) | |
52d168e2 AK |
662 | return; |
663 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 664 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
665 | add_timer(t); |
666 | } | |
667 | ||
d88203d1 | 668 | /* |
1da177e4 | 669 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 670 | * Must be called with preempt off: |
1da177e4 | 671 | */ |
e6982c67 | 672 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 673 | { |
5b4408fd | 674 | if (!mce_available(c)) |
1da177e4 LT |
675 | return; |
676 | ||
0d7482e3 AK |
677 | if (mce_cap_init() < 0) { |
678 | mce_dont_init = 1; | |
679 | return; | |
680 | } | |
681 | mce_cpu_quirks(c); | |
682 | ||
1da177e4 LT |
683 | mce_init(NULL); |
684 | mce_cpu_features(c); | |
52d168e2 | 685 | mce_init_timer(); |
1da177e4 LT |
686 | } |
687 | ||
688 | /* | |
689 | * Character device to read and clear the MCE log. | |
690 | */ | |
691 | ||
f528e7ba | 692 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
693 | static int open_count; /* #times opened */ |
694 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
695 | |
696 | static int mce_open(struct inode *inode, struct file *file) | |
697 | { | |
38c4c97c | 698 | lock_kernel(); |
f528e7ba TH |
699 | spin_lock(&mce_state_lock); |
700 | ||
701 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
702 | spin_unlock(&mce_state_lock); | |
38c4c97c | 703 | unlock_kernel(); |
e9eee03e | 704 | |
f528e7ba TH |
705 | return -EBUSY; |
706 | } | |
707 | ||
708 | if (file->f_flags & O_EXCL) | |
709 | open_exclu = 1; | |
710 | open_count++; | |
711 | ||
712 | spin_unlock(&mce_state_lock); | |
38c4c97c | 713 | unlock_kernel(); |
f528e7ba | 714 | |
bd78432c | 715 | return nonseekable_open(inode, file); |
f528e7ba TH |
716 | } |
717 | ||
718 | static int mce_release(struct inode *inode, struct file *file) | |
719 | { | |
720 | spin_lock(&mce_state_lock); | |
721 | ||
722 | open_count--; | |
723 | open_exclu = 0; | |
724 | ||
725 | spin_unlock(&mce_state_lock); | |
726 | ||
727 | return 0; | |
728 | } | |
729 | ||
d88203d1 TG |
730 | static void collect_tscs(void *data) |
731 | { | |
1da177e4 | 732 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 733 | |
1da177e4 | 734 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 735 | } |
1da177e4 | 736 | |
e9eee03e IM |
737 | static DEFINE_MUTEX(mce_read_mutex); |
738 | ||
d88203d1 TG |
739 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
740 | loff_t *off) | |
1da177e4 | 741 | { |
e9eee03e | 742 | char __user *buf = ubuf; |
f0de53bb | 743 | unsigned long *cpu_tsc; |
ef41df43 | 744 | unsigned prev, next; |
1da177e4 LT |
745 | int i, err; |
746 | ||
6bca67f9 | 747 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
748 | if (!cpu_tsc) |
749 | return -ENOMEM; | |
750 | ||
8c8b8859 | 751 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
752 | next = rcu_dereference(mcelog.next); |
753 | ||
754 | /* Only supports full reads right now */ | |
d88203d1 | 755 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 756 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 757 | kfree(cpu_tsc); |
e9eee03e | 758 | |
1da177e4 LT |
759 | return -EINVAL; |
760 | } | |
761 | ||
762 | err = 0; | |
ef41df43 HY |
763 | prev = 0; |
764 | do { | |
765 | for (i = prev; i < next; i++) { | |
766 | unsigned long start = jiffies; | |
767 | ||
768 | while (!mcelog.entry[i].finished) { | |
769 | if (time_after_eq(jiffies, start + 2)) { | |
770 | memset(mcelog.entry + i, 0, | |
771 | sizeof(struct mce)); | |
772 | goto timeout; | |
773 | } | |
774 | cpu_relax(); | |
673242c1 | 775 | } |
ef41df43 HY |
776 | smp_rmb(); |
777 | err |= copy_to_user(buf, mcelog.entry + i, | |
778 | sizeof(struct mce)); | |
779 | buf += sizeof(struct mce); | |
780 | timeout: | |
781 | ; | |
673242c1 | 782 | } |
1da177e4 | 783 | |
ef41df43 HY |
784 | memset(mcelog.entry + prev, 0, |
785 | (next - prev) * sizeof(struct mce)); | |
786 | prev = next; | |
787 | next = cmpxchg(&mcelog.next, prev, 0); | |
788 | } while (next != prev); | |
1da177e4 | 789 | |
b2b18660 | 790 | synchronize_sched(); |
1da177e4 | 791 | |
d88203d1 TG |
792 | /* |
793 | * Collect entries that were still getting written before the | |
794 | * synchronize. | |
795 | */ | |
15c8b6c1 | 796 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 797 | |
d88203d1 TG |
798 | for (i = next; i < MCE_LOG_LEN; i++) { |
799 | if (mcelog.entry[i].finished && | |
800 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
801 | err |= copy_to_user(buf, mcelog.entry+i, | |
802 | sizeof(struct mce)); | |
1da177e4 LT |
803 | smp_rmb(); |
804 | buf += sizeof(struct mce); | |
805 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
806 | } | |
d88203d1 | 807 | } |
8c8b8859 | 808 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 809 | kfree(cpu_tsc); |
e9eee03e | 810 | |
d88203d1 | 811 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
812 | } |
813 | ||
e02e68d3 TH |
814 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
815 | { | |
816 | poll_wait(file, &mce_wait, wait); | |
817 | if (rcu_dereference(mcelog.next)) | |
818 | return POLLIN | POLLRDNORM; | |
819 | return 0; | |
820 | } | |
821 | ||
c68461b6 | 822 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
823 | { |
824 | int __user *p = (int __user *)arg; | |
d88203d1 | 825 | |
1da177e4 | 826 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 827 | return -EPERM; |
e9eee03e | 828 | |
1da177e4 | 829 | switch (cmd) { |
d88203d1 | 830 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
831 | return put_user(sizeof(struct mce), p); |
832 | case MCE_GET_LOG_LEN: | |
d88203d1 | 833 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
834 | case MCE_GETCLEAR_FLAGS: { |
835 | unsigned flags; | |
d88203d1 TG |
836 | |
837 | do { | |
1da177e4 | 838 | flags = mcelog.flags; |
d88203d1 | 839 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 840 | |
d88203d1 | 841 | return put_user(flags, p); |
1da177e4 LT |
842 | } |
843 | default: | |
d88203d1 TG |
844 | return -ENOTTY; |
845 | } | |
1da177e4 LT |
846 | } |
847 | ||
5dfe4c96 | 848 | static const struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
849 | .open = mce_open, |
850 | .release = mce_release, | |
851 | .read = mce_read, | |
852 | .poll = mce_poll, | |
853 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 LT |
854 | }; |
855 | ||
856 | static struct miscdevice mce_log_device = { | |
857 | MISC_MCELOG_MINOR, | |
858 | "mcelog", | |
859 | &mce_chrdev_ops, | |
860 | }; | |
861 | ||
d88203d1 TG |
862 | /* |
863 | * Old style boot options parsing. Only for compatibility. | |
1da177e4 | 864 | */ |
1da177e4 LT |
865 | static int __init mcheck_disable(char *str) |
866 | { | |
867 | mce_dont_init = 1; | |
9b41046c | 868 | return 1; |
1da177e4 | 869 | } |
13503fa9 | 870 | __setup("nomce", mcheck_disable); |
1da177e4 | 871 | |
13503fa9 HS |
872 | /* |
873 | * mce=off disables machine check | |
874 | * mce=TOLERANCELEVEL (number, see above) | |
875 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
876 | * mce=nobootlog Don't log MCEs from before booting. | |
877 | */ | |
1da177e4 LT |
878 | static int __init mcheck_enable(char *str) |
879 | { | |
880 | if (!strcmp(str, "off")) | |
881 | mce_dont_init = 1; | |
13503fa9 HS |
882 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
883 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
884 | else if (isdigit(str[0])) |
885 | get_option(&str, &tolerant); | |
13503fa9 HS |
886 | else { |
887 | printk(KERN_INFO "mce= argument %s ignored. Please use /sys\n", | |
888 | str); | |
889 | return 0; | |
890 | } | |
9b41046c | 891 | return 1; |
1da177e4 | 892 | } |
909dd324 | 893 | __setup("mce=", mcheck_enable); |
1da177e4 | 894 | |
d88203d1 | 895 | /* |
1da177e4 | 896 | * Sysfs support |
d88203d1 | 897 | */ |
1da177e4 | 898 | |
973a2dd1 AK |
899 | /* |
900 | * Disable machine checks on suspend and shutdown. We can't really handle | |
901 | * them later. | |
902 | */ | |
903 | static int mce_disable(void) | |
904 | { | |
905 | int i; | |
906 | ||
907 | for (i = 0; i < banks; i++) | |
908 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
909 | return 0; | |
910 | } | |
911 | ||
912 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
913 | { | |
914 | return mce_disable(); | |
915 | } | |
916 | ||
917 | static int mce_shutdown(struct sys_device *dev) | |
918 | { | |
919 | return mce_disable(); | |
920 | } | |
921 | ||
e9eee03e IM |
922 | /* |
923 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
924 | * Only one CPU is active at this time, the others get re-added later using | |
925 | * CPU hotplug: | |
926 | */ | |
1da177e4 LT |
927 | static int mce_resume(struct sys_device *dev) |
928 | { | |
413588c7 | 929 | mce_init(NULL); |
6ec68bff | 930 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 931 | |
1da177e4 LT |
932 | return 0; |
933 | } | |
934 | ||
52d168e2 AK |
935 | static void mce_cpu_restart(void *data) |
936 | { | |
937 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
938 | if (mce_available(¤t_cpu_data)) | |
939 | mce_init(NULL); | |
940 | mce_init_timer(); | |
941 | } | |
942 | ||
1da177e4 | 943 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
944 | static void mce_restart(void) |
945 | { | |
52d168e2 | 946 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
947 | } |
948 | ||
949 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
950 | .suspend = mce_suspend, |
951 | .shutdown = mce_shutdown, | |
952 | .resume = mce_resume, | |
953 | .name = "machinecheck", | |
1da177e4 LT |
954 | }; |
955 | ||
fff2e89f | 956 | DEFINE_PER_CPU(struct sys_device, device_mce); |
e9eee03e IM |
957 | |
958 | __cpuinitdata | |
959 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 LT |
960 | |
961 | /* Why are there no generic functions for this? */ | |
962 | #define ACCESSOR(name, var, start) \ | |
4a0b2b4d AK |
963 | static ssize_t show_ ## name(struct sys_device *s, \ |
964 | struct sysdev_attribute *attr, \ | |
965 | char *buf) { \ | |
d88203d1 TG |
966 | return sprintf(buf, "%lx\n", (unsigned long)var); \ |
967 | } \ | |
4a0b2b4d AK |
968 | static ssize_t set_ ## name(struct sys_device *s, \ |
969 | struct sysdev_attribute *attr, \ | |
970 | const char *buf, size_t siz) { \ | |
d88203d1 TG |
971 | char *end; \ |
972 | unsigned long new = simple_strtoul(buf, &end, 0); \ | |
e9eee03e IM |
973 | \ |
974 | if (end == buf) \ | |
975 | return -EINVAL; \ | |
d88203d1 TG |
976 | var = new; \ |
977 | start; \ | |
e9eee03e | 978 | \ |
d88203d1 TG |
979 | return end-buf; \ |
980 | } \ | |
1da177e4 LT |
981 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); |
982 | ||
0d7482e3 AK |
983 | static struct sysdev_attribute *bank_attrs; |
984 | ||
985 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
986 | char *buf) | |
987 | { | |
988 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 989 | |
f6d1826d | 990 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
991 | } |
992 | ||
993 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
994 | const char *buf, size_t siz) | |
995 | { | |
996 | char *end; | |
997 | u64 new = simple_strtoull(buf, &end, 0); | |
e9eee03e | 998 | |
0d7482e3 AK |
999 | if (end == buf) |
1000 | return -EINVAL; | |
e9eee03e | 1001 | |
0d7482e3 AK |
1002 | bank[attr - bank_attrs] = new; |
1003 | mce_restart(); | |
e9eee03e | 1004 | |
0d7482e3 AK |
1005 | return end-buf; |
1006 | } | |
a98f0dd3 | 1007 | |
e9eee03e IM |
1008 | static ssize_t |
1009 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1010 | { |
1011 | strcpy(buf, trigger); | |
1012 | strcat(buf, "\n"); | |
1013 | return strlen(trigger) + 1; | |
1014 | } | |
1015 | ||
4a0b2b4d | 1016 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1017 | const char *buf, size_t siz) |
a98f0dd3 AK |
1018 | { |
1019 | char *p; | |
1020 | int len; | |
e9eee03e | 1021 | |
a98f0dd3 AK |
1022 | strncpy(trigger, buf, sizeof(trigger)); |
1023 | trigger[sizeof(trigger)-1] = 0; | |
1024 | len = strlen(trigger); | |
1025 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1026 | |
1027 | if (*p) | |
1028 | *p = 0; | |
1029 | ||
a98f0dd3 AK |
1030 | return len; |
1031 | } | |
1032 | ||
1033 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); | |
d95d62c0 | 1034 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e IM |
1035 | |
1036 | ACCESSOR(check_interval, check_interval, mce_restart()) | |
1037 | ||
a98f0dd3 | 1038 | static struct sysdev_attribute *mce_attributes[] = { |
d95d62c0 | 1039 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, |
a98f0dd3 AK |
1040 | NULL |
1041 | }; | |
1da177e4 | 1042 | |
996867d0 | 1043 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 1044 | |
e9eee03e | 1045 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1046 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1047 | { |
1048 | int err; | |
73ca5358 | 1049 | int i; |
92cb7612 | 1050 | |
90367556 | 1051 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1052 | return -EIO; |
1053 | ||
d435d862 | 1054 | memset(&per_cpu(device_mce, cpu).kobj, 0, sizeof(struct kobject)); |
e9eee03e IM |
1055 | per_cpu(device_mce, cpu).id = cpu; |
1056 | per_cpu(device_mce, cpu).cls = &mce_sysclass; | |
91c6d400 | 1057 | |
e9eee03e | 1058 | err = sysdev_register(&per_cpu(device_mce, cpu)); |
d435d862 AM |
1059 | if (err) |
1060 | return err; | |
1061 | ||
1062 | for (i = 0; mce_attributes[i]; i++) { | |
e9eee03e | 1063 | err = sysdev_create_file(&per_cpu(device_mce, cpu), |
d435d862 AM |
1064 | mce_attributes[i]); |
1065 | if (err) | |
1066 | goto error; | |
1067 | } | |
0d7482e3 AK |
1068 | for (i = 0; i < banks; i++) { |
1069 | err = sysdev_create_file(&per_cpu(device_mce, cpu), | |
1070 | &bank_attrs[i]); | |
1071 | if (err) | |
1072 | goto error2; | |
1073 | } | |
996867d0 | 1074 | cpumask_set_cpu(cpu, mce_device_initialized); |
91c6d400 | 1075 | |
d435d862 | 1076 | return 0; |
0d7482e3 AK |
1077 | error2: |
1078 | while (--i >= 0) { | |
1079 | sysdev_remove_file(&per_cpu(device_mce, cpu), | |
1080 | &bank_attrs[i]); | |
1081 | } | |
d435d862 | 1082 | error: |
0d7482e3 | 1083 | while (--i >= 0) { |
e9eee03e | 1084 | sysdev_remove_file(&per_cpu(device_mce, cpu), |
d435d862 | 1085 | mce_attributes[i]); |
91c6d400 | 1086 | } |
e9eee03e | 1087 | sysdev_unregister(&per_cpu(device_mce, cpu)); |
d435d862 | 1088 | |
91c6d400 AK |
1089 | return err; |
1090 | } | |
1091 | ||
2d9cd6c2 | 1092 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1093 | { |
73ca5358 SL |
1094 | int i; |
1095 | ||
996867d0 | 1096 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
1097 | return; |
1098 | ||
a98f0dd3 | 1099 | for (i = 0; mce_attributes[i]; i++) |
e9eee03e | 1100 | sysdev_remove_file(&per_cpu(device_mce, cpu), |
a98f0dd3 | 1101 | mce_attributes[i]); |
0d7482e3 AK |
1102 | for (i = 0; i < banks; i++) |
1103 | sysdev_remove_file(&per_cpu(device_mce, cpu), | |
1104 | &bank_attrs[i]); | |
e9eee03e | 1105 | sysdev_unregister(&per_cpu(device_mce, cpu)); |
996867d0 | 1106 | cpumask_clear_cpu(cpu, mce_device_initialized); |
91c6d400 | 1107 | } |
91c6d400 | 1108 | |
d6b75584 | 1109 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1110 | static void mce_disable_cpu(void *h) |
d6b75584 AK |
1111 | { |
1112 | int i; | |
88ccbedd | 1113 | unsigned long action = *(unsigned long *)h; |
d6b75584 AK |
1114 | |
1115 | if (!mce_available(¤t_cpu_data)) | |
1116 | return; | |
88ccbedd AK |
1117 | if (!(action & CPU_TASKS_FROZEN)) |
1118 | cmci_clear(); | |
d6b75584 AK |
1119 | for (i = 0; i < banks; i++) |
1120 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1121 | } | |
1122 | ||
ec5b3d32 | 1123 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1124 | { |
88ccbedd | 1125 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1126 | int i; |
d6b75584 AK |
1127 | |
1128 | if (!mce_available(¤t_cpu_data)) | |
1129 | return; | |
e9eee03e | 1130 | |
88ccbedd AK |
1131 | if (!(action & CPU_TASKS_FROZEN)) |
1132 | cmci_reenable(); | |
d6b75584 AK |
1133 | for (i = 0; i < banks; i++) |
1134 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1135 | } | |
1136 | ||
91c6d400 | 1137 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1138 | static int __cpuinit |
1139 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1140 | { |
1141 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1142 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1143 | |
1144 | switch (action) { | |
bae19fe0 AH |
1145 | case CPU_ONLINE: |
1146 | case CPU_ONLINE_FROZEN: | |
1147 | mce_create_device(cpu); | |
8735728e RW |
1148 | if (threshold_cpu_callback) |
1149 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1150 | break; |
91c6d400 | 1151 | case CPU_DEAD: |
8bb78442 | 1152 | case CPU_DEAD_FROZEN: |
8735728e RW |
1153 | if (threshold_cpu_callback) |
1154 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1155 | mce_remove_device(cpu); |
1156 | break; | |
52d168e2 AK |
1157 | case CPU_DOWN_PREPARE: |
1158 | case CPU_DOWN_PREPARE_FROZEN: | |
1159 | del_timer_sync(t); | |
88ccbedd | 1160 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1161 | break; |
1162 | case CPU_DOWN_FAILED: | |
1163 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1164 | t->expires = round_jiffies(jiffies + |
1165 | __get_cpu_var(next_interval)); | |
52d168e2 | 1166 | add_timer_on(t, cpu); |
88ccbedd AK |
1167 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1168 | break; | |
1169 | case CPU_POST_DEAD: | |
1170 | /* intentionally ignoring frozen here */ | |
1171 | cmci_rediscover(cpu); | |
52d168e2 | 1172 | break; |
91c6d400 | 1173 | } |
bae19fe0 | 1174 | return NOTIFY_OK; |
91c6d400 AK |
1175 | } |
1176 | ||
1e35669d | 1177 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1178 | .notifier_call = mce_cpu_callback, |
1179 | }; | |
1180 | ||
0d7482e3 AK |
1181 | static __init int mce_init_banks(void) |
1182 | { | |
1183 | int i; | |
1184 | ||
1185 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1186 | GFP_KERNEL); | |
1187 | if (!bank_attrs) | |
1188 | return -ENOMEM; | |
1189 | ||
1190 | for (i = 0; i < banks; i++) { | |
1191 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1192 | |
1193 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1194 | if (!a->attr.name) |
1195 | goto nomem; | |
e9eee03e IM |
1196 | |
1197 | a->attr.mode = 0644; | |
1198 | a->show = show_bank; | |
1199 | a->store = set_bank; | |
0d7482e3 AK |
1200 | } |
1201 | return 0; | |
1202 | ||
1203 | nomem: | |
1204 | while (--i >= 0) | |
1205 | kfree(bank_attrs[i].attr.name); | |
1206 | kfree(bank_attrs); | |
1207 | bank_attrs = NULL; | |
e9eee03e | 1208 | |
0d7482e3 AK |
1209 | return -ENOMEM; |
1210 | } | |
1211 | ||
91c6d400 AK |
1212 | static __init int mce_init_device(void) |
1213 | { | |
1214 | int err; | |
1215 | int i = 0; | |
1216 | ||
1da177e4 LT |
1217 | if (!mce_available(&boot_cpu_data)) |
1218 | return -EIO; | |
0d7482e3 | 1219 | |
996867d0 RR |
1220 | alloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
1221 | ||
0d7482e3 AK |
1222 | err = mce_init_banks(); |
1223 | if (err) | |
1224 | return err; | |
1225 | ||
1da177e4 | 1226 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1227 | if (err) |
1228 | return err; | |
91c6d400 AK |
1229 | |
1230 | for_each_online_cpu(i) { | |
d435d862 AM |
1231 | err = mce_create_device(i); |
1232 | if (err) | |
1233 | return err; | |
91c6d400 AK |
1234 | } |
1235 | ||
be6b5a35 | 1236 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1237 | misc_register(&mce_log_device); |
e9eee03e | 1238 | |
1da177e4 | 1239 | return err; |
1da177e4 | 1240 | } |
91c6d400 | 1241 | |
1da177e4 | 1242 | device_initcall(mce_init_device); |