Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
e9eee03e | 16 | #include <linux/kobject.h> |
14a02530 | 17 | #include <linux/uaccess.h> |
e9eee03e IM |
18 | #include <linux/kdebug.h> |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
14a02530 | 31 | #include <linux/smp.h> |
e9eee03e IM |
32 | #include <linux/fs.h> |
33 | ||
d88203d1 | 34 | #include <asm/processor.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
1da177e4 | 38 | |
711c2e48 IM |
39 | #include "mce.h" |
40 | ||
5d727926 AK |
41 | /* Handle unconfigured int18 (should never happen) */ |
42 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
43 | { | |
44 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
45 | smp_processor_id()); | |
46 | } | |
47 | ||
48 | /* Call the installed machine check handler for this CPU setup. */ | |
49 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
50 | unexpected_machine_check; | |
04b2b1a4 AK |
51 | |
52 | int mce_disabled; | |
53 | ||
4efc0670 | 54 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 55 | |
e9eee03e | 56 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 57 | |
553f265f AK |
58 | atomic_t mce_entry; |
59 | ||
01ca79f1 AK |
60 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
61 | ||
bd78432c TH |
62 | /* |
63 | * Tolerant levels: | |
64 | * 0: always panic on uncorrected errors, log corrected errors | |
65 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
66 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
67 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
68 | */ | |
e9eee03e IM |
69 | static int tolerant = 1; |
70 | static int banks; | |
71 | static u64 *bank; | |
72 | static unsigned long notify_user; | |
73 | static int rip_msr; | |
74 | static int mce_bootlog = -1; | |
a98f0dd3 | 75 | |
e9eee03e IM |
76 | static char trigger[128]; |
77 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 78 | |
06b7a7a5 AK |
79 | static unsigned long dont_init_banks; |
80 | ||
e02e68d3 TH |
81 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
82 | ||
ee031c31 AK |
83 | /* MCA banks polled by the period polling timer for corrected events */ |
84 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
85 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
86 | }; | |
87 | ||
06b7a7a5 AK |
88 | static inline int skip_bank_init(int i) |
89 | { | |
90 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
91 | } | |
92 | ||
b5f2fa4e AK |
93 | /* Do initial initialization of a struct mce */ |
94 | void mce_setup(struct mce *m) | |
95 | { | |
96 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 97 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e AK |
98 | rdtscll(m->tsc); |
99 | } | |
100 | ||
ea149b36 AK |
101 | DEFINE_PER_CPU(struct mce, injectm); |
102 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
103 | ||
1da177e4 LT |
104 | /* |
105 | * Lockless MCE logging infrastructure. | |
106 | * This avoids deadlocks on printk locks without having to break locks. Also | |
107 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
108 | */ | |
109 | ||
231fd906 | 110 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
111 | .signature = MCE_LOG_SIGNATURE, |
112 | .len = MCE_LOG_LEN, | |
113 | .recordlen = sizeof(struct mce), | |
d88203d1 | 114 | }; |
1da177e4 LT |
115 | |
116 | void mce_log(struct mce *mce) | |
117 | { | |
118 | unsigned next, entry; | |
e9eee03e | 119 | |
1da177e4 | 120 | mce->finished = 0; |
7644143c | 121 | wmb(); |
1da177e4 LT |
122 | for (;;) { |
123 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 124 | for (;;) { |
e9eee03e IM |
125 | /* |
126 | * When the buffer fills up discard new entries. | |
127 | * Assume that the earlier errors are the more | |
128 | * interesting ones: | |
129 | */ | |
673242c1 | 130 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
131 | set_bit(MCE_OVERFLOW, |
132 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
133 | return; |
134 | } | |
e9eee03e | 135 | /* Old left over entry. Skip: */ |
673242c1 AK |
136 | if (mcelog.entry[entry].finished) { |
137 | entry++; | |
138 | continue; | |
139 | } | |
7644143c | 140 | break; |
1da177e4 | 141 | } |
1da177e4 LT |
142 | smp_rmb(); |
143 | next = entry + 1; | |
144 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
145 | break; | |
146 | } | |
147 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 148 | wmb(); |
1da177e4 | 149 | mcelog.entry[entry].finished = 1; |
7644143c | 150 | wmb(); |
1da177e4 | 151 | |
e02e68d3 | 152 | set_bit(0, ¬ify_user); |
1da177e4 LT |
153 | } |
154 | ||
155 | static void print_mce(struct mce *m) | |
156 | { | |
157 | printk(KERN_EMERG "\n" | |
4855170f | 158 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
159 | KERN_EMERG |
160 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
d620c67f | 161 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 162 | if (m->ip) { |
d88203d1 | 163 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 164 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 165 | m->cs, m->ip); |
1da177e4 | 166 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 167 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
168 | printk("\n"); |
169 | } | |
f6d1826d | 170 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 171 | if (m->addr) |
f6d1826d | 172 | printk("ADDR %llx ", m->addr); |
1da177e4 | 173 | if (m->misc) |
f6d1826d | 174 | printk("MISC %llx ", m->misc); |
1da177e4 | 175 | printk("\n"); |
4855170f | 176 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
177 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
178 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
179 | } |
180 | ||
3cde5c8c | 181 | static void mce_panic(char *msg, struct mce *backup, u64 start) |
d88203d1 | 182 | { |
1da177e4 | 183 | int i; |
e02e68d3 | 184 | |
d896a940 AK |
185 | bust_spinlocks(1); |
186 | console_verbose(); | |
1da177e4 | 187 | for (i = 0; i < MCE_LOG_LEN; i++) { |
3cde5c8c | 188 | u64 tsc = mcelog.entry[i].tsc; |
d88203d1 | 189 | |
3cde5c8c | 190 | if ((s64)(tsc - start) < 0) |
1da177e4 | 191 | continue; |
d88203d1 | 192 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
193 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
194 | backup = NULL; | |
195 | } | |
196 | if (backup) | |
197 | print_mce(backup); | |
e02e68d3 | 198 | panic(msg); |
d88203d1 | 199 | } |
1da177e4 | 200 | |
ea149b36 AK |
201 | /* Support code for software error injection */ |
202 | ||
203 | static int msr_to_offset(u32 msr) | |
204 | { | |
205 | unsigned bank = __get_cpu_var(injectm.bank); | |
206 | if (msr == rip_msr) | |
207 | return offsetof(struct mce, ip); | |
208 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
209 | return offsetof(struct mce, status); | |
210 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
211 | return offsetof(struct mce, addr); | |
212 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
213 | return offsetof(struct mce, misc); | |
214 | if (msr == MSR_IA32_MCG_STATUS) | |
215 | return offsetof(struct mce, mcgstatus); | |
216 | return -1; | |
217 | } | |
218 | ||
5f8c1a54 AK |
219 | /* MSR access wrappers used for error injection */ |
220 | static u64 mce_rdmsrl(u32 msr) | |
221 | { | |
222 | u64 v; | |
ea149b36 AK |
223 | if (__get_cpu_var(injectm).finished) { |
224 | int offset = msr_to_offset(msr); | |
225 | if (offset < 0) | |
226 | return 0; | |
227 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
228 | } | |
5f8c1a54 AK |
229 | rdmsrl(msr, v); |
230 | return v; | |
231 | } | |
232 | ||
233 | static void mce_wrmsrl(u32 msr, u64 v) | |
234 | { | |
ea149b36 AK |
235 | if (__get_cpu_var(injectm).finished) { |
236 | int offset = msr_to_offset(msr); | |
237 | if (offset >= 0) | |
238 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
239 | return; | |
240 | } | |
5f8c1a54 AK |
241 | wrmsrl(msr, v); |
242 | } | |
243 | ||
88ccbedd | 244 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 245 | { |
04b2b1a4 | 246 | if (mce_disabled) |
5b4408fd | 247 | return 0; |
3d1712c9 | 248 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
249 | } |
250 | ||
94ad8474 AK |
251 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
252 | { | |
253 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 254 | m->ip = regs->ip; |
94ad8474 AK |
255 | m->cs = regs->cs; |
256 | } else { | |
65ea5b03 | 257 | m->ip = 0; |
94ad8474 AK |
258 | m->cs = 0; |
259 | } | |
260 | if (rip_msr) { | |
261 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
262 | m->mcgstatus |= MCG_STATUS_EIPV; | |
5f8c1a54 | 263 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
264 | m->cs = 0; |
265 | } | |
266 | } | |
267 | ||
ca84f696 AK |
268 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
269 | ||
d88203d1 | 270 | /* |
b79109c3 AK |
271 | * Poll for corrected events or events that happened before reset. |
272 | * Those are just logged through /dev/mcelog. | |
273 | * | |
274 | * This is executed in standard interrupt context. | |
275 | */ | |
ee031c31 | 276 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
277 | { |
278 | struct mce m; | |
279 | int i; | |
280 | ||
ca84f696 AK |
281 | __get_cpu_var(mce_poll_count)++; |
282 | ||
b79109c3 AK |
283 | mce_setup(&m); |
284 | ||
5f8c1a54 | 285 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 286 | for (i = 0; i < banks; i++) { |
ee031c31 | 287 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
288 | continue; |
289 | ||
290 | m.misc = 0; | |
291 | m.addr = 0; | |
292 | m.bank = i; | |
293 | m.tsc = 0; | |
294 | ||
295 | barrier(); | |
5f8c1a54 | 296 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
297 | if (!(m.status & MCI_STATUS_VAL)) |
298 | continue; | |
299 | ||
300 | /* | |
301 | * Uncorrected events are handled by the exception handler | |
302 | * when it is enabled. But when the exception is disabled log | |
303 | * everything. | |
304 | * | |
305 | * TBD do the same check for MCI_STATUS_EN here? | |
306 | */ | |
307 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
308 | continue; | |
309 | ||
310 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 311 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 312 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 313 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
314 | |
315 | if (!(flags & MCP_TIMESTAMP)) | |
316 | m.tsc = 0; | |
317 | /* | |
318 | * Don't get the IP here because it's unlikely to | |
319 | * have anything to do with the actual error location. | |
320 | */ | |
5679af4c AK |
321 | if (!(flags & MCP_DONTLOG)) { |
322 | mce_log(&m); | |
323 | add_taint(TAINT_MACHINE_CHECK); | |
324 | } | |
b79109c3 AK |
325 | |
326 | /* | |
327 | * Clear state for this bank. | |
328 | */ | |
5f8c1a54 | 329 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
330 | } |
331 | ||
332 | /* | |
333 | * Don't clear MCG_STATUS here because it's only defined for | |
334 | * exceptions. | |
335 | */ | |
88921be3 AK |
336 | |
337 | sync_core(); | |
b79109c3 | 338 | } |
ea149b36 | 339 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 AK |
340 | |
341 | /* | |
342 | * The actual machine check handler. This only handles real | |
343 | * exceptions when something got corrupted coming in through int 18. | |
344 | * | |
345 | * This is executed in NMI context not subject to normal locking rules. This | |
346 | * implies that most kernel services cannot be safely used. Don't even | |
347 | * think about putting a printk in there! | |
1da177e4 | 348 | */ |
e9eee03e | 349 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
350 | { |
351 | struct mce m, panicm; | |
e9eee03e | 352 | int panicm_found = 0; |
1da177e4 LT |
353 | u64 mcestart = 0; |
354 | int i; | |
bd78432c TH |
355 | /* |
356 | * If no_way_out gets set, there is no safe way to recover from this | |
357 | * MCE. If tolerant is cranked up, we'll try anyway. | |
358 | */ | |
359 | int no_way_out = 0; | |
360 | /* | |
361 | * If kill_it gets set, there might be a way to recover from this | |
362 | * error. | |
363 | */ | |
364 | int kill_it = 0; | |
b79109c3 | 365 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 366 | |
553f265f AK |
367 | atomic_inc(&mce_entry); |
368 | ||
01ca79f1 AK |
369 | __get_cpu_var(mce_exception_count)++; |
370 | ||
b79109c3 | 371 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 372 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 373 | goto out; |
b79109c3 | 374 | if (!banks) |
32561696 | 375 | goto out; |
1da177e4 | 376 | |
b5f2fa4e AK |
377 | mce_setup(&m); |
378 | ||
5f8c1a54 | 379 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
e9eee03e | 380 | |
bd78432c | 381 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 382 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 383 | no_way_out = 1; |
d88203d1 | 384 | |
1da177e4 LT |
385 | rdtscll(mcestart); |
386 | barrier(); | |
387 | ||
388 | for (i = 0; i < banks; i++) { | |
b79109c3 | 389 | __clear_bit(i, toclear); |
0d7482e3 | 390 | if (!bank[i]) |
1da177e4 | 391 | continue; |
d88203d1 TG |
392 | |
393 | m.misc = 0; | |
1da177e4 LT |
394 | m.addr = 0; |
395 | m.bank = i; | |
1da177e4 | 396 | |
5f8c1a54 | 397 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
398 | if ((m.status & MCI_STATUS_VAL) == 0) |
399 | continue; | |
400 | ||
b79109c3 AK |
401 | /* |
402 | * Non uncorrected errors are handled by machine_check_poll | |
403 | * Leave them alone. | |
404 | */ | |
405 | if ((m.status & MCI_STATUS_UC) == 0) | |
406 | continue; | |
407 | ||
408 | /* | |
409 | * Set taint even when machine check was not enabled. | |
410 | */ | |
411 | add_taint(TAINT_MACHINE_CHECK); | |
412 | ||
413 | __set_bit(i, toclear); | |
414 | ||
1da177e4 | 415 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
416 | /* if PCC was set, there's no way out */ |
417 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
418 | /* | |
419 | * If this error was uncorrectable and there was | |
420 | * an overflow, we're in trouble. If no overflow, | |
421 | * we might get away with just killing a task. | |
422 | */ | |
423 | if (m.status & MCI_STATUS_UC) { | |
424 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
425 | no_way_out = 1; | |
426 | kill_it = 1; | |
427 | } | |
b79109c3 AK |
428 | } else { |
429 | /* | |
430 | * Machine check event was not enabled. Clear, but | |
431 | * ignore. | |
432 | */ | |
433 | continue; | |
1da177e4 LT |
434 | } |
435 | ||
436 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 437 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 438 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 439 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 440 | |
94ad8474 | 441 | mce_get_rip(&m, regs); |
b79109c3 | 442 | mce_log(&m); |
1da177e4 | 443 | |
e9eee03e IM |
444 | /* |
445 | * Did this bank cause the exception? | |
446 | * | |
447 | * Assume that the bank with uncorrectable errors did it, | |
448 | * and that there is only a single one: | |
449 | */ | |
450 | if ((m.status & MCI_STATUS_UC) && | |
451 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
452 | panicm = m; |
453 | panicm_found = 1; | |
454 | } | |
1da177e4 LT |
455 | } |
456 | ||
e9eee03e IM |
457 | /* |
458 | * If we didn't find an uncorrectable error, pick | |
459 | * the last one (shouldn't happen, just being safe). | |
460 | */ | |
1da177e4 LT |
461 | if (!panicm_found) |
462 | panicm = m; | |
bd78432c TH |
463 | |
464 | /* | |
465 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 466 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
467 | */ |
468 | if (no_way_out && tolerant < 3) | |
1da177e4 | 469 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
470 | |
471 | /* | |
472 | * If the error seems to be unrecoverable, something should be | |
473 | * done. Try to kill as little as possible. If we can kill just | |
474 | * one task, do that. If the user has set the tolerance very | |
475 | * high, don't try to do anything at all. | |
476 | */ | |
477 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
478 | int user_space = 0; |
479 | ||
bd78432c TH |
480 | /* |
481 | * If the EIPV bit is set, it means the saved IP is the | |
482 | * instruction which caused the MCE. | |
483 | */ | |
484 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 485 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
486 | |
487 | /* | |
488 | * If we know that the error was in user space, send a | |
489 | * SIGBUS. Otherwise, panic if tolerance is low. | |
490 | * | |
380851bc | 491 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
492 | * risk of deadlocking. |
493 | */ | |
494 | if (user_space) { | |
380851bc | 495 | force_sig(SIGBUS, current); |
bd78432c TH |
496 | } else if (panic_on_oops || tolerant < 2) { |
497 | mce_panic("Uncorrected machine check", | |
498 | &panicm, mcestart); | |
499 | } | |
1da177e4 LT |
500 | } |
501 | ||
e02e68d3 TH |
502 | /* notify userspace ASAP */ |
503 | set_thread_flag(TIF_MCE_NOTIFY); | |
504 | ||
bd78432c | 505 | /* the last thing we do is clear state */ |
b79109c3 AK |
506 | for (i = 0; i < banks; i++) { |
507 | if (test_bit(i, toclear)) | |
5f8c1a54 | 508 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 | 509 | } |
5f8c1a54 | 510 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 511 | out: |
553f265f | 512 | atomic_dec(&mce_entry); |
88921be3 | 513 | sync_core(); |
1da177e4 | 514 | } |
ea149b36 | 515 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 516 | |
15d5f839 DZ |
517 | #ifdef CONFIG_X86_MCE_INTEL |
518 | /*** | |
519 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 520 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
521 | * @status: Event status information |
522 | * | |
523 | * This function should be called by the thermal interrupt after the | |
524 | * event has been processed and the decision was made to log the event | |
525 | * further. | |
526 | * | |
527 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
528 | * and historically has been the register value of the | |
529 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
530 | */ | |
b5f2fa4e | 531 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
532 | { |
533 | struct mce m; | |
534 | ||
b5f2fa4e | 535 | mce_setup(&m); |
15d5f839 DZ |
536 | m.bank = MCE_THERMAL_BANK; |
537 | m.status = status; | |
15d5f839 DZ |
538 | mce_log(&m); |
539 | } | |
540 | #endif /* CONFIG_X86_MCE_INTEL */ | |
541 | ||
1da177e4 | 542 | /* |
8a336b0a TH |
543 | * Periodic polling timer for "silent" machine check errors. If the |
544 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
545 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 546 | */ |
1da177e4 | 547 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 548 | |
6298c512 | 549 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 550 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 551 | |
52d168e2 | 552 | static void mcheck_timer(unsigned long data) |
1da177e4 | 553 | { |
52d168e2 | 554 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 555 | int *n; |
52d168e2 AK |
556 | |
557 | WARN_ON(smp_processor_id() != data); | |
558 | ||
e9eee03e | 559 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
560 | machine_check_poll(MCP_TIMESTAMP, |
561 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 562 | } |
1da177e4 LT |
563 | |
564 | /* | |
e02e68d3 TH |
565 | * Alert userspace if needed. If we logged an MCE, reduce the |
566 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 567 | */ |
6298c512 | 568 | n = &__get_cpu_var(next_interval); |
14a02530 | 569 | if (mce_notify_user()) |
6298c512 | 570 | *n = max(*n/2, HZ/100); |
14a02530 | 571 | else |
6298c512 | 572 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 573 | |
6298c512 | 574 | t->expires = jiffies + *n; |
52d168e2 | 575 | add_timer(t); |
e02e68d3 TH |
576 | } |
577 | ||
9bd98405 AK |
578 | static void mce_do_trigger(struct work_struct *work) |
579 | { | |
580 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
581 | } | |
582 | ||
583 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
584 | ||
e02e68d3 | 585 | /* |
9bd98405 AK |
586 | * Notify the user(s) about new machine check events. |
587 | * Can be called from interrupt context, but not from machine check/NMI | |
588 | * context. | |
e02e68d3 TH |
589 | */ |
590 | int mce_notify_user(void) | |
591 | { | |
8457c84d AK |
592 | /* Not more than two messages every minute */ |
593 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
594 | ||
e02e68d3 | 595 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 596 | |
e02e68d3 | 597 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 598 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
599 | |
600 | /* | |
601 | * There is no risk of missing notifications because | |
602 | * work_pending is always cleared before the function is | |
603 | * executed. | |
604 | */ | |
605 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
606 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 607 | |
8457c84d | 608 | if (__ratelimit(&ratelimit)) |
8a336b0a | 609 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
610 | |
611 | return 1; | |
1da177e4 | 612 | } |
e02e68d3 TH |
613 | return 0; |
614 | } | |
ea149b36 | 615 | EXPORT_SYMBOL_GPL(mce_notify_user); |
8a336b0a | 616 | |
d88203d1 | 617 | /* |
1da177e4 LT |
618 | * Initialize Machine Checks for a CPU. |
619 | */ | |
0d7482e3 | 620 | static int mce_cap_init(void) |
1da177e4 | 621 | { |
0d7482e3 | 622 | unsigned b; |
e9eee03e | 623 | u64 cap; |
1da177e4 LT |
624 | |
625 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
626 | |
627 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
628 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
629 | ||
0d7482e3 AK |
630 | if (b > MAX_NR_BANKS) { |
631 | printk(KERN_WARNING | |
632 | "MCE: Using only %u machine check banks out of %u\n", | |
633 | MAX_NR_BANKS, b); | |
634 | b = MAX_NR_BANKS; | |
635 | } | |
636 | ||
637 | /* Don't support asymmetric configurations today */ | |
638 | WARN_ON(banks != 0 && b != banks); | |
639 | banks = b; | |
640 | if (!bank) { | |
641 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
642 | if (!bank) | |
643 | return -ENOMEM; | |
644 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 645 | } |
0d7482e3 | 646 | |
94ad8474 | 647 | /* Use accurate RIP reporting if available. */ |
01c6680a | 648 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 649 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 650 | |
0d7482e3 AK |
651 | return 0; |
652 | } | |
653 | ||
8be91105 | 654 | static void mce_init(void) |
0d7482e3 | 655 | { |
e9eee03e | 656 | mce_banks_t all_banks; |
0d7482e3 AK |
657 | u64 cap; |
658 | int i; | |
659 | ||
b79109c3 AK |
660 | /* |
661 | * Log the machine checks left over from the previous reset. | |
662 | */ | |
ee031c31 | 663 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 664 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
665 | |
666 | set_in_cr4(X86_CR4_MCE); | |
667 | ||
0d7482e3 | 668 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
669 | if (cap & MCG_CTL_P) |
670 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
671 | ||
672 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
673 | if (skip_bank_init(i)) |
674 | continue; | |
0d7482e3 | 675 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 676 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 677 | } |
1da177e4 LT |
678 | } |
679 | ||
680 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 681 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 682 | { |
1da177e4 | 683 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 684 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
685 | if (c->x86 == 15 && banks > 4) { |
686 | /* | |
687 | * disable GART TBL walk error reporting, which | |
688 | * trips off incorrectly with the IOMMU & 3ware | |
689 | * & Cerberus: | |
690 | */ | |
0d7482e3 | 691 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
692 | } |
693 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
694 | /* | |
695 | * Lots of broken BIOS around that don't clear them | |
696 | * by default and leave crap in there. Don't log: | |
697 | */ | |
911f6a7b | 698 | mce_bootlog = 0; |
e9eee03e | 699 | } |
2e6f694f AK |
700 | /* |
701 | * Various K7s with broken bank 0 around. Always disable | |
702 | * by default. | |
703 | */ | |
704 | if (c->x86 == 6) | |
705 | bank[0] = 0; | |
1da177e4 | 706 | } |
e583538f | 707 | |
06b7a7a5 AK |
708 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
709 | /* | |
710 | * SDM documents that on family 6 bank 0 should not be written | |
711 | * because it aliases to another special BIOS controlled | |
712 | * register. | |
713 | * But it's not aliased anymore on model 0x1a+ | |
714 | * Don't ignore bank 0 completely because there could be a | |
715 | * valid event later, merely don't write CTL0. | |
716 | */ | |
717 | ||
718 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
719 | __set_bit(0, &dont_init_banks); | |
720 | } | |
d88203d1 | 721 | } |
1da177e4 | 722 | |
4efc0670 AK |
723 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
724 | { | |
725 | if (c->x86 != 5) | |
726 | return; | |
727 | switch (c->x86_vendor) { | |
728 | case X86_VENDOR_INTEL: | |
729 | if (mce_p5_enabled()) | |
730 | intel_p5_mcheck_init(c); | |
731 | break; | |
732 | case X86_VENDOR_CENTAUR: | |
733 | winchip_mcheck_init(c); | |
734 | break; | |
735 | } | |
736 | } | |
737 | ||
cc3ca220 | 738 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
739 | { |
740 | switch (c->x86_vendor) { | |
741 | case X86_VENDOR_INTEL: | |
742 | mce_intel_feature_init(c); | |
743 | break; | |
89b831ef JS |
744 | case X86_VENDOR_AMD: |
745 | mce_amd_feature_init(c); | |
746 | break; | |
1da177e4 LT |
747 | default: |
748 | break; | |
749 | } | |
750 | } | |
751 | ||
52d168e2 AK |
752 | static void mce_init_timer(void) |
753 | { | |
754 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 755 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 756 | |
6298c512 AK |
757 | *n = check_interval * HZ; |
758 | if (!*n) | |
52d168e2 AK |
759 | return; |
760 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 761 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
762 | add_timer(t); |
763 | } | |
764 | ||
d88203d1 | 765 | /* |
1da177e4 | 766 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 767 | * Must be called with preempt off: |
1da177e4 | 768 | */ |
e6982c67 | 769 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 770 | { |
4efc0670 AK |
771 | if (mce_disabled) |
772 | return; | |
773 | ||
774 | mce_ancient_init(c); | |
775 | ||
5b4408fd | 776 | if (!mce_available(c)) |
1da177e4 LT |
777 | return; |
778 | ||
0d7482e3 | 779 | if (mce_cap_init() < 0) { |
04b2b1a4 | 780 | mce_disabled = 1; |
0d7482e3 AK |
781 | return; |
782 | } | |
783 | mce_cpu_quirks(c); | |
784 | ||
5d727926 AK |
785 | machine_check_vector = do_machine_check; |
786 | ||
8be91105 | 787 | mce_init(); |
1da177e4 | 788 | mce_cpu_features(c); |
52d168e2 | 789 | mce_init_timer(); |
1da177e4 LT |
790 | } |
791 | ||
792 | /* | |
793 | * Character device to read and clear the MCE log. | |
794 | */ | |
795 | ||
f528e7ba | 796 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
797 | static int open_count; /* #times opened */ |
798 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
799 | |
800 | static int mce_open(struct inode *inode, struct file *file) | |
801 | { | |
802 | spin_lock(&mce_state_lock); | |
803 | ||
804 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
805 | spin_unlock(&mce_state_lock); | |
e9eee03e | 806 | |
f528e7ba TH |
807 | return -EBUSY; |
808 | } | |
809 | ||
810 | if (file->f_flags & O_EXCL) | |
811 | open_exclu = 1; | |
812 | open_count++; | |
813 | ||
814 | spin_unlock(&mce_state_lock); | |
815 | ||
bd78432c | 816 | return nonseekable_open(inode, file); |
f528e7ba TH |
817 | } |
818 | ||
819 | static int mce_release(struct inode *inode, struct file *file) | |
820 | { | |
821 | spin_lock(&mce_state_lock); | |
822 | ||
823 | open_count--; | |
824 | open_exclu = 0; | |
825 | ||
826 | spin_unlock(&mce_state_lock); | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
d88203d1 TG |
831 | static void collect_tscs(void *data) |
832 | { | |
1da177e4 | 833 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 834 | |
1da177e4 | 835 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 836 | } |
1da177e4 | 837 | |
e9eee03e IM |
838 | static DEFINE_MUTEX(mce_read_mutex); |
839 | ||
d88203d1 TG |
840 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
841 | loff_t *off) | |
1da177e4 | 842 | { |
e9eee03e | 843 | char __user *buf = ubuf; |
f0de53bb | 844 | unsigned long *cpu_tsc; |
ef41df43 | 845 | unsigned prev, next; |
1da177e4 LT |
846 | int i, err; |
847 | ||
6bca67f9 | 848 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
849 | if (!cpu_tsc) |
850 | return -ENOMEM; | |
851 | ||
8c8b8859 | 852 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
853 | next = rcu_dereference(mcelog.next); |
854 | ||
855 | /* Only supports full reads right now */ | |
d88203d1 | 856 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 857 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 858 | kfree(cpu_tsc); |
e9eee03e | 859 | |
1da177e4 LT |
860 | return -EINVAL; |
861 | } | |
862 | ||
863 | err = 0; | |
ef41df43 HY |
864 | prev = 0; |
865 | do { | |
866 | for (i = prev; i < next; i++) { | |
867 | unsigned long start = jiffies; | |
868 | ||
869 | while (!mcelog.entry[i].finished) { | |
870 | if (time_after_eq(jiffies, start + 2)) { | |
871 | memset(mcelog.entry + i, 0, | |
872 | sizeof(struct mce)); | |
873 | goto timeout; | |
874 | } | |
875 | cpu_relax(); | |
673242c1 | 876 | } |
ef41df43 HY |
877 | smp_rmb(); |
878 | err |= copy_to_user(buf, mcelog.entry + i, | |
879 | sizeof(struct mce)); | |
880 | buf += sizeof(struct mce); | |
881 | timeout: | |
882 | ; | |
673242c1 | 883 | } |
1da177e4 | 884 | |
ef41df43 HY |
885 | memset(mcelog.entry + prev, 0, |
886 | (next - prev) * sizeof(struct mce)); | |
887 | prev = next; | |
888 | next = cmpxchg(&mcelog.next, prev, 0); | |
889 | } while (next != prev); | |
1da177e4 | 890 | |
b2b18660 | 891 | synchronize_sched(); |
1da177e4 | 892 | |
d88203d1 TG |
893 | /* |
894 | * Collect entries that were still getting written before the | |
895 | * synchronize. | |
896 | */ | |
15c8b6c1 | 897 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 898 | |
d88203d1 TG |
899 | for (i = next; i < MCE_LOG_LEN; i++) { |
900 | if (mcelog.entry[i].finished && | |
901 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
902 | err |= copy_to_user(buf, mcelog.entry+i, | |
903 | sizeof(struct mce)); | |
1da177e4 LT |
904 | smp_rmb(); |
905 | buf += sizeof(struct mce); | |
906 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
907 | } | |
d88203d1 | 908 | } |
8c8b8859 | 909 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 910 | kfree(cpu_tsc); |
e9eee03e | 911 | |
d88203d1 | 912 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
913 | } |
914 | ||
e02e68d3 TH |
915 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
916 | { | |
917 | poll_wait(file, &mce_wait, wait); | |
918 | if (rcu_dereference(mcelog.next)) | |
919 | return POLLIN | POLLRDNORM; | |
920 | return 0; | |
921 | } | |
922 | ||
c68461b6 | 923 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
924 | { |
925 | int __user *p = (int __user *)arg; | |
d88203d1 | 926 | |
1da177e4 | 927 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 928 | return -EPERM; |
e9eee03e | 929 | |
1da177e4 | 930 | switch (cmd) { |
d88203d1 | 931 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
932 | return put_user(sizeof(struct mce), p); |
933 | case MCE_GET_LOG_LEN: | |
d88203d1 | 934 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
935 | case MCE_GETCLEAR_FLAGS: { |
936 | unsigned flags; | |
d88203d1 TG |
937 | |
938 | do { | |
1da177e4 | 939 | flags = mcelog.flags; |
d88203d1 | 940 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 941 | |
d88203d1 | 942 | return put_user(flags, p); |
1da177e4 LT |
943 | } |
944 | default: | |
d88203d1 TG |
945 | return -ENOTTY; |
946 | } | |
1da177e4 LT |
947 | } |
948 | ||
a1ff41bf | 949 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 950 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
951 | .open = mce_open, |
952 | .release = mce_release, | |
953 | .read = mce_read, | |
954 | .poll = mce_poll, | |
955 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 956 | }; |
ea149b36 | 957 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
958 | |
959 | static struct miscdevice mce_log_device = { | |
960 | MISC_MCELOG_MINOR, | |
961 | "mcelog", | |
962 | &mce_chrdev_ops, | |
963 | }; | |
964 | ||
13503fa9 HS |
965 | /* |
966 | * mce=off disables machine check | |
967 | * mce=TOLERANCELEVEL (number, see above) | |
968 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
969 | * mce=nobootlog Don't log MCEs from before booting. | |
970 | */ | |
1da177e4 LT |
971 | static int __init mcheck_enable(char *str) |
972 | { | |
4efc0670 AK |
973 | if (*str == 0) |
974 | enable_p5_mce(); | |
975 | if (*str == '=') | |
976 | str++; | |
1da177e4 | 977 | if (!strcmp(str, "off")) |
04b2b1a4 | 978 | mce_disabled = 1; |
13503fa9 HS |
979 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
980 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
981 | else if (isdigit(str[0])) |
982 | get_option(&str, &tolerant); | |
13503fa9 | 983 | else { |
4efc0670 | 984 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
985 | str); |
986 | return 0; | |
987 | } | |
9b41046c | 988 | return 1; |
1da177e4 | 989 | } |
4efc0670 | 990 | __setup("mce", mcheck_enable); |
1da177e4 | 991 | |
d88203d1 | 992 | /* |
1da177e4 | 993 | * Sysfs support |
d88203d1 | 994 | */ |
1da177e4 | 995 | |
973a2dd1 AK |
996 | /* |
997 | * Disable machine checks on suspend and shutdown. We can't really handle | |
998 | * them later. | |
999 | */ | |
1000 | static int mce_disable(void) | |
1001 | { | |
1002 | int i; | |
1003 | ||
06b7a7a5 AK |
1004 | for (i = 0; i < banks; i++) { |
1005 | if (!skip_bank_init(i)) | |
1006 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1007 | } | |
973a2dd1 AK |
1008 | return 0; |
1009 | } | |
1010 | ||
1011 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1012 | { | |
1013 | return mce_disable(); | |
1014 | } | |
1015 | ||
1016 | static int mce_shutdown(struct sys_device *dev) | |
1017 | { | |
1018 | return mce_disable(); | |
1019 | } | |
1020 | ||
e9eee03e IM |
1021 | /* |
1022 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1023 | * Only one CPU is active at this time, the others get re-added later using | |
1024 | * CPU hotplug: | |
1025 | */ | |
1da177e4 LT |
1026 | static int mce_resume(struct sys_device *dev) |
1027 | { | |
8be91105 | 1028 | mce_init(); |
6ec68bff | 1029 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1030 | |
1da177e4 LT |
1031 | return 0; |
1032 | } | |
1033 | ||
52d168e2 AK |
1034 | static void mce_cpu_restart(void *data) |
1035 | { | |
1036 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1037 | if (mce_available(¤t_cpu_data)) | |
8be91105 | 1038 | mce_init(); |
52d168e2 AK |
1039 | mce_init_timer(); |
1040 | } | |
1041 | ||
1da177e4 | 1042 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1043 | static void mce_restart(void) |
1044 | { | |
52d168e2 | 1045 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1046 | } |
1047 | ||
1048 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
1049 | .suspend = mce_suspend, |
1050 | .shutdown = mce_shutdown, | |
1051 | .resume = mce_resume, | |
1052 | .name = "machinecheck", | |
1da177e4 LT |
1053 | }; |
1054 | ||
cb491fca | 1055 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1056 | |
1057 | __cpuinitdata | |
1058 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1059 | |
0d7482e3 AK |
1060 | static struct sysdev_attribute *bank_attrs; |
1061 | ||
1062 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1063 | char *buf) | |
1064 | { | |
1065 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1066 | |
f6d1826d | 1067 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1068 | } |
1069 | ||
1070 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1071 | const char *buf, size_t size) |
0d7482e3 | 1072 | { |
9319cec8 | 1073 | u64 new; |
e9eee03e | 1074 | |
9319cec8 | 1075 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1076 | return -EINVAL; |
e9eee03e | 1077 | |
0d7482e3 AK |
1078 | bank[attr - bank_attrs] = new; |
1079 | mce_restart(); | |
e9eee03e | 1080 | |
9319cec8 | 1081 | return size; |
0d7482e3 | 1082 | } |
a98f0dd3 | 1083 | |
e9eee03e IM |
1084 | static ssize_t |
1085 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1086 | { |
1087 | strcpy(buf, trigger); | |
1088 | strcat(buf, "\n"); | |
1089 | return strlen(trigger) + 1; | |
1090 | } | |
1091 | ||
4a0b2b4d | 1092 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1093 | const char *buf, size_t siz) |
a98f0dd3 AK |
1094 | { |
1095 | char *p; | |
1096 | int len; | |
e9eee03e | 1097 | |
a98f0dd3 AK |
1098 | strncpy(trigger, buf, sizeof(trigger)); |
1099 | trigger[sizeof(trigger)-1] = 0; | |
1100 | len = strlen(trigger); | |
1101 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1102 | |
1103 | if (*p) | |
1104 | *p = 0; | |
1105 | ||
a98f0dd3 AK |
1106 | return len; |
1107 | } | |
1108 | ||
b56f642d AK |
1109 | static ssize_t store_int_with_restart(struct sys_device *s, |
1110 | struct sysdev_attribute *attr, | |
1111 | const char *buf, size_t size) | |
1112 | { | |
1113 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1114 | mce_restart(); | |
1115 | return ret; | |
1116 | } | |
1117 | ||
a98f0dd3 | 1118 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1119 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e | 1120 | |
b56f642d AK |
1121 | static struct sysdev_ext_attribute attr_check_interval = { |
1122 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1123 | store_int_with_restart), | |
1124 | &check_interval | |
1125 | }; | |
e9eee03e | 1126 | |
cb491fca | 1127 | static struct sysdev_attribute *mce_attrs[] = { |
b56f642d | 1128 | &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, |
a98f0dd3 AK |
1129 | NULL |
1130 | }; | |
1da177e4 | 1131 | |
cb491fca | 1132 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1133 | |
e9eee03e | 1134 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1135 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1136 | { |
1137 | int err; | |
73ca5358 | 1138 | int i; |
92cb7612 | 1139 | |
90367556 | 1140 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1141 | return -EIO; |
1142 | ||
cb491fca IM |
1143 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1144 | per_cpu(mce_dev, cpu).id = cpu; | |
1145 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1146 | |
cb491fca | 1147 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1148 | if (err) |
1149 | return err; | |
1150 | ||
cb491fca IM |
1151 | for (i = 0; mce_attrs[i]; i++) { |
1152 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1153 | if (err) |
1154 | goto error; | |
1155 | } | |
0d7482e3 | 1156 | for (i = 0; i < banks; i++) { |
cb491fca | 1157 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1158 | &bank_attrs[i]); |
1159 | if (err) | |
1160 | goto error2; | |
1161 | } | |
cb491fca | 1162 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1163 | |
d435d862 | 1164 | return 0; |
0d7482e3 | 1165 | error2: |
cb491fca IM |
1166 | while (--i >= 0) |
1167 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1168 | error: |
cb491fca IM |
1169 | while (--i >= 0) |
1170 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1171 | ||
1172 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1173 | |
91c6d400 AK |
1174 | return err; |
1175 | } | |
1176 | ||
2d9cd6c2 | 1177 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1178 | { |
73ca5358 SL |
1179 | int i; |
1180 | ||
cb491fca | 1181 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1182 | return; |
1183 | ||
cb491fca IM |
1184 | for (i = 0; mce_attrs[i]; i++) |
1185 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1186 | ||
0d7482e3 | 1187 | for (i = 0; i < banks; i++) |
cb491fca IM |
1188 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1189 | ||
1190 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1191 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1192 | } |
91c6d400 | 1193 | |
d6b75584 | 1194 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1195 | static void mce_disable_cpu(void *h) |
d6b75584 | 1196 | { |
88ccbedd | 1197 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1198 | int i; |
d6b75584 AK |
1199 | |
1200 | if (!mce_available(¤t_cpu_data)) | |
1201 | return; | |
88ccbedd AK |
1202 | if (!(action & CPU_TASKS_FROZEN)) |
1203 | cmci_clear(); | |
06b7a7a5 AK |
1204 | for (i = 0; i < banks; i++) { |
1205 | if (!skip_bank_init(i)) | |
1206 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1207 | } | |
d6b75584 AK |
1208 | } |
1209 | ||
ec5b3d32 | 1210 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1211 | { |
88ccbedd | 1212 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1213 | int i; |
d6b75584 AK |
1214 | |
1215 | if (!mce_available(¤t_cpu_data)) | |
1216 | return; | |
e9eee03e | 1217 | |
88ccbedd AK |
1218 | if (!(action & CPU_TASKS_FROZEN)) |
1219 | cmci_reenable(); | |
06b7a7a5 AK |
1220 | for (i = 0; i < banks; i++) { |
1221 | if (!skip_bank_init(i)) | |
1222 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1223 | } | |
d6b75584 AK |
1224 | } |
1225 | ||
91c6d400 | 1226 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1227 | static int __cpuinit |
1228 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1229 | { |
1230 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1231 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1232 | |
1233 | switch (action) { | |
bae19fe0 AH |
1234 | case CPU_ONLINE: |
1235 | case CPU_ONLINE_FROZEN: | |
1236 | mce_create_device(cpu); | |
8735728e RW |
1237 | if (threshold_cpu_callback) |
1238 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1239 | break; |
91c6d400 | 1240 | case CPU_DEAD: |
8bb78442 | 1241 | case CPU_DEAD_FROZEN: |
8735728e RW |
1242 | if (threshold_cpu_callback) |
1243 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1244 | mce_remove_device(cpu); |
1245 | break; | |
52d168e2 AK |
1246 | case CPU_DOWN_PREPARE: |
1247 | case CPU_DOWN_PREPARE_FROZEN: | |
1248 | del_timer_sync(t); | |
88ccbedd | 1249 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1250 | break; |
1251 | case CPU_DOWN_FAILED: | |
1252 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1253 | t->expires = round_jiffies(jiffies + |
1254 | __get_cpu_var(next_interval)); | |
52d168e2 | 1255 | add_timer_on(t, cpu); |
88ccbedd AK |
1256 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1257 | break; | |
1258 | case CPU_POST_DEAD: | |
1259 | /* intentionally ignoring frozen here */ | |
1260 | cmci_rediscover(cpu); | |
52d168e2 | 1261 | break; |
91c6d400 | 1262 | } |
bae19fe0 | 1263 | return NOTIFY_OK; |
91c6d400 AK |
1264 | } |
1265 | ||
1e35669d | 1266 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1267 | .notifier_call = mce_cpu_callback, |
1268 | }; | |
1269 | ||
0d7482e3 AK |
1270 | static __init int mce_init_banks(void) |
1271 | { | |
1272 | int i; | |
1273 | ||
1274 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1275 | GFP_KERNEL); | |
1276 | if (!bank_attrs) | |
1277 | return -ENOMEM; | |
1278 | ||
1279 | for (i = 0; i < banks; i++) { | |
1280 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1281 | |
1282 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1283 | if (!a->attr.name) |
1284 | goto nomem; | |
e9eee03e IM |
1285 | |
1286 | a->attr.mode = 0644; | |
1287 | a->show = show_bank; | |
1288 | a->store = set_bank; | |
0d7482e3 AK |
1289 | } |
1290 | return 0; | |
1291 | ||
1292 | nomem: | |
1293 | while (--i >= 0) | |
1294 | kfree(bank_attrs[i].attr.name); | |
1295 | kfree(bank_attrs); | |
1296 | bank_attrs = NULL; | |
e9eee03e | 1297 | |
0d7482e3 AK |
1298 | return -ENOMEM; |
1299 | } | |
1300 | ||
91c6d400 AK |
1301 | static __init int mce_init_device(void) |
1302 | { | |
1303 | int err; | |
1304 | int i = 0; | |
1305 | ||
1da177e4 LT |
1306 | if (!mce_available(&boot_cpu_data)) |
1307 | return -EIO; | |
0d7482e3 | 1308 | |
cb491fca | 1309 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1310 | |
0d7482e3 AK |
1311 | err = mce_init_banks(); |
1312 | if (err) | |
1313 | return err; | |
1314 | ||
1da177e4 | 1315 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1316 | if (err) |
1317 | return err; | |
91c6d400 AK |
1318 | |
1319 | for_each_online_cpu(i) { | |
d435d862 AM |
1320 | err = mce_create_device(i); |
1321 | if (err) | |
1322 | return err; | |
91c6d400 AK |
1323 | } |
1324 | ||
be6b5a35 | 1325 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1326 | misc_register(&mce_log_device); |
e9eee03e | 1327 | |
1da177e4 | 1328 | return err; |
1da177e4 | 1329 | } |
91c6d400 | 1330 | |
1da177e4 | 1331 | device_initcall(mce_init_device); |
a988d334 | 1332 | |
4efc0670 | 1333 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1334 | |
a988d334 IM |
1335 | int nr_mce_banks; |
1336 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1337 | ||
a988d334 IM |
1338 | /* This has to be run for each processor */ |
1339 | void mcheck_init(struct cpuinfo_x86 *c) | |
1340 | { | |
1341 | if (mce_disabled == 1) | |
1342 | return; | |
1343 | ||
1344 | switch (c->x86_vendor) { | |
1345 | case X86_VENDOR_AMD: | |
1346 | amd_mcheck_init(c); | |
1347 | break; | |
1348 | ||
1349 | case X86_VENDOR_INTEL: | |
1350 | if (c->x86 == 5) | |
1351 | intel_p5_mcheck_init(c); | |
1352 | if (c->x86 == 6) | |
1353 | intel_p6_mcheck_init(c); | |
1354 | if (c->x86 == 15) | |
1355 | intel_p4_mcheck_init(c); | |
1356 | break; | |
1357 | ||
1358 | case X86_VENDOR_CENTAUR: | |
1359 | if (c->x86 == 5) | |
1360 | winchip_mcheck_init(c); | |
1361 | break; | |
1362 | ||
1363 | default: | |
1364 | break; | |
1365 | } | |
b659294b | 1366 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1367 | } |
1368 | ||
a988d334 IM |
1369 | static int __init mcheck_enable(char *str) |
1370 | { | |
1371 | mce_disabled = -1; | |
1372 | return 1; | |
1373 | } | |
1374 | ||
a988d334 IM |
1375 | __setup("mce", mcheck_enable); |
1376 | ||
d7c3c9a6 AK |
1377 | #endif /* CONFIG_X86_OLD_MCE */ |
1378 | ||
1379 | /* | |
1380 | * Old style boot options parsing. Only for compatibility. | |
1381 | */ | |
1382 | static int __init mcheck_disable(char *str) | |
1383 | { | |
1384 | mce_disabled = 1; | |
1385 | return 1; | |
1386 | } | |
1387 | __setup("nomce", mcheck_disable); |