Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
8c566ef5 | 24 | #include <linux/ctype.h> |
e9eee03e | 25 | #include <linux/sched.h> |
0d7482e3 | 26 | #include <linux/sysfs.h> |
e9eee03e IM |
27 | #include <linux/types.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/kmod.h> | |
30 | #include <linux/poll.h> | |
31 | #include <linux/cpu.h> | |
14a02530 | 32 | #include <linux/smp.h> |
e9eee03e IM |
33 | #include <linux/fs.h> |
34 | ||
d88203d1 | 35 | #include <asm/processor.h> |
ccc3c319 AK |
36 | #include <asm/hw_irq.h> |
37 | #include <asm/apic.h> | |
e02e68d3 | 38 | #include <asm/idle.h> |
ccc3c319 | 39 | #include <asm/ipi.h> |
e9eee03e IM |
40 | #include <asm/mce.h> |
41 | #include <asm/msr.h> | |
1da177e4 | 42 | |
bd19a5e6 | 43 | #include "mce-internal.h" |
711c2e48 IM |
44 | #include "mce.h" |
45 | ||
5d727926 AK |
46 | /* Handle unconfigured int18 (should never happen) */ |
47 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
48 | { | |
49 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
50 | smp_processor_id()); | |
51 | } | |
52 | ||
53 | /* Call the installed machine check handler for this CPU setup. */ | |
54 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
55 | unexpected_machine_check; | |
04b2b1a4 AK |
56 | |
57 | int mce_disabled; | |
58 | ||
4efc0670 | 59 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 60 | |
e9eee03e | 61 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 62 | |
553f265f AK |
63 | atomic_t mce_entry; |
64 | ||
01ca79f1 AK |
65 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
66 | ||
bd78432c TH |
67 | /* |
68 | * Tolerant levels: | |
69 | * 0: always panic on uncorrected errors, log corrected errors | |
70 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
71 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
72 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
73 | */ | |
e9eee03e IM |
74 | static int tolerant = 1; |
75 | static int banks; | |
76 | static u64 *bank; | |
77 | static unsigned long notify_user; | |
78 | static int rip_msr; | |
79 | static int mce_bootlog = -1; | |
a98f0dd3 | 80 | |
e9eee03e IM |
81 | static char trigger[128]; |
82 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 83 | |
06b7a7a5 AK |
84 | static unsigned long dont_init_banks; |
85 | ||
e02e68d3 TH |
86 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
87 | ||
ee031c31 AK |
88 | /* MCA banks polled by the period polling timer for corrected events */ |
89 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
90 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
91 | }; | |
92 | ||
06b7a7a5 AK |
93 | static inline int skip_bank_init(int i) |
94 | { | |
95 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
96 | } | |
97 | ||
b5f2fa4e AK |
98 | /* Do initial initialization of a struct mce */ |
99 | void mce_setup(struct mce *m) | |
100 | { | |
101 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 102 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 103 | rdtscll(m->tsc); |
8ee08347 AK |
104 | /* We hope get_seconds stays lockless */ |
105 | m->time = get_seconds(); | |
106 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
107 | m->cpuid = cpuid_eax(1); | |
108 | #ifdef CONFIG_SMP | |
109 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
110 | #endif | |
111 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
112 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
113 | } |
114 | ||
ea149b36 AK |
115 | DEFINE_PER_CPU(struct mce, injectm); |
116 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
117 | ||
1da177e4 LT |
118 | /* |
119 | * Lockless MCE logging infrastructure. | |
120 | * This avoids deadlocks on printk locks without having to break locks. Also | |
121 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
122 | */ | |
123 | ||
231fd906 | 124 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
125 | .signature = MCE_LOG_SIGNATURE, |
126 | .len = MCE_LOG_LEN, | |
127 | .recordlen = sizeof(struct mce), | |
d88203d1 | 128 | }; |
1da177e4 LT |
129 | |
130 | void mce_log(struct mce *mce) | |
131 | { | |
132 | unsigned next, entry; | |
e9eee03e | 133 | |
1da177e4 | 134 | mce->finished = 0; |
7644143c | 135 | wmb(); |
1da177e4 LT |
136 | for (;;) { |
137 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 138 | for (;;) { |
e9eee03e IM |
139 | /* |
140 | * When the buffer fills up discard new entries. | |
141 | * Assume that the earlier errors are the more | |
142 | * interesting ones: | |
143 | */ | |
673242c1 | 144 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
145 | set_bit(MCE_OVERFLOW, |
146 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
147 | return; |
148 | } | |
e9eee03e | 149 | /* Old left over entry. Skip: */ |
673242c1 AK |
150 | if (mcelog.entry[entry].finished) { |
151 | entry++; | |
152 | continue; | |
153 | } | |
7644143c | 154 | break; |
1da177e4 | 155 | } |
1da177e4 LT |
156 | smp_rmb(); |
157 | next = entry + 1; | |
158 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
159 | break; | |
160 | } | |
161 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 162 | wmb(); |
1da177e4 | 163 | mcelog.entry[entry].finished = 1; |
7644143c | 164 | wmb(); |
1da177e4 | 165 | |
a0189c70 | 166 | mce->finished = 1; |
e02e68d3 | 167 | set_bit(0, ¬ify_user); |
1da177e4 LT |
168 | } |
169 | ||
170 | static void print_mce(struct mce *m) | |
171 | { | |
172 | printk(KERN_EMERG "\n" | |
4855170f | 173 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
174 | KERN_EMERG |
175 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
d620c67f | 176 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 177 | if (m->ip) { |
d88203d1 | 178 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 179 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 180 | m->cs, m->ip); |
1da177e4 | 181 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 182 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
183 | printk("\n"); |
184 | } | |
f6d1826d | 185 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 186 | if (m->addr) |
f6d1826d | 187 | printk("ADDR %llx ", m->addr); |
1da177e4 | 188 | if (m->misc) |
f6d1826d | 189 | printk("MISC %llx ", m->misc); |
1da177e4 | 190 | printk("\n"); |
8ee08347 AK |
191 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
192 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
193 | m->apicid); | |
4855170f | 194 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
195 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
196 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
197 | } |
198 | ||
bd19a5e6 | 199 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 200 | { |
1da177e4 | 201 | int i; |
e02e68d3 | 202 | |
d896a940 AK |
203 | bust_spinlocks(1); |
204 | console_verbose(); | |
a0189c70 | 205 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 206 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 AK |
207 | struct mce *m = &mcelog.entry[i]; |
208 | if ((m->status & MCI_STATUS_VAL) && | |
209 | !(m->status & MCI_STATUS_UC)) | |
210 | print_mce(m); | |
211 | } | |
212 | /* Now print uncorrected but with the final one last */ | |
213 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
214 | struct mce *m = &mcelog.entry[i]; | |
215 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 216 | continue; |
a0189c70 AK |
217 | if (!final || memcmp(m, final, sizeof(struct mce))) |
218 | print_mce(m); | |
1da177e4 | 219 | } |
a0189c70 AK |
220 | if (final) |
221 | print_mce(final); | |
bd19a5e6 AK |
222 | if (exp) |
223 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
e02e68d3 | 224 | panic(msg); |
d88203d1 | 225 | } |
1da177e4 | 226 | |
ea149b36 AK |
227 | /* Support code for software error injection */ |
228 | ||
229 | static int msr_to_offset(u32 msr) | |
230 | { | |
231 | unsigned bank = __get_cpu_var(injectm.bank); | |
232 | if (msr == rip_msr) | |
233 | return offsetof(struct mce, ip); | |
234 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | |
235 | return offsetof(struct mce, status); | |
236 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | |
237 | return offsetof(struct mce, addr); | |
238 | if (msr == MSR_IA32_MC0_MISC + bank*4) | |
239 | return offsetof(struct mce, misc); | |
240 | if (msr == MSR_IA32_MCG_STATUS) | |
241 | return offsetof(struct mce, mcgstatus); | |
242 | return -1; | |
243 | } | |
244 | ||
5f8c1a54 AK |
245 | /* MSR access wrappers used for error injection */ |
246 | static u64 mce_rdmsrl(u32 msr) | |
247 | { | |
248 | u64 v; | |
ea149b36 AK |
249 | if (__get_cpu_var(injectm).finished) { |
250 | int offset = msr_to_offset(msr); | |
251 | if (offset < 0) | |
252 | return 0; | |
253 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
254 | } | |
5f8c1a54 AK |
255 | rdmsrl(msr, v); |
256 | return v; | |
257 | } | |
258 | ||
259 | static void mce_wrmsrl(u32 msr, u64 v) | |
260 | { | |
ea149b36 AK |
261 | if (__get_cpu_var(injectm).finished) { |
262 | int offset = msr_to_offset(msr); | |
263 | if (offset >= 0) | |
264 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
265 | return; | |
266 | } | |
5f8c1a54 AK |
267 | wrmsrl(msr, v); |
268 | } | |
269 | ||
88ccbedd | 270 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 271 | { |
04b2b1a4 | 272 | if (mce_disabled) |
5b4408fd | 273 | return 0; |
3d1712c9 | 274 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
275 | } |
276 | ||
94ad8474 AK |
277 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
278 | { | |
279 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 280 | m->ip = regs->ip; |
94ad8474 AK |
281 | m->cs = regs->cs; |
282 | } else { | |
65ea5b03 | 283 | m->ip = 0; |
94ad8474 AK |
284 | m->cs = 0; |
285 | } | |
286 | if (rip_msr) { | |
287 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
288 | m->mcgstatus |= MCG_STATUS_EIPV; | |
5f8c1a54 | 289 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
290 | m->cs = 0; |
291 | } | |
292 | } | |
293 | ||
ccc3c319 AK |
294 | #ifdef CONFIG_X86_LOCAL_APIC |
295 | /* | |
296 | * Called after interrupts have been reenabled again | |
297 | * when a MCE happened during an interrupts off region | |
298 | * in the kernel. | |
299 | */ | |
300 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
301 | { | |
302 | ack_APIC_irq(); | |
303 | exit_idle(); | |
304 | irq_enter(); | |
305 | mce_notify_user(); | |
306 | irq_exit(); | |
307 | } | |
308 | #endif | |
309 | ||
310 | static void mce_report_event(struct pt_regs *regs) | |
311 | { | |
312 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
313 | mce_notify_user(); | |
314 | return; | |
315 | } | |
316 | ||
317 | #ifdef CONFIG_X86_LOCAL_APIC | |
318 | /* | |
319 | * Without APIC do not notify. The event will be picked | |
320 | * up eventually. | |
321 | */ | |
322 | if (!cpu_has_apic) | |
323 | return; | |
324 | ||
325 | /* | |
326 | * When interrupts are disabled we cannot use | |
327 | * kernel services safely. Trigger an self interrupt | |
328 | * through the APIC to instead do the notification | |
329 | * after interrupts are reenabled again. | |
330 | */ | |
331 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
332 | ||
333 | /* | |
334 | * Wait for idle afterwards again so that we don't leave the | |
335 | * APIC in a non idle state because the normal APIC writes | |
336 | * cannot exclude us. | |
337 | */ | |
338 | apic_wait_icr_idle(); | |
339 | #endif | |
340 | } | |
341 | ||
ca84f696 AK |
342 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
343 | ||
d88203d1 | 344 | /* |
b79109c3 AK |
345 | * Poll for corrected events or events that happened before reset. |
346 | * Those are just logged through /dev/mcelog. | |
347 | * | |
348 | * This is executed in standard interrupt context. | |
349 | */ | |
ee031c31 | 350 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
351 | { |
352 | struct mce m; | |
353 | int i; | |
354 | ||
ca84f696 AK |
355 | __get_cpu_var(mce_poll_count)++; |
356 | ||
b79109c3 AK |
357 | mce_setup(&m); |
358 | ||
5f8c1a54 | 359 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 360 | for (i = 0; i < banks; i++) { |
ee031c31 | 361 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
362 | continue; |
363 | ||
364 | m.misc = 0; | |
365 | m.addr = 0; | |
366 | m.bank = i; | |
367 | m.tsc = 0; | |
368 | ||
369 | barrier(); | |
5f8c1a54 | 370 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
b79109c3 AK |
371 | if (!(m.status & MCI_STATUS_VAL)) |
372 | continue; | |
373 | ||
374 | /* | |
375 | * Uncorrected events are handled by the exception handler | |
376 | * when it is enabled. But when the exception is disabled log | |
377 | * everything. | |
378 | * | |
379 | * TBD do the same check for MCI_STATUS_EN here? | |
380 | */ | |
381 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
382 | continue; | |
383 | ||
384 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 385 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
b79109c3 | 386 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 387 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
b79109c3 AK |
388 | |
389 | if (!(flags & MCP_TIMESTAMP)) | |
390 | m.tsc = 0; | |
391 | /* | |
392 | * Don't get the IP here because it's unlikely to | |
393 | * have anything to do with the actual error location. | |
394 | */ | |
5679af4c AK |
395 | if (!(flags & MCP_DONTLOG)) { |
396 | mce_log(&m); | |
397 | add_taint(TAINT_MACHINE_CHECK); | |
398 | } | |
b79109c3 AK |
399 | |
400 | /* | |
401 | * Clear state for this bank. | |
402 | */ | |
5f8c1a54 | 403 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 AK |
404 | } |
405 | ||
406 | /* | |
407 | * Don't clear MCG_STATUS here because it's only defined for | |
408 | * exceptions. | |
409 | */ | |
88921be3 AK |
410 | |
411 | sync_core(); | |
b79109c3 | 412 | } |
ea149b36 | 413 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 414 | |
bd19a5e6 AK |
415 | /* |
416 | * Do a quick check if any of the events requires a panic. | |
417 | * This decides if we keep the events around or clear them. | |
418 | */ | |
419 | static int mce_no_way_out(struct mce *m, char **msg) | |
420 | { | |
421 | int i; | |
422 | ||
423 | for (i = 0; i < banks; i++) { | |
424 | m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | |
425 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) | |
426 | return 1; | |
427 | } | |
428 | return 0; | |
429 | } | |
430 | ||
b79109c3 AK |
431 | /* |
432 | * The actual machine check handler. This only handles real | |
433 | * exceptions when something got corrupted coming in through int 18. | |
434 | * | |
435 | * This is executed in NMI context not subject to normal locking rules. This | |
436 | * implies that most kernel services cannot be safely used. Don't even | |
437 | * think about putting a printk in there! | |
1da177e4 | 438 | */ |
e9eee03e | 439 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
440 | { |
441 | struct mce m, panicm; | |
e9eee03e | 442 | int panicm_found = 0; |
1da177e4 | 443 | int i; |
bd78432c TH |
444 | /* |
445 | * If no_way_out gets set, there is no safe way to recover from this | |
446 | * MCE. If tolerant is cranked up, we'll try anyway. | |
447 | */ | |
448 | int no_way_out = 0; | |
449 | /* | |
450 | * If kill_it gets set, there might be a way to recover from this | |
451 | * error. | |
452 | */ | |
453 | int kill_it = 0; | |
b79109c3 | 454 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 455 | char *msg = "Unknown"; |
1da177e4 | 456 | |
553f265f AK |
457 | atomic_inc(&mce_entry); |
458 | ||
01ca79f1 AK |
459 | __get_cpu_var(mce_exception_count)++; |
460 | ||
b79109c3 | 461 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 462 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 463 | goto out; |
b79109c3 | 464 | if (!banks) |
32561696 | 465 | goto out; |
1da177e4 | 466 | |
b5f2fa4e AK |
467 | mce_setup(&m); |
468 | ||
5f8c1a54 | 469 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
bd19a5e6 | 470 | no_way_out = mce_no_way_out(&m, &msg); |
d88203d1 | 471 | |
1da177e4 LT |
472 | barrier(); |
473 | ||
474 | for (i = 0; i < banks; i++) { | |
b79109c3 | 475 | __clear_bit(i, toclear); |
0d7482e3 | 476 | if (!bank[i]) |
1da177e4 | 477 | continue; |
d88203d1 TG |
478 | |
479 | m.misc = 0; | |
1da177e4 LT |
480 | m.addr = 0; |
481 | m.bank = i; | |
1da177e4 | 482 | |
5f8c1a54 | 483 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); |
1da177e4 LT |
484 | if ((m.status & MCI_STATUS_VAL) == 0) |
485 | continue; | |
486 | ||
b79109c3 AK |
487 | /* |
488 | * Non uncorrected errors are handled by machine_check_poll | |
de8a84d8 | 489 | * Leave them alone, unless this panics. |
b79109c3 | 490 | */ |
de8a84d8 | 491 | if ((m.status & MCI_STATUS_UC) == 0 && !no_way_out) |
b79109c3 AK |
492 | continue; |
493 | ||
494 | /* | |
495 | * Set taint even when machine check was not enabled. | |
496 | */ | |
497 | add_taint(TAINT_MACHINE_CHECK); | |
498 | ||
499 | __set_bit(i, toclear); | |
500 | ||
1da177e4 | 501 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
502 | /* |
503 | * If this error was uncorrectable and there was | |
504 | * an overflow, we're in trouble. If no overflow, | |
505 | * we might get away with just killing a task. | |
506 | */ | |
bd19a5e6 | 507 | if (m.status & MCI_STATUS_UC) |
bd78432c | 508 | kill_it = 1; |
b79109c3 AK |
509 | } else { |
510 | /* | |
511 | * Machine check event was not enabled. Clear, but | |
512 | * ignore. | |
513 | */ | |
514 | continue; | |
1da177e4 LT |
515 | } |
516 | ||
517 | if (m.status & MCI_STATUS_MISCV) | |
5f8c1a54 | 518 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); |
1da177e4 | 519 | if (m.status & MCI_STATUS_ADDRV) |
5f8c1a54 | 520 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); |
1da177e4 | 521 | |
94ad8474 | 522 | mce_get_rip(&m, regs); |
b79109c3 | 523 | mce_log(&m); |
1da177e4 | 524 | |
e9eee03e IM |
525 | /* |
526 | * Did this bank cause the exception? | |
527 | * | |
528 | * Assume that the bank with uncorrectable errors did it, | |
529 | * and that there is only a single one: | |
530 | */ | |
531 | if ((m.status & MCI_STATUS_UC) && | |
532 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
533 | panicm = m; |
534 | panicm_found = 1; | |
535 | } | |
1da177e4 LT |
536 | } |
537 | ||
e9eee03e IM |
538 | /* |
539 | * If we didn't find an uncorrectable error, pick | |
540 | * the last one (shouldn't happen, just being safe). | |
541 | */ | |
1da177e4 LT |
542 | if (!panicm_found) |
543 | panicm = m; | |
bd78432c TH |
544 | |
545 | /* | |
546 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 547 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
548 | */ |
549 | if (no_way_out && tolerant < 3) | |
bd19a5e6 | 550 | mce_panic("Machine check", &panicm, msg); |
bd78432c TH |
551 | |
552 | /* | |
553 | * If the error seems to be unrecoverable, something should be | |
554 | * done. Try to kill as little as possible. If we can kill just | |
555 | * one task, do that. If the user has set the tolerance very | |
556 | * high, don't try to do anything at all. | |
557 | */ | |
558 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
559 | int user_space = 0; |
560 | ||
bd78432c TH |
561 | /* |
562 | * If the EIPV bit is set, it means the saved IP is the | |
563 | * instruction which caused the MCE. | |
564 | */ | |
565 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 566 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
567 | |
568 | /* | |
569 | * If we know that the error was in user space, send a | |
570 | * SIGBUS. Otherwise, panic if tolerance is low. | |
571 | * | |
380851bc | 572 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
573 | * risk of deadlocking. |
574 | */ | |
575 | if (user_space) { | |
380851bc | 576 | force_sig(SIGBUS, current); |
bd78432c | 577 | } else if (panic_on_oops || tolerant < 2) { |
bd19a5e6 | 578 | mce_panic("Uncorrected machine check", &panicm, msg); |
bd78432c | 579 | } |
1da177e4 LT |
580 | } |
581 | ||
e02e68d3 TH |
582 | /* notify userspace ASAP */ |
583 | set_thread_flag(TIF_MCE_NOTIFY); | |
584 | ||
ccc3c319 AK |
585 | mce_report_event(regs); |
586 | ||
bd78432c | 587 | /* the last thing we do is clear state */ |
b79109c3 AK |
588 | for (i = 0; i < banks; i++) { |
589 | if (test_bit(i, toclear)) | |
5f8c1a54 | 590 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
b79109c3 | 591 | } |
5f8c1a54 | 592 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 593 | out: |
553f265f | 594 | atomic_dec(&mce_entry); |
88921be3 | 595 | sync_core(); |
1da177e4 | 596 | } |
ea149b36 | 597 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 598 | |
15d5f839 DZ |
599 | #ifdef CONFIG_X86_MCE_INTEL |
600 | /*** | |
601 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 602 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
603 | * @status: Event status information |
604 | * | |
605 | * This function should be called by the thermal interrupt after the | |
606 | * event has been processed and the decision was made to log the event | |
607 | * further. | |
608 | * | |
609 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
610 | * and historically has been the register value of the | |
611 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
612 | */ | |
b5f2fa4e | 613 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
614 | { |
615 | struct mce m; | |
616 | ||
b5f2fa4e | 617 | mce_setup(&m); |
15d5f839 DZ |
618 | m.bank = MCE_THERMAL_BANK; |
619 | m.status = status; | |
15d5f839 DZ |
620 | mce_log(&m); |
621 | } | |
622 | #endif /* CONFIG_X86_MCE_INTEL */ | |
623 | ||
1da177e4 | 624 | /* |
8a336b0a TH |
625 | * Periodic polling timer for "silent" machine check errors. If the |
626 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
627 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 628 | */ |
1da177e4 | 629 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 630 | |
6298c512 | 631 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 632 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 633 | |
52d168e2 | 634 | static void mcheck_timer(unsigned long data) |
1da177e4 | 635 | { |
52d168e2 | 636 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 637 | int *n; |
52d168e2 AK |
638 | |
639 | WARN_ON(smp_processor_id() != data); | |
640 | ||
e9eee03e | 641 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
642 | machine_check_poll(MCP_TIMESTAMP, |
643 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 644 | } |
1da177e4 LT |
645 | |
646 | /* | |
e02e68d3 TH |
647 | * Alert userspace if needed. If we logged an MCE, reduce the |
648 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 649 | */ |
6298c512 | 650 | n = &__get_cpu_var(next_interval); |
14a02530 | 651 | if (mce_notify_user()) |
6298c512 | 652 | *n = max(*n/2, HZ/100); |
14a02530 | 653 | else |
6298c512 | 654 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 655 | |
6298c512 | 656 | t->expires = jiffies + *n; |
52d168e2 | 657 | add_timer(t); |
e02e68d3 TH |
658 | } |
659 | ||
9bd98405 AK |
660 | static void mce_do_trigger(struct work_struct *work) |
661 | { | |
662 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
663 | } | |
664 | ||
665 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
666 | ||
e02e68d3 | 667 | /* |
9bd98405 AK |
668 | * Notify the user(s) about new machine check events. |
669 | * Can be called from interrupt context, but not from machine check/NMI | |
670 | * context. | |
e02e68d3 TH |
671 | */ |
672 | int mce_notify_user(void) | |
673 | { | |
8457c84d AK |
674 | /* Not more than two messages every minute */ |
675 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
676 | ||
e02e68d3 | 677 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 678 | |
e02e68d3 | 679 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 680 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
681 | |
682 | /* | |
683 | * There is no risk of missing notifications because | |
684 | * work_pending is always cleared before the function is | |
685 | * executed. | |
686 | */ | |
687 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
688 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 689 | |
8457c84d | 690 | if (__ratelimit(&ratelimit)) |
8a336b0a | 691 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
692 | |
693 | return 1; | |
1da177e4 | 694 | } |
e02e68d3 TH |
695 | return 0; |
696 | } | |
ea149b36 | 697 | EXPORT_SYMBOL_GPL(mce_notify_user); |
8a336b0a | 698 | |
d88203d1 | 699 | /* |
1da177e4 LT |
700 | * Initialize Machine Checks for a CPU. |
701 | */ | |
0d7482e3 | 702 | static int mce_cap_init(void) |
1da177e4 | 703 | { |
0d7482e3 | 704 | unsigned b; |
e9eee03e | 705 | u64 cap; |
1da177e4 LT |
706 | |
707 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
708 | |
709 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
710 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
711 | ||
0d7482e3 AK |
712 | if (b > MAX_NR_BANKS) { |
713 | printk(KERN_WARNING | |
714 | "MCE: Using only %u machine check banks out of %u\n", | |
715 | MAX_NR_BANKS, b); | |
716 | b = MAX_NR_BANKS; | |
717 | } | |
718 | ||
719 | /* Don't support asymmetric configurations today */ | |
720 | WARN_ON(banks != 0 && b != banks); | |
721 | banks = b; | |
722 | if (!bank) { | |
723 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
724 | if (!bank) | |
725 | return -ENOMEM; | |
726 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 727 | } |
0d7482e3 | 728 | |
94ad8474 | 729 | /* Use accurate RIP reporting if available. */ |
01c6680a | 730 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 731 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 732 | |
0d7482e3 AK |
733 | return 0; |
734 | } | |
735 | ||
8be91105 | 736 | static void mce_init(void) |
0d7482e3 | 737 | { |
e9eee03e | 738 | mce_banks_t all_banks; |
0d7482e3 AK |
739 | u64 cap; |
740 | int i; | |
741 | ||
b79109c3 AK |
742 | /* |
743 | * Log the machine checks left over from the previous reset. | |
744 | */ | |
ee031c31 | 745 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 746 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
747 | |
748 | set_in_cr4(X86_CR4_MCE); | |
749 | ||
0d7482e3 | 750 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
751 | if (cap & MCG_CTL_P) |
752 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
753 | ||
754 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
755 | if (skip_bank_init(i)) |
756 | continue; | |
0d7482e3 | 757 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 758 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 759 | } |
1da177e4 LT |
760 | } |
761 | ||
762 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 763 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 764 | { |
1da177e4 | 765 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 766 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
767 | if (c->x86 == 15 && banks > 4) { |
768 | /* | |
769 | * disable GART TBL walk error reporting, which | |
770 | * trips off incorrectly with the IOMMU & 3ware | |
771 | * & Cerberus: | |
772 | */ | |
0d7482e3 | 773 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
774 | } |
775 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
776 | /* | |
777 | * Lots of broken BIOS around that don't clear them | |
778 | * by default and leave crap in there. Don't log: | |
779 | */ | |
911f6a7b | 780 | mce_bootlog = 0; |
e9eee03e | 781 | } |
2e6f694f AK |
782 | /* |
783 | * Various K7s with broken bank 0 around. Always disable | |
784 | * by default. | |
785 | */ | |
786 | if (c->x86 == 6) | |
787 | bank[0] = 0; | |
1da177e4 | 788 | } |
e583538f | 789 | |
06b7a7a5 AK |
790 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
791 | /* | |
792 | * SDM documents that on family 6 bank 0 should not be written | |
793 | * because it aliases to another special BIOS controlled | |
794 | * register. | |
795 | * But it's not aliased anymore on model 0x1a+ | |
796 | * Don't ignore bank 0 completely because there could be a | |
797 | * valid event later, merely don't write CTL0. | |
798 | */ | |
799 | ||
800 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
801 | __set_bit(0, &dont_init_banks); | |
802 | } | |
d88203d1 | 803 | } |
1da177e4 | 804 | |
4efc0670 AK |
805 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
806 | { | |
807 | if (c->x86 != 5) | |
808 | return; | |
809 | switch (c->x86_vendor) { | |
810 | case X86_VENDOR_INTEL: | |
811 | if (mce_p5_enabled()) | |
812 | intel_p5_mcheck_init(c); | |
813 | break; | |
814 | case X86_VENDOR_CENTAUR: | |
815 | winchip_mcheck_init(c); | |
816 | break; | |
817 | } | |
818 | } | |
819 | ||
cc3ca220 | 820 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
821 | { |
822 | switch (c->x86_vendor) { | |
823 | case X86_VENDOR_INTEL: | |
824 | mce_intel_feature_init(c); | |
825 | break; | |
89b831ef JS |
826 | case X86_VENDOR_AMD: |
827 | mce_amd_feature_init(c); | |
828 | break; | |
1da177e4 LT |
829 | default: |
830 | break; | |
831 | } | |
832 | } | |
833 | ||
52d168e2 AK |
834 | static void mce_init_timer(void) |
835 | { | |
836 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 837 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 838 | |
6298c512 AK |
839 | *n = check_interval * HZ; |
840 | if (!*n) | |
52d168e2 AK |
841 | return; |
842 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 843 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
844 | add_timer(t); |
845 | } | |
846 | ||
d88203d1 | 847 | /* |
1da177e4 | 848 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 849 | * Must be called with preempt off: |
1da177e4 | 850 | */ |
e6982c67 | 851 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 852 | { |
4efc0670 AK |
853 | if (mce_disabled) |
854 | return; | |
855 | ||
856 | mce_ancient_init(c); | |
857 | ||
5b4408fd | 858 | if (!mce_available(c)) |
1da177e4 LT |
859 | return; |
860 | ||
0d7482e3 | 861 | if (mce_cap_init() < 0) { |
04b2b1a4 | 862 | mce_disabled = 1; |
0d7482e3 AK |
863 | return; |
864 | } | |
865 | mce_cpu_quirks(c); | |
866 | ||
5d727926 AK |
867 | machine_check_vector = do_machine_check; |
868 | ||
8be91105 | 869 | mce_init(); |
1da177e4 | 870 | mce_cpu_features(c); |
52d168e2 | 871 | mce_init_timer(); |
1da177e4 LT |
872 | } |
873 | ||
874 | /* | |
875 | * Character device to read and clear the MCE log. | |
876 | */ | |
877 | ||
f528e7ba | 878 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
879 | static int open_count; /* #times opened */ |
880 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
881 | |
882 | static int mce_open(struct inode *inode, struct file *file) | |
883 | { | |
884 | spin_lock(&mce_state_lock); | |
885 | ||
886 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
887 | spin_unlock(&mce_state_lock); | |
e9eee03e | 888 | |
f528e7ba TH |
889 | return -EBUSY; |
890 | } | |
891 | ||
892 | if (file->f_flags & O_EXCL) | |
893 | open_exclu = 1; | |
894 | open_count++; | |
895 | ||
896 | spin_unlock(&mce_state_lock); | |
897 | ||
bd78432c | 898 | return nonseekable_open(inode, file); |
f528e7ba TH |
899 | } |
900 | ||
901 | static int mce_release(struct inode *inode, struct file *file) | |
902 | { | |
903 | spin_lock(&mce_state_lock); | |
904 | ||
905 | open_count--; | |
906 | open_exclu = 0; | |
907 | ||
908 | spin_unlock(&mce_state_lock); | |
909 | ||
910 | return 0; | |
911 | } | |
912 | ||
d88203d1 TG |
913 | static void collect_tscs(void *data) |
914 | { | |
1da177e4 | 915 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 916 | |
1da177e4 | 917 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 918 | } |
1da177e4 | 919 | |
e9eee03e IM |
920 | static DEFINE_MUTEX(mce_read_mutex); |
921 | ||
d88203d1 TG |
922 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
923 | loff_t *off) | |
1da177e4 | 924 | { |
e9eee03e | 925 | char __user *buf = ubuf; |
f0de53bb | 926 | unsigned long *cpu_tsc; |
ef41df43 | 927 | unsigned prev, next; |
1da177e4 LT |
928 | int i, err; |
929 | ||
6bca67f9 | 930 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
931 | if (!cpu_tsc) |
932 | return -ENOMEM; | |
933 | ||
8c8b8859 | 934 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
935 | next = rcu_dereference(mcelog.next); |
936 | ||
937 | /* Only supports full reads right now */ | |
d88203d1 | 938 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 939 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 940 | kfree(cpu_tsc); |
e9eee03e | 941 | |
1da177e4 LT |
942 | return -EINVAL; |
943 | } | |
944 | ||
945 | err = 0; | |
ef41df43 HY |
946 | prev = 0; |
947 | do { | |
948 | for (i = prev; i < next; i++) { | |
949 | unsigned long start = jiffies; | |
950 | ||
951 | while (!mcelog.entry[i].finished) { | |
952 | if (time_after_eq(jiffies, start + 2)) { | |
953 | memset(mcelog.entry + i, 0, | |
954 | sizeof(struct mce)); | |
955 | goto timeout; | |
956 | } | |
957 | cpu_relax(); | |
673242c1 | 958 | } |
ef41df43 HY |
959 | smp_rmb(); |
960 | err |= copy_to_user(buf, mcelog.entry + i, | |
961 | sizeof(struct mce)); | |
962 | buf += sizeof(struct mce); | |
963 | timeout: | |
964 | ; | |
673242c1 | 965 | } |
1da177e4 | 966 | |
ef41df43 HY |
967 | memset(mcelog.entry + prev, 0, |
968 | (next - prev) * sizeof(struct mce)); | |
969 | prev = next; | |
970 | next = cmpxchg(&mcelog.next, prev, 0); | |
971 | } while (next != prev); | |
1da177e4 | 972 | |
b2b18660 | 973 | synchronize_sched(); |
1da177e4 | 974 | |
d88203d1 TG |
975 | /* |
976 | * Collect entries that were still getting written before the | |
977 | * synchronize. | |
978 | */ | |
15c8b6c1 | 979 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 980 | |
d88203d1 TG |
981 | for (i = next; i < MCE_LOG_LEN; i++) { |
982 | if (mcelog.entry[i].finished && | |
983 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
984 | err |= copy_to_user(buf, mcelog.entry+i, | |
985 | sizeof(struct mce)); | |
1da177e4 LT |
986 | smp_rmb(); |
987 | buf += sizeof(struct mce); | |
988 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
989 | } | |
d88203d1 | 990 | } |
8c8b8859 | 991 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 992 | kfree(cpu_tsc); |
e9eee03e | 993 | |
d88203d1 | 994 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
995 | } |
996 | ||
e02e68d3 TH |
997 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
998 | { | |
999 | poll_wait(file, &mce_wait, wait); | |
1000 | if (rcu_dereference(mcelog.next)) | |
1001 | return POLLIN | POLLRDNORM; | |
1002 | return 0; | |
1003 | } | |
1004 | ||
c68461b6 | 1005 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1006 | { |
1007 | int __user *p = (int __user *)arg; | |
d88203d1 | 1008 | |
1da177e4 | 1009 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1010 | return -EPERM; |
e9eee03e | 1011 | |
1da177e4 | 1012 | switch (cmd) { |
d88203d1 | 1013 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1014 | return put_user(sizeof(struct mce), p); |
1015 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1016 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1017 | case MCE_GETCLEAR_FLAGS: { |
1018 | unsigned flags; | |
d88203d1 TG |
1019 | |
1020 | do { | |
1da177e4 | 1021 | flags = mcelog.flags; |
d88203d1 | 1022 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1023 | |
d88203d1 | 1024 | return put_user(flags, p); |
1da177e4 LT |
1025 | } |
1026 | default: | |
d88203d1 TG |
1027 | return -ENOTTY; |
1028 | } | |
1da177e4 LT |
1029 | } |
1030 | ||
a1ff41bf | 1031 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1032 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1033 | .open = mce_open, |
1034 | .release = mce_release, | |
1035 | .read = mce_read, | |
1036 | .poll = mce_poll, | |
1037 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1038 | }; |
ea149b36 | 1039 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1040 | |
1041 | static struct miscdevice mce_log_device = { | |
1042 | MISC_MCELOG_MINOR, | |
1043 | "mcelog", | |
1044 | &mce_chrdev_ops, | |
1045 | }; | |
1046 | ||
13503fa9 HS |
1047 | /* |
1048 | * mce=off disables machine check | |
1049 | * mce=TOLERANCELEVEL (number, see above) | |
1050 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
1051 | * mce=nobootlog Don't log MCEs from before booting. | |
1052 | */ | |
1da177e4 LT |
1053 | static int __init mcheck_enable(char *str) |
1054 | { | |
4efc0670 AK |
1055 | if (*str == 0) |
1056 | enable_p5_mce(); | |
1057 | if (*str == '=') | |
1058 | str++; | |
1da177e4 | 1059 | if (!strcmp(str, "off")) |
04b2b1a4 | 1060 | mce_disabled = 1; |
13503fa9 HS |
1061 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1062 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
1063 | else if (isdigit(str[0])) |
1064 | get_option(&str, &tolerant); | |
13503fa9 | 1065 | else { |
4efc0670 | 1066 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1067 | str); |
1068 | return 0; | |
1069 | } | |
9b41046c | 1070 | return 1; |
1da177e4 | 1071 | } |
4efc0670 | 1072 | __setup("mce", mcheck_enable); |
1da177e4 | 1073 | |
d88203d1 | 1074 | /* |
1da177e4 | 1075 | * Sysfs support |
d88203d1 | 1076 | */ |
1da177e4 | 1077 | |
973a2dd1 AK |
1078 | /* |
1079 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1080 | * them later. | |
1081 | */ | |
1082 | static int mce_disable(void) | |
1083 | { | |
1084 | int i; | |
1085 | ||
06b7a7a5 AK |
1086 | for (i = 0; i < banks; i++) { |
1087 | if (!skip_bank_init(i)) | |
1088 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1089 | } | |
973a2dd1 AK |
1090 | return 0; |
1091 | } | |
1092 | ||
1093 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1094 | { | |
1095 | return mce_disable(); | |
1096 | } | |
1097 | ||
1098 | static int mce_shutdown(struct sys_device *dev) | |
1099 | { | |
1100 | return mce_disable(); | |
1101 | } | |
1102 | ||
e9eee03e IM |
1103 | /* |
1104 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1105 | * Only one CPU is active at this time, the others get re-added later using | |
1106 | * CPU hotplug: | |
1107 | */ | |
1da177e4 LT |
1108 | static int mce_resume(struct sys_device *dev) |
1109 | { | |
8be91105 | 1110 | mce_init(); |
6ec68bff | 1111 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1112 | |
1da177e4 LT |
1113 | return 0; |
1114 | } | |
1115 | ||
52d168e2 AK |
1116 | static void mce_cpu_restart(void *data) |
1117 | { | |
1118 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1119 | if (mce_available(¤t_cpu_data)) | |
8be91105 | 1120 | mce_init(); |
52d168e2 AK |
1121 | mce_init_timer(); |
1122 | } | |
1123 | ||
1da177e4 | 1124 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1125 | static void mce_restart(void) |
1126 | { | |
52d168e2 | 1127 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1128 | } |
1129 | ||
1130 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
1131 | .suspend = mce_suspend, |
1132 | .shutdown = mce_shutdown, | |
1133 | .resume = mce_resume, | |
1134 | .name = "machinecheck", | |
1da177e4 LT |
1135 | }; |
1136 | ||
cb491fca | 1137 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1138 | |
1139 | __cpuinitdata | |
1140 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1141 | |
0d7482e3 AK |
1142 | static struct sysdev_attribute *bank_attrs; |
1143 | ||
1144 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1145 | char *buf) | |
1146 | { | |
1147 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1148 | |
f6d1826d | 1149 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1150 | } |
1151 | ||
1152 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1153 | const char *buf, size_t size) |
0d7482e3 | 1154 | { |
9319cec8 | 1155 | u64 new; |
e9eee03e | 1156 | |
9319cec8 | 1157 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1158 | return -EINVAL; |
e9eee03e | 1159 | |
0d7482e3 AK |
1160 | bank[attr - bank_attrs] = new; |
1161 | mce_restart(); | |
e9eee03e | 1162 | |
9319cec8 | 1163 | return size; |
0d7482e3 | 1164 | } |
a98f0dd3 | 1165 | |
e9eee03e IM |
1166 | static ssize_t |
1167 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1168 | { |
1169 | strcpy(buf, trigger); | |
1170 | strcat(buf, "\n"); | |
1171 | return strlen(trigger) + 1; | |
1172 | } | |
1173 | ||
4a0b2b4d | 1174 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1175 | const char *buf, size_t siz) |
a98f0dd3 AK |
1176 | { |
1177 | char *p; | |
1178 | int len; | |
e9eee03e | 1179 | |
a98f0dd3 AK |
1180 | strncpy(trigger, buf, sizeof(trigger)); |
1181 | trigger[sizeof(trigger)-1] = 0; | |
1182 | len = strlen(trigger); | |
1183 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1184 | |
1185 | if (*p) | |
1186 | *p = 0; | |
1187 | ||
a98f0dd3 AK |
1188 | return len; |
1189 | } | |
1190 | ||
b56f642d AK |
1191 | static ssize_t store_int_with_restart(struct sys_device *s, |
1192 | struct sysdev_attribute *attr, | |
1193 | const char *buf, size_t size) | |
1194 | { | |
1195 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1196 | mce_restart(); | |
1197 | return ret; | |
1198 | } | |
1199 | ||
a98f0dd3 | 1200 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1201 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e | 1202 | |
b56f642d AK |
1203 | static struct sysdev_ext_attribute attr_check_interval = { |
1204 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1205 | store_int_with_restart), | |
1206 | &check_interval | |
1207 | }; | |
e9eee03e | 1208 | |
cb491fca | 1209 | static struct sysdev_attribute *mce_attrs[] = { |
b56f642d | 1210 | &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger, |
a98f0dd3 AK |
1211 | NULL |
1212 | }; | |
1da177e4 | 1213 | |
cb491fca | 1214 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1215 | |
e9eee03e | 1216 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1217 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1218 | { |
1219 | int err; | |
73ca5358 | 1220 | int i; |
92cb7612 | 1221 | |
90367556 | 1222 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1223 | return -EIO; |
1224 | ||
cb491fca IM |
1225 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1226 | per_cpu(mce_dev, cpu).id = cpu; | |
1227 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1228 | |
cb491fca | 1229 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1230 | if (err) |
1231 | return err; | |
1232 | ||
cb491fca IM |
1233 | for (i = 0; mce_attrs[i]; i++) { |
1234 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1235 | if (err) |
1236 | goto error; | |
1237 | } | |
0d7482e3 | 1238 | for (i = 0; i < banks; i++) { |
cb491fca | 1239 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1240 | &bank_attrs[i]); |
1241 | if (err) | |
1242 | goto error2; | |
1243 | } | |
cb491fca | 1244 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1245 | |
d435d862 | 1246 | return 0; |
0d7482e3 | 1247 | error2: |
cb491fca IM |
1248 | while (--i >= 0) |
1249 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1250 | error: |
cb491fca IM |
1251 | while (--i >= 0) |
1252 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1253 | ||
1254 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1255 | |
91c6d400 AK |
1256 | return err; |
1257 | } | |
1258 | ||
2d9cd6c2 | 1259 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1260 | { |
73ca5358 SL |
1261 | int i; |
1262 | ||
cb491fca | 1263 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1264 | return; |
1265 | ||
cb491fca IM |
1266 | for (i = 0; mce_attrs[i]; i++) |
1267 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1268 | ||
0d7482e3 | 1269 | for (i = 0; i < banks; i++) |
cb491fca IM |
1270 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1271 | ||
1272 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1273 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1274 | } |
91c6d400 | 1275 | |
d6b75584 | 1276 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1277 | static void mce_disable_cpu(void *h) |
d6b75584 | 1278 | { |
88ccbedd | 1279 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1280 | int i; |
d6b75584 AK |
1281 | |
1282 | if (!mce_available(¤t_cpu_data)) | |
1283 | return; | |
88ccbedd AK |
1284 | if (!(action & CPU_TASKS_FROZEN)) |
1285 | cmci_clear(); | |
06b7a7a5 AK |
1286 | for (i = 0; i < banks; i++) { |
1287 | if (!skip_bank_init(i)) | |
1288 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1289 | } | |
d6b75584 AK |
1290 | } |
1291 | ||
ec5b3d32 | 1292 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1293 | { |
88ccbedd | 1294 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1295 | int i; |
d6b75584 AK |
1296 | |
1297 | if (!mce_available(¤t_cpu_data)) | |
1298 | return; | |
e9eee03e | 1299 | |
88ccbedd AK |
1300 | if (!(action & CPU_TASKS_FROZEN)) |
1301 | cmci_reenable(); | |
06b7a7a5 AK |
1302 | for (i = 0; i < banks; i++) { |
1303 | if (!skip_bank_init(i)) | |
1304 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1305 | } | |
d6b75584 AK |
1306 | } |
1307 | ||
91c6d400 | 1308 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1309 | static int __cpuinit |
1310 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1311 | { |
1312 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1313 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1314 | |
1315 | switch (action) { | |
bae19fe0 AH |
1316 | case CPU_ONLINE: |
1317 | case CPU_ONLINE_FROZEN: | |
1318 | mce_create_device(cpu); | |
8735728e RW |
1319 | if (threshold_cpu_callback) |
1320 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1321 | break; |
91c6d400 | 1322 | case CPU_DEAD: |
8bb78442 | 1323 | case CPU_DEAD_FROZEN: |
8735728e RW |
1324 | if (threshold_cpu_callback) |
1325 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1326 | mce_remove_device(cpu); |
1327 | break; | |
52d168e2 AK |
1328 | case CPU_DOWN_PREPARE: |
1329 | case CPU_DOWN_PREPARE_FROZEN: | |
1330 | del_timer_sync(t); | |
88ccbedd | 1331 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1332 | break; |
1333 | case CPU_DOWN_FAILED: | |
1334 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1335 | t->expires = round_jiffies(jiffies + |
1336 | __get_cpu_var(next_interval)); | |
52d168e2 | 1337 | add_timer_on(t, cpu); |
88ccbedd AK |
1338 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1339 | break; | |
1340 | case CPU_POST_DEAD: | |
1341 | /* intentionally ignoring frozen here */ | |
1342 | cmci_rediscover(cpu); | |
52d168e2 | 1343 | break; |
91c6d400 | 1344 | } |
bae19fe0 | 1345 | return NOTIFY_OK; |
91c6d400 AK |
1346 | } |
1347 | ||
1e35669d | 1348 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1349 | .notifier_call = mce_cpu_callback, |
1350 | }; | |
1351 | ||
0d7482e3 AK |
1352 | static __init int mce_init_banks(void) |
1353 | { | |
1354 | int i; | |
1355 | ||
1356 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1357 | GFP_KERNEL); | |
1358 | if (!bank_attrs) | |
1359 | return -ENOMEM; | |
1360 | ||
1361 | for (i = 0; i < banks; i++) { | |
1362 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1363 | |
1364 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1365 | if (!a->attr.name) |
1366 | goto nomem; | |
e9eee03e IM |
1367 | |
1368 | a->attr.mode = 0644; | |
1369 | a->show = show_bank; | |
1370 | a->store = set_bank; | |
0d7482e3 AK |
1371 | } |
1372 | return 0; | |
1373 | ||
1374 | nomem: | |
1375 | while (--i >= 0) | |
1376 | kfree(bank_attrs[i].attr.name); | |
1377 | kfree(bank_attrs); | |
1378 | bank_attrs = NULL; | |
e9eee03e | 1379 | |
0d7482e3 AK |
1380 | return -ENOMEM; |
1381 | } | |
1382 | ||
91c6d400 AK |
1383 | static __init int mce_init_device(void) |
1384 | { | |
1385 | int err; | |
1386 | int i = 0; | |
1387 | ||
1da177e4 LT |
1388 | if (!mce_available(&boot_cpu_data)) |
1389 | return -EIO; | |
0d7482e3 | 1390 | |
cb491fca | 1391 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1392 | |
0d7482e3 AK |
1393 | err = mce_init_banks(); |
1394 | if (err) | |
1395 | return err; | |
1396 | ||
1da177e4 | 1397 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1398 | if (err) |
1399 | return err; | |
91c6d400 AK |
1400 | |
1401 | for_each_online_cpu(i) { | |
d435d862 AM |
1402 | err = mce_create_device(i); |
1403 | if (err) | |
1404 | return err; | |
91c6d400 AK |
1405 | } |
1406 | ||
be6b5a35 | 1407 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1408 | misc_register(&mce_log_device); |
e9eee03e | 1409 | |
1da177e4 | 1410 | return err; |
1da177e4 | 1411 | } |
91c6d400 | 1412 | |
1da177e4 | 1413 | device_initcall(mce_init_device); |
a988d334 | 1414 | |
4efc0670 | 1415 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1416 | |
a988d334 IM |
1417 | int nr_mce_banks; |
1418 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1419 | ||
a988d334 IM |
1420 | /* This has to be run for each processor */ |
1421 | void mcheck_init(struct cpuinfo_x86 *c) | |
1422 | { | |
1423 | if (mce_disabled == 1) | |
1424 | return; | |
1425 | ||
1426 | switch (c->x86_vendor) { | |
1427 | case X86_VENDOR_AMD: | |
1428 | amd_mcheck_init(c); | |
1429 | break; | |
1430 | ||
1431 | case X86_VENDOR_INTEL: | |
1432 | if (c->x86 == 5) | |
1433 | intel_p5_mcheck_init(c); | |
1434 | if (c->x86 == 6) | |
1435 | intel_p6_mcheck_init(c); | |
1436 | if (c->x86 == 15) | |
1437 | intel_p4_mcheck_init(c); | |
1438 | break; | |
1439 | ||
1440 | case X86_VENDOR_CENTAUR: | |
1441 | if (c->x86 == 5) | |
1442 | winchip_mcheck_init(c); | |
1443 | break; | |
1444 | ||
1445 | default: | |
1446 | break; | |
1447 | } | |
b659294b | 1448 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1449 | } |
1450 | ||
a988d334 IM |
1451 | static int __init mcheck_enable(char *str) |
1452 | { | |
1453 | mce_disabled = -1; | |
1454 | return 1; | |
1455 | } | |
1456 | ||
a988d334 IM |
1457 | __setup("mce", mcheck_enable); |
1458 | ||
d7c3c9a6 AK |
1459 | #endif /* CONFIG_X86_OLD_MCE */ |
1460 | ||
1461 | /* | |
1462 | * Old style boot options parsing. Only for compatibility. | |
1463 | */ | |
1464 | static int __init mcheck_disable(char *str) | |
1465 | { | |
1466 | mce_disabled = 1; | |
1467 | return 1; | |
1468 | } | |
1469 | __setup("nomce", mcheck_disable); |