Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
13 | #include <linux/ratelimit.h> | |
14 | #include <linux/kallsyms.h> | |
15 | #include <linux/rcupdate.h> | |
38c4c97c | 16 | #include <linux/smp_lock.h> |
e9eee03e IM |
17 | #include <linux/kobject.h> |
18 | #include <linux/kdebug.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/percpu.h> | |
1da177e4 | 21 | #include <linux/string.h> |
1da177e4 | 22 | #include <linux/sysdev.h> |
8c566ef5 | 23 | #include <linux/ctype.h> |
e9eee03e | 24 | #include <linux/sched.h> |
0d7482e3 | 25 | #include <linux/sysfs.h> |
e9eee03e IM |
26 | #include <linux/types.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/kmod.h> | |
29 | #include <linux/poll.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/fs.h> | |
32 | ||
d88203d1 | 33 | #include <asm/processor.h> |
1da177e4 | 34 | #include <asm/uaccess.h> |
e02e68d3 | 35 | #include <asm/idle.h> |
e9eee03e IM |
36 | #include <asm/mce.h> |
37 | #include <asm/msr.h> | |
38 | #include <asm/smp.h> | |
1da177e4 | 39 | |
711c2e48 IM |
40 | #include "mce.h" |
41 | ||
5d727926 AK |
42 | /* Handle unconfigured int18 (should never happen) */ |
43 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
44 | { | |
45 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
46 | smp_processor_id()); | |
47 | } | |
48 | ||
49 | /* Call the installed machine check handler for this CPU setup. */ | |
50 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
51 | unexpected_machine_check; | |
04b2b1a4 AK |
52 | |
53 | int mce_disabled; | |
54 | ||
4efc0670 | 55 | #ifdef CONFIG_X86_NEW_MCE |
711c2e48 | 56 | |
e9eee03e | 57 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 58 | |
553f265f AK |
59 | atomic_t mce_entry; |
60 | ||
bd78432c TH |
61 | /* |
62 | * Tolerant levels: | |
63 | * 0: always panic on uncorrected errors, log corrected errors | |
64 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
65 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
66 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
67 | */ | |
e9eee03e IM |
68 | static int tolerant = 1; |
69 | static int banks; | |
70 | static u64 *bank; | |
71 | static unsigned long notify_user; | |
72 | static int rip_msr; | |
73 | static int mce_bootlog = -1; | |
74 | static atomic_t mce_events; | |
a98f0dd3 | 75 | |
e9eee03e IM |
76 | static char trigger[128]; |
77 | static char *trigger_argv[2] = { trigger, NULL }; | |
1da177e4 | 78 | |
06b7a7a5 AK |
79 | static unsigned long dont_init_banks; |
80 | ||
e02e68d3 TH |
81 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
82 | ||
ee031c31 AK |
83 | /* MCA banks polled by the period polling timer for corrected events */ |
84 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
85 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
86 | }; | |
87 | ||
06b7a7a5 AK |
88 | static inline int skip_bank_init(int i) |
89 | { | |
90 | return i < BITS_PER_LONG && test_bit(i, &dont_init_banks); | |
91 | } | |
92 | ||
b5f2fa4e AK |
93 | /* Do initial initialization of a struct mce */ |
94 | void mce_setup(struct mce *m) | |
95 | { | |
96 | memset(m, 0, sizeof(struct mce)); | |
97 | m->cpu = smp_processor_id(); | |
98 | rdtscll(m->tsc); | |
99 | } | |
100 | ||
1da177e4 LT |
101 | /* |
102 | * Lockless MCE logging infrastructure. | |
103 | * This avoids deadlocks on printk locks without having to break locks. Also | |
104 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
105 | */ | |
106 | ||
231fd906 | 107 | static struct mce_log mcelog = { |
1da177e4 LT |
108 | MCE_LOG_SIGNATURE, |
109 | MCE_LOG_LEN, | |
d88203d1 | 110 | }; |
1da177e4 LT |
111 | |
112 | void mce_log(struct mce *mce) | |
113 | { | |
114 | unsigned next, entry; | |
e9eee03e | 115 | |
a98f0dd3 | 116 | atomic_inc(&mce_events); |
1da177e4 | 117 | mce->finished = 0; |
7644143c | 118 | wmb(); |
1da177e4 LT |
119 | for (;;) { |
120 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 121 | for (;;) { |
e9eee03e IM |
122 | /* |
123 | * When the buffer fills up discard new entries. | |
124 | * Assume that the earlier errors are the more | |
125 | * interesting ones: | |
126 | */ | |
673242c1 | 127 | if (entry >= MCE_LOG_LEN) { |
53756d37 | 128 | set_bit(MCE_OVERFLOW, (unsigned long *)&mcelog.flags); |
673242c1 AK |
129 | return; |
130 | } | |
e9eee03e | 131 | /* Old left over entry. Skip: */ |
673242c1 AK |
132 | if (mcelog.entry[entry].finished) { |
133 | entry++; | |
134 | continue; | |
135 | } | |
7644143c | 136 | break; |
1da177e4 | 137 | } |
1da177e4 LT |
138 | smp_rmb(); |
139 | next = entry + 1; | |
140 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
141 | break; | |
142 | } | |
143 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 144 | wmb(); |
1da177e4 | 145 | mcelog.entry[entry].finished = 1; |
7644143c | 146 | wmb(); |
1da177e4 | 147 | |
e02e68d3 | 148 | set_bit(0, ¬ify_user); |
1da177e4 LT |
149 | } |
150 | ||
151 | static void print_mce(struct mce *m) | |
152 | { | |
153 | printk(KERN_EMERG "\n" | |
4855170f | 154 | KERN_EMERG "HARDWARE ERROR\n" |
1da177e4 LT |
155 | KERN_EMERG |
156 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", | |
157 | m->cpu, m->mcgstatus, m->bank, m->status); | |
65ea5b03 | 158 | if (m->ip) { |
d88203d1 | 159 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 160 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 161 | m->cs, m->ip); |
1da177e4 | 162 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 163 | print_symbol("{%s}", m->ip); |
1da177e4 LT |
164 | printk("\n"); |
165 | } | |
f6d1826d | 166 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 167 | if (m->addr) |
f6d1826d | 168 | printk("ADDR %llx ", m->addr); |
1da177e4 | 169 | if (m->misc) |
f6d1826d | 170 | printk("MISC %llx ", m->misc); |
1da177e4 | 171 | printk("\n"); |
4855170f | 172 | printk(KERN_EMERG "This is not a software problem!\n"); |
d88203d1 TG |
173 | printk(KERN_EMERG "Run through mcelog --ascii to decode " |
174 | "and contact your hardware vendor\n"); | |
1da177e4 LT |
175 | } |
176 | ||
3cde5c8c | 177 | static void mce_panic(char *msg, struct mce *backup, u64 start) |
d88203d1 | 178 | { |
1da177e4 | 179 | int i; |
e02e68d3 | 180 | |
d896a940 AK |
181 | bust_spinlocks(1); |
182 | console_verbose(); | |
1da177e4 | 183 | for (i = 0; i < MCE_LOG_LEN; i++) { |
3cde5c8c | 184 | u64 tsc = mcelog.entry[i].tsc; |
d88203d1 | 185 | |
3cde5c8c | 186 | if ((s64)(tsc - start) < 0) |
1da177e4 | 187 | continue; |
d88203d1 | 188 | print_mce(&mcelog.entry[i]); |
1da177e4 LT |
189 | if (backup && mcelog.entry[i].tsc == backup->tsc) |
190 | backup = NULL; | |
191 | } | |
192 | if (backup) | |
193 | print_mce(backup); | |
e02e68d3 | 194 | panic(msg); |
d88203d1 | 195 | } |
1da177e4 | 196 | |
88ccbedd | 197 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 198 | { |
04b2b1a4 | 199 | if (mce_disabled) |
5b4408fd | 200 | return 0; |
3d1712c9 | 201 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
202 | } |
203 | ||
94ad8474 AK |
204 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
205 | { | |
206 | if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) { | |
65ea5b03 | 207 | m->ip = regs->ip; |
94ad8474 AK |
208 | m->cs = regs->cs; |
209 | } else { | |
65ea5b03 | 210 | m->ip = 0; |
94ad8474 AK |
211 | m->cs = 0; |
212 | } | |
213 | if (rip_msr) { | |
214 | /* Assume the RIP in the MSR is exact. Is this true? */ | |
215 | m->mcgstatus |= MCG_STATUS_EIPV; | |
65ea5b03 | 216 | rdmsrl(rip_msr, m->ip); |
94ad8474 AK |
217 | m->cs = 0; |
218 | } | |
219 | } | |
220 | ||
d88203d1 | 221 | /* |
b79109c3 AK |
222 | * Poll for corrected events or events that happened before reset. |
223 | * Those are just logged through /dev/mcelog. | |
224 | * | |
225 | * This is executed in standard interrupt context. | |
226 | */ | |
ee031c31 | 227 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
228 | { |
229 | struct mce m; | |
230 | int i; | |
231 | ||
232 | mce_setup(&m); | |
233 | ||
234 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); | |
235 | for (i = 0; i < banks; i++) { | |
ee031c31 | 236 | if (!bank[i] || !test_bit(i, *b)) |
b79109c3 AK |
237 | continue; |
238 | ||
239 | m.misc = 0; | |
240 | m.addr = 0; | |
241 | m.bank = i; | |
242 | m.tsc = 0; | |
243 | ||
244 | barrier(); | |
245 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
246 | if (!(m.status & MCI_STATUS_VAL)) | |
247 | continue; | |
248 | ||
249 | /* | |
250 | * Uncorrected events are handled by the exception handler | |
251 | * when it is enabled. But when the exception is disabled log | |
252 | * everything. | |
253 | * | |
254 | * TBD do the same check for MCI_STATUS_EN here? | |
255 | */ | |
256 | if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC)) | |
257 | continue; | |
258 | ||
259 | if (m.status & MCI_STATUS_MISCV) | |
260 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
261 | if (m.status & MCI_STATUS_ADDRV) | |
262 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
263 | ||
264 | if (!(flags & MCP_TIMESTAMP)) | |
265 | m.tsc = 0; | |
266 | /* | |
267 | * Don't get the IP here because it's unlikely to | |
268 | * have anything to do with the actual error location. | |
269 | */ | |
5679af4c AK |
270 | if (!(flags & MCP_DONTLOG)) { |
271 | mce_log(&m); | |
272 | add_taint(TAINT_MACHINE_CHECK); | |
273 | } | |
b79109c3 AK |
274 | |
275 | /* | |
276 | * Clear state for this bank. | |
277 | */ | |
278 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
279 | } | |
280 | ||
281 | /* | |
282 | * Don't clear MCG_STATUS here because it's only defined for | |
283 | * exceptions. | |
284 | */ | |
285 | } | |
286 | ||
287 | /* | |
288 | * The actual machine check handler. This only handles real | |
289 | * exceptions when something got corrupted coming in through int 18. | |
290 | * | |
291 | * This is executed in NMI context not subject to normal locking rules. This | |
292 | * implies that most kernel services cannot be safely used. Don't even | |
293 | * think about putting a printk in there! | |
1da177e4 | 294 | */ |
e9eee03e | 295 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 LT |
296 | { |
297 | struct mce m, panicm; | |
e9eee03e | 298 | int panicm_found = 0; |
1da177e4 LT |
299 | u64 mcestart = 0; |
300 | int i; | |
bd78432c TH |
301 | /* |
302 | * If no_way_out gets set, there is no safe way to recover from this | |
303 | * MCE. If tolerant is cranked up, we'll try anyway. | |
304 | */ | |
305 | int no_way_out = 0; | |
306 | /* | |
307 | * If kill_it gets set, there might be a way to recover from this | |
308 | * error. | |
309 | */ | |
310 | int kill_it = 0; | |
b79109c3 | 311 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
1da177e4 | 312 | |
553f265f AK |
313 | atomic_inc(&mce_entry); |
314 | ||
b79109c3 | 315 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 316 | 18, SIGKILL) == NOTIFY_STOP) |
b79109c3 AK |
317 | goto out2; |
318 | if (!banks) | |
553f265f | 319 | goto out2; |
1da177e4 | 320 | |
b5f2fa4e AK |
321 | mce_setup(&m); |
322 | ||
1da177e4 | 323 | rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
e9eee03e | 324 | |
bd78432c | 325 | /* if the restart IP is not valid, we're done for */ |
1da177e4 | 326 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) |
bd78432c | 327 | no_way_out = 1; |
d88203d1 | 328 | |
1da177e4 LT |
329 | rdtscll(mcestart); |
330 | barrier(); | |
331 | ||
332 | for (i = 0; i < banks; i++) { | |
b79109c3 | 333 | __clear_bit(i, toclear); |
0d7482e3 | 334 | if (!bank[i]) |
1da177e4 | 335 | continue; |
d88203d1 TG |
336 | |
337 | m.misc = 0; | |
1da177e4 LT |
338 | m.addr = 0; |
339 | m.bank = i; | |
1da177e4 LT |
340 | |
341 | rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); | |
342 | if ((m.status & MCI_STATUS_VAL) == 0) | |
343 | continue; | |
344 | ||
b79109c3 AK |
345 | /* |
346 | * Non uncorrected errors are handled by machine_check_poll | |
347 | * Leave them alone. | |
348 | */ | |
349 | if ((m.status & MCI_STATUS_UC) == 0) | |
350 | continue; | |
351 | ||
352 | /* | |
353 | * Set taint even when machine check was not enabled. | |
354 | */ | |
355 | add_taint(TAINT_MACHINE_CHECK); | |
356 | ||
357 | __set_bit(i, toclear); | |
358 | ||
1da177e4 | 359 | if (m.status & MCI_STATUS_EN) { |
bd78432c TH |
360 | /* if PCC was set, there's no way out */ |
361 | no_way_out |= !!(m.status & MCI_STATUS_PCC); | |
362 | /* | |
363 | * If this error was uncorrectable and there was | |
364 | * an overflow, we're in trouble. If no overflow, | |
365 | * we might get away with just killing a task. | |
366 | */ | |
367 | if (m.status & MCI_STATUS_UC) { | |
368 | if (tolerant < 1 || m.status & MCI_STATUS_OVER) | |
369 | no_way_out = 1; | |
370 | kill_it = 1; | |
371 | } | |
b79109c3 AK |
372 | } else { |
373 | /* | |
374 | * Machine check event was not enabled. Clear, but | |
375 | * ignore. | |
376 | */ | |
377 | continue; | |
1da177e4 LT |
378 | } |
379 | ||
380 | if (m.status & MCI_STATUS_MISCV) | |
381 | rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); | |
382 | if (m.status & MCI_STATUS_ADDRV) | |
383 | rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); | |
384 | ||
94ad8474 | 385 | mce_get_rip(&m, regs); |
b79109c3 | 386 | mce_log(&m); |
1da177e4 | 387 | |
e9eee03e IM |
388 | /* |
389 | * Did this bank cause the exception? | |
390 | * | |
391 | * Assume that the bank with uncorrectable errors did it, | |
392 | * and that there is only a single one: | |
393 | */ | |
394 | if ((m.status & MCI_STATUS_UC) && | |
395 | (m.status & MCI_STATUS_EN)) { | |
1da177e4 LT |
396 | panicm = m; |
397 | panicm_found = 1; | |
398 | } | |
1da177e4 LT |
399 | } |
400 | ||
e9eee03e IM |
401 | /* |
402 | * If we didn't find an uncorrectable error, pick | |
403 | * the last one (shouldn't happen, just being safe). | |
404 | */ | |
1da177e4 LT |
405 | if (!panicm_found) |
406 | panicm = m; | |
bd78432c TH |
407 | |
408 | /* | |
409 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 410 | * has not set tolerant to an insane level, give up and die. |
bd78432c TH |
411 | */ |
412 | if (no_way_out && tolerant < 3) | |
1da177e4 | 413 | mce_panic("Machine check", &panicm, mcestart); |
bd78432c TH |
414 | |
415 | /* | |
416 | * If the error seems to be unrecoverable, something should be | |
417 | * done. Try to kill as little as possible. If we can kill just | |
418 | * one task, do that. If the user has set the tolerance very | |
419 | * high, don't try to do anything at all. | |
420 | */ | |
421 | if (kill_it && tolerant < 3) { | |
1da177e4 LT |
422 | int user_space = 0; |
423 | ||
bd78432c TH |
424 | /* |
425 | * If the EIPV bit is set, it means the saved IP is the | |
426 | * instruction which caused the MCE. | |
427 | */ | |
428 | if (m.mcgstatus & MCG_STATUS_EIPV) | |
65ea5b03 | 429 | user_space = panicm.ip && (panicm.cs & 3); |
bd78432c TH |
430 | |
431 | /* | |
432 | * If we know that the error was in user space, send a | |
433 | * SIGBUS. Otherwise, panic if tolerance is low. | |
434 | * | |
380851bc | 435 | * force_sig() takes an awful lot of locks and has a slight |
bd78432c TH |
436 | * risk of deadlocking. |
437 | */ | |
438 | if (user_space) { | |
380851bc | 439 | force_sig(SIGBUS, current); |
bd78432c TH |
440 | } else if (panic_on_oops || tolerant < 2) { |
441 | mce_panic("Uncorrected machine check", | |
442 | &panicm, mcestart); | |
443 | } | |
1da177e4 LT |
444 | } |
445 | ||
e02e68d3 TH |
446 | /* notify userspace ASAP */ |
447 | set_thread_flag(TIF_MCE_NOTIFY); | |
448 | ||
bd78432c | 449 | /* the last thing we do is clear state */ |
b79109c3 AK |
450 | for (i = 0; i < banks; i++) { |
451 | if (test_bit(i, toclear)) | |
452 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | |
453 | } | |
1da177e4 | 454 | wrmsrl(MSR_IA32_MCG_STATUS, 0); |
553f265f AK |
455 | out2: |
456 | atomic_dec(&mce_entry); | |
1da177e4 LT |
457 | } |
458 | ||
15d5f839 DZ |
459 | #ifdef CONFIG_X86_MCE_INTEL |
460 | /*** | |
461 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 462 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
463 | * @status: Event status information |
464 | * | |
465 | * This function should be called by the thermal interrupt after the | |
466 | * event has been processed and the decision was made to log the event | |
467 | * further. | |
468 | * | |
469 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
470 | * and historically has been the register value of the | |
471 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
472 | */ | |
b5f2fa4e | 473 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
474 | { |
475 | struct mce m; | |
476 | ||
b5f2fa4e | 477 | mce_setup(&m); |
15d5f839 DZ |
478 | m.bank = MCE_THERMAL_BANK; |
479 | m.status = status; | |
15d5f839 DZ |
480 | mce_log(&m); |
481 | } | |
482 | #endif /* CONFIG_X86_MCE_INTEL */ | |
483 | ||
1da177e4 | 484 | /* |
8a336b0a TH |
485 | * Periodic polling timer for "silent" machine check errors. If the |
486 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
487 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 488 | */ |
1da177e4 | 489 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 490 | |
6298c512 | 491 | static DEFINE_PER_CPU(int, next_interval); /* in jiffies */ |
52d168e2 | 492 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 493 | |
52d168e2 | 494 | static void mcheck_timer(unsigned long data) |
1da177e4 | 495 | { |
52d168e2 | 496 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 497 | int *n; |
52d168e2 AK |
498 | |
499 | WARN_ON(smp_processor_id() != data); | |
500 | ||
e9eee03e | 501 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
502 | machine_check_poll(MCP_TIMESTAMP, |
503 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 504 | } |
1da177e4 LT |
505 | |
506 | /* | |
e02e68d3 TH |
507 | * Alert userspace if needed. If we logged an MCE, reduce the |
508 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 509 | */ |
6298c512 | 510 | n = &__get_cpu_var(next_interval); |
e02e68d3 | 511 | if (mce_notify_user()) { |
6298c512 | 512 | *n = max(*n/2, HZ/100); |
e02e68d3 | 513 | } else { |
6298c512 | 514 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 TH |
515 | } |
516 | ||
6298c512 | 517 | t->expires = jiffies + *n; |
52d168e2 | 518 | add_timer(t); |
e02e68d3 TH |
519 | } |
520 | ||
9bd98405 AK |
521 | static void mce_do_trigger(struct work_struct *work) |
522 | { | |
523 | call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT); | |
524 | } | |
525 | ||
526 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
527 | ||
e02e68d3 | 528 | /* |
9bd98405 AK |
529 | * Notify the user(s) about new machine check events. |
530 | * Can be called from interrupt context, but not from machine check/NMI | |
531 | * context. | |
e02e68d3 TH |
532 | */ |
533 | int mce_notify_user(void) | |
534 | { | |
8457c84d AK |
535 | /* Not more than two messages every minute */ |
536 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
537 | ||
e02e68d3 | 538 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 539 | |
e02e68d3 | 540 | if (test_and_clear_bit(0, ¬ify_user)) { |
e02e68d3 | 541 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
542 | |
543 | /* | |
544 | * There is no risk of missing notifications because | |
545 | * work_pending is always cleared before the function is | |
546 | * executed. | |
547 | */ | |
548 | if (trigger[0] && !work_pending(&mce_trigger_work)) | |
549 | schedule_work(&mce_trigger_work); | |
e02e68d3 | 550 | |
8457c84d | 551 | if (__ratelimit(&ratelimit)) |
8a336b0a | 552 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
553 | |
554 | return 1; | |
1da177e4 | 555 | } |
e02e68d3 TH |
556 | return 0; |
557 | } | |
8a336b0a | 558 | |
d88203d1 | 559 | /* |
1da177e4 LT |
560 | * Initialize Machine Checks for a CPU. |
561 | */ | |
0d7482e3 | 562 | static int mce_cap_init(void) |
1da177e4 | 563 | { |
0d7482e3 | 564 | unsigned b; |
e9eee03e | 565 | u64 cap; |
1da177e4 LT |
566 | |
567 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
568 | |
569 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
570 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
571 | ||
0d7482e3 AK |
572 | if (b > MAX_NR_BANKS) { |
573 | printk(KERN_WARNING | |
574 | "MCE: Using only %u machine check banks out of %u\n", | |
575 | MAX_NR_BANKS, b); | |
576 | b = MAX_NR_BANKS; | |
577 | } | |
578 | ||
579 | /* Don't support asymmetric configurations today */ | |
580 | WARN_ON(banks != 0 && b != banks); | |
581 | banks = b; | |
582 | if (!bank) { | |
583 | bank = kmalloc(banks * sizeof(u64), GFP_KERNEL); | |
584 | if (!bank) | |
585 | return -ENOMEM; | |
586 | memset(bank, 0xff, banks * sizeof(u64)); | |
1da177e4 | 587 | } |
0d7482e3 | 588 | |
94ad8474 | 589 | /* Use accurate RIP reporting if available. */ |
01c6680a | 590 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 591 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 592 | |
0d7482e3 AK |
593 | return 0; |
594 | } | |
595 | ||
596 | static void mce_init(void *dummy) | |
597 | { | |
e9eee03e | 598 | mce_banks_t all_banks; |
0d7482e3 AK |
599 | u64 cap; |
600 | int i; | |
601 | ||
b79109c3 AK |
602 | /* |
603 | * Log the machine checks left over from the previous reset. | |
604 | */ | |
ee031c31 | 605 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 606 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
607 | |
608 | set_in_cr4(X86_CR4_MCE); | |
609 | ||
0d7482e3 | 610 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
611 | if (cap & MCG_CTL_P) |
612 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
613 | ||
614 | for (i = 0; i < banks; i++) { | |
06b7a7a5 AK |
615 | if (skip_bank_init(i)) |
616 | continue; | |
0d7482e3 | 617 | wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]); |
1da177e4 | 618 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); |
d88203d1 | 619 | } |
1da177e4 LT |
620 | } |
621 | ||
622 | /* Add per CPU specific workarounds here */ | |
ec5b3d32 | 623 | static void mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 624 | { |
1da177e4 | 625 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 626 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
627 | if (c->x86 == 15 && banks > 4) { |
628 | /* | |
629 | * disable GART TBL walk error reporting, which | |
630 | * trips off incorrectly with the IOMMU & 3ware | |
631 | * & Cerberus: | |
632 | */ | |
0d7482e3 | 633 | clear_bit(10, (unsigned long *)&bank[4]); |
e9eee03e IM |
634 | } |
635 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
636 | /* | |
637 | * Lots of broken BIOS around that don't clear them | |
638 | * by default and leave crap in there. Don't log: | |
639 | */ | |
911f6a7b | 640 | mce_bootlog = 0; |
e9eee03e | 641 | } |
2e6f694f AK |
642 | /* |
643 | * Various K7s with broken bank 0 around. Always disable | |
644 | * by default. | |
645 | */ | |
646 | if (c->x86 == 6) | |
647 | bank[0] = 0; | |
1da177e4 | 648 | } |
e583538f | 649 | |
06b7a7a5 AK |
650 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
651 | /* | |
652 | * SDM documents that on family 6 bank 0 should not be written | |
653 | * because it aliases to another special BIOS controlled | |
654 | * register. | |
655 | * But it's not aliased anymore on model 0x1a+ | |
656 | * Don't ignore bank 0 completely because there could be a | |
657 | * valid event later, merely don't write CTL0. | |
658 | */ | |
659 | ||
660 | if (c->x86 == 6 && c->x86_model < 0x1A) | |
661 | __set_bit(0, &dont_init_banks); | |
662 | } | |
d88203d1 | 663 | } |
1da177e4 | 664 | |
4efc0670 AK |
665 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
666 | { | |
667 | if (c->x86 != 5) | |
668 | return; | |
669 | switch (c->x86_vendor) { | |
670 | case X86_VENDOR_INTEL: | |
671 | if (mce_p5_enabled()) | |
672 | intel_p5_mcheck_init(c); | |
673 | break; | |
674 | case X86_VENDOR_CENTAUR: | |
675 | winchip_mcheck_init(c); | |
676 | break; | |
677 | } | |
678 | } | |
679 | ||
cc3ca220 | 680 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
681 | { |
682 | switch (c->x86_vendor) { | |
683 | case X86_VENDOR_INTEL: | |
684 | mce_intel_feature_init(c); | |
685 | break; | |
89b831ef JS |
686 | case X86_VENDOR_AMD: |
687 | mce_amd_feature_init(c); | |
688 | break; | |
1da177e4 LT |
689 | default: |
690 | break; | |
691 | } | |
692 | } | |
693 | ||
52d168e2 AK |
694 | static void mce_init_timer(void) |
695 | { | |
696 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
6298c512 | 697 | int *n = &__get_cpu_var(next_interval); |
52d168e2 | 698 | |
6298c512 AK |
699 | *n = check_interval * HZ; |
700 | if (!*n) | |
52d168e2 AK |
701 | return; |
702 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 703 | t->expires = round_jiffies(jiffies + *n); |
52d168e2 AK |
704 | add_timer(t); |
705 | } | |
706 | ||
d88203d1 | 707 | /* |
1da177e4 | 708 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 709 | * Must be called with preempt off: |
1da177e4 | 710 | */ |
e6982c67 | 711 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 712 | { |
4efc0670 AK |
713 | if (mce_disabled) |
714 | return; | |
715 | ||
716 | mce_ancient_init(c); | |
717 | ||
5b4408fd | 718 | if (!mce_available(c)) |
1da177e4 LT |
719 | return; |
720 | ||
0d7482e3 | 721 | if (mce_cap_init() < 0) { |
04b2b1a4 | 722 | mce_disabled = 1; |
0d7482e3 AK |
723 | return; |
724 | } | |
725 | mce_cpu_quirks(c); | |
726 | ||
5d727926 AK |
727 | machine_check_vector = do_machine_check; |
728 | ||
1da177e4 LT |
729 | mce_init(NULL); |
730 | mce_cpu_features(c); | |
52d168e2 | 731 | mce_init_timer(); |
1da177e4 LT |
732 | } |
733 | ||
734 | /* | |
735 | * Character device to read and clear the MCE log. | |
736 | */ | |
737 | ||
f528e7ba | 738 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
739 | static int open_count; /* #times opened */ |
740 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
741 | |
742 | static int mce_open(struct inode *inode, struct file *file) | |
743 | { | |
38c4c97c | 744 | lock_kernel(); |
f528e7ba TH |
745 | spin_lock(&mce_state_lock); |
746 | ||
747 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
748 | spin_unlock(&mce_state_lock); | |
38c4c97c | 749 | unlock_kernel(); |
e9eee03e | 750 | |
f528e7ba TH |
751 | return -EBUSY; |
752 | } | |
753 | ||
754 | if (file->f_flags & O_EXCL) | |
755 | open_exclu = 1; | |
756 | open_count++; | |
757 | ||
758 | spin_unlock(&mce_state_lock); | |
38c4c97c | 759 | unlock_kernel(); |
f528e7ba | 760 | |
bd78432c | 761 | return nonseekable_open(inode, file); |
f528e7ba TH |
762 | } |
763 | ||
764 | static int mce_release(struct inode *inode, struct file *file) | |
765 | { | |
766 | spin_lock(&mce_state_lock); | |
767 | ||
768 | open_count--; | |
769 | open_exclu = 0; | |
770 | ||
771 | spin_unlock(&mce_state_lock); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
d88203d1 TG |
776 | static void collect_tscs(void *data) |
777 | { | |
1da177e4 | 778 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 779 | |
1da177e4 | 780 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 781 | } |
1da177e4 | 782 | |
e9eee03e IM |
783 | static DEFINE_MUTEX(mce_read_mutex); |
784 | ||
d88203d1 TG |
785 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
786 | loff_t *off) | |
1da177e4 | 787 | { |
e9eee03e | 788 | char __user *buf = ubuf; |
f0de53bb | 789 | unsigned long *cpu_tsc; |
ef41df43 | 790 | unsigned prev, next; |
1da177e4 LT |
791 | int i, err; |
792 | ||
6bca67f9 | 793 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
794 | if (!cpu_tsc) |
795 | return -ENOMEM; | |
796 | ||
8c8b8859 | 797 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
798 | next = rcu_dereference(mcelog.next); |
799 | ||
800 | /* Only supports full reads right now */ | |
d88203d1 | 801 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 802 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 803 | kfree(cpu_tsc); |
e9eee03e | 804 | |
1da177e4 LT |
805 | return -EINVAL; |
806 | } | |
807 | ||
808 | err = 0; | |
ef41df43 HY |
809 | prev = 0; |
810 | do { | |
811 | for (i = prev; i < next; i++) { | |
812 | unsigned long start = jiffies; | |
813 | ||
814 | while (!mcelog.entry[i].finished) { | |
815 | if (time_after_eq(jiffies, start + 2)) { | |
816 | memset(mcelog.entry + i, 0, | |
817 | sizeof(struct mce)); | |
818 | goto timeout; | |
819 | } | |
820 | cpu_relax(); | |
673242c1 | 821 | } |
ef41df43 HY |
822 | smp_rmb(); |
823 | err |= copy_to_user(buf, mcelog.entry + i, | |
824 | sizeof(struct mce)); | |
825 | buf += sizeof(struct mce); | |
826 | timeout: | |
827 | ; | |
673242c1 | 828 | } |
1da177e4 | 829 | |
ef41df43 HY |
830 | memset(mcelog.entry + prev, 0, |
831 | (next - prev) * sizeof(struct mce)); | |
832 | prev = next; | |
833 | next = cmpxchg(&mcelog.next, prev, 0); | |
834 | } while (next != prev); | |
1da177e4 | 835 | |
b2b18660 | 836 | synchronize_sched(); |
1da177e4 | 837 | |
d88203d1 TG |
838 | /* |
839 | * Collect entries that were still getting written before the | |
840 | * synchronize. | |
841 | */ | |
15c8b6c1 | 842 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 843 | |
d88203d1 TG |
844 | for (i = next; i < MCE_LOG_LEN; i++) { |
845 | if (mcelog.entry[i].finished && | |
846 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
847 | err |= copy_to_user(buf, mcelog.entry+i, | |
848 | sizeof(struct mce)); | |
1da177e4 LT |
849 | smp_rmb(); |
850 | buf += sizeof(struct mce); | |
851 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
852 | } | |
d88203d1 | 853 | } |
8c8b8859 | 854 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 855 | kfree(cpu_tsc); |
e9eee03e | 856 | |
d88203d1 | 857 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
858 | } |
859 | ||
e02e68d3 TH |
860 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
861 | { | |
862 | poll_wait(file, &mce_wait, wait); | |
863 | if (rcu_dereference(mcelog.next)) | |
864 | return POLLIN | POLLRDNORM; | |
865 | return 0; | |
866 | } | |
867 | ||
c68461b6 | 868 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
869 | { |
870 | int __user *p = (int __user *)arg; | |
d88203d1 | 871 | |
1da177e4 | 872 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 873 | return -EPERM; |
e9eee03e | 874 | |
1da177e4 | 875 | switch (cmd) { |
d88203d1 | 876 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
877 | return put_user(sizeof(struct mce), p); |
878 | case MCE_GET_LOG_LEN: | |
d88203d1 | 879 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
880 | case MCE_GETCLEAR_FLAGS: { |
881 | unsigned flags; | |
d88203d1 TG |
882 | |
883 | do { | |
1da177e4 | 884 | flags = mcelog.flags; |
d88203d1 | 885 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 886 | |
d88203d1 | 887 | return put_user(flags, p); |
1da177e4 LT |
888 | } |
889 | default: | |
d88203d1 TG |
890 | return -ENOTTY; |
891 | } | |
1da177e4 LT |
892 | } |
893 | ||
5dfe4c96 | 894 | static const struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
895 | .open = mce_open, |
896 | .release = mce_release, | |
897 | .read = mce_read, | |
898 | .poll = mce_poll, | |
899 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 LT |
900 | }; |
901 | ||
902 | static struct miscdevice mce_log_device = { | |
903 | MISC_MCELOG_MINOR, | |
904 | "mcelog", | |
905 | &mce_chrdev_ops, | |
906 | }; | |
907 | ||
13503fa9 HS |
908 | /* |
909 | * mce=off disables machine check | |
910 | * mce=TOLERANCELEVEL (number, see above) | |
911 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. | |
912 | * mce=nobootlog Don't log MCEs from before booting. | |
913 | */ | |
1da177e4 LT |
914 | static int __init mcheck_enable(char *str) |
915 | { | |
4efc0670 AK |
916 | if (*str == 0) |
917 | enable_p5_mce(); | |
918 | if (*str == '=') | |
919 | str++; | |
1da177e4 | 920 | if (!strcmp(str, "off")) |
04b2b1a4 | 921 | mce_disabled = 1; |
13503fa9 HS |
922 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
923 | mce_bootlog = (str[0] == 'b'); | |
8c566ef5 AK |
924 | else if (isdigit(str[0])) |
925 | get_option(&str, &tolerant); | |
13503fa9 | 926 | else { |
4efc0670 | 927 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
928 | str); |
929 | return 0; | |
930 | } | |
9b41046c | 931 | return 1; |
1da177e4 | 932 | } |
4efc0670 | 933 | __setup("mce", mcheck_enable); |
1da177e4 | 934 | |
d88203d1 | 935 | /* |
1da177e4 | 936 | * Sysfs support |
d88203d1 | 937 | */ |
1da177e4 | 938 | |
973a2dd1 AK |
939 | /* |
940 | * Disable machine checks on suspend and shutdown. We can't really handle | |
941 | * them later. | |
942 | */ | |
943 | static int mce_disable(void) | |
944 | { | |
945 | int i; | |
946 | ||
06b7a7a5 AK |
947 | for (i = 0; i < banks; i++) { |
948 | if (!skip_bank_init(i)) | |
949 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
950 | } | |
973a2dd1 AK |
951 | return 0; |
952 | } | |
953 | ||
954 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
955 | { | |
956 | return mce_disable(); | |
957 | } | |
958 | ||
959 | static int mce_shutdown(struct sys_device *dev) | |
960 | { | |
961 | return mce_disable(); | |
962 | } | |
963 | ||
e9eee03e IM |
964 | /* |
965 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
966 | * Only one CPU is active at this time, the others get re-added later using | |
967 | * CPU hotplug: | |
968 | */ | |
1da177e4 LT |
969 | static int mce_resume(struct sys_device *dev) |
970 | { | |
413588c7 | 971 | mce_init(NULL); |
6ec68bff | 972 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 973 | |
1da177e4 LT |
974 | return 0; |
975 | } | |
976 | ||
52d168e2 AK |
977 | static void mce_cpu_restart(void *data) |
978 | { | |
979 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
980 | if (mce_available(¤t_cpu_data)) | |
981 | mce_init(NULL); | |
982 | mce_init_timer(); | |
983 | } | |
984 | ||
1da177e4 | 985 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
986 | static void mce_restart(void) |
987 | { | |
52d168e2 | 988 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
989 | } |
990 | ||
991 | static struct sysdev_class mce_sysclass = { | |
e9eee03e IM |
992 | .suspend = mce_suspend, |
993 | .shutdown = mce_shutdown, | |
994 | .resume = mce_resume, | |
995 | .name = "machinecheck", | |
1da177e4 LT |
996 | }; |
997 | ||
cb491fca | 998 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
999 | |
1000 | __cpuinitdata | |
1001 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 LT |
1002 | |
1003 | /* Why are there no generic functions for this? */ | |
1004 | #define ACCESSOR(name, var, start) \ | |
4a0b2b4d AK |
1005 | static ssize_t show_ ## name(struct sys_device *s, \ |
1006 | struct sysdev_attribute *attr, \ | |
1007 | char *buf) { \ | |
3cde5c8c | 1008 | return sprintf(buf, "%Lx\n", (u64)var); \ |
d88203d1 | 1009 | } \ |
4a0b2b4d AK |
1010 | static ssize_t set_ ## name(struct sys_device *s, \ |
1011 | struct sysdev_attribute *attr, \ | |
1012 | const char *buf, size_t siz) { \ | |
d88203d1 | 1013 | char *end; \ |
3cde5c8c | 1014 | u64 new = simple_strtoull(buf, &end, 0); \ |
e9eee03e IM |
1015 | \ |
1016 | if (end == buf) \ | |
1017 | return -EINVAL; \ | |
d88203d1 TG |
1018 | var = new; \ |
1019 | start; \ | |
e9eee03e | 1020 | \ |
d88203d1 TG |
1021 | return end-buf; \ |
1022 | } \ | |
1da177e4 LT |
1023 | static SYSDEV_ATTR(name, 0644, show_ ## name, set_ ## name); |
1024 | ||
0d7482e3 AK |
1025 | static struct sysdev_attribute *bank_attrs; |
1026 | ||
1027 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1028 | char *buf) | |
1029 | { | |
1030 | u64 b = bank[attr - bank_attrs]; | |
e9eee03e | 1031 | |
f6d1826d | 1032 | return sprintf(buf, "%llx\n", b); |
0d7482e3 AK |
1033 | } |
1034 | ||
1035 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1036 | const char *buf, size_t siz) | |
1037 | { | |
1038 | char *end; | |
1039 | u64 new = simple_strtoull(buf, &end, 0); | |
e9eee03e | 1040 | |
0d7482e3 AK |
1041 | if (end == buf) |
1042 | return -EINVAL; | |
e9eee03e | 1043 | |
0d7482e3 AK |
1044 | bank[attr - bank_attrs] = new; |
1045 | mce_restart(); | |
e9eee03e | 1046 | |
0d7482e3 AK |
1047 | return end-buf; |
1048 | } | |
a98f0dd3 | 1049 | |
e9eee03e IM |
1050 | static ssize_t |
1051 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 AK |
1052 | { |
1053 | strcpy(buf, trigger); | |
1054 | strcat(buf, "\n"); | |
1055 | return strlen(trigger) + 1; | |
1056 | } | |
1057 | ||
4a0b2b4d | 1058 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1059 | const char *buf, size_t siz) |
a98f0dd3 AK |
1060 | { |
1061 | char *p; | |
1062 | int len; | |
e9eee03e | 1063 | |
a98f0dd3 AK |
1064 | strncpy(trigger, buf, sizeof(trigger)); |
1065 | trigger[sizeof(trigger)-1] = 0; | |
1066 | len = strlen(trigger); | |
1067 | p = strchr(trigger, '\n'); | |
e9eee03e IM |
1068 | |
1069 | if (*p) | |
1070 | *p = 0; | |
1071 | ||
a98f0dd3 AK |
1072 | return len; |
1073 | } | |
1074 | ||
1075 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); | |
d95d62c0 | 1076 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
e9eee03e IM |
1077 | |
1078 | ACCESSOR(check_interval, check_interval, mce_restart()) | |
1079 | ||
cb491fca | 1080 | static struct sysdev_attribute *mce_attrs[] = { |
d95d62c0 | 1081 | &attr_tolerant.attr, &attr_check_interval, &attr_trigger, |
a98f0dd3 AK |
1082 | NULL |
1083 | }; | |
1da177e4 | 1084 | |
cb491fca | 1085 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1086 | |
e9eee03e | 1087 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1088 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1089 | { |
1090 | int err; | |
73ca5358 | 1091 | int i; |
92cb7612 | 1092 | |
90367556 | 1093 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1094 | return -EIO; |
1095 | ||
cb491fca IM |
1096 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1097 | per_cpu(mce_dev, cpu).id = cpu; | |
1098 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1099 | |
cb491fca | 1100 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1101 | if (err) |
1102 | return err; | |
1103 | ||
cb491fca IM |
1104 | for (i = 0; mce_attrs[i]; i++) { |
1105 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1106 | if (err) |
1107 | goto error; | |
1108 | } | |
0d7482e3 | 1109 | for (i = 0; i < banks; i++) { |
cb491fca | 1110 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
0d7482e3 AK |
1111 | &bank_attrs[i]); |
1112 | if (err) | |
1113 | goto error2; | |
1114 | } | |
cb491fca | 1115 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1116 | |
d435d862 | 1117 | return 0; |
0d7482e3 | 1118 | error2: |
cb491fca IM |
1119 | while (--i >= 0) |
1120 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); | |
d435d862 | 1121 | error: |
cb491fca IM |
1122 | while (--i >= 0) |
1123 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1124 | ||
1125 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1126 | |
91c6d400 AK |
1127 | return err; |
1128 | } | |
1129 | ||
2d9cd6c2 | 1130 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1131 | { |
73ca5358 SL |
1132 | int i; |
1133 | ||
cb491fca | 1134 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1135 | return; |
1136 | ||
cb491fca IM |
1137 | for (i = 0; mce_attrs[i]; i++) |
1138 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1139 | ||
0d7482e3 | 1140 | for (i = 0; i < banks; i++) |
cb491fca IM |
1141 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]); |
1142 | ||
1143 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1144 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1145 | } |
91c6d400 | 1146 | |
d6b75584 | 1147 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1148 | static void mce_disable_cpu(void *h) |
d6b75584 | 1149 | { |
88ccbedd | 1150 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1151 | int i; |
d6b75584 AK |
1152 | |
1153 | if (!mce_available(¤t_cpu_data)) | |
1154 | return; | |
88ccbedd AK |
1155 | if (!(action & CPU_TASKS_FROZEN)) |
1156 | cmci_clear(); | |
06b7a7a5 AK |
1157 | for (i = 0; i < banks; i++) { |
1158 | if (!skip_bank_init(i)) | |
1159 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | |
1160 | } | |
d6b75584 AK |
1161 | } |
1162 | ||
ec5b3d32 | 1163 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1164 | { |
88ccbedd | 1165 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1166 | int i; |
d6b75584 AK |
1167 | |
1168 | if (!mce_available(¤t_cpu_data)) | |
1169 | return; | |
e9eee03e | 1170 | |
88ccbedd AK |
1171 | if (!(action & CPU_TASKS_FROZEN)) |
1172 | cmci_reenable(); | |
06b7a7a5 AK |
1173 | for (i = 0; i < banks; i++) { |
1174 | if (!skip_bank_init(i)) | |
1175 | wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]); | |
1176 | } | |
d6b75584 AK |
1177 | } |
1178 | ||
91c6d400 | 1179 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1180 | static int __cpuinit |
1181 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1182 | { |
1183 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1184 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1185 | |
1186 | switch (action) { | |
bae19fe0 AH |
1187 | case CPU_ONLINE: |
1188 | case CPU_ONLINE_FROZEN: | |
1189 | mce_create_device(cpu); | |
8735728e RW |
1190 | if (threshold_cpu_callback) |
1191 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1192 | break; |
91c6d400 | 1193 | case CPU_DEAD: |
8bb78442 | 1194 | case CPU_DEAD_FROZEN: |
8735728e RW |
1195 | if (threshold_cpu_callback) |
1196 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1197 | mce_remove_device(cpu); |
1198 | break; | |
52d168e2 AK |
1199 | case CPU_DOWN_PREPARE: |
1200 | case CPU_DOWN_PREPARE_FROZEN: | |
1201 | del_timer_sync(t); | |
88ccbedd | 1202 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1203 | break; |
1204 | case CPU_DOWN_FAILED: | |
1205 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 AK |
1206 | t->expires = round_jiffies(jiffies + |
1207 | __get_cpu_var(next_interval)); | |
52d168e2 | 1208 | add_timer_on(t, cpu); |
88ccbedd AK |
1209 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1210 | break; | |
1211 | case CPU_POST_DEAD: | |
1212 | /* intentionally ignoring frozen here */ | |
1213 | cmci_rediscover(cpu); | |
52d168e2 | 1214 | break; |
91c6d400 | 1215 | } |
bae19fe0 | 1216 | return NOTIFY_OK; |
91c6d400 AK |
1217 | } |
1218 | ||
1e35669d | 1219 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1220 | .notifier_call = mce_cpu_callback, |
1221 | }; | |
1222 | ||
0d7482e3 AK |
1223 | static __init int mce_init_banks(void) |
1224 | { | |
1225 | int i; | |
1226 | ||
1227 | bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks, | |
1228 | GFP_KERNEL); | |
1229 | if (!bank_attrs) | |
1230 | return -ENOMEM; | |
1231 | ||
1232 | for (i = 0; i < banks; i++) { | |
1233 | struct sysdev_attribute *a = &bank_attrs[i]; | |
e9eee03e IM |
1234 | |
1235 | a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i); | |
0d7482e3 AK |
1236 | if (!a->attr.name) |
1237 | goto nomem; | |
e9eee03e IM |
1238 | |
1239 | a->attr.mode = 0644; | |
1240 | a->show = show_bank; | |
1241 | a->store = set_bank; | |
0d7482e3 AK |
1242 | } |
1243 | return 0; | |
1244 | ||
1245 | nomem: | |
1246 | while (--i >= 0) | |
1247 | kfree(bank_attrs[i].attr.name); | |
1248 | kfree(bank_attrs); | |
1249 | bank_attrs = NULL; | |
e9eee03e | 1250 | |
0d7482e3 AK |
1251 | return -ENOMEM; |
1252 | } | |
1253 | ||
91c6d400 AK |
1254 | static __init int mce_init_device(void) |
1255 | { | |
1256 | int err; | |
1257 | int i = 0; | |
1258 | ||
1da177e4 LT |
1259 | if (!mce_available(&boot_cpu_data)) |
1260 | return -EIO; | |
0d7482e3 | 1261 | |
cb491fca | 1262 | alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 1263 | |
0d7482e3 AK |
1264 | err = mce_init_banks(); |
1265 | if (err) | |
1266 | return err; | |
1267 | ||
1da177e4 | 1268 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
1269 | if (err) |
1270 | return err; | |
91c6d400 AK |
1271 | |
1272 | for_each_online_cpu(i) { | |
d435d862 AM |
1273 | err = mce_create_device(i); |
1274 | if (err) | |
1275 | return err; | |
91c6d400 AK |
1276 | } |
1277 | ||
be6b5a35 | 1278 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 1279 | misc_register(&mce_log_device); |
e9eee03e | 1280 | |
1da177e4 | 1281 | return err; |
1da177e4 | 1282 | } |
91c6d400 | 1283 | |
1da177e4 | 1284 | device_initcall(mce_init_device); |
a988d334 | 1285 | |
4efc0670 | 1286 | #else /* CONFIG_X86_OLD_MCE: */ |
a988d334 | 1287 | |
a988d334 IM |
1288 | int nr_mce_banks; |
1289 | EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */ | |
1290 | ||
a988d334 IM |
1291 | /* This has to be run for each processor */ |
1292 | void mcheck_init(struct cpuinfo_x86 *c) | |
1293 | { | |
1294 | if (mce_disabled == 1) | |
1295 | return; | |
1296 | ||
1297 | switch (c->x86_vendor) { | |
1298 | case X86_VENDOR_AMD: | |
1299 | amd_mcheck_init(c); | |
1300 | break; | |
1301 | ||
1302 | case X86_VENDOR_INTEL: | |
1303 | if (c->x86 == 5) | |
1304 | intel_p5_mcheck_init(c); | |
1305 | if (c->x86 == 6) | |
1306 | intel_p6_mcheck_init(c); | |
1307 | if (c->x86 == 15) | |
1308 | intel_p4_mcheck_init(c); | |
1309 | break; | |
1310 | ||
1311 | case X86_VENDOR_CENTAUR: | |
1312 | if (c->x86 == 5) | |
1313 | winchip_mcheck_init(c); | |
1314 | break; | |
1315 | ||
1316 | default: | |
1317 | break; | |
1318 | } | |
b659294b | 1319 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks); |
a988d334 IM |
1320 | } |
1321 | ||
a988d334 IM |
1322 | static int __init mcheck_enable(char *str) |
1323 | { | |
1324 | mce_disabled = -1; | |
1325 | return 1; | |
1326 | } | |
1327 | ||
a988d334 IM |
1328 | __setup("mce", mcheck_enable); |
1329 | ||
d7c3c9a6 AK |
1330 | #endif /* CONFIG_X86_OLD_MCE */ |
1331 | ||
1332 | /* | |
1333 | * Old style boot options parsing. Only for compatibility. | |
1334 | */ | |
1335 | static int __init mcheck_disable(char *str) | |
1336 | { | |
1337 | mce_disabled = 1; | |
1338 | return 1; | |
1339 | } | |
1340 | __setup("nomce", mcheck_disable); |