Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
e9eee03e | 44 | |
d88203d1 | 45 | #include <asm/processor.h> |
e9eee03e IM |
46 | #include <asm/mce.h> |
47 | #include <asm/msr.h> | |
1da177e4 | 48 | |
bd19a5e6 | 49 | #include "mce-internal.h" |
711c2e48 | 50 | |
93b62c3c | 51 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 52 | |
f56e8a07 | 53 | #define rcu_dereference_check_mce(p) \ |
ec8c27e0 | 54 | rcu_dereference_index_check((p), \ |
f56e8a07 | 55 | rcu_read_lock_sched_held() || \ |
93b62c3c | 56 | lockdep_is_held(&mce_chrdev_read_mutex)) |
f56e8a07 | 57 | |
8968f9d3 HS |
58 | #define CREATE_TRACE_POINTS |
59 | #include <trace/events/mce.h> | |
60 | ||
3c079792 AK |
61 | #define SPINUNIT 100 /* 100ns */ |
62 | ||
553f265f AK |
63 | atomic_t mce_entry; |
64 | ||
01ca79f1 AK |
65 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
66 | ||
1462594b | 67 | struct mce_bank *mce_banks __read_mostly; |
cebe1820 | 68 | |
d203f0b8 | 69 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 70 | .bootlog = -1, |
d203f0b8 BP |
71 | /* |
72 | * Tolerant levels: | |
73 | * 0: always panic on uncorrected errors, log corrected errors | |
74 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
75 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
76 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
77 | */ | |
84c2559d BP |
78 | .tolerant = 1, |
79 | .monarch_timeout = -1 | |
d203f0b8 BP |
80 | }; |
81 | ||
1020bcbc HS |
82 | /* User mode helper program triggered by machine check event */ |
83 | static unsigned long mce_need_notify; | |
84 | static char mce_helper[128]; | |
85 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 86 | |
93b62c3c HS |
87 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
88 | ||
3c079792 AK |
89 | static DEFINE_PER_CPU(struct mce, mces_seen); |
90 | static int cpu_missing; | |
91 | ||
27f6c573 CG |
92 | /* CMCI storm detection filter */ |
93 | static DEFINE_PER_CPU(unsigned long, mce_polled_error); | |
94 | ||
0644414e NR |
95 | /* |
96 | * MCA banks polled by the period polling timer for corrected events. | |
97 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
98 | */ | |
ee031c31 AK |
99 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
100 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
101 | }; | |
102 | ||
c3d1fb56 NR |
103 | /* |
104 | * MCA banks controlled through firmware first for corrected errors. | |
105 | * This is a global list of banks for which we won't enable CMCI and we | |
106 | * won't poll. Firmware controls these banks and is responsible for | |
107 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
108 | * errors are still notified through a machine check. | |
109 | */ | |
110 | mce_banks_t mce_banks_ce_disabled; | |
111 | ||
9b1beaf2 AK |
112 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
113 | ||
61b0fccd TL |
114 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
115 | ||
3653ada5 BP |
116 | /* |
117 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
118 | * MCE errors in a human-readable form. | |
119 | */ | |
120 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); | |
121 | ||
b5f2fa4e AK |
122 | /* Do initial initialization of a struct mce */ |
123 | void mce_setup(struct mce *m) | |
124 | { | |
125 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 126 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 127 | rdtscll(m->tsc); |
8ee08347 AK |
128 | /* We hope get_seconds stays lockless */ |
129 | m->time = get_seconds(); | |
130 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
131 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 132 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
133 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
134 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
135 | } |
136 | ||
ea149b36 AK |
137 | DEFINE_PER_CPU(struct mce, injectm); |
138 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
139 | ||
1da177e4 LT |
140 | /* |
141 | * Lockless MCE logging infrastructure. | |
142 | * This avoids deadlocks on printk locks without having to break locks. Also | |
143 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
144 | */ | |
145 | ||
231fd906 | 146 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
147 | .signature = MCE_LOG_SIGNATURE, |
148 | .len = MCE_LOG_LEN, | |
149 | .recordlen = sizeof(struct mce), | |
d88203d1 | 150 | }; |
1da177e4 LT |
151 | |
152 | void mce_log(struct mce *mce) | |
153 | { | |
154 | unsigned next, entry; | |
f0cb5452 | 155 | int ret = 0; |
e9eee03e | 156 | |
8968f9d3 HS |
157 | /* Emit the trace record: */ |
158 | trace_mce_record(mce); | |
159 | ||
f0cb5452 BP |
160 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce); |
161 | if (ret == NOTIFY_STOP) | |
162 | return; | |
163 | ||
1da177e4 | 164 | mce->finished = 0; |
7644143c | 165 | wmb(); |
1da177e4 | 166 | for (;;) { |
f56e8a07 | 167 | entry = rcu_dereference_check_mce(mcelog.next); |
673242c1 | 168 | for (;;) { |
696e409d | 169 | |
e9eee03e IM |
170 | /* |
171 | * When the buffer fills up discard new entries. | |
172 | * Assume that the earlier errors are the more | |
173 | * interesting ones: | |
174 | */ | |
673242c1 | 175 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
176 | set_bit(MCE_OVERFLOW, |
177 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
178 | return; |
179 | } | |
e9eee03e | 180 | /* Old left over entry. Skip: */ |
673242c1 AK |
181 | if (mcelog.entry[entry].finished) { |
182 | entry++; | |
183 | continue; | |
184 | } | |
7644143c | 185 | break; |
1da177e4 | 186 | } |
1da177e4 LT |
187 | smp_rmb(); |
188 | next = entry + 1; | |
189 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
190 | break; | |
191 | } | |
192 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 193 | wmb(); |
1da177e4 | 194 | mcelog.entry[entry].finished = 1; |
7644143c | 195 | wmb(); |
1da177e4 | 196 | |
a0189c70 | 197 | mce->finished = 1; |
1020bcbc | 198 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
199 | } |
200 | ||
09371957 BP |
201 | static void drain_mcelog_buffer(void) |
202 | { | |
203 | unsigned int next, i, prev = 0; | |
204 | ||
b11e3d78 | 205 | next = ACCESS_ONCE(mcelog.next); |
09371957 BP |
206 | |
207 | do { | |
208 | struct mce *m; | |
209 | ||
210 | /* drain what was logged during boot */ | |
211 | for (i = prev; i < next; i++) { | |
212 | unsigned long start = jiffies; | |
213 | unsigned retries = 1; | |
214 | ||
215 | m = &mcelog.entry[i]; | |
216 | ||
217 | while (!m->finished) { | |
218 | if (time_after_eq(jiffies, start + 2*retries)) | |
219 | retries++; | |
220 | ||
221 | cpu_relax(); | |
222 | ||
223 | if (!m->finished && retries >= 4) { | |
c767a54b | 224 | pr_err("skipping error being logged currently!\n"); |
09371957 BP |
225 | break; |
226 | } | |
227 | } | |
228 | smp_rmb(); | |
229 | atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); | |
230 | } | |
231 | ||
232 | memset(mcelog.entry + prev, 0, (next - prev) * sizeof(*m)); | |
233 | prev = next; | |
234 | next = cmpxchg(&mcelog.next, prev, 0); | |
235 | } while (next != prev); | |
236 | } | |
237 | ||
238 | ||
3653ada5 BP |
239 | void mce_register_decode_chain(struct notifier_block *nb) |
240 | { | |
241 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); | |
09371957 | 242 | drain_mcelog_buffer(); |
3653ada5 BP |
243 | } |
244 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
245 | ||
246 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
247 | { | |
248 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
249 | } | |
250 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
251 | ||
77e26cca | 252 | static void print_mce(struct mce *m) |
1da177e4 | 253 | { |
dffa4b2f BP |
254 | int ret = 0; |
255 | ||
a2d7b0d4 | 256 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 257 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 258 | |
65ea5b03 | 259 | if (m->ip) { |
a2d7b0d4 | 260 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
261 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
262 | m->cs, m->ip); | |
263 | ||
1da177e4 | 264 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 265 | print_symbol("{%s}", m->ip); |
f436f8bb | 266 | pr_cont("\n"); |
1da177e4 | 267 | } |
f436f8bb | 268 | |
a2d7b0d4 | 269 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 270 | if (m->addr) |
f436f8bb | 271 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 272 | if (m->misc) |
f436f8bb | 273 | pr_cont("MISC %llx ", m->misc); |
549d042d | 274 | |
f436f8bb | 275 | pr_cont("\n"); |
506ed6b5 AK |
276 | /* |
277 | * Note this output is parsed by external tools and old fields | |
278 | * should not be changed. | |
279 | */ | |
881e23e5 | 280 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
281 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
282 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
283 | |
284 | /* | |
285 | * Print out human-readable details about the MCE error, | |
fb253195 | 286 | * (if the CPU has an implementation for that) |
f436f8bb | 287 | */ |
dffa4b2f BP |
288 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
289 | if (ret == NOTIFY_STOP) | |
290 | return; | |
291 | ||
292 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
293 | } |
294 | ||
f94b61c2 AK |
295 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
296 | ||
297 | static atomic_t mce_paniced; | |
298 | ||
bf783f9f HY |
299 | static int fake_panic; |
300 | static atomic_t mce_fake_paniced; | |
301 | ||
f94b61c2 AK |
302 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
303 | static void wait_for_panic(void) | |
304 | { | |
305 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 306 | |
f94b61c2 AK |
307 | preempt_disable(); |
308 | local_irq_enable(); | |
309 | while (timeout-- > 0) | |
310 | udelay(1); | |
29b0f591 | 311 | if (panic_timeout == 0) |
7af19e4a | 312 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
313 | panic("Panicing machine check CPU died"); |
314 | } | |
315 | ||
bd19a5e6 | 316 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 317 | { |
482908b4 | 318 | int i, apei_err = 0; |
e02e68d3 | 319 | |
bf783f9f HY |
320 | if (!fake_panic) { |
321 | /* | |
322 | * Make sure only one CPU runs in machine check panic | |
323 | */ | |
324 | if (atomic_inc_return(&mce_paniced) > 1) | |
325 | wait_for_panic(); | |
326 | barrier(); | |
f94b61c2 | 327 | |
bf783f9f HY |
328 | bust_spinlocks(1); |
329 | console_verbose(); | |
330 | } else { | |
331 | /* Don't log too much for fake panic */ | |
332 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
333 | return; | |
334 | } | |
a0189c70 | 335 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 336 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 337 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
338 | if (!(m->status & MCI_STATUS_VAL)) |
339 | continue; | |
482908b4 | 340 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 341 | print_mce(m); |
482908b4 HY |
342 | if (!apei_err) |
343 | apei_err = apei_write_mce(m); | |
344 | } | |
a0189c70 AK |
345 | } |
346 | /* Now print uncorrected but with the final one last */ | |
347 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
348 | struct mce *m = &mcelog.entry[i]; | |
349 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 350 | continue; |
77e26cca HS |
351 | if (!(m->status & MCI_STATUS_UC)) |
352 | continue; | |
482908b4 | 353 | if (!final || memcmp(m, final, sizeof(struct mce))) { |
77e26cca | 354 | print_mce(m); |
482908b4 HY |
355 | if (!apei_err) |
356 | apei_err = apei_write_mce(m); | |
357 | } | |
1da177e4 | 358 | } |
482908b4 | 359 | if (final) { |
77e26cca | 360 | print_mce(final); |
482908b4 HY |
361 | if (!apei_err) |
362 | apei_err = apei_write_mce(final); | |
363 | } | |
3c079792 | 364 | if (cpu_missing) |
a2d7b0d4 | 365 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 366 | if (exp) |
a2d7b0d4 | 367 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
368 | if (!fake_panic) { |
369 | if (panic_timeout == 0) | |
7af19e4a | 370 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
371 | panic(msg); |
372 | } else | |
a2d7b0d4 | 373 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 374 | } |
1da177e4 | 375 | |
ea149b36 AK |
376 | /* Support code for software error injection */ |
377 | ||
378 | static int msr_to_offset(u32 msr) | |
379 | { | |
0a3aee0d | 380 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 381 | |
84c2559d | 382 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 383 | return offsetof(struct mce, ip); |
a2d32bcb | 384 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 385 | return offsetof(struct mce, status); |
a2d32bcb | 386 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 387 | return offsetof(struct mce, addr); |
a2d32bcb | 388 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
389 | return offsetof(struct mce, misc); |
390 | if (msr == MSR_IA32_MCG_STATUS) | |
391 | return offsetof(struct mce, mcgstatus); | |
392 | return -1; | |
393 | } | |
394 | ||
5f8c1a54 AK |
395 | /* MSR access wrappers used for error injection */ |
396 | static u64 mce_rdmsrl(u32 msr) | |
397 | { | |
398 | u64 v; | |
11868a2d | 399 | |
0a3aee0d | 400 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 401 | int offset = msr_to_offset(msr); |
11868a2d | 402 | |
ea149b36 AK |
403 | if (offset < 0) |
404 | return 0; | |
405 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
406 | } | |
11868a2d IM |
407 | |
408 | if (rdmsrl_safe(msr, &v)) { | |
409 | WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr); | |
410 | /* | |
411 | * Return zero in case the access faulted. This should | |
412 | * not happen normally but can happen if the CPU does | |
413 | * something weird, or if the code is buggy. | |
414 | */ | |
415 | v = 0; | |
416 | } | |
417 | ||
5f8c1a54 AK |
418 | return v; |
419 | } | |
420 | ||
421 | static void mce_wrmsrl(u32 msr, u64 v) | |
422 | { | |
0a3aee0d | 423 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 424 | int offset = msr_to_offset(msr); |
11868a2d | 425 | |
ea149b36 AK |
426 | if (offset >= 0) |
427 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
428 | return; | |
429 | } | |
5f8c1a54 AK |
430 | wrmsrl(msr, v); |
431 | } | |
432 | ||
b8325c5b HS |
433 | /* |
434 | * Collect all global (w.r.t. this processor) status about this machine | |
435 | * check into our "mce" struct so that we can use it later to assess | |
436 | * the severity of the problem as we read per-bank specific details. | |
437 | */ | |
438 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
439 | { | |
440 | mce_setup(m); | |
441 | ||
442 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
443 | if (regs) { | |
444 | /* | |
445 | * Get the address of the instruction at the time of | |
446 | * the machine check error. | |
447 | */ | |
448 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
449 | m->ip = regs->ip; | |
450 | m->cs = regs->cs; | |
a129a7c8 AK |
451 | |
452 | /* | |
453 | * When in VM86 mode make the cs look like ring 3 | |
454 | * always. This is a lie, but it's better than passing | |
455 | * the additional vm86 bit around everywhere. | |
456 | */ | |
457 | if (v8086_mode(regs)) | |
458 | m->cs |= 3; | |
b8325c5b HS |
459 | } |
460 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
461 | if (mca_cfg.rip_msr) |
462 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
463 | } |
464 | } | |
465 | ||
9b1beaf2 AK |
466 | /* |
467 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
468 | * process context work function. This is vastly simplified because there's | |
469 | * only a single reader and a single writer. | |
470 | */ | |
471 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
472 | ||
473 | struct mce_ring { | |
474 | unsigned short start; | |
475 | unsigned short end; | |
476 | unsigned long ring[MCE_RING_SIZE]; | |
477 | }; | |
478 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
479 | ||
480 | /* Runs with CPU affinity in workqueue */ | |
481 | static int mce_ring_empty(void) | |
482 | { | |
483 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
484 | ||
485 | return r->start == r->end; | |
486 | } | |
487 | ||
488 | static int mce_ring_get(unsigned long *pfn) | |
489 | { | |
490 | struct mce_ring *r; | |
491 | int ret = 0; | |
492 | ||
493 | *pfn = 0; | |
494 | get_cpu(); | |
495 | r = &__get_cpu_var(mce_ring); | |
496 | if (r->start == r->end) | |
497 | goto out; | |
498 | *pfn = r->ring[r->start]; | |
499 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
500 | ret = 1; | |
501 | out: | |
502 | put_cpu(); | |
503 | return ret; | |
504 | } | |
505 | ||
506 | /* Always runs in MCE context with preempt off */ | |
507 | static int mce_ring_add(unsigned long pfn) | |
508 | { | |
509 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
510 | unsigned next; | |
511 | ||
512 | next = (r->end + 1) % MCE_RING_SIZE; | |
513 | if (next == r->start) | |
514 | return -1; | |
515 | r->ring[r->end] = pfn; | |
516 | wmb(); | |
517 | r->end = next; | |
518 | return 0; | |
519 | } | |
520 | ||
88ccbedd | 521 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 522 | { |
1462594b | 523 | if (mca_cfg.disabled) |
5b4408fd | 524 | return 0; |
3d1712c9 | 525 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
526 | } |
527 | ||
9b1beaf2 AK |
528 | static void mce_schedule_work(void) |
529 | { | |
4d899be5 TH |
530 | if (!mce_ring_empty()) |
531 | schedule_work(&__get_cpu_var(mce_work)); | |
9b1beaf2 AK |
532 | } |
533 | ||
b77e70bf HS |
534 | DEFINE_PER_CPU(struct irq_work, mce_irq_work); |
535 | ||
536 | static void mce_irq_work_cb(struct irq_work *entry) | |
ccc3c319 | 537 | { |
9ff36ee9 | 538 | mce_notify_irq(); |
9b1beaf2 | 539 | mce_schedule_work(); |
ccc3c319 | 540 | } |
ccc3c319 AK |
541 | |
542 | static void mce_report_event(struct pt_regs *regs) | |
543 | { | |
544 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 545 | mce_notify_irq(); |
9b1beaf2 AK |
546 | /* |
547 | * Triggering the work queue here is just an insurance | |
548 | * policy in case the syscall exit notify handler | |
549 | * doesn't run soon enough or ends up running on the | |
550 | * wrong CPU (can happen when audit sleeps) | |
551 | */ | |
552 | mce_schedule_work(); | |
ccc3c319 AK |
553 | return; |
554 | } | |
555 | ||
b77e70bf | 556 | irq_work_queue(&__get_cpu_var(mce_irq_work)); |
ccc3c319 AK |
557 | } |
558 | ||
85f92694 TL |
559 | /* |
560 | * Read ADDR and MISC registers. | |
561 | */ | |
562 | static void mce_read_aux(struct mce *m, int i) | |
563 | { | |
564 | if (m->status & MCI_STATUS_MISCV) | |
565 | m->misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); | |
566 | if (m->status & MCI_STATUS_ADDRV) { | |
567 | m->addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); | |
568 | ||
569 | /* | |
570 | * Mask the reported address by the reported granularity. | |
571 | */ | |
1462594b | 572 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
573 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
574 | m->addr >>= shift; | |
575 | m->addr <<= shift; | |
576 | } | |
577 | } | |
578 | } | |
579 | ||
ca84f696 AK |
580 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
581 | ||
d88203d1 | 582 | /* |
b79109c3 AK |
583 | * Poll for corrected events or events that happened before reset. |
584 | * Those are just logged through /dev/mcelog. | |
585 | * | |
586 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
587 | * |
588 | * Note: spec recommends to panic for fatal unsignalled | |
589 | * errors here. However this would be quite problematic -- | |
590 | * we would need to reimplement the Monarch handling and | |
591 | * it would mess up the exclusion between exception handler | |
592 | * and poll hander -- * so we skip this for now. | |
593 | * These cases should not happen anyways, or only when the CPU | |
594 | * is already totally * confused. In this case it's likely it will | |
595 | * not fully execute the machine check handler either. | |
b79109c3 | 596 | */ |
ee031c31 | 597 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
598 | { |
599 | struct mce m; | |
600 | int i; | |
27f6c573 | 601 | unsigned long *v; |
b79109c3 | 602 | |
c6ae41e7 | 603 | this_cpu_inc(mce_poll_count); |
ca84f696 | 604 | |
b8325c5b | 605 | mce_gather_info(&m, NULL); |
b79109c3 | 606 | |
d203f0b8 | 607 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 608 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
609 | continue; |
610 | ||
611 | m.misc = 0; | |
612 | m.addr = 0; | |
613 | m.bank = i; | |
614 | m.tsc = 0; | |
615 | ||
616 | barrier(); | |
a2d32bcb | 617 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
618 | if (!(m.status & MCI_STATUS_VAL)) |
619 | continue; | |
620 | ||
27f6c573 CG |
621 | v = &get_cpu_var(mce_polled_error); |
622 | set_bit(0, v); | |
b79109c3 | 623 | /* |
ed7290d0 AK |
624 | * Uncorrected or signalled events are handled by the exception |
625 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
626 | * |
627 | * TBD do the same check for MCI_STATUS_EN here? | |
628 | */ | |
ed7290d0 | 629 | if (!(flags & MCP_UC) && |
1462594b | 630 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
631 | continue; |
632 | ||
85f92694 | 633 | mce_read_aux(&m, i); |
b79109c3 AK |
634 | |
635 | if (!(flags & MCP_TIMESTAMP)) | |
636 | m.tsc = 0; | |
637 | /* | |
638 | * Don't get the IP here because it's unlikely to | |
639 | * have anything to do with the actual error location. | |
640 | */ | |
d203f0b8 | 641 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 642 | mce_log(&m); |
b79109c3 AK |
643 | |
644 | /* | |
645 | * Clear state for this bank. | |
646 | */ | |
a2d32bcb | 647 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
648 | } |
649 | ||
650 | /* | |
651 | * Don't clear MCG_STATUS here because it's only defined for | |
652 | * exceptions. | |
653 | */ | |
88921be3 AK |
654 | |
655 | sync_core(); | |
b79109c3 | 656 | } |
ea149b36 | 657 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 658 | |
bd19a5e6 AK |
659 | /* |
660 | * Do a quick check if any of the events requires a panic. | |
661 | * This decides if we keep the events around or clear them. | |
662 | */ | |
61b0fccd TL |
663 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
664 | struct pt_regs *regs) | |
bd19a5e6 | 665 | { |
95022b8c | 666 | int i, ret = 0; |
bd19a5e6 | 667 | |
d203f0b8 | 668 | for (i = 0; i < mca_cfg.banks; i++) { |
a2d32bcb | 669 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
61b0fccd | 670 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 671 | __set_bit(i, validp); |
61b0fccd TL |
672 | if (quirk_no_way_out) |
673 | quirk_no_way_out(i, m, regs); | |
674 | } | |
d203f0b8 | 675 | if (mce_severity(m, mca_cfg.tolerant, msg) >= MCE_PANIC_SEVERITY) |
95022b8c | 676 | ret = 1; |
bd19a5e6 | 677 | } |
95022b8c | 678 | return ret; |
bd19a5e6 AK |
679 | } |
680 | ||
3c079792 AK |
681 | /* |
682 | * Variable to establish order between CPUs while scanning. | |
683 | * Each CPU spins initially until executing is equal its number. | |
684 | */ | |
685 | static atomic_t mce_executing; | |
686 | ||
687 | /* | |
688 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
689 | */ | |
690 | static atomic_t mce_callin; | |
691 | ||
692 | /* | |
693 | * Check if a timeout waiting for other CPUs happened. | |
694 | */ | |
695 | static int mce_timed_out(u64 *t) | |
696 | { | |
697 | /* | |
698 | * The others already did panic for some reason. | |
699 | * Bail out like in a timeout. | |
700 | * rmb() to tell the compiler that system_state | |
701 | * might have been modified by someone else. | |
702 | */ | |
703 | rmb(); | |
704 | if (atomic_read(&mce_paniced)) | |
705 | wait_for_panic(); | |
84c2559d | 706 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
707 | goto out; |
708 | if ((s64)*t < SPINUNIT) { | |
709 | /* CHECKME: Make panic default for 1 too? */ | |
d203f0b8 | 710 | if (mca_cfg.tolerant < 1) |
3c079792 AK |
711 | mce_panic("Timeout synchronizing machine check over CPUs", |
712 | NULL, NULL); | |
713 | cpu_missing = 1; | |
714 | return 1; | |
715 | } | |
716 | *t -= SPINUNIT; | |
717 | out: | |
718 | touch_nmi_watchdog(); | |
719 | return 0; | |
720 | } | |
721 | ||
722 | /* | |
723 | * The Monarch's reign. The Monarch is the CPU who entered | |
724 | * the machine check handler first. It waits for the others to | |
725 | * raise the exception too and then grades them. When any | |
726 | * error is fatal panic. Only then let the others continue. | |
727 | * | |
728 | * The other CPUs entering the MCE handler will be controlled by the | |
729 | * Monarch. They are called Subjects. | |
730 | * | |
731 | * This way we prevent any potential data corruption in a unrecoverable case | |
732 | * and also makes sure always all CPU's errors are examined. | |
733 | * | |
680b6cfd | 734 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
735 | * space (not detected by any CPUs) In this case some external agent wants |
736 | * us to shut down, so panic too. | |
737 | * | |
738 | * The other CPUs might still decide to panic if the handler happens | |
739 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
740 | * state and won't corrupt anything by itself. It's ok to let the others | |
741 | * continue for a bit first. | |
742 | * | |
743 | * All the spin loops have timeouts; when a timeout happens a CPU | |
744 | * typically elects itself to be Monarch. | |
745 | */ | |
746 | static void mce_reign(void) | |
747 | { | |
748 | int cpu; | |
749 | struct mce *m = NULL; | |
750 | int global_worst = 0; | |
751 | char *msg = NULL; | |
752 | char *nmsg = NULL; | |
753 | ||
754 | /* | |
755 | * This CPU is the Monarch and the other CPUs have run | |
756 | * through their handlers. | |
757 | * Grade the severity of the errors of all the CPUs. | |
758 | */ | |
759 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
760 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
761 | mca_cfg.tolerant, | |
3c079792 AK |
762 | &nmsg); |
763 | if (severity > global_worst) { | |
764 | msg = nmsg; | |
765 | global_worst = severity; | |
766 | m = &per_cpu(mces_seen, cpu); | |
767 | } | |
768 | } | |
769 | ||
770 | /* | |
771 | * Cannot recover? Panic here then. | |
772 | * This dumps all the mces in the log buffer and stops the | |
773 | * other CPUs. | |
774 | */ | |
d203f0b8 | 775 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
ac960375 | 776 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
777 | |
778 | /* | |
779 | * For UC somewhere we let the CPU who detects it handle it. | |
780 | * Also must let continue the others, otherwise the handling | |
781 | * CPU could deadlock on a lock. | |
782 | */ | |
783 | ||
784 | /* | |
785 | * No machine check event found. Must be some external | |
786 | * source or one CPU is hung. Panic. | |
787 | */ | |
d203f0b8 | 788 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
3c079792 AK |
789 | mce_panic("Machine check from unknown source", NULL, NULL); |
790 | ||
791 | /* | |
792 | * Now clear all the mces_seen so that they don't reappear on | |
793 | * the next mce. | |
794 | */ | |
795 | for_each_possible_cpu(cpu) | |
796 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
797 | } | |
798 | ||
799 | static atomic_t global_nwo; | |
800 | ||
801 | /* | |
802 | * Start of Monarch synchronization. This waits until all CPUs have | |
803 | * entered the exception handler and then determines if any of them | |
804 | * saw a fatal event that requires panic. Then it executes them | |
805 | * in the entry order. | |
806 | * TBD double check parallel CPU hotunplug | |
807 | */ | |
7fb06fc9 | 808 | static int mce_start(int *no_way_out) |
3c079792 | 809 | { |
7fb06fc9 | 810 | int order; |
3c079792 | 811 | int cpus = num_online_cpus(); |
84c2559d | 812 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 813 | |
7fb06fc9 HS |
814 | if (!timeout) |
815 | return -1; | |
3c079792 | 816 | |
7fb06fc9 | 817 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
818 | /* |
819 | * global_nwo should be updated before mce_callin | |
820 | */ | |
821 | smp_wmb(); | |
a95436e4 | 822 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
823 | |
824 | /* | |
825 | * Wait for everyone. | |
826 | */ | |
827 | while (atomic_read(&mce_callin) != cpus) { | |
828 | if (mce_timed_out(&timeout)) { | |
829 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 830 | return -1; |
3c079792 AK |
831 | } |
832 | ndelay(SPINUNIT); | |
833 | } | |
834 | ||
184e1fdf HY |
835 | /* |
836 | * mce_callin should be read before global_nwo | |
837 | */ | |
838 | smp_rmb(); | |
3c079792 | 839 | |
7fb06fc9 HS |
840 | if (order == 1) { |
841 | /* | |
842 | * Monarch: Starts executing now, the others wait. | |
843 | */ | |
3c079792 | 844 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
845 | } else { |
846 | /* | |
847 | * Subject: Now start the scanning loop one by one in | |
848 | * the original callin order. | |
849 | * This way when there are any shared banks it will be | |
850 | * only seen by one CPU before cleared, avoiding duplicates. | |
851 | */ | |
852 | while (atomic_read(&mce_executing) < order) { | |
853 | if (mce_timed_out(&timeout)) { | |
854 | atomic_set(&global_nwo, 0); | |
855 | return -1; | |
856 | } | |
857 | ndelay(SPINUNIT); | |
858 | } | |
3c079792 AK |
859 | } |
860 | ||
861 | /* | |
7fb06fc9 | 862 | * Cache the global no_way_out state. |
3c079792 | 863 | */ |
7fb06fc9 HS |
864 | *no_way_out = atomic_read(&global_nwo); |
865 | ||
866 | return order; | |
3c079792 AK |
867 | } |
868 | ||
869 | /* | |
870 | * Synchronize between CPUs after main scanning loop. | |
871 | * This invokes the bulk of the Monarch processing. | |
872 | */ | |
873 | static int mce_end(int order) | |
874 | { | |
875 | int ret = -1; | |
84c2559d | 876 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
877 | |
878 | if (!timeout) | |
879 | goto reset; | |
880 | if (order < 0) | |
881 | goto reset; | |
882 | ||
883 | /* | |
884 | * Allow others to run. | |
885 | */ | |
886 | atomic_inc(&mce_executing); | |
887 | ||
888 | if (order == 1) { | |
889 | /* CHECKME: Can this race with a parallel hotplug? */ | |
890 | int cpus = num_online_cpus(); | |
891 | ||
892 | /* | |
893 | * Monarch: Wait for everyone to go through their scanning | |
894 | * loops. | |
895 | */ | |
896 | while (atomic_read(&mce_executing) <= cpus) { | |
897 | if (mce_timed_out(&timeout)) | |
898 | goto reset; | |
899 | ndelay(SPINUNIT); | |
900 | } | |
901 | ||
902 | mce_reign(); | |
903 | barrier(); | |
904 | ret = 0; | |
905 | } else { | |
906 | /* | |
907 | * Subject: Wait for Monarch to finish. | |
908 | */ | |
909 | while (atomic_read(&mce_executing) != 0) { | |
910 | if (mce_timed_out(&timeout)) | |
911 | goto reset; | |
912 | ndelay(SPINUNIT); | |
913 | } | |
914 | ||
915 | /* | |
916 | * Don't reset anything. That's done by the Monarch. | |
917 | */ | |
918 | return 0; | |
919 | } | |
920 | ||
921 | /* | |
922 | * Reset all global state. | |
923 | */ | |
924 | reset: | |
925 | atomic_set(&global_nwo, 0); | |
926 | atomic_set(&mce_callin, 0); | |
927 | barrier(); | |
928 | ||
929 | /* | |
930 | * Let others run again. | |
931 | */ | |
932 | atomic_set(&mce_executing, 0); | |
933 | return ret; | |
934 | } | |
935 | ||
9b1beaf2 AK |
936 | /* |
937 | * Check if the address reported by the CPU is in a format we can parse. | |
938 | * It would be possible to add code for most other cases, but all would | |
939 | * be somewhat complicated (e.g. segment offset would require an instruction | |
0d2eb44f | 940 | * parser). So only support physical addresses up to page granuality for now. |
9b1beaf2 AK |
941 | */ |
942 | static int mce_usable_address(struct mce *m) | |
943 | { | |
944 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
945 | return 0; | |
2b90e77e | 946 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) |
9b1beaf2 | 947 | return 0; |
2b90e77e | 948 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) |
9b1beaf2 AK |
949 | return 0; |
950 | return 1; | |
951 | } | |
952 | ||
3c079792 AK |
953 | static void mce_clear_state(unsigned long *toclear) |
954 | { | |
955 | int i; | |
956 | ||
d203f0b8 | 957 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 958 | if (test_bit(i, toclear)) |
a2d32bcb | 959 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
960 | } |
961 | } | |
962 | ||
af104e39 TL |
963 | /* |
964 | * Need to save faulting physical address associated with a process | |
965 | * in the machine check handler some place where we can grab it back | |
966 | * later in mce_notify_process() | |
967 | */ | |
968 | #define MCE_INFO_MAX 16 | |
969 | ||
970 | struct mce_info { | |
971 | atomic_t inuse; | |
972 | struct task_struct *t; | |
973 | __u64 paddr; | |
dad1743e | 974 | int restartable; |
af104e39 TL |
975 | } mce_info[MCE_INFO_MAX]; |
976 | ||
dad1743e | 977 | static void mce_save_info(__u64 addr, int c) |
af104e39 TL |
978 | { |
979 | struct mce_info *mi; | |
980 | ||
981 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) { | |
982 | if (atomic_cmpxchg(&mi->inuse, 0, 1) == 0) { | |
983 | mi->t = current; | |
984 | mi->paddr = addr; | |
dad1743e | 985 | mi->restartable = c; |
af104e39 TL |
986 | return; |
987 | } | |
988 | } | |
989 | ||
990 | mce_panic("Too many concurrent recoverable errors", NULL, NULL); | |
991 | } | |
992 | ||
993 | static struct mce_info *mce_find_info(void) | |
994 | { | |
995 | struct mce_info *mi; | |
996 | ||
997 | for (mi = mce_info; mi < &mce_info[MCE_INFO_MAX]; mi++) | |
998 | if (atomic_read(&mi->inuse) && mi->t == current) | |
999 | return mi; | |
1000 | return NULL; | |
1001 | } | |
1002 | ||
1003 | static void mce_clear_info(struct mce_info *mi) | |
1004 | { | |
1005 | atomic_set(&mi->inuse, 0); | |
1006 | } | |
1007 | ||
b79109c3 AK |
1008 | /* |
1009 | * The actual machine check handler. This only handles real | |
1010 | * exceptions when something got corrupted coming in through int 18. | |
1011 | * | |
1012 | * This is executed in NMI context not subject to normal locking rules. This | |
1013 | * implies that most kernel services cannot be safely used. Don't even | |
1014 | * think about putting a printk in there! | |
3c079792 AK |
1015 | * |
1016 | * On Intel systems this is entered on all CPUs in parallel through | |
1017 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1018 | * so be always careful when synchronizing with others. | |
1da177e4 | 1019 | */ |
e9eee03e | 1020 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1021 | { |
1462594b | 1022 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1023 | struct mce m, *final; |
1da177e4 | 1024 | int i; |
3c079792 AK |
1025 | int worst = 0; |
1026 | int severity; | |
1027 | /* | |
1028 | * Establish sequential order between the CPUs entering the machine | |
1029 | * check handler. | |
1030 | */ | |
7fb06fc9 | 1031 | int order; |
bd78432c TH |
1032 | /* |
1033 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1034 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1035 | */ |
1036 | int no_way_out = 0; | |
1037 | /* | |
1038 | * If kill_it gets set, there might be a way to recover from this | |
1039 | * error. | |
1040 | */ | |
1041 | int kill_it = 0; | |
b79109c3 | 1042 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1043 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1044 | char *msg = "Unknown"; |
1da177e4 | 1045 | |
553f265f AK |
1046 | atomic_inc(&mce_entry); |
1047 | ||
c6ae41e7 | 1048 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1049 | |
1462594b | 1050 | if (!cfg->banks) |
32561696 | 1051 | goto out; |
1da177e4 | 1052 | |
b8325c5b | 1053 | mce_gather_info(&m, regs); |
b5f2fa4e | 1054 | |
3c079792 AK |
1055 | final = &__get_cpu_var(mces_seen); |
1056 | *final = m; | |
1057 | ||
95022b8c | 1058 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1059 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1060 | |
1da177e4 LT |
1061 | barrier(); |
1062 | ||
ed7290d0 | 1063 | /* |
a8c321fb TL |
1064 | * When no restart IP might need to kill or panic. |
1065 | * Assume the worst for now, but if we find the | |
1066 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1067 | */ |
1068 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1069 | kill_it = 1; | |
1070 | ||
3c079792 AK |
1071 | /* |
1072 | * Go through all the banks in exclusion of the other CPUs. | |
1073 | * This way we don't report duplicated events on shared banks | |
1074 | * because the first one to see it will clear it. | |
1075 | */ | |
7fb06fc9 | 1076 | order = mce_start(&no_way_out); |
1462594b | 1077 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1078 | __clear_bit(i, toclear); |
95022b8c TL |
1079 | if (!test_bit(i, valid_banks)) |
1080 | continue; | |
cebe1820 | 1081 | if (!mce_banks[i].ctl) |
1da177e4 | 1082 | continue; |
d88203d1 TG |
1083 | |
1084 | m.misc = 0; | |
1da177e4 LT |
1085 | m.addr = 0; |
1086 | m.bank = i; | |
1da177e4 | 1087 | |
a2d32bcb | 1088 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
1089 | if ((m.status & MCI_STATUS_VAL) == 0) |
1090 | continue; | |
1091 | ||
b79109c3 | 1092 | /* |
ed7290d0 AK |
1093 | * Non uncorrected or non signaled errors are handled by |
1094 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1095 | */ |
1462594b | 1096 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1097 | !no_way_out) |
b79109c3 AK |
1098 | continue; |
1099 | ||
1100 | /* | |
1101 | * Set taint even when machine check was not enabled. | |
1102 | */ | |
373d4d09 | 1103 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1104 | |
1462594b | 1105 | severity = mce_severity(&m, cfg->tolerant, NULL); |
b79109c3 | 1106 | |
ed7290d0 AK |
1107 | /* |
1108 | * When machine check was for corrected handler don't touch, | |
1109 | * unless we're panicing. | |
1110 | */ | |
1111 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
1112 | continue; | |
1113 | __set_bit(i, toclear); | |
1114 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1115 | /* |
1116 | * Machine check event was not enabled. Clear, but | |
1117 | * ignore. | |
1118 | */ | |
1119 | continue; | |
1da177e4 LT |
1120 | } |
1121 | ||
85f92694 | 1122 | mce_read_aux(&m, i); |
1da177e4 | 1123 | |
9b1beaf2 AK |
1124 | /* |
1125 | * Action optional error. Queue address for later processing. | |
1126 | * When the ring overflows we just ignore the AO error. | |
1127 | * RED-PEN add some logging mechanism when | |
1128 | * usable_address or mce_add_ring fails. | |
d203f0b8 | 1129 | * RED-PEN don't ignore overflow for mca_cfg.tolerant == 0 |
9b1beaf2 AK |
1130 | */ |
1131 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
1132 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
1133 | ||
b79109c3 | 1134 | mce_log(&m); |
1da177e4 | 1135 | |
3c079792 AK |
1136 | if (severity > worst) { |
1137 | *final = m; | |
1138 | worst = severity; | |
1da177e4 | 1139 | } |
1da177e4 LT |
1140 | } |
1141 | ||
a8c321fb TL |
1142 | /* mce_clear_state will clear *final, save locally for use later */ |
1143 | m = *final; | |
1144 | ||
3c079792 AK |
1145 | if (!no_way_out) |
1146 | mce_clear_state(toclear); | |
1147 | ||
e9eee03e | 1148 | /* |
3c079792 AK |
1149 | * Do most of the synchronization with other CPUs. |
1150 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1151 | */ |
3c079792 AK |
1152 | if (mce_end(order) < 0) |
1153 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1154 | |
1155 | /* | |
a8c321fb TL |
1156 | * At insane "tolerant" levels we take no action. Otherwise |
1157 | * we only die if we have no other choice. For less serious | |
1158 | * issues we try to recover, or limit damage to the current | |
1159 | * process. | |
bd78432c | 1160 | */ |
1462594b | 1161 | if (cfg->tolerant < 3) { |
a8c321fb TL |
1162 | if (no_way_out) |
1163 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
1164 | if (worst == MCE_AR_SEVERITY) { | |
1165 | /* schedule action before return to userland */ | |
dad1743e | 1166 | mce_save_info(m.addr, m.mcgstatus & MCG_STATUS_RIPV); |
a8c321fb TL |
1167 | set_thread_flag(TIF_MCE_NOTIFY); |
1168 | } else if (kill_it) { | |
1169 | force_sig(SIGBUS, current); | |
1170 | } | |
1171 | } | |
e02e68d3 | 1172 | |
3c079792 AK |
1173 | if (worst > 0) |
1174 | mce_report_event(regs); | |
5f8c1a54 | 1175 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1176 | out: |
553f265f | 1177 | atomic_dec(&mce_entry); |
88921be3 | 1178 | sync_core(); |
1da177e4 | 1179 | } |
ea149b36 | 1180 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1181 | |
cd42f4a3 TL |
1182 | #ifndef CONFIG_MEMORY_FAILURE |
1183 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1184 | { |
a8c321fb TL |
1185 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1186 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1187 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1188 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1189 | pfn); | |
cd42f4a3 TL |
1190 | |
1191 | return 0; | |
9b1beaf2 | 1192 | } |
cd42f4a3 | 1193 | #endif |
9b1beaf2 AK |
1194 | |
1195 | /* | |
a8c321fb TL |
1196 | * Called in process context that interrupted by MCE and marked with |
1197 | * TIF_MCE_NOTIFY, just before returning to erroneous userland. | |
1198 | * This code is allowed to sleep. | |
1199 | * Attempt possible recovery such as calling the high level VM handler to | |
1200 | * process any corrupted pages, and kill/signal current process if required. | |
1201 | * Action required errors are handled here. | |
9b1beaf2 AK |
1202 | */ |
1203 | void mce_notify_process(void) | |
1204 | { | |
1205 | unsigned long pfn; | |
a8c321fb | 1206 | struct mce_info *mi = mce_find_info(); |
6751ed65 | 1207 | int flags = MF_ACTION_REQUIRED; |
a8c321fb TL |
1208 | |
1209 | if (!mi) | |
1210 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | |
1211 | pfn = mi->paddr >> PAGE_SHIFT; | |
1212 | ||
1213 | clear_thread_flag(TIF_MCE_NOTIFY); | |
1214 | ||
1215 | pr_err("Uncorrected hardware memory error in user-access at %llx", | |
1216 | mi->paddr); | |
dad1743e TL |
1217 | /* |
1218 | * We must call memory_failure() here even if the current process is | |
1219 | * doomed. We still need to mark the page as poisoned and alert any | |
1220 | * other users of the page. | |
1221 | */ | |
6751ed65 TL |
1222 | if (!mi->restartable) |
1223 | flags |= MF_MUST_KILL; | |
1224 | if (memory_failure(pfn, MCE_VECTOR, flags) < 0) { | |
a8c321fb TL |
1225 | pr_err("Memory error not recovered"); |
1226 | force_sig(SIGBUS, current); | |
1227 | } | |
1228 | mce_clear_info(mi); | |
9b1beaf2 AK |
1229 | } |
1230 | ||
a8c321fb TL |
1231 | /* |
1232 | * Action optional processing happens here (picking up | |
1233 | * from the list of faulting pages that do_machine_check() | |
1234 | * placed into the "ring"). | |
1235 | */ | |
9b1beaf2 AK |
1236 | static void mce_process_work(struct work_struct *dummy) |
1237 | { | |
a8c321fb TL |
1238 | unsigned long pfn; |
1239 | ||
1240 | while (mce_ring_get(&pfn)) | |
1241 | memory_failure(pfn, MCE_VECTOR, 0); | |
9b1beaf2 AK |
1242 | } |
1243 | ||
15d5f839 DZ |
1244 | #ifdef CONFIG_X86_MCE_INTEL |
1245 | /*** | |
1246 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1247 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1248 | * @status: Event status information |
1249 | * | |
1250 | * This function should be called by the thermal interrupt after the | |
1251 | * event has been processed and the decision was made to log the event | |
1252 | * further. | |
1253 | * | |
1254 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1255 | * and historically has been the register value of the | |
1256 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1257 | */ | |
b5f2fa4e | 1258 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1259 | { |
1260 | struct mce m; | |
1261 | ||
b5f2fa4e | 1262 | mce_setup(&m); |
15d5f839 DZ |
1263 | m.bank = MCE_THERMAL_BANK; |
1264 | m.status = status; | |
15d5f839 DZ |
1265 | mce_log(&m); |
1266 | } | |
1267 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1268 | ||
1da177e4 | 1269 | /* |
8a336b0a TH |
1270 | * Periodic polling timer for "silent" machine check errors. If the |
1271 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1272 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1273 | */ |
82f7af09 | 1274 | static unsigned long check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1275 | |
82f7af09 | 1276 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1277 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1278 | |
55babd8f CG |
1279 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1280 | { | |
1281 | return interval; | |
1282 | } | |
1283 | ||
1284 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = | |
1285 | mce_adjust_timer_default; | |
1286 | ||
27f6c573 CG |
1287 | static int cmc_error_seen(void) |
1288 | { | |
1289 | unsigned long *v = &__get_cpu_var(mce_polled_error); | |
1290 | ||
1291 | return test_and_clear_bit(0, v); | |
1292 | } | |
1293 | ||
82f7af09 | 1294 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1295 | { |
82f7af09 TG |
1296 | struct timer_list *t = &__get_cpu_var(mce_timer); |
1297 | unsigned long iv; | |
27f6c573 | 1298 | int notify; |
52d168e2 AK |
1299 | |
1300 | WARN_ON(smp_processor_id() != data); | |
1301 | ||
7b543a53 | 1302 | if (mce_available(__this_cpu_ptr(&cpu_info))) { |
ee031c31 AK |
1303 | machine_check_poll(MCP_TIMESTAMP, |
1304 | &__get_cpu_var(mce_poll_banks)); | |
55babd8f | 1305 | mce_intel_cmci_poll(); |
e9eee03e | 1306 | } |
1da177e4 LT |
1307 | |
1308 | /* | |
e02e68d3 TH |
1309 | * Alert userspace if needed. If we logged an MCE, reduce the |
1310 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1311 | */ |
82f7af09 | 1312 | iv = __this_cpu_read(mce_next_interval); |
27f6c573 CG |
1313 | notify = mce_notify_irq(); |
1314 | notify |= cmc_error_seen(); | |
1315 | if (notify) { | |
958fb3c5 | 1316 | iv = max(iv / 2, (unsigned long) HZ/100); |
55babd8f | 1317 | } else { |
82f7af09 | 1318 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
55babd8f CG |
1319 | iv = mce_adjust_timer(iv); |
1320 | } | |
82f7af09 | 1321 | __this_cpu_write(mce_next_interval, iv); |
55babd8f CG |
1322 | /* Might have become 0 after CMCI storm subsided */ |
1323 | if (iv) { | |
1324 | t->expires = jiffies + iv; | |
1325 | add_timer_on(t, smp_processor_id()); | |
1326 | } | |
1327 | } | |
e02e68d3 | 1328 | |
55babd8f CG |
1329 | /* |
1330 | * Ensure that the timer is firing in @interval from now. | |
1331 | */ | |
1332 | void mce_timer_kick(unsigned long interval) | |
1333 | { | |
1334 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1335 | unsigned long when = jiffies + interval; | |
1336 | unsigned long iv = __this_cpu_read(mce_next_interval); | |
1337 | ||
1338 | if (timer_pending(t)) { | |
1339 | if (time_before(when, t->expires)) | |
1340 | mod_timer_pinned(t, when); | |
1341 | } else { | |
1342 | t->expires = round_jiffies(when); | |
1343 | add_timer_on(t, smp_processor_id()); | |
1344 | } | |
1345 | if (interval < iv) | |
1346 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1347 | } |
1348 | ||
9aaef96f HS |
1349 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1350 | static void mce_timer_delete_all(void) | |
1351 | { | |
1352 | int cpu; | |
1353 | ||
1354 | for_each_online_cpu(cpu) | |
1355 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1356 | } | |
1357 | ||
9bd98405 AK |
1358 | static void mce_do_trigger(struct work_struct *work) |
1359 | { | |
1020bcbc | 1360 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1361 | } |
1362 | ||
1363 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1364 | ||
e02e68d3 | 1365 | /* |
9bd98405 AK |
1366 | * Notify the user(s) about new machine check events. |
1367 | * Can be called from interrupt context, but not from machine check/NMI | |
1368 | * context. | |
e02e68d3 | 1369 | */ |
9ff36ee9 | 1370 | int mce_notify_irq(void) |
e02e68d3 | 1371 | { |
8457c84d AK |
1372 | /* Not more than two messages every minute */ |
1373 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1374 | ||
1020bcbc | 1375 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1376 | /* wake processes polling /dev/mcelog */ |
1377 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1378 | |
4d899be5 | 1379 | if (mce_helper[0]) |
9bd98405 | 1380 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1381 | |
8457c84d | 1382 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1383 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1384 | |
1385 | return 1; | |
1da177e4 | 1386 | } |
e02e68d3 TH |
1387 | return 0; |
1388 | } | |
9ff36ee9 | 1389 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1390 | |
148f9bb8 | 1391 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1392 | { |
1393 | int i; | |
d203f0b8 | 1394 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1395 | |
d203f0b8 | 1396 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1397 | if (!mce_banks) |
1398 | return -ENOMEM; | |
d203f0b8 BP |
1399 | |
1400 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1401 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1402 | |
cebe1820 AK |
1403 | b->ctl = -1ULL; |
1404 | b->init = 1; | |
1405 | } | |
1406 | return 0; | |
1407 | } | |
1408 | ||
d88203d1 | 1409 | /* |
1da177e4 LT |
1410 | * Initialize Machine Checks for a CPU. |
1411 | */ | |
148f9bb8 | 1412 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1413 | { |
0d7482e3 | 1414 | unsigned b; |
e9eee03e | 1415 | u64 cap; |
1da177e4 LT |
1416 | |
1417 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1418 | |
1419 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1420 | if (!mca_cfg.banks) |
c767a54b | 1421 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1422 | |
0d7482e3 | 1423 | if (b > MAX_NR_BANKS) { |
c767a54b | 1424 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1425 | MAX_NR_BANKS, b); |
1426 | b = MAX_NR_BANKS; | |
1427 | } | |
1428 | ||
1429 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1430 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1431 | mca_cfg.banks = b; | |
1432 | ||
cebe1820 | 1433 | if (!mce_banks) { |
cffd377e | 1434 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1435 | |
cebe1820 AK |
1436 | if (err) |
1437 | return err; | |
1da177e4 | 1438 | } |
0d7482e3 | 1439 | |
94ad8474 | 1440 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1441 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1442 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1443 | |
ed7290d0 | 1444 | if (cap & MCG_SER_P) |
1462594b | 1445 | mca_cfg.ser = true; |
ed7290d0 | 1446 | |
0d7482e3 AK |
1447 | return 0; |
1448 | } | |
1449 | ||
5e09954a | 1450 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1451 | { |
84c2559d | 1452 | enum mcp_flags m_fl = 0; |
e9eee03e | 1453 | mce_banks_t all_banks; |
0d7482e3 AK |
1454 | u64 cap; |
1455 | int i; | |
1456 | ||
84c2559d BP |
1457 | if (!mca_cfg.bootlog) |
1458 | m_fl = MCP_DONTLOG; | |
1459 | ||
b79109c3 AK |
1460 | /* |
1461 | * Log the machine checks left over from the previous reset. | |
1462 | */ | |
ee031c31 | 1463 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1464 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 LT |
1465 | |
1466 | set_in_cr4(X86_CR4_MCE); | |
1467 | ||
0d7482e3 | 1468 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1469 | if (cap & MCG_CTL_P) |
1470 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1471 | ||
d203f0b8 | 1472 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1473 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1474 | |
cebe1820 | 1475 | if (!b->init) |
06b7a7a5 | 1476 | continue; |
a2d32bcb AK |
1477 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1478 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1479 | } |
1da177e4 LT |
1480 | } |
1481 | ||
61b0fccd TL |
1482 | /* |
1483 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1484 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1485 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1486 | * whether the machine check occurred in kernel or user mode, and also | |
1487 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1488 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1489 | */ | |
1490 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1491 | { | |
1492 | if (bank != 0) | |
1493 | return; | |
1494 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1495 | return; | |
1496 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1497 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1498 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1499 | MCACOD)) != | |
1500 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1501 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1502 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1503 | return; | |
1504 | ||
1505 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1506 | m->ip = regs->ip; | |
1507 | m->cs = regs->cs; | |
1508 | } | |
1509 | ||
1da177e4 | 1510 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1511 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1512 | { |
d203f0b8 BP |
1513 | struct mca_config *cfg = &mca_cfg; |
1514 | ||
e412cd25 | 1515 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1516 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1517 | return -EOPNOTSUPP; |
1518 | } | |
1519 | ||
1da177e4 | 1520 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1521 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1522 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1523 | /* |
1524 | * disable GART TBL walk error reporting, which | |
1525 | * trips off incorrectly with the IOMMU & 3ware | |
1526 | * & Cerberus: | |
1527 | */ | |
cebe1820 | 1528 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1529 | } |
84c2559d | 1530 | if (c->x86 <= 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1531 | /* |
1532 | * Lots of broken BIOS around that don't clear them | |
1533 | * by default and leave crap in there. Don't log: | |
1534 | */ | |
84c2559d | 1535 | cfg->bootlog = 0; |
e9eee03e | 1536 | } |
2e6f694f AK |
1537 | /* |
1538 | * Various K7s with broken bank 0 around. Always disable | |
1539 | * by default. | |
1540 | */ | |
d203f0b8 | 1541 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1542 | mce_banks[0].ctl = 0; |
575203b4 BP |
1543 | |
1544 | /* | |
1545 | * Turn off MC4_MISC thresholding banks on those models since | |
1546 | * they're not supported there. | |
1547 | */ | |
1548 | if (c->x86 == 0x15 && | |
1549 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1550 | int i; | |
1551 | u64 val, hwcr; | |
1552 | bool need_toggle; | |
1553 | u32 msrs[] = { | |
1554 | 0x00000413, /* MC4_MISC0 */ | |
1555 | 0xc0000408, /* MC4_MISC1 */ | |
1556 | }; | |
1557 | ||
1558 | rdmsrl(MSR_K7_HWCR, hwcr); | |
1559 | ||
1560 | /* McStatusWrEn has to be set */ | |
1561 | need_toggle = !(hwcr & BIT(18)); | |
1562 | ||
1563 | if (need_toggle) | |
1564 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
1565 | ||
1566 | for (i = 0; i < ARRAY_SIZE(msrs); i++) { | |
1567 | rdmsrl(msrs[i], val); | |
1568 | ||
1569 | /* CntP bit set? */ | |
80f03361 BP |
1570 | if (val & BIT_64(62)) { |
1571 | val &= ~BIT_64(62); | |
1572 | wrmsrl(msrs[i], val); | |
575203b4 BP |
1573 | } |
1574 | } | |
1575 | ||
1576 | /* restore old settings */ | |
1577 | if (need_toggle) | |
1578 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1579 | } | |
1da177e4 | 1580 | } |
e583538f | 1581 | |
06b7a7a5 AK |
1582 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1583 | /* | |
1584 | * SDM documents that on family 6 bank 0 should not be written | |
1585 | * because it aliases to another special BIOS controlled | |
1586 | * register. | |
1587 | * But it's not aliased anymore on model 0x1a+ | |
1588 | * Don't ignore bank 0 completely because there could be a | |
1589 | * valid event later, merely don't write CTL0. | |
1590 | */ | |
1591 | ||
d203f0b8 | 1592 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1593 | mce_banks[0].init = 0; |
3c079792 AK |
1594 | |
1595 | /* | |
1596 | * All newer Intel systems support MCE broadcasting. Enable | |
1597 | * synchronization with a one second timeout. | |
1598 | */ | |
1599 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1600 | cfg->monarch_timeout < 0) |
1601 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1602 | |
e412cd25 IM |
1603 | /* |
1604 | * There are also broken BIOSes on some Pentium M and | |
1605 | * earlier systems: | |
1606 | */ | |
84c2559d BP |
1607 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1608 | cfg->bootlog = 0; | |
61b0fccd TL |
1609 | |
1610 | if (c->x86 == 6 && c->x86_model == 45) | |
1611 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1612 | } |
84c2559d BP |
1613 | if (cfg->monarch_timeout < 0) |
1614 | cfg->monarch_timeout = 0; | |
1615 | if (cfg->bootlog != 0) | |
7af19e4a | 1616 | cfg->panic_timeout = 30; |
e412cd25 IM |
1617 | |
1618 | return 0; | |
d88203d1 | 1619 | } |
1da177e4 | 1620 | |
148f9bb8 | 1621 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1622 | { |
1623 | if (c->x86 != 5) | |
3a97fc34 HS |
1624 | return 0; |
1625 | ||
4efc0670 AK |
1626 | switch (c->x86_vendor) { |
1627 | case X86_VENDOR_INTEL: | |
c6978369 | 1628 | intel_p5_mcheck_init(c); |
3a97fc34 | 1629 | return 1; |
4efc0670 AK |
1630 | break; |
1631 | case X86_VENDOR_CENTAUR: | |
1632 | winchip_mcheck_init(c); | |
3a97fc34 | 1633 | return 1; |
4efc0670 AK |
1634 | break; |
1635 | } | |
3a97fc34 HS |
1636 | |
1637 | return 0; | |
4efc0670 AK |
1638 | } |
1639 | ||
5e09954a | 1640 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1641 | { |
1642 | switch (c->x86_vendor) { | |
1643 | case X86_VENDOR_INTEL: | |
1644 | mce_intel_feature_init(c); | |
55babd8f | 1645 | mce_adjust_timer = mce_intel_adjust_timer; |
1da177e4 | 1646 | break; |
89b831ef JS |
1647 | case X86_VENDOR_AMD: |
1648 | mce_amd_feature_init(c); | |
1649 | break; | |
1da177e4 LT |
1650 | default: |
1651 | break; | |
1652 | } | |
1653 | } | |
1654 | ||
26c3c283 | 1655 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1656 | { |
4f75d841 | 1657 | unsigned long iv = check_interval * HZ; |
bc09effa | 1658 | |
7af19e4a | 1659 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1660 | return; |
1661 | ||
4f75d841 BP |
1662 | per_cpu(mce_next_interval, cpu) = iv; |
1663 | ||
82f7af09 | 1664 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1665 | add_timer_on(t, cpu); |
52d168e2 AK |
1666 | } |
1667 | ||
26c3c283 TG |
1668 | static void __mcheck_cpu_init_timer(void) |
1669 | { | |
1670 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
1671 | unsigned int cpu = smp_processor_id(); | |
1672 | ||
1673 | setup_timer(t, mce_timer_fn, cpu); | |
1674 | mce_start_timer(cpu, t); | |
1675 | } | |
1676 | ||
9eda8cb3 AK |
1677 | /* Handle unconfigured int18 (should never happen) */ |
1678 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1679 | { | |
c767a54b | 1680 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1681 | smp_processor_id()); |
1682 | } | |
1683 | ||
1684 | /* Call the installed machine check handler for this CPU setup. */ | |
1685 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1686 | unexpected_machine_check; | |
1687 | ||
d88203d1 | 1688 | /* |
1da177e4 | 1689 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1690 | * Must be called with preempt off: |
1da177e4 | 1691 | */ |
148f9bb8 | 1692 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1693 | { |
1462594b | 1694 | if (mca_cfg.disabled) |
4efc0670 AK |
1695 | return; |
1696 | ||
3a97fc34 HS |
1697 | if (__mcheck_cpu_ancient_init(c)) |
1698 | return; | |
4efc0670 | 1699 | |
5b4408fd | 1700 | if (!mce_available(c)) |
1da177e4 LT |
1701 | return; |
1702 | ||
5e09954a | 1703 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1704 | mca_cfg.disabled = true; |
0d7482e3 AK |
1705 | return; |
1706 | } | |
0d7482e3 | 1707 | |
5d727926 AK |
1708 | machine_check_vector = do_machine_check; |
1709 | ||
5e09954a BP |
1710 | __mcheck_cpu_init_generic(); |
1711 | __mcheck_cpu_init_vendor(c); | |
1712 | __mcheck_cpu_init_timer(); | |
9b1beaf2 | 1713 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
b77e70bf | 1714 | init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb); |
1da177e4 LT |
1715 | } |
1716 | ||
1717 | /* | |
93b62c3c | 1718 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1719 | */ |
1720 | ||
93b62c3c HS |
1721 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1722 | static int mce_chrdev_open_count; /* #times opened */ | |
1723 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1724 | |
93b62c3c | 1725 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1726 | { |
93b62c3c | 1727 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1728 | |
93b62c3c HS |
1729 | if (mce_chrdev_open_exclu || |
1730 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1731 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1732 | |
f528e7ba TH |
1733 | return -EBUSY; |
1734 | } | |
1735 | ||
1736 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1737 | mce_chrdev_open_exclu = 1; |
1738 | mce_chrdev_open_count++; | |
f528e7ba | 1739 | |
93b62c3c | 1740 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1741 | |
bd78432c | 1742 | return nonseekable_open(inode, file); |
f528e7ba TH |
1743 | } |
1744 | ||
93b62c3c | 1745 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1746 | { |
93b62c3c | 1747 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1748 | |
93b62c3c HS |
1749 | mce_chrdev_open_count--; |
1750 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1751 | |
93b62c3c | 1752 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1753 | |
1754 | return 0; | |
1755 | } | |
1756 | ||
d88203d1 TG |
1757 | static void collect_tscs(void *data) |
1758 | { | |
1da177e4 | 1759 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1760 | |
1da177e4 | 1761 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1762 | } |
1da177e4 | 1763 | |
482908b4 HY |
1764 | static int mce_apei_read_done; |
1765 | ||
1766 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1767 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1768 | { | |
1769 | int rc; | |
1770 | u64 record_id; | |
1771 | struct mce m; | |
1772 | ||
1773 | if (usize < sizeof(struct mce)) | |
1774 | return -EINVAL; | |
1775 | ||
1776 | rc = apei_read_mce(&m, &record_id); | |
1777 | /* Error or no more MCE record */ | |
1778 | if (rc <= 0) { | |
1779 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1780 | /* |
1781 | * When ERST is disabled, mce_chrdev_read() should return | |
1782 | * "no record" instead of "no device." | |
1783 | */ | |
1784 | if (rc == -ENODEV) | |
1785 | return 0; | |
482908b4 HY |
1786 | return rc; |
1787 | } | |
1788 | rc = -EFAULT; | |
1789 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1790 | return rc; | |
1791 | /* | |
1792 | * In fact, we should have cleared the record after that has | |
1793 | * been flushed to the disk or sent to network in | |
1794 | * /sbin/mcelog, but we have no interface to support that now, | |
1795 | * so just clear it to avoid duplication. | |
1796 | */ | |
1797 | rc = apei_clear_mce(record_id); | |
1798 | if (rc) { | |
1799 | mce_apei_read_done = 1; | |
1800 | return rc; | |
1801 | } | |
1802 | *ubuf += sizeof(struct mce); | |
1803 | ||
1804 | return 0; | |
1805 | } | |
1806 | ||
93b62c3c HS |
1807 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1808 | size_t usize, loff_t *off) | |
1da177e4 | 1809 | { |
e9eee03e | 1810 | char __user *buf = ubuf; |
f0de53bb | 1811 | unsigned long *cpu_tsc; |
ef41df43 | 1812 | unsigned prev, next; |
1da177e4 LT |
1813 | int i, err; |
1814 | ||
6bca67f9 | 1815 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1816 | if (!cpu_tsc) |
1817 | return -ENOMEM; | |
1818 | ||
93b62c3c | 1819 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1820 | |
1821 | if (!mce_apei_read_done) { | |
1822 | err = __mce_read_apei(&buf, usize); | |
1823 | if (err || buf != ubuf) | |
1824 | goto out; | |
1825 | } | |
1826 | ||
f56e8a07 | 1827 | next = rcu_dereference_check_mce(mcelog.next); |
1da177e4 LT |
1828 | |
1829 | /* Only supports full reads right now */ | |
482908b4 HY |
1830 | err = -EINVAL; |
1831 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1832 | goto out; | |
1da177e4 LT |
1833 | |
1834 | err = 0; | |
ef41df43 HY |
1835 | prev = 0; |
1836 | do { | |
1837 | for (i = prev; i < next; i++) { | |
1838 | unsigned long start = jiffies; | |
559faa6b | 1839 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1840 | |
559faa6b | 1841 | while (!m->finished) { |
ef41df43 | 1842 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1843 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1844 | goto timeout; |
1845 | } | |
1846 | cpu_relax(); | |
673242c1 | 1847 | } |
ef41df43 | 1848 | smp_rmb(); |
559faa6b HS |
1849 | err |= copy_to_user(buf, m, sizeof(*m)); |
1850 | buf += sizeof(*m); | |
ef41df43 HY |
1851 | timeout: |
1852 | ; | |
673242c1 | 1853 | } |
1da177e4 | 1854 | |
ef41df43 HY |
1855 | memset(mcelog.entry + prev, 0, |
1856 | (next - prev) * sizeof(struct mce)); | |
1857 | prev = next; | |
1858 | next = cmpxchg(&mcelog.next, prev, 0); | |
1859 | } while (next != prev); | |
1da177e4 | 1860 | |
b2b18660 | 1861 | synchronize_sched(); |
1da177e4 | 1862 | |
d88203d1 TG |
1863 | /* |
1864 | * Collect entries that were still getting written before the | |
1865 | * synchronize. | |
1866 | */ | |
15c8b6c1 | 1867 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1868 | |
d88203d1 | 1869 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1870 | struct mce *m = &mcelog.entry[i]; |
1871 | ||
1872 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1873 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1874 | smp_rmb(); |
559faa6b HS |
1875 | buf += sizeof(*m); |
1876 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1877 | } |
d88203d1 | 1878 | } |
482908b4 HY |
1879 | |
1880 | if (err) | |
1881 | err = -EFAULT; | |
1882 | ||
1883 | out: | |
93b62c3c | 1884 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1885 | kfree(cpu_tsc); |
e9eee03e | 1886 | |
482908b4 | 1887 | return err ? err : buf - ubuf; |
1da177e4 LT |
1888 | } |
1889 | ||
93b62c3c | 1890 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 1891 | { |
93b62c3c | 1892 | poll_wait(file, &mce_chrdev_wait, wait); |
a4dd9925 | 1893 | if (rcu_access_index(mcelog.next)) |
e02e68d3 | 1894 | return POLLIN | POLLRDNORM; |
482908b4 HY |
1895 | if (!mce_apei_read_done && apei_check_mce()) |
1896 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
1897 | return 0; |
1898 | } | |
1899 | ||
93b62c3c HS |
1900 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
1901 | unsigned long arg) | |
1da177e4 LT |
1902 | { |
1903 | int __user *p = (int __user *)arg; | |
d88203d1 | 1904 | |
1da177e4 | 1905 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1906 | return -EPERM; |
e9eee03e | 1907 | |
1da177e4 | 1908 | switch (cmd) { |
d88203d1 | 1909 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1910 | return put_user(sizeof(struct mce), p); |
1911 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1912 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1913 | case MCE_GETCLEAR_FLAGS: { |
1914 | unsigned flags; | |
d88203d1 TG |
1915 | |
1916 | do { | |
1da177e4 | 1917 | flags = mcelog.flags; |
d88203d1 | 1918 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1919 | |
d88203d1 | 1920 | return put_user(flags, p); |
1da177e4 LT |
1921 | } |
1922 | default: | |
d88203d1 TG |
1923 | return -ENOTTY; |
1924 | } | |
1da177e4 LT |
1925 | } |
1926 | ||
66f5ddf3 LT |
1927 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
1928 | size_t usize, loff_t *off); | |
1929 | ||
1930 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
1931 | const char __user *ubuf, | |
1932 | size_t usize, loff_t *off)) | |
1933 | { | |
1934 | mce_write = fn; | |
1935 | } | |
1936 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
1937 | ||
1938 | ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, | |
1939 | size_t usize, loff_t *off) | |
1940 | { | |
1941 | if (mce_write) | |
1942 | return mce_write(filp, ubuf, usize, off); | |
1943 | else | |
1944 | return -EINVAL; | |
1945 | } | |
1946 | ||
1947 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
1948 | .open = mce_chrdev_open, |
1949 | .release = mce_chrdev_release, | |
1950 | .read = mce_chrdev_read, | |
66f5ddf3 | 1951 | .write = mce_chrdev_write, |
93b62c3c HS |
1952 | .poll = mce_chrdev_poll, |
1953 | .unlocked_ioctl = mce_chrdev_ioctl, | |
1954 | .llseek = no_llseek, | |
1da177e4 LT |
1955 | }; |
1956 | ||
93b62c3c | 1957 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
1958 | MISC_MCELOG_MINOR, |
1959 | "mcelog", | |
1960 | &mce_chrdev_ops, | |
1961 | }; | |
1962 | ||
c3d1fb56 NR |
1963 | static void __mce_disable_bank(void *arg) |
1964 | { | |
1965 | int bank = *((int *)arg); | |
1966 | __clear_bit(bank, __get_cpu_var(mce_poll_banks)); | |
1967 | cmci_disable_bank(bank); | |
1968 | } | |
1969 | ||
1970 | void mce_disable_bank(int bank) | |
1971 | { | |
1972 | if (bank >= mca_cfg.banks) { | |
1973 | pr_warn(FW_BUG | |
1974 | "Ignoring request to disable invalid MCA bank %d.\n", | |
1975 | bank); | |
1976 | return; | |
1977 | } | |
1978 | set_bit(bank, mce_banks_ce_disabled); | |
1979 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
1980 | } | |
1981 | ||
13503fa9 | 1982 | /* |
62fdac59 HS |
1983 | * mce=off Disables machine check |
1984 | * mce=no_cmci Disables CMCI | |
1985 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1986 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1987 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1988 | * monarchtimeout is how long to wait for other CPUs on machine | |
1989 | * check, or 0 to not wait | |
13503fa9 HS |
1990 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1991 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 1992 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
13503fa9 | 1993 | */ |
1da177e4 LT |
1994 | static int __init mcheck_enable(char *str) |
1995 | { | |
d203f0b8 BP |
1996 | struct mca_config *cfg = &mca_cfg; |
1997 | ||
e3346fc4 | 1998 | if (*str == 0) { |
4efc0670 | 1999 | enable_p5_mce(); |
e3346fc4 BZ |
2000 | return 1; |
2001 | } | |
4efc0670 AK |
2002 | if (*str == '=') |
2003 | str++; | |
1da177e4 | 2004 | if (!strcmp(str, "off")) |
1462594b | 2005 | cfg->disabled = true; |
62fdac59 | 2006 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2007 | cfg->cmci_disabled = true; |
62fdac59 | 2008 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2009 | cfg->dont_log_ce = true; |
62fdac59 | 2010 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2011 | cfg->ignore_ce = true; |
13503fa9 | 2012 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2013 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2014 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2015 | cfg->bios_cmci_threshold = true; |
3c079792 | 2016 | else if (isdigit(str[0])) { |
d203f0b8 | 2017 | get_option(&str, &(cfg->tolerant)); |
3c079792 AK |
2018 | if (*str == ',') { |
2019 | ++str; | |
84c2559d | 2020 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 AK |
2021 | } |
2022 | } else { | |
c767a54b | 2023 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2024 | return 0; |
2025 | } | |
9b41046c | 2026 | return 1; |
1da177e4 | 2027 | } |
4efc0670 | 2028 | __setup("mce", mcheck_enable); |
1da177e4 | 2029 | |
a2202aa2 | 2030 | int __init mcheck_init(void) |
b33a6363 | 2031 | { |
a2202aa2 YW |
2032 | mcheck_intel_therm_init(); |
2033 | ||
b33a6363 BP |
2034 | return 0; |
2035 | } | |
b33a6363 | 2036 | |
d88203d1 | 2037 | /* |
c7cece89 | 2038 | * mce_syscore: PM support |
d88203d1 | 2039 | */ |
1da177e4 | 2040 | |
973a2dd1 AK |
2041 | /* |
2042 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2043 | * them later. | |
2044 | */ | |
5e09954a | 2045 | static int mce_disable_error_reporting(void) |
973a2dd1 AK |
2046 | { |
2047 | int i; | |
2048 | ||
d203f0b8 | 2049 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2050 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2051 | |
cebe1820 | 2052 | if (b->init) |
a2d32bcb | 2053 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2054 | } |
973a2dd1 AK |
2055 | return 0; |
2056 | } | |
2057 | ||
c7cece89 | 2058 | static int mce_syscore_suspend(void) |
973a2dd1 | 2059 | { |
5e09954a | 2060 | return mce_disable_error_reporting(); |
973a2dd1 AK |
2061 | } |
2062 | ||
c7cece89 | 2063 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2064 | { |
f3c6ea1b | 2065 | mce_disable_error_reporting(); |
973a2dd1 AK |
2066 | } |
2067 | ||
e9eee03e IM |
2068 | /* |
2069 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2070 | * Only one CPU is active at this time, the others get re-added later using | |
2071 | * CPU hotplug: | |
2072 | */ | |
c7cece89 | 2073 | static void mce_syscore_resume(void) |
1da177e4 | 2074 | { |
5e09954a | 2075 | __mcheck_cpu_init_generic(); |
7b543a53 | 2076 | __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info)); |
1da177e4 LT |
2077 | } |
2078 | ||
f3c6ea1b | 2079 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2080 | .suspend = mce_syscore_suspend, |
2081 | .shutdown = mce_syscore_shutdown, | |
2082 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2083 | }; |
2084 | ||
c7cece89 | 2085 | /* |
8a25a2fd | 2086 | * mce_device: Sysfs support |
c7cece89 HS |
2087 | */ |
2088 | ||
52d168e2 AK |
2089 | static void mce_cpu_restart(void *data) |
2090 | { | |
7b543a53 | 2091 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
33edbf02 | 2092 | return; |
5e09954a BP |
2093 | __mcheck_cpu_init_generic(); |
2094 | __mcheck_cpu_init_timer(); | |
52d168e2 AK |
2095 | } |
2096 | ||
1da177e4 | 2097 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2098 | static void mce_restart(void) |
2099 | { | |
9aaef96f | 2100 | mce_timer_delete_all(); |
52d168e2 | 2101 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2102 | } |
2103 | ||
9af43b54 | 2104 | /* Toggle features for corrected errors */ |
9aaef96f | 2105 | static void mce_disable_cmci(void *data) |
9af43b54 | 2106 | { |
7b543a53 | 2107 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 | 2108 | return; |
9af43b54 HS |
2109 | cmci_clear(); |
2110 | } | |
2111 | ||
2112 | static void mce_enable_ce(void *all) | |
2113 | { | |
7b543a53 | 2114 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2115 | return; |
2116 | cmci_reenable(); | |
2117 | cmci_recheck(); | |
2118 | if (all) | |
5e09954a | 2119 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2120 | } |
2121 | ||
8a25a2fd | 2122 | static struct bus_type mce_subsys = { |
e9eee03e | 2123 | .name = "machinecheck", |
8a25a2fd | 2124 | .dev_name = "machinecheck", |
1da177e4 LT |
2125 | }; |
2126 | ||
d6126ef5 | 2127 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2128 | |
e9eee03e | 2129 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); |
1da177e4 | 2130 | |
8a25a2fd | 2131 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2132 | { |
2133 | return container_of(attr, struct mce_bank, attr); | |
2134 | } | |
0d7482e3 | 2135 | |
8a25a2fd | 2136 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2137 | char *buf) |
2138 | { | |
cebe1820 | 2139 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2140 | } |
2141 | ||
8a25a2fd | 2142 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2143 | const char *buf, size_t size) |
0d7482e3 | 2144 | { |
9319cec8 | 2145 | u64 new; |
e9eee03e | 2146 | |
9319cec8 | 2147 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 2148 | return -EINVAL; |
e9eee03e | 2149 | |
cebe1820 | 2150 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2151 | mce_restart(); |
e9eee03e | 2152 | |
9319cec8 | 2153 | return size; |
0d7482e3 | 2154 | } |
a98f0dd3 | 2155 | |
e9eee03e | 2156 | static ssize_t |
8a25a2fd | 2157 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2158 | { |
1020bcbc | 2159 | strcpy(buf, mce_helper); |
a98f0dd3 | 2160 | strcat(buf, "\n"); |
1020bcbc | 2161 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2162 | } |
2163 | ||
8a25a2fd | 2164 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2165 | const char *buf, size_t siz) |
a98f0dd3 AK |
2166 | { |
2167 | char *p; | |
e9eee03e | 2168 | |
1020bcbc HS |
2169 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2170 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2171 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2172 | |
e9084ec9 | 2173 | if (p) |
e9eee03e IM |
2174 | *p = 0; |
2175 | ||
e9084ec9 | 2176 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2177 | } |
2178 | ||
8a25a2fd KS |
2179 | static ssize_t set_ignore_ce(struct device *s, |
2180 | struct device_attribute *attr, | |
9af43b54 HS |
2181 | const char *buf, size_t size) |
2182 | { | |
2183 | u64 new; | |
2184 | ||
2185 | if (strict_strtoull(buf, 0, &new) < 0) | |
2186 | return -EINVAL; | |
2187 | ||
7af19e4a | 2188 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2189 | if (new) { |
2190 | /* disable ce features */ | |
9aaef96f HS |
2191 | mce_timer_delete_all(); |
2192 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2193 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2194 | } else { |
2195 | /* enable ce features */ | |
7af19e4a | 2196 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2197 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2198 | } | |
2199 | } | |
2200 | return size; | |
2201 | } | |
2202 | ||
8a25a2fd KS |
2203 | static ssize_t set_cmci_disabled(struct device *s, |
2204 | struct device_attribute *attr, | |
9af43b54 HS |
2205 | const char *buf, size_t size) |
2206 | { | |
2207 | u64 new; | |
2208 | ||
2209 | if (strict_strtoull(buf, 0, &new) < 0) | |
2210 | return -EINVAL; | |
2211 | ||
7af19e4a | 2212 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2213 | if (new) { |
2214 | /* disable cmci */ | |
9aaef96f | 2215 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2216 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2217 | } else { |
2218 | /* enable cmci */ | |
7af19e4a | 2219 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2220 | on_each_cpu(mce_enable_ce, NULL, 1); |
2221 | } | |
2222 | } | |
2223 | return size; | |
2224 | } | |
2225 | ||
8a25a2fd KS |
2226 | static ssize_t store_int_with_restart(struct device *s, |
2227 | struct device_attribute *attr, | |
b56f642d AK |
2228 | const char *buf, size_t size) |
2229 | { | |
8a25a2fd | 2230 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2231 | mce_restart(); |
2232 | return ret; | |
2233 | } | |
2234 | ||
8a25a2fd | 2235 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2236 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2237 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2238 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2239 | |
8a25a2fd KS |
2240 | static struct dev_ext_attribute dev_attr_check_interval = { |
2241 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2242 | &check_interval |
2243 | }; | |
e9eee03e | 2244 | |
8a25a2fd | 2245 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2246 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2247 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2248 | }; |
2249 | ||
8a25a2fd | 2250 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2251 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2252 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2253 | }; |
2254 | ||
8a25a2fd KS |
2255 | static struct device_attribute *mce_device_attrs[] = { |
2256 | &dev_attr_tolerant.attr, | |
2257 | &dev_attr_check_interval.attr, | |
2258 | &dev_attr_trigger, | |
2259 | &dev_attr_monarch_timeout.attr, | |
2260 | &dev_attr_dont_log_ce.attr, | |
2261 | &dev_attr_ignore_ce.attr, | |
2262 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2263 | NULL |
2264 | }; | |
1da177e4 | 2265 | |
8a25a2fd | 2266 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2267 | |
e032d807 GKH |
2268 | static void mce_device_release(struct device *dev) |
2269 | { | |
2270 | kfree(dev); | |
2271 | } | |
2272 | ||
8a25a2fd | 2273 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2274 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2275 | { |
e032d807 | 2276 | struct device *dev; |
1da177e4 | 2277 | int err; |
b1f49f95 | 2278 | int i, j; |
92cb7612 | 2279 | |
90367556 | 2280 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2281 | return -EIO; |
2282 | ||
e032d807 GKH |
2283 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2284 | if (!dev) | |
2285 | return -ENOMEM; | |
8a25a2fd KS |
2286 | dev->id = cpu; |
2287 | dev->bus = &mce_subsys; | |
e032d807 | 2288 | dev->release = &mce_device_release; |
91c6d400 | 2289 | |
8a25a2fd | 2290 | err = device_register(dev); |
853d9b18 LK |
2291 | if (err) { |
2292 | put_device(dev); | |
d435d862 | 2293 | return err; |
853d9b18 | 2294 | } |
d435d862 | 2295 | |
8a25a2fd KS |
2296 | for (i = 0; mce_device_attrs[i]; i++) { |
2297 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2298 | if (err) |
2299 | goto error; | |
2300 | } | |
d203f0b8 | 2301 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2302 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2303 | if (err) |
2304 | goto error2; | |
2305 | } | |
8a25a2fd | 2306 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2307 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2308 | |
d435d862 | 2309 | return 0; |
0d7482e3 | 2310 | error2: |
b1f49f95 | 2311 | while (--j >= 0) |
8a25a2fd | 2312 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2313 | error: |
cb491fca | 2314 | while (--i >= 0) |
8a25a2fd | 2315 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2316 | |
8a25a2fd | 2317 | device_unregister(dev); |
d435d862 | 2318 | |
91c6d400 AK |
2319 | return err; |
2320 | } | |
2321 | ||
148f9bb8 | 2322 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2323 | { |
d6126ef5 | 2324 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2325 | int i; |
2326 | ||
8a25a2fd | 2327 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2328 | return; |
2329 | ||
8a25a2fd KS |
2330 | for (i = 0; mce_device_attrs[i]; i++) |
2331 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2332 | |
d203f0b8 | 2333 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2334 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2335 | |
8a25a2fd KS |
2336 | device_unregister(dev); |
2337 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2338 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2339 | } |
91c6d400 | 2340 | |
d6b75584 | 2341 | /* Make sure there are no machine checks on offlined CPUs. */ |
148f9bb8 | 2342 | static void mce_disable_cpu(void *h) |
d6b75584 | 2343 | { |
88ccbedd | 2344 | unsigned long action = *(unsigned long *)h; |
cb491fca | 2345 | int i; |
d6b75584 | 2346 | |
7b543a53 | 2347 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2348 | return; |
767df1bd | 2349 | |
88ccbedd AK |
2350 | if (!(action & CPU_TASKS_FROZEN)) |
2351 | cmci_clear(); | |
d203f0b8 | 2352 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2353 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2354 | |
cebe1820 | 2355 | if (b->init) |
a2d32bcb | 2356 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 2357 | } |
d6b75584 AK |
2358 | } |
2359 | ||
148f9bb8 | 2360 | static void mce_reenable_cpu(void *h) |
d6b75584 | 2361 | { |
88ccbedd | 2362 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 2363 | int i; |
d6b75584 | 2364 | |
7b543a53 | 2365 | if (!mce_available(__this_cpu_ptr(&cpu_info))) |
d6b75584 | 2366 | return; |
e9eee03e | 2367 | |
88ccbedd AK |
2368 | if (!(action & CPU_TASKS_FROZEN)) |
2369 | cmci_reenable(); | |
d203f0b8 | 2370 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2371 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2372 | |
cebe1820 | 2373 | if (b->init) |
a2d32bcb | 2374 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 2375 | } |
d6b75584 AK |
2376 | } |
2377 | ||
91c6d400 | 2378 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
148f9bb8 | 2379 | static int |
e9eee03e | 2380 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) |
91c6d400 AK |
2381 | { |
2382 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 2383 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 | 2384 | |
1a65f970 | 2385 | switch (action & ~CPU_TASKS_FROZEN) { |
bae19fe0 | 2386 | case CPU_ONLINE: |
8a25a2fd | 2387 | mce_device_create(cpu); |
8735728e RW |
2388 | if (threshold_cpu_callback) |
2389 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 2390 | break; |
91c6d400 | 2391 | case CPU_DEAD: |
8735728e RW |
2392 | if (threshold_cpu_callback) |
2393 | threshold_cpu_callback(action, cpu); | |
8a25a2fd | 2394 | mce_device_remove(cpu); |
55babd8f | 2395 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2396 | break; |
52d168e2 | 2397 | case CPU_DOWN_PREPARE: |
88ccbedd | 2398 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
55babd8f | 2399 | del_timer_sync(t); |
52d168e2 AK |
2400 | break; |
2401 | case CPU_DOWN_FAILED: | |
88ccbedd | 2402 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
26c3c283 | 2403 | mce_start_timer(cpu, t); |
88ccbedd | 2404 | break; |
1a65f970 TG |
2405 | } |
2406 | ||
2407 | if (action == CPU_POST_DEAD) { | |
88ccbedd | 2408 | /* intentionally ignoring frozen here */ |
7a0c819d | 2409 | cmci_rediscover(); |
91c6d400 | 2410 | } |
1a65f970 | 2411 | |
bae19fe0 | 2412 | return NOTIFY_OK; |
91c6d400 AK |
2413 | } |
2414 | ||
148f9bb8 | 2415 | static struct notifier_block mce_cpu_notifier = { |
91c6d400 AK |
2416 | .notifier_call = mce_cpu_callback, |
2417 | }; | |
2418 | ||
cebe1820 | 2419 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2420 | { |
2421 | int i; | |
2422 | ||
d203f0b8 | 2423 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2424 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2425 | struct device_attribute *a = &b->attr; |
e9eee03e | 2426 | |
a07e4156 | 2427 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2428 | a->attr.name = b->attrname; |
2429 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2430 | |
2431 | a->attr.mode = 0644; | |
2432 | a->show = show_bank; | |
2433 | a->store = set_bank; | |
0d7482e3 | 2434 | } |
0d7482e3 AK |
2435 | } |
2436 | ||
5e09954a | 2437 | static __init int mcheck_init_device(void) |
91c6d400 AK |
2438 | { |
2439 | int err; | |
2440 | int i = 0; | |
2441 | ||
1da177e4 LT |
2442 | if (!mce_available(&boot_cpu_data)) |
2443 | return -EIO; | |
0d7482e3 | 2444 | |
8a25a2fd | 2445 | zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL); |
996867d0 | 2446 | |
cebe1820 | 2447 | mce_init_banks(); |
0d7482e3 | 2448 | |
8a25a2fd | 2449 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 AM |
2450 | if (err) |
2451 | return err; | |
91c6d400 | 2452 | |
82a8f131 | 2453 | cpu_notifier_register_begin(); |
91c6d400 | 2454 | for_each_online_cpu(i) { |
8a25a2fd | 2455 | err = mce_device_create(i); |
82a8f131 SB |
2456 | if (err) { |
2457 | cpu_notifier_register_done(); | |
d435d862 | 2458 | return err; |
82a8f131 | 2459 | } |
91c6d400 AK |
2460 | } |
2461 | ||
f3c6ea1b | 2462 | register_syscore_ops(&mce_syscore_ops); |
82a8f131 SB |
2463 | __register_hotcpu_notifier(&mce_cpu_notifier); |
2464 | cpu_notifier_register_done(); | |
93b62c3c HS |
2465 | |
2466 | /* register character device /dev/mcelog */ | |
2467 | misc_register(&mce_chrdev_device); | |
e9eee03e | 2468 | |
1da177e4 | 2469 | return err; |
1da177e4 | 2470 | } |
cef12ee5 | 2471 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2472 | |
d7c3c9a6 AK |
2473 | /* |
2474 | * Old style boot options parsing. Only for compatibility. | |
2475 | */ | |
2476 | static int __init mcheck_disable(char *str) | |
2477 | { | |
1462594b | 2478 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2479 | return 1; |
2480 | } | |
2481 | __setup("nomce", mcheck_disable); | |
a988d334 | 2482 | |
5be9ed25 HY |
2483 | #ifdef CONFIG_DEBUG_FS |
2484 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2485 | { |
5be9ed25 | 2486 | static struct dentry *dmce; |
a988d334 | 2487 | |
5be9ed25 HY |
2488 | if (!dmce) |
2489 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2490 | |
5be9ed25 HY |
2491 | return dmce; |
2492 | } | |
a988d334 | 2493 | |
bf783f9f HY |
2494 | static void mce_reset(void) |
2495 | { | |
2496 | cpu_missing = 0; | |
2497 | atomic_set(&mce_fake_paniced, 0); | |
2498 | atomic_set(&mce_executing, 0); | |
2499 | atomic_set(&mce_callin, 0); | |
2500 | atomic_set(&global_nwo, 0); | |
2501 | } | |
a988d334 | 2502 | |
bf783f9f HY |
2503 | static int fake_panic_get(void *data, u64 *val) |
2504 | { | |
2505 | *val = fake_panic; | |
2506 | return 0; | |
a988d334 IM |
2507 | } |
2508 | ||
bf783f9f | 2509 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2510 | { |
bf783f9f HY |
2511 | mce_reset(); |
2512 | fake_panic = val; | |
2513 | return 0; | |
a988d334 | 2514 | } |
a988d334 | 2515 | |
bf783f9f HY |
2516 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2517 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2518 | |
5e09954a | 2519 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2520 | { |
bf783f9f HY |
2521 | struct dentry *dmce, *ffake_panic; |
2522 | ||
2523 | dmce = mce_get_debugfs_dir(); | |
2524 | if (!dmce) | |
2525 | return -ENOMEM; | |
2526 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2527 | &fake_panic_fops); | |
2528 | if (!ffake_panic) | |
2529 | return -ENOMEM; | |
2530 | ||
2531 | return 0; | |
d7c3c9a6 | 2532 | } |
5e09954a | 2533 | late_initcall(mcheck_debugfs_init); |
5be9ed25 | 2534 | #endif |