Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
e9eee03e IM |
10 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | |
12 | #include <linux/miscdevice.h> | |
ccc3c319 | 13 | #include <linux/interrupt.h> |
e9eee03e IM |
14 | #include <linux/ratelimit.h> |
15 | #include <linux/kallsyms.h> | |
16 | #include <linux/rcupdate.h> | |
e9eee03e | 17 | #include <linux/kobject.h> |
14a02530 | 18 | #include <linux/uaccess.h> |
e9eee03e IM |
19 | #include <linux/kdebug.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/percpu.h> | |
1da177e4 | 22 | #include <linux/string.h> |
1da177e4 | 23 | #include <linux/sysdev.h> |
3c079792 | 24 | #include <linux/delay.h> |
8c566ef5 | 25 | #include <linux/ctype.h> |
e9eee03e | 26 | #include <linux/sched.h> |
0d7482e3 | 27 | #include <linux/sysfs.h> |
e9eee03e IM |
28 | #include <linux/types.h> |
29 | #include <linux/init.h> | |
30 | #include <linux/kmod.h> | |
31 | #include <linux/poll.h> | |
3c079792 | 32 | #include <linux/nmi.h> |
e9eee03e | 33 | #include <linux/cpu.h> |
14a02530 | 34 | #include <linux/smp.h> |
e9eee03e | 35 | #include <linux/fs.h> |
9b1beaf2 | 36 | #include <linux/mm.h> |
5be9ed25 | 37 | #include <linux/debugfs.h> |
e9eee03e | 38 | |
d88203d1 | 39 | #include <asm/processor.h> |
ccc3c319 AK |
40 | #include <asm/hw_irq.h> |
41 | #include <asm/apic.h> | |
e02e68d3 | 42 | #include <asm/idle.h> |
ccc3c319 | 43 | #include <asm/ipi.h> |
e9eee03e IM |
44 | #include <asm/mce.h> |
45 | #include <asm/msr.h> | |
1da177e4 | 46 | |
bd19a5e6 | 47 | #include "mce-internal.h" |
711c2e48 | 48 | |
4e5b3e69 | 49 | int mce_disabled __read_mostly; |
04b2b1a4 | 50 | |
e9eee03e | 51 | #define MISC_MCELOG_MINOR 227 |
0d7482e3 | 52 | |
3c079792 AK |
53 | #define SPINUNIT 100 /* 100ns */ |
54 | ||
553f265f AK |
55 | atomic_t mce_entry; |
56 | ||
01ca79f1 AK |
57 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
58 | ||
bd78432c TH |
59 | /* |
60 | * Tolerant levels: | |
61 | * 0: always panic on uncorrected errors, log corrected errors | |
62 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
63 | * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors | |
64 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
65 | */ | |
4e5b3e69 HS |
66 | static int tolerant __read_mostly = 1; |
67 | static int banks __read_mostly; | |
4e5b3e69 HS |
68 | static int rip_msr __read_mostly; |
69 | static int mce_bootlog __read_mostly = -1; | |
70 | static int monarch_timeout __read_mostly = -1; | |
71 | static int mce_panic_timeout __read_mostly; | |
72 | static int mce_dont_log_ce __read_mostly; | |
73 | int mce_cmci_disabled __read_mostly; | |
74 | int mce_ignore_ce __read_mostly; | |
75 | int mce_ser __read_mostly; | |
a98f0dd3 | 76 | |
cebe1820 AK |
77 | struct mce_bank *mce_banks __read_mostly; |
78 | ||
1020bcbc HS |
79 | /* User mode helper program triggered by machine check event */ |
80 | static unsigned long mce_need_notify; | |
81 | static char mce_helper[128]; | |
82 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 83 | |
e02e68d3 | 84 | static DECLARE_WAIT_QUEUE_HEAD(mce_wait); |
3c079792 AK |
85 | static DEFINE_PER_CPU(struct mce, mces_seen); |
86 | static int cpu_missing; | |
87 | ||
e02e68d3 | 88 | |
ee031c31 AK |
89 | /* MCA banks polled by the period polling timer for corrected events */ |
90 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | |
91 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
92 | }; | |
93 | ||
9b1beaf2 AK |
94 | static DEFINE_PER_CPU(struct work_struct, mce_work); |
95 | ||
b5f2fa4e AK |
96 | /* Do initial initialization of a struct mce */ |
97 | void mce_setup(struct mce *m) | |
98 | { | |
99 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 100 | m->cpu = m->extcpu = smp_processor_id(); |
b5f2fa4e | 101 | rdtscll(m->tsc); |
8ee08347 AK |
102 | /* We hope get_seconds stays lockless */ |
103 | m->time = get_seconds(); | |
104 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
105 | m->cpuid = cpuid_eax(1); | |
106 | #ifdef CONFIG_SMP | |
107 | m->socketid = cpu_data(m->extcpu).phys_proc_id; | |
108 | #endif | |
109 | m->apicid = cpu_data(m->extcpu).initial_apicid; | |
110 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
111 | } |
112 | ||
ea149b36 AK |
113 | DEFINE_PER_CPU(struct mce, injectm); |
114 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
115 | ||
1da177e4 LT |
116 | /* |
117 | * Lockless MCE logging infrastructure. | |
118 | * This avoids deadlocks on printk locks without having to break locks. Also | |
119 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
120 | */ | |
121 | ||
231fd906 | 122 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
123 | .signature = MCE_LOG_SIGNATURE, |
124 | .len = MCE_LOG_LEN, | |
125 | .recordlen = sizeof(struct mce), | |
d88203d1 | 126 | }; |
1da177e4 LT |
127 | |
128 | void mce_log(struct mce *mce) | |
129 | { | |
130 | unsigned next, entry; | |
e9eee03e | 131 | |
1da177e4 | 132 | mce->finished = 0; |
7644143c | 133 | wmb(); |
1da177e4 LT |
134 | for (;;) { |
135 | entry = rcu_dereference(mcelog.next); | |
673242c1 | 136 | for (;;) { |
e9eee03e IM |
137 | /* |
138 | * When the buffer fills up discard new entries. | |
139 | * Assume that the earlier errors are the more | |
140 | * interesting ones: | |
141 | */ | |
673242c1 | 142 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
143 | set_bit(MCE_OVERFLOW, |
144 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
145 | return; |
146 | } | |
e9eee03e | 147 | /* Old left over entry. Skip: */ |
673242c1 AK |
148 | if (mcelog.entry[entry].finished) { |
149 | entry++; | |
150 | continue; | |
151 | } | |
7644143c | 152 | break; |
1da177e4 | 153 | } |
1da177e4 LT |
154 | smp_rmb(); |
155 | next = entry + 1; | |
156 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
157 | break; | |
158 | } | |
159 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 160 | wmb(); |
1da177e4 | 161 | mcelog.entry[entry].finished = 1; |
7644143c | 162 | wmb(); |
1da177e4 | 163 | |
a0189c70 | 164 | mce->finished = 1; |
1020bcbc | 165 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
166 | } |
167 | ||
549d042d BP |
168 | void __weak decode_mce(struct mce *m) |
169 | { | |
170 | return; | |
171 | } | |
172 | ||
77e26cca | 173 | static void print_mce(struct mce *m) |
1da177e4 | 174 | { |
86503560 | 175 | printk(KERN_EMERG |
1da177e4 | 176 | "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n", |
d620c67f | 177 | m->extcpu, m->mcgstatus, m->bank, m->status); |
65ea5b03 | 178 | if (m->ip) { |
d88203d1 | 179 | printk(KERN_EMERG "RIP%s %02x:<%016Lx> ", |
1da177e4 | 180 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
65ea5b03 | 181 | m->cs, m->ip); |
1da177e4 | 182 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 183 | print_symbol("{%s}", m->ip); |
ad361c98 | 184 | printk(KERN_CONT "\n"); |
1da177e4 | 185 | } |
f6d1826d | 186 | printk(KERN_EMERG "TSC %llx ", m->tsc); |
1da177e4 | 187 | if (m->addr) |
ad361c98 | 188 | printk(KERN_CONT "ADDR %llx ", m->addr); |
1da177e4 | 189 | if (m->misc) |
ad361c98 JP |
190 | printk(KERN_CONT "MISC %llx ", m->misc); |
191 | printk(KERN_CONT "\n"); | |
8ee08347 AK |
192 | printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n", |
193 | m->cpuvendor, m->cpuid, m->time, m->socketid, | |
194 | m->apicid); | |
549d042d BP |
195 | |
196 | decode_mce(m); | |
86503560 AK |
197 | } |
198 | ||
77e26cca HS |
199 | static void print_mce_head(void) |
200 | { | |
ad361c98 | 201 | printk(KERN_EMERG "\nHARDWARE ERROR\n"); |
77e26cca HS |
202 | } |
203 | ||
86503560 AK |
204 | static void print_mce_tail(void) |
205 | { | |
206 | printk(KERN_EMERG "This is not a software problem!\n" | |
22223c9b BP |
207 | #if (!defined(CONFIG_EDAC) || !defined(CONFIG_CPU_SUP_AMD)) |
208 | "Run through mcelog --ascii to decode and contact your hardware vendor\n" | |
209 | #endif | |
210 | ); | |
1da177e4 LT |
211 | } |
212 | ||
f94b61c2 AK |
213 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
214 | ||
215 | static atomic_t mce_paniced; | |
216 | ||
bf783f9f HY |
217 | static int fake_panic; |
218 | static atomic_t mce_fake_paniced; | |
219 | ||
f94b61c2 AK |
220 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
221 | static void wait_for_panic(void) | |
222 | { | |
223 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
224 | preempt_disable(); | |
225 | local_irq_enable(); | |
226 | while (timeout-- > 0) | |
227 | udelay(1); | |
29b0f591 AK |
228 | if (panic_timeout == 0) |
229 | panic_timeout = mce_panic_timeout; | |
f94b61c2 AK |
230 | panic("Panicing machine check CPU died"); |
231 | } | |
232 | ||
bd19a5e6 | 233 | static void mce_panic(char *msg, struct mce *final, char *exp) |
d88203d1 | 234 | { |
1da177e4 | 235 | int i; |
e02e68d3 | 236 | |
bf783f9f HY |
237 | if (!fake_panic) { |
238 | /* | |
239 | * Make sure only one CPU runs in machine check panic | |
240 | */ | |
241 | if (atomic_inc_return(&mce_paniced) > 1) | |
242 | wait_for_panic(); | |
243 | barrier(); | |
f94b61c2 | 244 | |
bf783f9f HY |
245 | bust_spinlocks(1); |
246 | console_verbose(); | |
247 | } else { | |
248 | /* Don't log too much for fake panic */ | |
249 | if (atomic_inc_return(&mce_fake_paniced) > 1) | |
250 | return; | |
251 | } | |
77e26cca | 252 | print_mce_head(); |
a0189c70 | 253 | /* First print corrected ones that are still unlogged */ |
1da177e4 | 254 | for (i = 0; i < MCE_LOG_LEN; i++) { |
a0189c70 | 255 | struct mce *m = &mcelog.entry[i]; |
77e26cca HS |
256 | if (!(m->status & MCI_STATUS_VAL)) |
257 | continue; | |
258 | if (!(m->status & MCI_STATUS_UC)) | |
259 | print_mce(m); | |
a0189c70 AK |
260 | } |
261 | /* Now print uncorrected but with the final one last */ | |
262 | for (i = 0; i < MCE_LOG_LEN; i++) { | |
263 | struct mce *m = &mcelog.entry[i]; | |
264 | if (!(m->status & MCI_STATUS_VAL)) | |
1da177e4 | 265 | continue; |
77e26cca HS |
266 | if (!(m->status & MCI_STATUS_UC)) |
267 | continue; | |
a0189c70 | 268 | if (!final || memcmp(m, final, sizeof(struct mce))) |
77e26cca | 269 | print_mce(m); |
1da177e4 | 270 | } |
a0189c70 | 271 | if (final) |
77e26cca | 272 | print_mce(final); |
3c079792 AK |
273 | if (cpu_missing) |
274 | printk(KERN_EMERG "Some CPUs didn't answer in synchronization\n"); | |
86503560 | 275 | print_mce_tail(); |
bd19a5e6 AK |
276 | if (exp) |
277 | printk(KERN_EMERG "Machine check: %s\n", exp); | |
bf783f9f HY |
278 | if (!fake_panic) { |
279 | if (panic_timeout == 0) | |
280 | panic_timeout = mce_panic_timeout; | |
281 | panic(msg); | |
282 | } else | |
283 | printk(KERN_EMERG "Fake kernel panic: %s\n", msg); | |
d88203d1 | 284 | } |
1da177e4 | 285 | |
ea149b36 AK |
286 | /* Support code for software error injection */ |
287 | ||
288 | static int msr_to_offset(u32 msr) | |
289 | { | |
290 | unsigned bank = __get_cpu_var(injectm.bank); | |
291 | if (msr == rip_msr) | |
292 | return offsetof(struct mce, ip); | |
a2d32bcb | 293 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
ea149b36 | 294 | return offsetof(struct mce, status); |
a2d32bcb | 295 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
ea149b36 | 296 | return offsetof(struct mce, addr); |
a2d32bcb | 297 | if (msr == MSR_IA32_MCx_MISC(bank)) |
ea149b36 AK |
298 | return offsetof(struct mce, misc); |
299 | if (msr == MSR_IA32_MCG_STATUS) | |
300 | return offsetof(struct mce, mcgstatus); | |
301 | return -1; | |
302 | } | |
303 | ||
5f8c1a54 AK |
304 | /* MSR access wrappers used for error injection */ |
305 | static u64 mce_rdmsrl(u32 msr) | |
306 | { | |
307 | u64 v; | |
ea149b36 AK |
308 | if (__get_cpu_var(injectm).finished) { |
309 | int offset = msr_to_offset(msr); | |
310 | if (offset < 0) | |
311 | return 0; | |
312 | return *(u64 *)((char *)&__get_cpu_var(injectm) + offset); | |
313 | } | |
5f8c1a54 AK |
314 | rdmsrl(msr, v); |
315 | return v; | |
316 | } | |
317 | ||
318 | static void mce_wrmsrl(u32 msr, u64 v) | |
319 | { | |
ea149b36 AK |
320 | if (__get_cpu_var(injectm).finished) { |
321 | int offset = msr_to_offset(msr); | |
322 | if (offset >= 0) | |
323 | *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v; | |
324 | return; | |
325 | } | |
5f8c1a54 AK |
326 | wrmsrl(msr, v); |
327 | } | |
328 | ||
9b1beaf2 AK |
329 | /* |
330 | * Simple lockless ring to communicate PFNs from the exception handler with the | |
331 | * process context work function. This is vastly simplified because there's | |
332 | * only a single reader and a single writer. | |
333 | */ | |
334 | #define MCE_RING_SIZE 16 /* we use one entry less */ | |
335 | ||
336 | struct mce_ring { | |
337 | unsigned short start; | |
338 | unsigned short end; | |
339 | unsigned long ring[MCE_RING_SIZE]; | |
340 | }; | |
341 | static DEFINE_PER_CPU(struct mce_ring, mce_ring); | |
342 | ||
343 | /* Runs with CPU affinity in workqueue */ | |
344 | static int mce_ring_empty(void) | |
345 | { | |
346 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
347 | ||
348 | return r->start == r->end; | |
349 | } | |
350 | ||
351 | static int mce_ring_get(unsigned long *pfn) | |
352 | { | |
353 | struct mce_ring *r; | |
354 | int ret = 0; | |
355 | ||
356 | *pfn = 0; | |
357 | get_cpu(); | |
358 | r = &__get_cpu_var(mce_ring); | |
359 | if (r->start == r->end) | |
360 | goto out; | |
361 | *pfn = r->ring[r->start]; | |
362 | r->start = (r->start + 1) % MCE_RING_SIZE; | |
363 | ret = 1; | |
364 | out: | |
365 | put_cpu(); | |
366 | return ret; | |
367 | } | |
368 | ||
369 | /* Always runs in MCE context with preempt off */ | |
370 | static int mce_ring_add(unsigned long pfn) | |
371 | { | |
372 | struct mce_ring *r = &__get_cpu_var(mce_ring); | |
373 | unsigned next; | |
374 | ||
375 | next = (r->end + 1) % MCE_RING_SIZE; | |
376 | if (next == r->start) | |
377 | return -1; | |
378 | r->ring[r->end] = pfn; | |
379 | wmb(); | |
380 | r->end = next; | |
381 | return 0; | |
382 | } | |
383 | ||
88ccbedd | 384 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 385 | { |
04b2b1a4 | 386 | if (mce_disabled) |
5b4408fd | 387 | return 0; |
3d1712c9 | 388 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
389 | } |
390 | ||
9b1beaf2 AK |
391 | static void mce_schedule_work(void) |
392 | { | |
393 | if (!mce_ring_empty()) { | |
394 | struct work_struct *work = &__get_cpu_var(mce_work); | |
395 | if (!work_pending(work)) | |
396 | schedule_work(work); | |
397 | } | |
398 | } | |
399 | ||
1b2797dc HY |
400 | /* |
401 | * Get the address of the instruction at the time of the machine check | |
402 | * error. | |
403 | */ | |
94ad8474 AK |
404 | static inline void mce_get_rip(struct mce *m, struct pt_regs *regs) |
405 | { | |
1b2797dc HY |
406 | |
407 | if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) { | |
65ea5b03 | 408 | m->ip = regs->ip; |
94ad8474 AK |
409 | m->cs = regs->cs; |
410 | } else { | |
65ea5b03 | 411 | m->ip = 0; |
94ad8474 AK |
412 | m->cs = 0; |
413 | } | |
1b2797dc | 414 | if (rip_msr) |
5f8c1a54 | 415 | m->ip = mce_rdmsrl(rip_msr); |
94ad8474 AK |
416 | } |
417 | ||
ccc3c319 AK |
418 | #ifdef CONFIG_X86_LOCAL_APIC |
419 | /* | |
420 | * Called after interrupts have been reenabled again | |
421 | * when a MCE happened during an interrupts off region | |
422 | * in the kernel. | |
423 | */ | |
424 | asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs) | |
425 | { | |
426 | ack_APIC_irq(); | |
427 | exit_idle(); | |
428 | irq_enter(); | |
9ff36ee9 | 429 | mce_notify_irq(); |
9b1beaf2 | 430 | mce_schedule_work(); |
ccc3c319 AK |
431 | irq_exit(); |
432 | } | |
433 | #endif | |
434 | ||
435 | static void mce_report_event(struct pt_regs *regs) | |
436 | { | |
437 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 438 | mce_notify_irq(); |
9b1beaf2 AK |
439 | /* |
440 | * Triggering the work queue here is just an insurance | |
441 | * policy in case the syscall exit notify handler | |
442 | * doesn't run soon enough or ends up running on the | |
443 | * wrong CPU (can happen when audit sleeps) | |
444 | */ | |
445 | mce_schedule_work(); | |
ccc3c319 AK |
446 | return; |
447 | } | |
448 | ||
449 | #ifdef CONFIG_X86_LOCAL_APIC | |
450 | /* | |
451 | * Without APIC do not notify. The event will be picked | |
452 | * up eventually. | |
453 | */ | |
454 | if (!cpu_has_apic) | |
455 | return; | |
456 | ||
457 | /* | |
458 | * When interrupts are disabled we cannot use | |
459 | * kernel services safely. Trigger an self interrupt | |
460 | * through the APIC to instead do the notification | |
461 | * after interrupts are reenabled again. | |
462 | */ | |
463 | apic->send_IPI_self(MCE_SELF_VECTOR); | |
464 | ||
465 | /* | |
466 | * Wait for idle afterwards again so that we don't leave the | |
467 | * APIC in a non idle state because the normal APIC writes | |
468 | * cannot exclude us. | |
469 | */ | |
470 | apic_wait_icr_idle(); | |
471 | #endif | |
472 | } | |
473 | ||
ca84f696 AK |
474 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
475 | ||
d88203d1 | 476 | /* |
b79109c3 AK |
477 | * Poll for corrected events or events that happened before reset. |
478 | * Those are just logged through /dev/mcelog. | |
479 | * | |
480 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
481 | * |
482 | * Note: spec recommends to panic for fatal unsignalled | |
483 | * errors here. However this would be quite problematic -- | |
484 | * we would need to reimplement the Monarch handling and | |
485 | * it would mess up the exclusion between exception handler | |
486 | * and poll hander -- * so we skip this for now. | |
487 | * These cases should not happen anyways, or only when the CPU | |
488 | * is already totally * confused. In this case it's likely it will | |
489 | * not fully execute the machine check handler either. | |
b79109c3 | 490 | */ |
ee031c31 | 491 | void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 AK |
492 | { |
493 | struct mce m; | |
494 | int i; | |
495 | ||
ca84f696 AK |
496 | __get_cpu_var(mce_poll_count)++; |
497 | ||
b79109c3 AK |
498 | mce_setup(&m); |
499 | ||
5f8c1a54 | 500 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
b79109c3 | 501 | for (i = 0; i < banks; i++) { |
cebe1820 | 502 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
503 | continue; |
504 | ||
505 | m.misc = 0; | |
506 | m.addr = 0; | |
507 | m.bank = i; | |
508 | m.tsc = 0; | |
509 | ||
510 | barrier(); | |
a2d32bcb | 511 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
b79109c3 AK |
512 | if (!(m.status & MCI_STATUS_VAL)) |
513 | continue; | |
514 | ||
515 | /* | |
ed7290d0 AK |
516 | * Uncorrected or signalled events are handled by the exception |
517 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
518 | * |
519 | * TBD do the same check for MCI_STATUS_EN here? | |
520 | */ | |
ed7290d0 AK |
521 | if (!(flags & MCP_UC) && |
522 | (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC))) | |
b79109c3 AK |
523 | continue; |
524 | ||
525 | if (m.status & MCI_STATUS_MISCV) | |
a2d32bcb | 526 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
b79109c3 | 527 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 528 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
b79109c3 AK |
529 | |
530 | if (!(flags & MCP_TIMESTAMP)) | |
531 | m.tsc = 0; | |
532 | /* | |
533 | * Don't get the IP here because it's unlikely to | |
534 | * have anything to do with the actual error location. | |
535 | */ | |
62fdac59 | 536 | if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) { |
5679af4c AK |
537 | mce_log(&m); |
538 | add_taint(TAINT_MACHINE_CHECK); | |
539 | } | |
b79109c3 AK |
540 | |
541 | /* | |
542 | * Clear state for this bank. | |
543 | */ | |
a2d32bcb | 544 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
b79109c3 AK |
545 | } |
546 | ||
547 | /* | |
548 | * Don't clear MCG_STATUS here because it's only defined for | |
549 | * exceptions. | |
550 | */ | |
88921be3 AK |
551 | |
552 | sync_core(); | |
b79109c3 | 553 | } |
ea149b36 | 554 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 555 | |
bd19a5e6 AK |
556 | /* |
557 | * Do a quick check if any of the events requires a panic. | |
558 | * This decides if we keep the events around or clear them. | |
559 | */ | |
560 | static int mce_no_way_out(struct mce *m, char **msg) | |
561 | { | |
562 | int i; | |
563 | ||
564 | for (i = 0; i < banks; i++) { | |
a2d32bcb | 565 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
bd19a5e6 AK |
566 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
567 | return 1; | |
568 | } | |
569 | return 0; | |
570 | } | |
571 | ||
3c079792 AK |
572 | /* |
573 | * Variable to establish order between CPUs while scanning. | |
574 | * Each CPU spins initially until executing is equal its number. | |
575 | */ | |
576 | static atomic_t mce_executing; | |
577 | ||
578 | /* | |
579 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
580 | */ | |
581 | static atomic_t mce_callin; | |
582 | ||
583 | /* | |
584 | * Check if a timeout waiting for other CPUs happened. | |
585 | */ | |
586 | static int mce_timed_out(u64 *t) | |
587 | { | |
588 | /* | |
589 | * The others already did panic for some reason. | |
590 | * Bail out like in a timeout. | |
591 | * rmb() to tell the compiler that system_state | |
592 | * might have been modified by someone else. | |
593 | */ | |
594 | rmb(); | |
595 | if (atomic_read(&mce_paniced)) | |
596 | wait_for_panic(); | |
597 | if (!monarch_timeout) | |
598 | goto out; | |
599 | if ((s64)*t < SPINUNIT) { | |
600 | /* CHECKME: Make panic default for 1 too? */ | |
601 | if (tolerant < 1) | |
602 | mce_panic("Timeout synchronizing machine check over CPUs", | |
603 | NULL, NULL); | |
604 | cpu_missing = 1; | |
605 | return 1; | |
606 | } | |
607 | *t -= SPINUNIT; | |
608 | out: | |
609 | touch_nmi_watchdog(); | |
610 | return 0; | |
611 | } | |
612 | ||
613 | /* | |
614 | * The Monarch's reign. The Monarch is the CPU who entered | |
615 | * the machine check handler first. It waits for the others to | |
616 | * raise the exception too and then grades them. When any | |
617 | * error is fatal panic. Only then let the others continue. | |
618 | * | |
619 | * The other CPUs entering the MCE handler will be controlled by the | |
620 | * Monarch. They are called Subjects. | |
621 | * | |
622 | * This way we prevent any potential data corruption in a unrecoverable case | |
623 | * and also makes sure always all CPU's errors are examined. | |
624 | * | |
680b6cfd | 625 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
626 | * space (not detected by any CPUs) In this case some external agent wants |
627 | * us to shut down, so panic too. | |
628 | * | |
629 | * The other CPUs might still decide to panic if the handler happens | |
630 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
631 | * state and won't corrupt anything by itself. It's ok to let the others | |
632 | * continue for a bit first. | |
633 | * | |
634 | * All the spin loops have timeouts; when a timeout happens a CPU | |
635 | * typically elects itself to be Monarch. | |
636 | */ | |
637 | static void mce_reign(void) | |
638 | { | |
639 | int cpu; | |
640 | struct mce *m = NULL; | |
641 | int global_worst = 0; | |
642 | char *msg = NULL; | |
643 | char *nmsg = NULL; | |
644 | ||
645 | /* | |
646 | * This CPU is the Monarch and the other CPUs have run | |
647 | * through their handlers. | |
648 | * Grade the severity of the errors of all the CPUs. | |
649 | */ | |
650 | for_each_possible_cpu(cpu) { | |
651 | int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant, | |
652 | &nmsg); | |
653 | if (severity > global_worst) { | |
654 | msg = nmsg; | |
655 | global_worst = severity; | |
656 | m = &per_cpu(mces_seen, cpu); | |
657 | } | |
658 | } | |
659 | ||
660 | /* | |
661 | * Cannot recover? Panic here then. | |
662 | * This dumps all the mces in the log buffer and stops the | |
663 | * other CPUs. | |
664 | */ | |
665 | if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3) | |
ac960375 | 666 | mce_panic("Fatal Machine check", m, msg); |
3c079792 AK |
667 | |
668 | /* | |
669 | * For UC somewhere we let the CPU who detects it handle it. | |
670 | * Also must let continue the others, otherwise the handling | |
671 | * CPU could deadlock on a lock. | |
672 | */ | |
673 | ||
674 | /* | |
675 | * No machine check event found. Must be some external | |
676 | * source or one CPU is hung. Panic. | |
677 | */ | |
680b6cfd | 678 | if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3) |
3c079792 AK |
679 | mce_panic("Machine check from unknown source", NULL, NULL); |
680 | ||
681 | /* | |
682 | * Now clear all the mces_seen so that they don't reappear on | |
683 | * the next mce. | |
684 | */ | |
685 | for_each_possible_cpu(cpu) | |
686 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
687 | } | |
688 | ||
689 | static atomic_t global_nwo; | |
690 | ||
691 | /* | |
692 | * Start of Monarch synchronization. This waits until all CPUs have | |
693 | * entered the exception handler and then determines if any of them | |
694 | * saw a fatal event that requires panic. Then it executes them | |
695 | * in the entry order. | |
696 | * TBD double check parallel CPU hotunplug | |
697 | */ | |
7fb06fc9 | 698 | static int mce_start(int *no_way_out) |
3c079792 | 699 | { |
7fb06fc9 | 700 | int order; |
3c079792 AK |
701 | int cpus = num_online_cpus(); |
702 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
703 | ||
7fb06fc9 HS |
704 | if (!timeout) |
705 | return -1; | |
3c079792 | 706 | |
7fb06fc9 | 707 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf HY |
708 | /* |
709 | * global_nwo should be updated before mce_callin | |
710 | */ | |
711 | smp_wmb(); | |
a95436e4 | 712 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
713 | |
714 | /* | |
715 | * Wait for everyone. | |
716 | */ | |
717 | while (atomic_read(&mce_callin) != cpus) { | |
718 | if (mce_timed_out(&timeout)) { | |
719 | atomic_set(&global_nwo, 0); | |
7fb06fc9 | 720 | return -1; |
3c079792 AK |
721 | } |
722 | ndelay(SPINUNIT); | |
723 | } | |
724 | ||
184e1fdf HY |
725 | /* |
726 | * mce_callin should be read before global_nwo | |
727 | */ | |
728 | smp_rmb(); | |
3c079792 | 729 | |
7fb06fc9 HS |
730 | if (order == 1) { |
731 | /* | |
732 | * Monarch: Starts executing now, the others wait. | |
733 | */ | |
3c079792 | 734 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
735 | } else { |
736 | /* | |
737 | * Subject: Now start the scanning loop one by one in | |
738 | * the original callin order. | |
739 | * This way when there are any shared banks it will be | |
740 | * only seen by one CPU before cleared, avoiding duplicates. | |
741 | */ | |
742 | while (atomic_read(&mce_executing) < order) { | |
743 | if (mce_timed_out(&timeout)) { | |
744 | atomic_set(&global_nwo, 0); | |
745 | return -1; | |
746 | } | |
747 | ndelay(SPINUNIT); | |
748 | } | |
3c079792 AK |
749 | } |
750 | ||
751 | /* | |
7fb06fc9 | 752 | * Cache the global no_way_out state. |
3c079792 | 753 | */ |
7fb06fc9 HS |
754 | *no_way_out = atomic_read(&global_nwo); |
755 | ||
756 | return order; | |
3c079792 AK |
757 | } |
758 | ||
759 | /* | |
760 | * Synchronize between CPUs after main scanning loop. | |
761 | * This invokes the bulk of the Monarch processing. | |
762 | */ | |
763 | static int mce_end(int order) | |
764 | { | |
765 | int ret = -1; | |
766 | u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC; | |
767 | ||
768 | if (!timeout) | |
769 | goto reset; | |
770 | if (order < 0) | |
771 | goto reset; | |
772 | ||
773 | /* | |
774 | * Allow others to run. | |
775 | */ | |
776 | atomic_inc(&mce_executing); | |
777 | ||
778 | if (order == 1) { | |
779 | /* CHECKME: Can this race with a parallel hotplug? */ | |
780 | int cpus = num_online_cpus(); | |
781 | ||
782 | /* | |
783 | * Monarch: Wait for everyone to go through their scanning | |
784 | * loops. | |
785 | */ | |
786 | while (atomic_read(&mce_executing) <= cpus) { | |
787 | if (mce_timed_out(&timeout)) | |
788 | goto reset; | |
789 | ndelay(SPINUNIT); | |
790 | } | |
791 | ||
792 | mce_reign(); | |
793 | barrier(); | |
794 | ret = 0; | |
795 | } else { | |
796 | /* | |
797 | * Subject: Wait for Monarch to finish. | |
798 | */ | |
799 | while (atomic_read(&mce_executing) != 0) { | |
800 | if (mce_timed_out(&timeout)) | |
801 | goto reset; | |
802 | ndelay(SPINUNIT); | |
803 | } | |
804 | ||
805 | /* | |
806 | * Don't reset anything. That's done by the Monarch. | |
807 | */ | |
808 | return 0; | |
809 | } | |
810 | ||
811 | /* | |
812 | * Reset all global state. | |
813 | */ | |
814 | reset: | |
815 | atomic_set(&global_nwo, 0); | |
816 | atomic_set(&mce_callin, 0); | |
817 | barrier(); | |
818 | ||
819 | /* | |
820 | * Let others run again. | |
821 | */ | |
822 | atomic_set(&mce_executing, 0); | |
823 | return ret; | |
824 | } | |
825 | ||
9b1beaf2 AK |
826 | /* |
827 | * Check if the address reported by the CPU is in a format we can parse. | |
828 | * It would be possible to add code for most other cases, but all would | |
829 | * be somewhat complicated (e.g. segment offset would require an instruction | |
830 | * parser). So only support physical addresses upto page granuality for now. | |
831 | */ | |
832 | static int mce_usable_address(struct mce *m) | |
833 | { | |
834 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
835 | return 0; | |
836 | if ((m->misc & 0x3f) > PAGE_SHIFT) | |
837 | return 0; | |
838 | if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS) | |
839 | return 0; | |
840 | return 1; | |
841 | } | |
842 | ||
3c079792 AK |
843 | static void mce_clear_state(unsigned long *toclear) |
844 | { | |
845 | int i; | |
846 | ||
847 | for (i = 0; i < banks; i++) { | |
848 | if (test_bit(i, toclear)) | |
a2d32bcb | 849 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
3c079792 AK |
850 | } |
851 | } | |
852 | ||
b79109c3 AK |
853 | /* |
854 | * The actual machine check handler. This only handles real | |
855 | * exceptions when something got corrupted coming in through int 18. | |
856 | * | |
857 | * This is executed in NMI context not subject to normal locking rules. This | |
858 | * implies that most kernel services cannot be safely used. Don't even | |
859 | * think about putting a printk in there! | |
3c079792 AK |
860 | * |
861 | * On Intel systems this is entered on all CPUs in parallel through | |
862 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
863 | * so be always careful when synchronizing with others. | |
1da177e4 | 864 | */ |
e9eee03e | 865 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 866 | { |
3c079792 | 867 | struct mce m, *final; |
1da177e4 | 868 | int i; |
3c079792 AK |
869 | int worst = 0; |
870 | int severity; | |
871 | /* | |
872 | * Establish sequential order between the CPUs entering the machine | |
873 | * check handler. | |
874 | */ | |
7fb06fc9 | 875 | int order; |
bd78432c TH |
876 | /* |
877 | * If no_way_out gets set, there is no safe way to recover from this | |
878 | * MCE. If tolerant is cranked up, we'll try anyway. | |
879 | */ | |
880 | int no_way_out = 0; | |
881 | /* | |
882 | * If kill_it gets set, there might be a way to recover from this | |
883 | * error. | |
884 | */ | |
885 | int kill_it = 0; | |
b79109c3 | 886 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
bd19a5e6 | 887 | char *msg = "Unknown"; |
1da177e4 | 888 | |
553f265f AK |
889 | atomic_inc(&mce_entry); |
890 | ||
01ca79f1 AK |
891 | __get_cpu_var(mce_exception_count)++; |
892 | ||
b79109c3 | 893 | if (notify_die(DIE_NMI, "machine check", regs, error_code, |
22f5991c | 894 | 18, SIGKILL) == NOTIFY_STOP) |
32561696 | 895 | goto out; |
b79109c3 | 896 | if (!banks) |
32561696 | 897 | goto out; |
1da177e4 | 898 | |
b5f2fa4e AK |
899 | mce_setup(&m); |
900 | ||
5f8c1a54 | 901 | m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); |
3c079792 AK |
902 | final = &__get_cpu_var(mces_seen); |
903 | *final = m; | |
904 | ||
680b6cfd HS |
905 | no_way_out = mce_no_way_out(&m, &msg); |
906 | ||
1da177e4 LT |
907 | barrier(); |
908 | ||
ed7290d0 AK |
909 | /* |
910 | * When no restart IP must always kill or panic. | |
911 | */ | |
912 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
913 | kill_it = 1; | |
914 | ||
3c079792 AK |
915 | /* |
916 | * Go through all the banks in exclusion of the other CPUs. | |
917 | * This way we don't report duplicated events on shared banks | |
918 | * because the first one to see it will clear it. | |
919 | */ | |
7fb06fc9 | 920 | order = mce_start(&no_way_out); |
1da177e4 | 921 | for (i = 0; i < banks; i++) { |
b79109c3 | 922 | __clear_bit(i, toclear); |
cebe1820 | 923 | if (!mce_banks[i].ctl) |
1da177e4 | 924 | continue; |
d88203d1 TG |
925 | |
926 | m.misc = 0; | |
1da177e4 LT |
927 | m.addr = 0; |
928 | m.bank = i; | |
1da177e4 | 929 | |
a2d32bcb | 930 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
1da177e4 LT |
931 | if ((m.status & MCI_STATUS_VAL) == 0) |
932 | continue; | |
933 | ||
b79109c3 | 934 | /* |
ed7290d0 AK |
935 | * Non uncorrected or non signaled errors are handled by |
936 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 937 | */ |
ed7290d0 AK |
938 | if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
939 | !no_way_out) | |
b79109c3 AK |
940 | continue; |
941 | ||
942 | /* | |
943 | * Set taint even when machine check was not enabled. | |
944 | */ | |
945 | add_taint(TAINT_MACHINE_CHECK); | |
946 | ||
ed7290d0 | 947 | severity = mce_severity(&m, tolerant, NULL); |
b79109c3 | 948 | |
ed7290d0 AK |
949 | /* |
950 | * When machine check was for corrected handler don't touch, | |
951 | * unless we're panicing. | |
952 | */ | |
953 | if (severity == MCE_KEEP_SEVERITY && !no_way_out) | |
954 | continue; | |
955 | __set_bit(i, toclear); | |
956 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
957 | /* |
958 | * Machine check event was not enabled. Clear, but | |
959 | * ignore. | |
960 | */ | |
961 | continue; | |
1da177e4 LT |
962 | } |
963 | ||
ed7290d0 AK |
964 | /* |
965 | * Kill on action required. | |
966 | */ | |
967 | if (severity == MCE_AR_SEVERITY) | |
968 | kill_it = 1; | |
969 | ||
1da177e4 | 970 | if (m.status & MCI_STATUS_MISCV) |
a2d32bcb | 971 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
1da177e4 | 972 | if (m.status & MCI_STATUS_ADDRV) |
a2d32bcb | 973 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
1da177e4 | 974 | |
9b1beaf2 AK |
975 | /* |
976 | * Action optional error. Queue address for later processing. | |
977 | * When the ring overflows we just ignore the AO error. | |
978 | * RED-PEN add some logging mechanism when | |
979 | * usable_address or mce_add_ring fails. | |
980 | * RED-PEN don't ignore overflow for tolerant == 0 | |
981 | */ | |
982 | if (severity == MCE_AO_SEVERITY && mce_usable_address(&m)) | |
983 | mce_ring_add(m.addr >> PAGE_SHIFT); | |
984 | ||
94ad8474 | 985 | mce_get_rip(&m, regs); |
b79109c3 | 986 | mce_log(&m); |
1da177e4 | 987 | |
3c079792 AK |
988 | if (severity > worst) { |
989 | *final = m; | |
990 | worst = severity; | |
1da177e4 | 991 | } |
1da177e4 LT |
992 | } |
993 | ||
3c079792 AK |
994 | if (!no_way_out) |
995 | mce_clear_state(toclear); | |
996 | ||
e9eee03e | 997 | /* |
3c079792 AK |
998 | * Do most of the synchronization with other CPUs. |
999 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1000 | */ |
3c079792 AK |
1001 | if (mce_end(order) < 0) |
1002 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
bd78432c TH |
1003 | |
1004 | /* | |
1005 | * If we have decided that we just CAN'T continue, and the user | |
e9eee03e | 1006 | * has not set tolerant to an insane level, give up and die. |
3c079792 AK |
1007 | * |
1008 | * This is mainly used in the case when the system doesn't | |
1009 | * support MCE broadcasting or it has been disabled. | |
bd78432c TH |
1010 | */ |
1011 | if (no_way_out && tolerant < 3) | |
ac960375 | 1012 | mce_panic("Fatal machine check on current CPU", final, msg); |
bd78432c TH |
1013 | |
1014 | /* | |
1015 | * If the error seems to be unrecoverable, something should be | |
1016 | * done. Try to kill as little as possible. If we can kill just | |
1017 | * one task, do that. If the user has set the tolerance very | |
1018 | * high, don't try to do anything at all. | |
1019 | */ | |
bd78432c | 1020 | |
ed7290d0 AK |
1021 | if (kill_it && tolerant < 3) |
1022 | force_sig(SIGBUS, current); | |
1da177e4 | 1023 | |
e02e68d3 TH |
1024 | /* notify userspace ASAP */ |
1025 | set_thread_flag(TIF_MCE_NOTIFY); | |
1026 | ||
3c079792 AK |
1027 | if (worst > 0) |
1028 | mce_report_event(regs); | |
5f8c1a54 | 1029 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1030 | out: |
553f265f | 1031 | atomic_dec(&mce_entry); |
88921be3 | 1032 | sync_core(); |
1da177e4 | 1033 | } |
ea149b36 | 1034 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1035 | |
9b1beaf2 AK |
1036 | /* dummy to break dependency. actual code is in mm/memory-failure.c */ |
1037 | void __attribute__((weak)) memory_failure(unsigned long pfn, int vector) | |
1038 | { | |
1039 | printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn); | |
1040 | } | |
1041 | ||
1042 | /* | |
1043 | * Called after mce notification in process context. This code | |
1044 | * is allowed to sleep. Call the high level VM handler to process | |
1045 | * any corrupted pages. | |
1046 | * Assume that the work queue code only calls this one at a time | |
1047 | * per CPU. | |
1048 | * Note we don't disable preemption, so this code might run on the wrong | |
1049 | * CPU. In this case the event is picked up by the scheduled work queue. | |
1050 | * This is merely a fast path to expedite processing in some common | |
1051 | * cases. | |
1052 | */ | |
1053 | void mce_notify_process(void) | |
1054 | { | |
1055 | unsigned long pfn; | |
1056 | mce_notify_irq(); | |
1057 | while (mce_ring_get(&pfn)) | |
1058 | memory_failure(pfn, MCE_VECTOR); | |
1059 | } | |
1060 | ||
1061 | static void mce_process_work(struct work_struct *dummy) | |
1062 | { | |
1063 | mce_notify_process(); | |
1064 | } | |
1065 | ||
15d5f839 DZ |
1066 | #ifdef CONFIG_X86_MCE_INTEL |
1067 | /*** | |
1068 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1069 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1070 | * @status: Event status information |
1071 | * | |
1072 | * This function should be called by the thermal interrupt after the | |
1073 | * event has been processed and the decision was made to log the event | |
1074 | * further. | |
1075 | * | |
1076 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1077 | * and historically has been the register value of the | |
1078 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1079 | */ | |
b5f2fa4e | 1080 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1081 | { |
1082 | struct mce m; | |
1083 | ||
b5f2fa4e | 1084 | mce_setup(&m); |
15d5f839 DZ |
1085 | m.bank = MCE_THERMAL_BANK; |
1086 | m.status = status; | |
15d5f839 DZ |
1087 | mce_log(&m); |
1088 | } | |
1089 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1090 | ||
1da177e4 | 1091 | /* |
8a336b0a TH |
1092 | * Periodic polling timer for "silent" machine check errors. If the |
1093 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1094 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1095 | */ |
1da177e4 | 1096 | static int check_interval = 5 * 60; /* 5 minutes */ |
e9eee03e | 1097 | |
245b2e70 | 1098 | static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */ |
52d168e2 | 1099 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1100 | |
52d168e2 | 1101 | static void mcheck_timer(unsigned long data) |
1da177e4 | 1102 | { |
52d168e2 | 1103 | struct timer_list *t = &per_cpu(mce_timer, data); |
6298c512 | 1104 | int *n; |
52d168e2 AK |
1105 | |
1106 | WARN_ON(smp_processor_id() != data); | |
1107 | ||
e9eee03e | 1108 | if (mce_available(¤t_cpu_data)) { |
ee031c31 AK |
1109 | machine_check_poll(MCP_TIMESTAMP, |
1110 | &__get_cpu_var(mce_poll_banks)); | |
e9eee03e | 1111 | } |
1da177e4 LT |
1112 | |
1113 | /* | |
e02e68d3 TH |
1114 | * Alert userspace if needed. If we logged an MCE, reduce the |
1115 | * polling interval, otherwise increase the polling interval. | |
1da177e4 | 1116 | */ |
245b2e70 | 1117 | n = &__get_cpu_var(mce_next_interval); |
9ff36ee9 | 1118 | if (mce_notify_irq()) |
6298c512 | 1119 | *n = max(*n/2, HZ/100); |
14a02530 | 1120 | else |
6298c512 | 1121 | *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ)); |
e02e68d3 | 1122 | |
6298c512 | 1123 | t->expires = jiffies + *n; |
5be6066a | 1124 | add_timer_on(t, smp_processor_id()); |
e02e68d3 TH |
1125 | } |
1126 | ||
9bd98405 AK |
1127 | static void mce_do_trigger(struct work_struct *work) |
1128 | { | |
1020bcbc | 1129 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1130 | } |
1131 | ||
1132 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1133 | ||
e02e68d3 | 1134 | /* |
9bd98405 AK |
1135 | * Notify the user(s) about new machine check events. |
1136 | * Can be called from interrupt context, but not from machine check/NMI | |
1137 | * context. | |
e02e68d3 | 1138 | */ |
9ff36ee9 | 1139 | int mce_notify_irq(void) |
e02e68d3 | 1140 | { |
8457c84d AK |
1141 | /* Not more than two messages every minute */ |
1142 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1143 | ||
e02e68d3 | 1144 | clear_thread_flag(TIF_MCE_NOTIFY); |
e9eee03e | 1145 | |
1020bcbc | 1146 | if (test_and_clear_bit(0, &mce_need_notify)) { |
e02e68d3 | 1147 | wake_up_interruptible(&mce_wait); |
9bd98405 AK |
1148 | |
1149 | /* | |
1150 | * There is no risk of missing notifications because | |
1151 | * work_pending is always cleared before the function is | |
1152 | * executed. | |
1153 | */ | |
1020bcbc | 1154 | if (mce_helper[0] && !work_pending(&mce_trigger_work)) |
9bd98405 | 1155 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1156 | |
8457c84d | 1157 | if (__ratelimit(&ratelimit)) |
8a336b0a | 1158 | printk(KERN_INFO "Machine check events logged\n"); |
e02e68d3 TH |
1159 | |
1160 | return 1; | |
1da177e4 | 1161 | } |
e02e68d3 TH |
1162 | return 0; |
1163 | } | |
9ff36ee9 | 1164 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1165 | |
cebe1820 AK |
1166 | static int mce_banks_init(void) |
1167 | { | |
1168 | int i; | |
1169 | ||
1170 | mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL); | |
1171 | if (!mce_banks) | |
1172 | return -ENOMEM; | |
1173 | for (i = 0; i < banks; i++) { | |
1174 | struct mce_bank *b = &mce_banks[i]; | |
1175 | b->ctl = -1ULL; | |
1176 | b->init = 1; | |
1177 | } | |
1178 | return 0; | |
1179 | } | |
1180 | ||
d88203d1 | 1181 | /* |
1da177e4 LT |
1182 | * Initialize Machine Checks for a CPU. |
1183 | */ | |
419d6162 | 1184 | static int __cpuinit mce_cap_init(void) |
1da177e4 | 1185 | { |
0d7482e3 | 1186 | unsigned b; |
e9eee03e | 1187 | u64 cap; |
1da177e4 LT |
1188 | |
1189 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1190 | |
1191 | b = cap & MCG_BANKCNT_MASK; | |
b659294b IM |
1192 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); |
1193 | ||
0d7482e3 AK |
1194 | if (b > MAX_NR_BANKS) { |
1195 | printk(KERN_WARNING | |
1196 | "MCE: Using only %u machine check banks out of %u\n", | |
1197 | MAX_NR_BANKS, b); | |
1198 | b = MAX_NR_BANKS; | |
1199 | } | |
1200 | ||
1201 | /* Don't support asymmetric configurations today */ | |
1202 | WARN_ON(banks != 0 && b != banks); | |
1203 | banks = b; | |
cebe1820 AK |
1204 | if (!mce_banks) { |
1205 | int err = mce_banks_init(); | |
1206 | if (err) | |
1207 | return err; | |
1da177e4 | 1208 | } |
0d7482e3 | 1209 | |
94ad8474 | 1210 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1211 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
94ad8474 | 1212 | rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1213 | |
ed7290d0 AK |
1214 | if (cap & MCG_SER_P) |
1215 | mce_ser = 1; | |
1216 | ||
0d7482e3 AK |
1217 | return 0; |
1218 | } | |
1219 | ||
8be91105 | 1220 | static void mce_init(void) |
0d7482e3 | 1221 | { |
e9eee03e | 1222 | mce_banks_t all_banks; |
0d7482e3 AK |
1223 | u64 cap; |
1224 | int i; | |
1225 | ||
b79109c3 AK |
1226 | /* |
1227 | * Log the machine checks left over from the previous reset. | |
1228 | */ | |
ee031c31 | 1229 | bitmap_fill(all_banks, MAX_NR_BANKS); |
5679af4c | 1230 | machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks); |
1da177e4 LT |
1231 | |
1232 | set_in_cr4(X86_CR4_MCE); | |
1233 | ||
0d7482e3 | 1234 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1235 | if (cap & MCG_CTL_P) |
1236 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
1237 | ||
1238 | for (i = 0; i < banks; i++) { | |
cebe1820 AK |
1239 | struct mce_bank *b = &mce_banks[i]; |
1240 | if (!b->init) | |
06b7a7a5 | 1241 | continue; |
a2d32bcb AK |
1242 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1243 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); | |
d88203d1 | 1244 | } |
1da177e4 LT |
1245 | } |
1246 | ||
1247 | /* Add per CPU specific workarounds here */ | |
df58bee2 | 1248 | static int __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1249 | { |
e412cd25 IM |
1250 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1251 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | |
1252 | return -EOPNOTSUPP; | |
1253 | } | |
1254 | ||
1da177e4 | 1255 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1256 | if (c->x86_vendor == X86_VENDOR_AMD) { |
e9eee03e IM |
1257 | if (c->x86 == 15 && banks > 4) { |
1258 | /* | |
1259 | * disable GART TBL walk error reporting, which | |
1260 | * trips off incorrectly with the IOMMU & 3ware | |
1261 | * & Cerberus: | |
1262 | */ | |
cebe1820 | 1263 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e IM |
1264 | } |
1265 | if (c->x86 <= 17 && mce_bootlog < 0) { | |
1266 | /* | |
1267 | * Lots of broken BIOS around that don't clear them | |
1268 | * by default and leave crap in there. Don't log: | |
1269 | */ | |
911f6a7b | 1270 | mce_bootlog = 0; |
e9eee03e | 1271 | } |
2e6f694f AK |
1272 | /* |
1273 | * Various K7s with broken bank 0 around. Always disable | |
1274 | * by default. | |
1275 | */ | |
203abd67 | 1276 | if (c->x86 == 6 && banks > 0) |
cebe1820 | 1277 | mce_banks[0].ctl = 0; |
1da177e4 | 1278 | } |
e583538f | 1279 | |
06b7a7a5 AK |
1280 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1281 | /* | |
1282 | * SDM documents that on family 6 bank 0 should not be written | |
1283 | * because it aliases to another special BIOS controlled | |
1284 | * register. | |
1285 | * But it's not aliased anymore on model 0x1a+ | |
1286 | * Don't ignore bank 0 completely because there could be a | |
1287 | * valid event later, merely don't write CTL0. | |
1288 | */ | |
1289 | ||
cebe1820 AK |
1290 | if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0) |
1291 | mce_banks[0].init = 0; | |
3c079792 AK |
1292 | |
1293 | /* | |
1294 | * All newer Intel systems support MCE broadcasting. Enable | |
1295 | * synchronization with a one second timeout. | |
1296 | */ | |
1297 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
1298 | monarch_timeout < 0) | |
1299 | monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1300 | |
e412cd25 IM |
1301 | /* |
1302 | * There are also broken BIOSes on some Pentium M and | |
1303 | * earlier systems: | |
1304 | */ | |
1305 | if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0) | |
c7f6fa44 | 1306 | mce_bootlog = 0; |
06b7a7a5 | 1307 | } |
3c079792 AK |
1308 | if (monarch_timeout < 0) |
1309 | monarch_timeout = 0; | |
29b0f591 AK |
1310 | if (mce_bootlog != 0) |
1311 | mce_panic_timeout = 30; | |
e412cd25 IM |
1312 | |
1313 | return 0; | |
d88203d1 | 1314 | } |
1da177e4 | 1315 | |
4efc0670 AK |
1316 | static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c) |
1317 | { | |
1318 | if (c->x86 != 5) | |
1319 | return; | |
1320 | switch (c->x86_vendor) { | |
1321 | case X86_VENDOR_INTEL: | |
c6978369 | 1322 | intel_p5_mcheck_init(c); |
4efc0670 AK |
1323 | break; |
1324 | case X86_VENDOR_CENTAUR: | |
1325 | winchip_mcheck_init(c); | |
1326 | break; | |
1327 | } | |
1328 | } | |
1329 | ||
cc3ca220 | 1330 | static void mce_cpu_features(struct cpuinfo_x86 *c) |
1da177e4 LT |
1331 | { |
1332 | switch (c->x86_vendor) { | |
1333 | case X86_VENDOR_INTEL: | |
1334 | mce_intel_feature_init(c); | |
1335 | break; | |
89b831ef JS |
1336 | case X86_VENDOR_AMD: |
1337 | mce_amd_feature_init(c); | |
1338 | break; | |
1da177e4 LT |
1339 | default: |
1340 | break; | |
1341 | } | |
1342 | } | |
1343 | ||
52d168e2 AK |
1344 | static void mce_init_timer(void) |
1345 | { | |
1346 | struct timer_list *t = &__get_cpu_var(mce_timer); | |
245b2e70 | 1347 | int *n = &__get_cpu_var(mce_next_interval); |
52d168e2 | 1348 | |
62fdac59 HS |
1349 | if (mce_ignore_ce) |
1350 | return; | |
1351 | ||
6298c512 AK |
1352 | *n = check_interval * HZ; |
1353 | if (!*n) | |
52d168e2 AK |
1354 | return; |
1355 | setup_timer(t, mcheck_timer, smp_processor_id()); | |
6298c512 | 1356 | t->expires = round_jiffies(jiffies + *n); |
5be6066a | 1357 | add_timer_on(t, smp_processor_id()); |
52d168e2 AK |
1358 | } |
1359 | ||
9eda8cb3 AK |
1360 | /* Handle unconfigured int18 (should never happen) */ |
1361 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1362 | { | |
1363 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | |
1364 | smp_processor_id()); | |
1365 | } | |
1366 | ||
1367 | /* Call the installed machine check handler for this CPU setup. */ | |
1368 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1369 | unexpected_machine_check; | |
1370 | ||
d88203d1 | 1371 | /* |
1da177e4 | 1372 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1373 | * Must be called with preempt off: |
1da177e4 | 1374 | */ |
e6982c67 | 1375 | void __cpuinit mcheck_init(struct cpuinfo_x86 *c) |
1da177e4 | 1376 | { |
4efc0670 AK |
1377 | if (mce_disabled) |
1378 | return; | |
1379 | ||
1380 | mce_ancient_init(c); | |
1381 | ||
5b4408fd | 1382 | if (!mce_available(c)) |
1da177e4 LT |
1383 | return; |
1384 | ||
e412cd25 | 1385 | if (mce_cap_init() < 0 || mce_cpu_quirks(c) < 0) { |
04b2b1a4 | 1386 | mce_disabled = 1; |
0d7482e3 AK |
1387 | return; |
1388 | } | |
0d7482e3 | 1389 | |
5d727926 AK |
1390 | machine_check_vector = do_machine_check; |
1391 | ||
8be91105 | 1392 | mce_init(); |
1da177e4 | 1393 | mce_cpu_features(c); |
52d168e2 | 1394 | mce_init_timer(); |
9b1beaf2 | 1395 | INIT_WORK(&__get_cpu_var(mce_work), mce_process_work); |
1da177e4 LT |
1396 | } |
1397 | ||
1398 | /* | |
1399 | * Character device to read and clear the MCE log. | |
1400 | */ | |
1401 | ||
f528e7ba | 1402 | static DEFINE_SPINLOCK(mce_state_lock); |
e9eee03e IM |
1403 | static int open_count; /* #times opened */ |
1404 | static int open_exclu; /* already open exclusive? */ | |
f528e7ba TH |
1405 | |
1406 | static int mce_open(struct inode *inode, struct file *file) | |
1407 | { | |
1408 | spin_lock(&mce_state_lock); | |
1409 | ||
1410 | if (open_exclu || (open_count && (file->f_flags & O_EXCL))) { | |
1411 | spin_unlock(&mce_state_lock); | |
e9eee03e | 1412 | |
f528e7ba TH |
1413 | return -EBUSY; |
1414 | } | |
1415 | ||
1416 | if (file->f_flags & O_EXCL) | |
1417 | open_exclu = 1; | |
1418 | open_count++; | |
1419 | ||
1420 | spin_unlock(&mce_state_lock); | |
1421 | ||
bd78432c | 1422 | return nonseekable_open(inode, file); |
f528e7ba TH |
1423 | } |
1424 | ||
1425 | static int mce_release(struct inode *inode, struct file *file) | |
1426 | { | |
1427 | spin_lock(&mce_state_lock); | |
1428 | ||
1429 | open_count--; | |
1430 | open_exclu = 0; | |
1431 | ||
1432 | spin_unlock(&mce_state_lock); | |
1433 | ||
1434 | return 0; | |
1435 | } | |
1436 | ||
d88203d1 TG |
1437 | static void collect_tscs(void *data) |
1438 | { | |
1da177e4 | 1439 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1440 | |
1da177e4 | 1441 | rdtscll(cpu_tsc[smp_processor_id()]); |
d88203d1 | 1442 | } |
1da177e4 | 1443 | |
e9eee03e IM |
1444 | static DEFINE_MUTEX(mce_read_mutex); |
1445 | ||
d88203d1 TG |
1446 | static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize, |
1447 | loff_t *off) | |
1da177e4 | 1448 | { |
e9eee03e | 1449 | char __user *buf = ubuf; |
f0de53bb | 1450 | unsigned long *cpu_tsc; |
ef41df43 | 1451 | unsigned prev, next; |
1da177e4 LT |
1452 | int i, err; |
1453 | ||
6bca67f9 | 1454 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1455 | if (!cpu_tsc) |
1456 | return -ENOMEM; | |
1457 | ||
8c8b8859 | 1458 | mutex_lock(&mce_read_mutex); |
1da177e4 LT |
1459 | next = rcu_dereference(mcelog.next); |
1460 | ||
1461 | /* Only supports full reads right now */ | |
d88203d1 | 1462 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) { |
8c8b8859 | 1463 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1464 | kfree(cpu_tsc); |
e9eee03e | 1465 | |
1da177e4 LT |
1466 | return -EINVAL; |
1467 | } | |
1468 | ||
1469 | err = 0; | |
ef41df43 HY |
1470 | prev = 0; |
1471 | do { | |
1472 | for (i = prev; i < next; i++) { | |
1473 | unsigned long start = jiffies; | |
1474 | ||
1475 | while (!mcelog.entry[i].finished) { | |
1476 | if (time_after_eq(jiffies, start + 2)) { | |
1477 | memset(mcelog.entry + i, 0, | |
1478 | sizeof(struct mce)); | |
1479 | goto timeout; | |
1480 | } | |
1481 | cpu_relax(); | |
673242c1 | 1482 | } |
ef41df43 HY |
1483 | smp_rmb(); |
1484 | err |= copy_to_user(buf, mcelog.entry + i, | |
1485 | sizeof(struct mce)); | |
1486 | buf += sizeof(struct mce); | |
1487 | timeout: | |
1488 | ; | |
673242c1 | 1489 | } |
1da177e4 | 1490 | |
ef41df43 HY |
1491 | memset(mcelog.entry + prev, 0, |
1492 | (next - prev) * sizeof(struct mce)); | |
1493 | prev = next; | |
1494 | next = cmpxchg(&mcelog.next, prev, 0); | |
1495 | } while (next != prev); | |
1da177e4 | 1496 | |
b2b18660 | 1497 | synchronize_sched(); |
1da177e4 | 1498 | |
d88203d1 TG |
1499 | /* |
1500 | * Collect entries that were still getting written before the | |
1501 | * synchronize. | |
1502 | */ | |
15c8b6c1 | 1503 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1504 | |
d88203d1 TG |
1505 | for (i = next; i < MCE_LOG_LEN; i++) { |
1506 | if (mcelog.entry[i].finished && | |
1507 | mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) { | |
1508 | err |= copy_to_user(buf, mcelog.entry+i, | |
1509 | sizeof(struct mce)); | |
1da177e4 LT |
1510 | smp_rmb(); |
1511 | buf += sizeof(struct mce); | |
1512 | memset(&mcelog.entry[i], 0, sizeof(struct mce)); | |
1513 | } | |
d88203d1 | 1514 | } |
8c8b8859 | 1515 | mutex_unlock(&mce_read_mutex); |
f0de53bb | 1516 | kfree(cpu_tsc); |
e9eee03e | 1517 | |
d88203d1 | 1518 | return err ? -EFAULT : buf - ubuf; |
1da177e4 LT |
1519 | } |
1520 | ||
e02e68d3 TH |
1521 | static unsigned int mce_poll(struct file *file, poll_table *wait) |
1522 | { | |
1523 | poll_wait(file, &mce_wait, wait); | |
1524 | if (rcu_dereference(mcelog.next)) | |
1525 | return POLLIN | POLLRDNORM; | |
1526 | return 0; | |
1527 | } | |
1528 | ||
c68461b6 | 1529 | static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1530 | { |
1531 | int __user *p = (int __user *)arg; | |
d88203d1 | 1532 | |
1da177e4 | 1533 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 1534 | return -EPERM; |
e9eee03e | 1535 | |
1da177e4 | 1536 | switch (cmd) { |
d88203d1 | 1537 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
1538 | return put_user(sizeof(struct mce), p); |
1539 | case MCE_GET_LOG_LEN: | |
d88203d1 | 1540 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
1541 | case MCE_GETCLEAR_FLAGS: { |
1542 | unsigned flags; | |
d88203d1 TG |
1543 | |
1544 | do { | |
1da177e4 | 1545 | flags = mcelog.flags; |
d88203d1 | 1546 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 1547 | |
d88203d1 | 1548 | return put_user(flags, p); |
1da177e4 LT |
1549 | } |
1550 | default: | |
d88203d1 TG |
1551 | return -ENOTTY; |
1552 | } | |
1da177e4 LT |
1553 | } |
1554 | ||
a1ff41bf | 1555 | /* Modified in mce-inject.c, so not static or const */ |
ea149b36 | 1556 | struct file_operations mce_chrdev_ops = { |
e9eee03e IM |
1557 | .open = mce_open, |
1558 | .release = mce_release, | |
1559 | .read = mce_read, | |
1560 | .poll = mce_poll, | |
1561 | .unlocked_ioctl = mce_ioctl, | |
1da177e4 | 1562 | }; |
ea149b36 | 1563 | EXPORT_SYMBOL_GPL(mce_chrdev_ops); |
1da177e4 LT |
1564 | |
1565 | static struct miscdevice mce_log_device = { | |
1566 | MISC_MCELOG_MINOR, | |
1567 | "mcelog", | |
1568 | &mce_chrdev_ops, | |
1569 | }; | |
1570 | ||
13503fa9 | 1571 | /* |
62fdac59 HS |
1572 | * mce=off Disables machine check |
1573 | * mce=no_cmci Disables CMCI | |
1574 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. | |
1575 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
1576 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
1577 | * monarchtimeout is how long to wait for other CPUs on machine | |
1578 | * check, or 0 to not wait | |
13503fa9 HS |
1579 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
1580 | * mce=nobootlog Don't log MCEs from before booting. | |
1581 | */ | |
1da177e4 LT |
1582 | static int __init mcheck_enable(char *str) |
1583 | { | |
e3346fc4 | 1584 | if (*str == 0) { |
4efc0670 | 1585 | enable_p5_mce(); |
e3346fc4 BZ |
1586 | return 1; |
1587 | } | |
4efc0670 AK |
1588 | if (*str == '=') |
1589 | str++; | |
1da177e4 | 1590 | if (!strcmp(str, "off")) |
04b2b1a4 | 1591 | mce_disabled = 1; |
62fdac59 HS |
1592 | else if (!strcmp(str, "no_cmci")) |
1593 | mce_cmci_disabled = 1; | |
1594 | else if (!strcmp(str, "dont_log_ce")) | |
1595 | mce_dont_log_ce = 1; | |
1596 | else if (!strcmp(str, "ignore_ce")) | |
1597 | mce_ignore_ce = 1; | |
13503fa9 HS |
1598 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
1599 | mce_bootlog = (str[0] == 'b'); | |
3c079792 | 1600 | else if (isdigit(str[0])) { |
8c566ef5 | 1601 | get_option(&str, &tolerant); |
3c079792 AK |
1602 | if (*str == ',') { |
1603 | ++str; | |
1604 | get_option(&str, &monarch_timeout); | |
1605 | } | |
1606 | } else { | |
4efc0670 | 1607 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", |
13503fa9 HS |
1608 | str); |
1609 | return 0; | |
1610 | } | |
9b41046c | 1611 | return 1; |
1da177e4 | 1612 | } |
4efc0670 | 1613 | __setup("mce", mcheck_enable); |
1da177e4 | 1614 | |
d88203d1 | 1615 | /* |
1da177e4 | 1616 | * Sysfs support |
d88203d1 | 1617 | */ |
1da177e4 | 1618 | |
973a2dd1 AK |
1619 | /* |
1620 | * Disable machine checks on suspend and shutdown. We can't really handle | |
1621 | * them later. | |
1622 | */ | |
1623 | static int mce_disable(void) | |
1624 | { | |
1625 | int i; | |
1626 | ||
06b7a7a5 | 1627 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
1628 | struct mce_bank *b = &mce_banks[i]; |
1629 | if (b->init) | |
a2d32bcb | 1630 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1631 | } |
973a2dd1 AK |
1632 | return 0; |
1633 | } | |
1634 | ||
1635 | static int mce_suspend(struct sys_device *dev, pm_message_t state) | |
1636 | { | |
1637 | return mce_disable(); | |
1638 | } | |
1639 | ||
1640 | static int mce_shutdown(struct sys_device *dev) | |
1641 | { | |
1642 | return mce_disable(); | |
1643 | } | |
1644 | ||
e9eee03e IM |
1645 | /* |
1646 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
1647 | * Only one CPU is active at this time, the others get re-added later using | |
1648 | * CPU hotplug: | |
1649 | */ | |
1da177e4 LT |
1650 | static int mce_resume(struct sys_device *dev) |
1651 | { | |
8be91105 | 1652 | mce_init(); |
6ec68bff | 1653 | mce_cpu_features(¤t_cpu_data); |
e9eee03e | 1654 | |
1da177e4 LT |
1655 | return 0; |
1656 | } | |
1657 | ||
52d168e2 AK |
1658 | static void mce_cpu_restart(void *data) |
1659 | { | |
1660 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
33edbf02 HS |
1661 | if (!mce_available(¤t_cpu_data)) |
1662 | return; | |
1663 | mce_init(); | |
52d168e2 AK |
1664 | mce_init_timer(); |
1665 | } | |
1666 | ||
1da177e4 | 1667 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
1668 | static void mce_restart(void) |
1669 | { | |
52d168e2 | 1670 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
1671 | } |
1672 | ||
9af43b54 HS |
1673 | /* Toggle features for corrected errors */ |
1674 | static void mce_disable_ce(void *all) | |
1675 | { | |
1676 | if (!mce_available(¤t_cpu_data)) | |
1677 | return; | |
1678 | if (all) | |
1679 | del_timer_sync(&__get_cpu_var(mce_timer)); | |
1680 | cmci_clear(); | |
1681 | } | |
1682 | ||
1683 | static void mce_enable_ce(void *all) | |
1684 | { | |
1685 | if (!mce_available(¤t_cpu_data)) | |
1686 | return; | |
1687 | cmci_reenable(); | |
1688 | cmci_recheck(); | |
1689 | if (all) | |
1690 | mce_init_timer(); | |
1691 | } | |
1692 | ||
1da177e4 | 1693 | static struct sysdev_class mce_sysclass = { |
e9eee03e IM |
1694 | .suspend = mce_suspend, |
1695 | .shutdown = mce_shutdown, | |
1696 | .resume = mce_resume, | |
1697 | .name = "machinecheck", | |
1da177e4 LT |
1698 | }; |
1699 | ||
cb491fca | 1700 | DEFINE_PER_CPU(struct sys_device, mce_dev); |
e9eee03e IM |
1701 | |
1702 | __cpuinitdata | |
1703 | void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); | |
1da177e4 | 1704 | |
cebe1820 AK |
1705 | static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr) |
1706 | { | |
1707 | return container_of(attr, struct mce_bank, attr); | |
1708 | } | |
0d7482e3 AK |
1709 | |
1710 | static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
1711 | char *buf) | |
1712 | { | |
cebe1820 | 1713 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
1714 | } |
1715 | ||
1716 | static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr, | |
9319cec8 | 1717 | const char *buf, size_t size) |
0d7482e3 | 1718 | { |
9319cec8 | 1719 | u64 new; |
e9eee03e | 1720 | |
9319cec8 | 1721 | if (strict_strtoull(buf, 0, &new) < 0) |
0d7482e3 | 1722 | return -EINVAL; |
e9eee03e | 1723 | |
cebe1820 | 1724 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 1725 | mce_restart(); |
e9eee03e | 1726 | |
9319cec8 | 1727 | return size; |
0d7482e3 | 1728 | } |
a98f0dd3 | 1729 | |
e9eee03e IM |
1730 | static ssize_t |
1731 | show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf) | |
a98f0dd3 | 1732 | { |
1020bcbc | 1733 | strcpy(buf, mce_helper); |
a98f0dd3 | 1734 | strcat(buf, "\n"); |
1020bcbc | 1735 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
1736 | } |
1737 | ||
4a0b2b4d | 1738 | static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr, |
e9eee03e | 1739 | const char *buf, size_t siz) |
a98f0dd3 AK |
1740 | { |
1741 | char *p; | |
e9eee03e | 1742 | |
1020bcbc HS |
1743 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
1744 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 1745 | p = strchr(mce_helper, '\n'); |
e9eee03e | 1746 | |
e9084ec9 | 1747 | if (p) |
e9eee03e IM |
1748 | *p = 0; |
1749 | ||
e9084ec9 | 1750 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
1751 | } |
1752 | ||
9af43b54 HS |
1753 | static ssize_t set_ignore_ce(struct sys_device *s, |
1754 | struct sysdev_attribute *attr, | |
1755 | const char *buf, size_t size) | |
1756 | { | |
1757 | u64 new; | |
1758 | ||
1759 | if (strict_strtoull(buf, 0, &new) < 0) | |
1760 | return -EINVAL; | |
1761 | ||
1762 | if (mce_ignore_ce ^ !!new) { | |
1763 | if (new) { | |
1764 | /* disable ce features */ | |
1765 | on_each_cpu(mce_disable_ce, (void *)1, 1); | |
1766 | mce_ignore_ce = 1; | |
1767 | } else { | |
1768 | /* enable ce features */ | |
1769 | mce_ignore_ce = 0; | |
1770 | on_each_cpu(mce_enable_ce, (void *)1, 1); | |
1771 | } | |
1772 | } | |
1773 | return size; | |
1774 | } | |
1775 | ||
1776 | static ssize_t set_cmci_disabled(struct sys_device *s, | |
1777 | struct sysdev_attribute *attr, | |
1778 | const char *buf, size_t size) | |
1779 | { | |
1780 | u64 new; | |
1781 | ||
1782 | if (strict_strtoull(buf, 0, &new) < 0) | |
1783 | return -EINVAL; | |
1784 | ||
1785 | if (mce_cmci_disabled ^ !!new) { | |
1786 | if (new) { | |
1787 | /* disable cmci */ | |
1788 | on_each_cpu(mce_disable_ce, NULL, 1); | |
1789 | mce_cmci_disabled = 1; | |
1790 | } else { | |
1791 | /* enable cmci */ | |
1792 | mce_cmci_disabled = 0; | |
1793 | on_each_cpu(mce_enable_ce, NULL, 1); | |
1794 | } | |
1795 | } | |
1796 | return size; | |
1797 | } | |
1798 | ||
b56f642d AK |
1799 | static ssize_t store_int_with_restart(struct sys_device *s, |
1800 | struct sysdev_attribute *attr, | |
1801 | const char *buf, size_t size) | |
1802 | { | |
1803 | ssize_t ret = sysdev_store_int(s, attr, buf, size); | |
1804 | mce_restart(); | |
1805 | return ret; | |
1806 | } | |
1807 | ||
a98f0dd3 | 1808 | static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger); |
d95d62c0 | 1809 | static SYSDEV_INT_ATTR(tolerant, 0644, tolerant); |
3c079792 | 1810 | static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout); |
9af43b54 | 1811 | static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce); |
e9eee03e | 1812 | |
b56f642d AK |
1813 | static struct sysdev_ext_attribute attr_check_interval = { |
1814 | _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int, | |
1815 | store_int_with_restart), | |
1816 | &check_interval | |
1817 | }; | |
e9eee03e | 1818 | |
9af43b54 HS |
1819 | static struct sysdev_ext_attribute attr_ignore_ce = { |
1820 | _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce), | |
1821 | &mce_ignore_ce | |
1822 | }; | |
1823 | ||
1824 | static struct sysdev_ext_attribute attr_cmci_disabled = { | |
74b602c7 | 1825 | _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled), |
9af43b54 HS |
1826 | &mce_cmci_disabled |
1827 | }; | |
1828 | ||
cb491fca | 1829 | static struct sysdev_attribute *mce_attrs[] = { |
9af43b54 HS |
1830 | &attr_tolerant.attr, |
1831 | &attr_check_interval.attr, | |
1832 | &attr_trigger, | |
3c079792 | 1833 | &attr_monarch_timeout.attr, |
9af43b54 HS |
1834 | &attr_dont_log_ce.attr, |
1835 | &attr_ignore_ce.attr, | |
1836 | &attr_cmci_disabled.attr, | |
a98f0dd3 AK |
1837 | NULL |
1838 | }; | |
1da177e4 | 1839 | |
cb491fca | 1840 | static cpumask_var_t mce_dev_initialized; |
bae19fe0 | 1841 | |
e9eee03e | 1842 | /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */ |
91c6d400 | 1843 | static __cpuinit int mce_create_device(unsigned int cpu) |
1da177e4 LT |
1844 | { |
1845 | int err; | |
b1f49f95 | 1846 | int i, j; |
92cb7612 | 1847 | |
90367556 | 1848 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
1849 | return -EIO; |
1850 | ||
cb491fca IM |
1851 | memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject)); |
1852 | per_cpu(mce_dev, cpu).id = cpu; | |
1853 | per_cpu(mce_dev, cpu).cls = &mce_sysclass; | |
91c6d400 | 1854 | |
cb491fca | 1855 | err = sysdev_register(&per_cpu(mce_dev, cpu)); |
d435d862 AM |
1856 | if (err) |
1857 | return err; | |
1858 | ||
cb491fca IM |
1859 | for (i = 0; mce_attrs[i]; i++) { |
1860 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
d435d862 AM |
1861 | if (err) |
1862 | goto error; | |
1863 | } | |
b1f49f95 | 1864 | for (j = 0; j < banks; j++) { |
cb491fca | 1865 | err = sysdev_create_file(&per_cpu(mce_dev, cpu), |
cebe1820 | 1866 | &mce_banks[j].attr); |
0d7482e3 AK |
1867 | if (err) |
1868 | goto error2; | |
1869 | } | |
cb491fca | 1870 | cpumask_set_cpu(cpu, mce_dev_initialized); |
91c6d400 | 1871 | |
d435d862 | 1872 | return 0; |
0d7482e3 | 1873 | error2: |
b1f49f95 | 1874 | while (--j >= 0) |
cebe1820 | 1875 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr); |
d435d862 | 1876 | error: |
cb491fca | 1877 | while (--i >= 0) |
cebe1820 | 1878 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1879 | |
1880 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
d435d862 | 1881 | |
91c6d400 AK |
1882 | return err; |
1883 | } | |
1884 | ||
2d9cd6c2 | 1885 | static __cpuinit void mce_remove_device(unsigned int cpu) |
91c6d400 | 1886 | { |
73ca5358 SL |
1887 | int i; |
1888 | ||
cb491fca | 1889 | if (!cpumask_test_cpu(cpu, mce_dev_initialized)) |
bae19fe0 AH |
1890 | return; |
1891 | ||
cb491fca IM |
1892 | for (i = 0; mce_attrs[i]; i++) |
1893 | sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]); | |
1894 | ||
0d7482e3 | 1895 | for (i = 0; i < banks; i++) |
cebe1820 | 1896 | sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr); |
cb491fca IM |
1897 | |
1898 | sysdev_unregister(&per_cpu(mce_dev, cpu)); | |
1899 | cpumask_clear_cpu(cpu, mce_dev_initialized); | |
91c6d400 | 1900 | } |
91c6d400 | 1901 | |
d6b75584 | 1902 | /* Make sure there are no machine checks on offlined CPUs. */ |
ec5b3d32 | 1903 | static void mce_disable_cpu(void *h) |
d6b75584 | 1904 | { |
88ccbedd | 1905 | unsigned long action = *(unsigned long *)h; |
cb491fca | 1906 | int i; |
d6b75584 AK |
1907 | |
1908 | if (!mce_available(¤t_cpu_data)) | |
1909 | return; | |
88ccbedd AK |
1910 | if (!(action & CPU_TASKS_FROZEN)) |
1911 | cmci_clear(); | |
06b7a7a5 | 1912 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
1913 | struct mce_bank *b = &mce_banks[i]; |
1914 | if (b->init) | |
a2d32bcb | 1915 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
06b7a7a5 | 1916 | } |
d6b75584 AK |
1917 | } |
1918 | ||
ec5b3d32 | 1919 | static void mce_reenable_cpu(void *h) |
d6b75584 | 1920 | { |
88ccbedd | 1921 | unsigned long action = *(unsigned long *)h; |
e9eee03e | 1922 | int i; |
d6b75584 AK |
1923 | |
1924 | if (!mce_available(¤t_cpu_data)) | |
1925 | return; | |
e9eee03e | 1926 | |
88ccbedd AK |
1927 | if (!(action & CPU_TASKS_FROZEN)) |
1928 | cmci_reenable(); | |
06b7a7a5 | 1929 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
1930 | struct mce_bank *b = &mce_banks[i]; |
1931 | if (b->init) | |
a2d32bcb | 1932 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
06b7a7a5 | 1933 | } |
d6b75584 AK |
1934 | } |
1935 | ||
91c6d400 | 1936 | /* Get notified when a cpu comes on/off. Be hotplug friendly. */ |
e9eee03e IM |
1937 | static int __cpuinit |
1938 | mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu) | |
91c6d400 AK |
1939 | { |
1940 | unsigned int cpu = (unsigned long)hcpu; | |
52d168e2 | 1941 | struct timer_list *t = &per_cpu(mce_timer, cpu); |
91c6d400 AK |
1942 | |
1943 | switch (action) { | |
bae19fe0 AH |
1944 | case CPU_ONLINE: |
1945 | case CPU_ONLINE_FROZEN: | |
1946 | mce_create_device(cpu); | |
8735728e RW |
1947 | if (threshold_cpu_callback) |
1948 | threshold_cpu_callback(action, cpu); | |
91c6d400 | 1949 | break; |
91c6d400 | 1950 | case CPU_DEAD: |
8bb78442 | 1951 | case CPU_DEAD_FROZEN: |
8735728e RW |
1952 | if (threshold_cpu_callback) |
1953 | threshold_cpu_callback(action, cpu); | |
91c6d400 AK |
1954 | mce_remove_device(cpu); |
1955 | break; | |
52d168e2 AK |
1956 | case CPU_DOWN_PREPARE: |
1957 | case CPU_DOWN_PREPARE_FROZEN: | |
1958 | del_timer_sync(t); | |
88ccbedd | 1959 | smp_call_function_single(cpu, mce_disable_cpu, &action, 1); |
52d168e2 AK |
1960 | break; |
1961 | case CPU_DOWN_FAILED: | |
1962 | case CPU_DOWN_FAILED_FROZEN: | |
6298c512 | 1963 | t->expires = round_jiffies(jiffies + |
245b2e70 | 1964 | __get_cpu_var(mce_next_interval)); |
52d168e2 | 1965 | add_timer_on(t, cpu); |
88ccbedd AK |
1966 | smp_call_function_single(cpu, mce_reenable_cpu, &action, 1); |
1967 | break; | |
1968 | case CPU_POST_DEAD: | |
1969 | /* intentionally ignoring frozen here */ | |
1970 | cmci_rediscover(cpu); | |
52d168e2 | 1971 | break; |
91c6d400 | 1972 | } |
bae19fe0 | 1973 | return NOTIFY_OK; |
91c6d400 AK |
1974 | } |
1975 | ||
1e35669d | 1976 | static struct notifier_block mce_cpu_notifier __cpuinitdata = { |
91c6d400 AK |
1977 | .notifier_call = mce_cpu_callback, |
1978 | }; | |
1979 | ||
cebe1820 | 1980 | static __init void mce_init_banks(void) |
0d7482e3 AK |
1981 | { |
1982 | int i; | |
1983 | ||
0d7482e3 | 1984 | for (i = 0; i < banks; i++) { |
cebe1820 AK |
1985 | struct mce_bank *b = &mce_banks[i]; |
1986 | struct sysdev_attribute *a = &b->attr; | |
e9eee03e | 1987 | |
cebe1820 AK |
1988 | a->attr.name = b->attrname; |
1989 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
1990 | |
1991 | a->attr.mode = 0644; | |
1992 | a->show = show_bank; | |
1993 | a->store = set_bank; | |
0d7482e3 | 1994 | } |
0d7482e3 AK |
1995 | } |
1996 | ||
91c6d400 AK |
1997 | static __init int mce_init_device(void) |
1998 | { | |
1999 | int err; | |
2000 | int i = 0; | |
2001 | ||
1da177e4 LT |
2002 | if (!mce_available(&boot_cpu_data)) |
2003 | return -EIO; | |
0d7482e3 | 2004 | |
e92fae06 | 2005 | zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL); |
996867d0 | 2006 | |
cebe1820 | 2007 | mce_init_banks(); |
0d7482e3 | 2008 | |
1da177e4 | 2009 | err = sysdev_class_register(&mce_sysclass); |
d435d862 AM |
2010 | if (err) |
2011 | return err; | |
91c6d400 AK |
2012 | |
2013 | for_each_online_cpu(i) { | |
d435d862 AM |
2014 | err = mce_create_device(i); |
2015 | if (err) | |
2016 | return err; | |
91c6d400 AK |
2017 | } |
2018 | ||
be6b5a35 | 2019 | register_hotcpu_notifier(&mce_cpu_notifier); |
1da177e4 | 2020 | misc_register(&mce_log_device); |
e9eee03e | 2021 | |
1da177e4 | 2022 | return err; |
1da177e4 | 2023 | } |
91c6d400 | 2024 | |
1da177e4 | 2025 | device_initcall(mce_init_device); |
a988d334 | 2026 | |
d7c3c9a6 AK |
2027 | /* |
2028 | * Old style boot options parsing. Only for compatibility. | |
2029 | */ | |
2030 | static int __init mcheck_disable(char *str) | |
2031 | { | |
2032 | mce_disabled = 1; | |
2033 | return 1; | |
2034 | } | |
2035 | __setup("nomce", mcheck_disable); | |
a988d334 | 2036 | |
5be9ed25 HY |
2037 | #ifdef CONFIG_DEBUG_FS |
2038 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2039 | { |
5be9ed25 | 2040 | static struct dentry *dmce; |
a988d334 | 2041 | |
5be9ed25 HY |
2042 | if (!dmce) |
2043 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2044 | |
5be9ed25 HY |
2045 | return dmce; |
2046 | } | |
a988d334 | 2047 | |
bf783f9f HY |
2048 | static void mce_reset(void) |
2049 | { | |
2050 | cpu_missing = 0; | |
2051 | atomic_set(&mce_fake_paniced, 0); | |
2052 | atomic_set(&mce_executing, 0); | |
2053 | atomic_set(&mce_callin, 0); | |
2054 | atomic_set(&global_nwo, 0); | |
2055 | } | |
a988d334 | 2056 | |
bf783f9f HY |
2057 | static int fake_panic_get(void *data, u64 *val) |
2058 | { | |
2059 | *val = fake_panic; | |
2060 | return 0; | |
a988d334 IM |
2061 | } |
2062 | ||
bf783f9f | 2063 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2064 | { |
bf783f9f HY |
2065 | mce_reset(); |
2066 | fake_panic = val; | |
2067 | return 0; | |
a988d334 | 2068 | } |
a988d334 | 2069 | |
bf783f9f HY |
2070 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2071 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2072 | |
bf783f9f | 2073 | static int __init mce_debugfs_init(void) |
d7c3c9a6 | 2074 | { |
bf783f9f HY |
2075 | struct dentry *dmce, *ffake_panic; |
2076 | ||
2077 | dmce = mce_get_debugfs_dir(); | |
2078 | if (!dmce) | |
2079 | return -ENOMEM; | |
2080 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2081 | &fake_panic_fops); | |
2082 | if (!ffake_panic) | |
2083 | return -ENOMEM; | |
2084 | ||
2085 | return 0; | |
d7c3c9a6 | 2086 | } |
bf783f9f | 2087 | late_initcall(mce_debugfs_init); |
5be9ed25 | 2088 | #endif |