Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
f0fc4aff | 5 | #include <linux/module.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
1da177e4 | 8 | #include <linux/delay.h> |
9766cdbc JSR |
9 | #include <linux/sched.h> |
10 | #include <linux/init.h> | |
11 | #include <linux/kgdb.h> | |
1da177e4 | 12 | #include <linux/smp.h> |
9766cdbc JSR |
13 | #include <linux/io.h> |
14 | ||
15 | #include <asm/stackprotector.h> | |
cdd6c482 | 16 | #include <asm/perf_event.h> |
1da177e4 | 17 | #include <asm/mmu_context.h> |
49d859d7 | 18 | #include <asm/archrandom.h> |
9766cdbc JSR |
19 | #include <asm/hypervisor.h> |
20 | #include <asm/processor.h> | |
f649e938 | 21 | #include <asm/debugreg.h> |
9766cdbc | 22 | #include <asm/sections.h> |
8bdbd962 AC |
23 | #include <linux/topology.h> |
24 | #include <linux/cpumask.h> | |
9766cdbc | 25 | #include <asm/pgtable.h> |
60063497 | 26 | #include <linux/atomic.h> |
9766cdbc JSR |
27 | #include <asm/proto.h> |
28 | #include <asm/setup.h> | |
29 | #include <asm/apic.h> | |
30 | #include <asm/desc.h> | |
31 | #include <asm/i387.h> | |
1361b83a | 32 | #include <asm/fpu-internal.h> |
27b07da7 | 33 | #include <asm/mtrr.h> |
8bdbd962 | 34 | #include <linux/numa.h> |
9766cdbc JSR |
35 | #include <asm/asm.h> |
36 | #include <asm/cpu.h> | |
a03a3e28 | 37 | #include <asm/mce.h> |
9766cdbc | 38 | #include <asm/msr.h> |
8d4a4300 | 39 | #include <asm/pat.h> |
e641f5f5 IM |
40 | |
41 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 42 | #include <asm/uv/uv.h> |
1da177e4 LT |
43 | #endif |
44 | ||
45 | #include "cpu.h" | |
46 | ||
c2d1cec1 | 47 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 48 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
49 | cpumask_var_t cpu_callout_mask; |
50 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
51 | |
52 | /* representing cpus for which sibling maps can be computed */ | |
53 | cpumask_var_t cpu_sibling_setup_mask; | |
54 | ||
2f2f52ba | 55 | /* correctly size the local cpu masks */ |
4369f1fb | 56 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
57 | { |
58 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
59 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
60 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
61 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
62 | } | |
63 | ||
e8055139 OZ |
64 | static void __cpuinit default_init(struct cpuinfo_x86 *c) |
65 | { | |
66 | #ifdef CONFIG_X86_64 | |
27c13ece | 67 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
68 | #else |
69 | /* Not much we can do here... */ | |
70 | /* Check if at least it has cpuid */ | |
71 | if (c->cpuid_level == -1) { | |
72 | /* No cpuid. It must be an ancient CPU */ | |
73 | if (c->x86 == 4) | |
74 | strcpy(c->x86_model_id, "486"); | |
75 | else if (c->x86 == 3) | |
76 | strcpy(c->x86_model_id, "386"); | |
77 | } | |
78 | #endif | |
79 | } | |
80 | ||
81 | static const struct cpu_dev __cpuinitconst default_cpu = { | |
82 | .c_init = default_init, | |
83 | .c_vendor = "Unknown", | |
84 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
85 | }; | |
86 | ||
87 | static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu; | |
0a488a53 | 88 | |
06deef89 | 89 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 90 | #ifdef CONFIG_X86_64 |
06deef89 BG |
91 | /* |
92 | * We need valid kernel segments for data and code in long mode too | |
93 | * IRET will check the segment types kkeil 2000/10/28 | |
94 | * Also sysret mandates a special GDT layout | |
95 | * | |
9766cdbc | 96 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
97 | * Hopefully nobody expects them at a fixed place (Wine?) |
98 | */ | |
1e5de182 AM |
99 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
100 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
101 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
102 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
103 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
104 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 105 | #else |
1e5de182 AM |
106 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
107 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
108 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
109 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
110 | /* |
111 | * Segments used for calling PnP BIOS have byte granularity. | |
112 | * They code segments and data segments have fixed 64k limits, | |
113 | * the transfer segment sizes are set at run time. | |
114 | */ | |
6842ef0e | 115 | /* 32-bit code */ |
1e5de182 | 116 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 117 | /* 16-bit code */ |
1e5de182 | 118 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 119 | /* 16-bit data */ |
1e5de182 | 120 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 121 | /* 16-bit data */ |
1e5de182 | 122 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 123 | /* 16-bit data */ |
1e5de182 | 124 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
125 | /* |
126 | * The APM segments have byte granularity and their bases | |
127 | * are set at run time. All have 64k limits. | |
128 | */ | |
6842ef0e | 129 | /* 32-bit code */ |
1e5de182 | 130 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 131 | /* 16-bit code */ |
1e5de182 | 132 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 133 | /* data */ |
72c4d853 | 134 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 135 | |
1e5de182 AM |
136 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
137 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 138 | GDT_STACK_CANARY_INIT |
950ad7ff | 139 | #endif |
06deef89 | 140 | } }; |
7a61d35d | 141 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 142 | |
0c752a93 SS |
143 | static int __init x86_xsave_setup(char *s) |
144 | { | |
145 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
6bad06b7 | 146 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); |
c6fd893d SS |
147 | setup_clear_cpu_cap(X86_FEATURE_AVX); |
148 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
0c752a93 SS |
149 | return 1; |
150 | } | |
151 | __setup("noxsave", x86_xsave_setup); | |
152 | ||
6bad06b7 SS |
153 | static int __init x86_xsaveopt_setup(char *s) |
154 | { | |
155 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
156 | return 1; | |
157 | } | |
158 | __setup("noxsaveopt", x86_xsaveopt_setup); | |
159 | ||
ba51dced | 160 | #ifdef CONFIG_X86_32 |
3bc9b76b | 161 | static int cachesize_override __cpuinitdata = -1; |
3bc9b76b | 162 | static int disable_x86_serial_nr __cpuinitdata = 1; |
1da177e4 | 163 | |
0a488a53 YL |
164 | static int __init cachesize_setup(char *str) |
165 | { | |
166 | get_option(&str, &cachesize_override); | |
167 | return 1; | |
168 | } | |
169 | __setup("cachesize=", cachesize_setup); | |
170 | ||
0a488a53 YL |
171 | static int __init x86_fxsr_setup(char *s) |
172 | { | |
173 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
174 | setup_clear_cpu_cap(X86_FEATURE_XMM); | |
175 | return 1; | |
176 | } | |
177 | __setup("nofxsr", x86_fxsr_setup); | |
178 | ||
179 | static int __init x86_sep_setup(char *s) | |
180 | { | |
181 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
182 | return 1; | |
183 | } | |
184 | __setup("nosep", x86_sep_setup); | |
185 | ||
186 | /* Standard macro to see if a specific flag is changeable */ | |
187 | static inline int flag_is_changeable_p(u32 flag) | |
188 | { | |
189 | u32 f1, f2; | |
190 | ||
94f6bac1 KH |
191 | /* |
192 | * Cyrix and IDT cpus allow disabling of CPUID | |
193 | * so the code below may return different results | |
194 | * when it is executed before and after enabling | |
195 | * the CPUID. Add "volatile" to not allow gcc to | |
196 | * optimize the subsequent calls to this function. | |
197 | */ | |
0f3fa48a IM |
198 | asm volatile ("pushfl \n\t" |
199 | "pushfl \n\t" | |
200 | "popl %0 \n\t" | |
201 | "movl %0, %1 \n\t" | |
202 | "xorl %2, %0 \n\t" | |
203 | "pushl %0 \n\t" | |
204 | "popfl \n\t" | |
205 | "pushfl \n\t" | |
206 | "popl %0 \n\t" | |
207 | "popfl \n\t" | |
208 | ||
94f6bac1 KH |
209 | : "=&r" (f1), "=&r" (f2) |
210 | : "ir" (flag)); | |
0a488a53 YL |
211 | |
212 | return ((f1^f2) & flag) != 0; | |
213 | } | |
214 | ||
215 | /* Probe for the CPUID instruction */ | |
216 | static int __cpuinit have_cpuid_p(void) | |
217 | { | |
218 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
219 | } | |
220 | ||
221 | static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c) | |
222 | { | |
0f3fa48a IM |
223 | unsigned long lo, hi; |
224 | ||
225 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
226 | return; | |
227 | ||
228 | /* Disable processor serial number: */ | |
229 | ||
230 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
231 | lo |= 0x200000; | |
232 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
233 | ||
234 | printk(KERN_NOTICE "CPU serial number disabled.\n"); | |
235 | clear_cpu_cap(c, X86_FEATURE_PN); | |
236 | ||
237 | /* Disabling the serial number may affect the cpuid level */ | |
238 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
239 | } |
240 | ||
241 | static int __init x86_serial_nr_setup(char *s) | |
242 | { | |
243 | disable_x86_serial_nr = 0; | |
244 | return 1; | |
245 | } | |
246 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 247 | #else |
102bbe3a YL |
248 | static inline int flag_is_changeable_p(u32 flag) |
249 | { | |
250 | return 1; | |
251 | } | |
ba51dced YL |
252 | /* Probe for the CPUID instruction */ |
253 | static inline int have_cpuid_p(void) | |
254 | { | |
255 | return 1; | |
256 | } | |
102bbe3a YL |
257 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
258 | { | |
259 | } | |
ba51dced | 260 | #endif |
0a488a53 | 261 | |
82da65da | 262 | static int disable_smep __cpuinitdata; |
de5397ad FY |
263 | static __init int setup_disable_smep(char *arg) |
264 | { | |
265 | disable_smep = 1; | |
266 | return 1; | |
267 | } | |
268 | __setup("nosmep", setup_disable_smep); | |
269 | ||
82da65da | 270 | static __cpuinit void setup_smep(struct cpuinfo_x86 *c) |
de5397ad FY |
271 | { |
272 | if (cpu_has(c, X86_FEATURE_SMEP)) { | |
273 | if (unlikely(disable_smep)) { | |
274 | setup_clear_cpu_cap(X86_FEATURE_SMEP); | |
275 | clear_in_cr4(X86_CR4_SMEP); | |
276 | } else | |
277 | set_in_cr4(X86_CR4_SMEP); | |
278 | } | |
279 | } | |
280 | ||
52b6179a PA |
281 | static int disable_smap __cpuinitdata; |
282 | static __init int setup_disable_smap(char *arg) | |
283 | { | |
284 | disable_smap = 1; | |
285 | return 1; | |
286 | } | |
287 | __setup("nosmap", setup_disable_smap); | |
288 | ||
289 | static __cpuinit void setup_smap(struct cpuinfo_x86 *c) | |
290 | { | |
291 | if (cpu_has(c, X86_FEATURE_SMAP)) { | |
292 | if (unlikely(disable_smap)) { | |
293 | setup_clear_cpu_cap(X86_FEATURE_SMAP); | |
294 | clear_in_cr4(X86_CR4_SMAP); | |
295 | } else { | |
296 | set_in_cr4(X86_CR4_SMAP); | |
297 | /* | |
298 | * Don't use clac() here since alternatives | |
299 | * haven't run yet... | |
300 | */ | |
301 | asm volatile(__stringify(__ASM_CLAC) ::: "memory"); | |
302 | } | |
303 | } | |
304 | } | |
305 | ||
b38b0665 PA |
306 | /* |
307 | * Some CPU features depend on higher CPUID levels, which may not always | |
308 | * be available due to CPUID level capping or broken virtualization | |
309 | * software. Add those features to this table to auto-disable them. | |
310 | */ | |
311 | struct cpuid_dependent_feature { | |
312 | u32 feature; | |
313 | u32 level; | |
314 | }; | |
0f3fa48a | 315 | |
b38b0665 PA |
316 | static const struct cpuid_dependent_feature __cpuinitconst |
317 | cpuid_dependent_features[] = { | |
318 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
319 | { X86_FEATURE_DCA, 0x00000009 }, | |
320 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
321 | { 0, 0 } | |
322 | }; | |
323 | ||
324 | static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) | |
325 | { | |
326 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 327 | |
b38b0665 | 328 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
329 | |
330 | if (!cpu_has(c, df->feature)) | |
331 | continue; | |
b38b0665 PA |
332 | /* |
333 | * Note: cpuid_level is set to -1 if unavailable, but | |
334 | * extended_extended_level is set to 0 if unavailable | |
335 | * and the legitimate extended levels are all negative | |
336 | * when signed; hence the weird messing around with | |
337 | * signs here... | |
338 | */ | |
0f3fa48a | 339 | if (!((s32)df->level < 0 ? |
f6db44df | 340 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
341 | (s32)df->level > (s32)c->cpuid_level)) |
342 | continue; | |
343 | ||
344 | clear_cpu_cap(c, df->feature); | |
345 | if (!warn) | |
346 | continue; | |
347 | ||
348 | printk(KERN_WARNING | |
349 | "CPU: CPU feature %s disabled, no CPUID level 0x%x\n", | |
350 | x86_cap_flags[df->feature], df->level); | |
b38b0665 | 351 | } |
f6db44df | 352 | } |
b38b0665 | 353 | |
102bbe3a YL |
354 | /* |
355 | * Naming convention should be: <Name> [(<Codename>)] | |
356 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
357 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
358 | * isn't used | |
102bbe3a YL |
359 | */ |
360 | ||
361 | /* Look up CPU names by table lookup. */ | |
02dde8b4 | 362 | static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 363 | { |
02dde8b4 | 364 | const struct cpu_model_info *info; |
102bbe3a YL |
365 | |
366 | if (c->x86_model >= 16) | |
367 | return NULL; /* Range check */ | |
368 | ||
369 | if (!this_cpu) | |
370 | return NULL; | |
371 | ||
372 | info = this_cpu->c_models; | |
373 | ||
374 | while (info && info->family) { | |
375 | if (info->family == c->x86) | |
376 | return info->model_names[c->x86_model]; | |
377 | info++; | |
378 | } | |
379 | return NULL; /* Not found */ | |
380 | } | |
381 | ||
3e0c3737 YL |
382 | __u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata; |
383 | __u32 cpu_caps_set[NCAPINTS] __cpuinitdata; | |
7d851c8d | 384 | |
11e3a840 JF |
385 | void load_percpu_segment(int cpu) |
386 | { | |
387 | #ifdef CONFIG_X86_32 | |
388 | loadsegment(fs, __KERNEL_PERCPU); | |
389 | #else | |
390 | loadsegment(gs, 0); | |
391 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); | |
392 | #endif | |
60a5317f | 393 | load_stack_canary_segment(); |
11e3a840 JF |
394 | } |
395 | ||
0f3fa48a IM |
396 | /* |
397 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
398 | * it's on the real one. | |
399 | */ | |
552be871 | 400 | void switch_to_new_gdt(int cpu) |
9d31d35b YL |
401 | { |
402 | struct desc_ptr gdt_descr; | |
403 | ||
2697fbd5 | 404 | gdt_descr.address = (long)get_cpu_gdt_table(cpu); |
9d31d35b YL |
405 | gdt_descr.size = GDT_SIZE - 1; |
406 | load_gdt(&gdt_descr); | |
2697fbd5 | 407 | /* Reload the per-cpu base */ |
11e3a840 JF |
408 | |
409 | load_percpu_segment(cpu); | |
9d31d35b YL |
410 | } |
411 | ||
02dde8b4 | 412 | static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 413 | |
1b05d60d | 414 | static void __cpuinit get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
415 | { |
416 | unsigned int *v; | |
417 | char *p, *q; | |
418 | ||
3da99c97 | 419 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 420 | return; |
1da177e4 | 421 | |
0f3fa48a | 422 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
423 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
424 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
425 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
426 | c->x86_model_id[48] = 0; | |
427 | ||
0f3fa48a IM |
428 | /* |
429 | * Intel chips right-justify this string for some dumb reason; | |
430 | * undo that brain damage: | |
431 | */ | |
1da177e4 | 432 | p = q = &c->x86_model_id[0]; |
34048c9e | 433 | while (*p == ' ') |
9766cdbc | 434 | p++; |
34048c9e | 435 | if (p != q) { |
9766cdbc JSR |
436 | while (*p) |
437 | *q++ = *p++; | |
438 | while (q <= &c->x86_model_id[48]) | |
439 | *q++ = '\0'; /* Zero-pad the rest */ | |
1da177e4 | 440 | } |
1da177e4 LT |
441 | } |
442 | ||
27c13ece | 443 | void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 444 | { |
9d31d35b | 445 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 446 | |
3da99c97 | 447 | n = c->extended_cpuid_level; |
1da177e4 LT |
448 | |
449 | if (n >= 0x80000005) { | |
9d31d35b | 450 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 451 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
452 | #ifdef CONFIG_X86_64 |
453 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
454 | c->x86_tlbsize = 0; | |
455 | #endif | |
1da177e4 LT |
456 | } |
457 | ||
458 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
459 | return; | |
460 | ||
0a488a53 | 461 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 462 | l2size = ecx >> 16; |
34048c9e | 463 | |
140fc727 YL |
464 | #ifdef CONFIG_X86_64 |
465 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
466 | #else | |
1da177e4 LT |
467 | /* do processor-specific cache resizing */ |
468 | if (this_cpu->c_size_cache) | |
34048c9e | 469 | l2size = this_cpu->c_size_cache(c, l2size); |
1da177e4 LT |
470 | |
471 | /* Allow user to override all this if necessary. */ | |
472 | if (cachesize_override != -1) | |
473 | l2size = cachesize_override; | |
474 | ||
34048c9e | 475 | if (l2size == 0) |
1da177e4 | 476 | return; /* Again, no L2 cache is possible */ |
140fc727 | 477 | #endif |
1da177e4 LT |
478 | |
479 | c->x86_cache_size = l2size; | |
1da177e4 LT |
480 | } |
481 | ||
e0ba94f1 AS |
482 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
483 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
484 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
485 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
486 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
487 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
488 | ||
c4211f42 AS |
489 | /* |
490 | * tlb_flushall_shift shows the balance point in replacing cr3 write | |
491 | * with multiple 'invlpg'. It will do this replacement when | |
492 | * flush_tlb_lines <= active_lines/2^tlb_flushall_shift. | |
493 | * If tlb_flushall_shift is -1, means the replacement will be disabled. | |
494 | */ | |
495 | s8 __read_mostly tlb_flushall_shift = -1; | |
496 | ||
e0ba94f1 AS |
497 | void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c) |
498 | { | |
499 | if (this_cpu->c_detect_tlb) | |
500 | this_cpu->c_detect_tlb(c); | |
501 | ||
502 | printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ | |
c4211f42 AS |
503 | "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \ |
504 | "tlb_flushall_shift is 0x%x\n", | |
e0ba94f1 AS |
505 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
506 | tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES], | |
c4211f42 AS |
507 | tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES], |
508 | tlb_flushall_shift); | |
e0ba94f1 AS |
509 | } |
510 | ||
9d31d35b | 511 | void __cpuinit detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 512 | { |
97e4db7c | 513 | #ifdef CONFIG_X86_HT |
0a488a53 YL |
514 | u32 eax, ebx, ecx, edx; |
515 | int index_msb, core_bits; | |
2eaad1fd | 516 | static bool printed; |
1da177e4 | 517 | |
0a488a53 | 518 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 519 | return; |
1da177e4 | 520 | |
0a488a53 YL |
521 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
522 | goto out; | |
1da177e4 | 523 | |
1cd78776 YL |
524 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
525 | return; | |
1da177e4 | 526 | |
0a488a53 | 527 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 528 | |
9d31d35b YL |
529 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
530 | ||
531 | if (smp_num_siblings == 1) { | |
2eaad1fd | 532 | printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
533 | goto out; |
534 | } | |
9d31d35b | 535 | |
0f3fa48a IM |
536 | if (smp_num_siblings <= 1) |
537 | goto out; | |
9d31d35b | 538 | |
0f3fa48a IM |
539 | index_msb = get_count_order(smp_num_siblings); |
540 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 541 | |
0f3fa48a | 542 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 543 | |
0f3fa48a | 544 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 545 | |
0f3fa48a | 546 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 547 | |
0f3fa48a IM |
548 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
549 | ((1 << core_bits) - 1); | |
1da177e4 | 550 | |
0a488a53 | 551 | out: |
2eaad1fd | 552 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
0a488a53 YL |
553 | printk(KERN_INFO "CPU: Physical Processor ID: %d\n", |
554 | c->phys_proc_id); | |
555 | printk(KERN_INFO "CPU: Processor Core ID: %d\n", | |
556 | c->cpu_core_id); | |
2eaad1fd | 557 | printed = 1; |
9d31d35b | 558 | } |
9d31d35b | 559 | #endif |
97e4db7c | 560 | } |
1da177e4 | 561 | |
3da99c97 | 562 | static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
563 | { |
564 | char *v = c->x86_vendor_id; | |
0f3fa48a | 565 | int i; |
1da177e4 LT |
566 | |
567 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
568 | if (!cpu_devs[i]) |
569 | break; | |
570 | ||
571 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
572 | (cpu_devs[i]->c_ident[1] && | |
573 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 574 | |
10a434fc YL |
575 | this_cpu = cpu_devs[i]; |
576 | c->x86_vendor = this_cpu->c_x86_vendor; | |
577 | return; | |
1da177e4 LT |
578 | } |
579 | } | |
10a434fc | 580 | |
a9c56953 MK |
581 | printk_once(KERN_ERR |
582 | "CPU: vendor_id '%s' unknown, using generic init.\n" \ | |
583 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 584 | |
fe38d855 CE |
585 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
586 | this_cpu = &default_cpu; | |
1da177e4 LT |
587 | } |
588 | ||
9d31d35b | 589 | void __cpuinit cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 590 | { |
1da177e4 | 591 | /* Get vendor name */ |
4a148513 HH |
592 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
593 | (unsigned int *)&c->x86_vendor_id[0], | |
594 | (unsigned int *)&c->x86_vendor_id[8], | |
595 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 596 | |
1da177e4 | 597 | c->x86 = 4; |
9d31d35b | 598 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
599 | if (c->cpuid_level >= 0x00000001) { |
600 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 601 | |
1da177e4 | 602 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
9d31d35b YL |
603 | c->x86 = (tfms >> 8) & 0xf; |
604 | c->x86_model = (tfms >> 4) & 0xf; | |
605 | c->x86_mask = tfms & 0xf; | |
0f3fa48a | 606 | |
f5f786d0 | 607 | if (c->x86 == 0xf) |
1da177e4 | 608 | c->x86 += (tfms >> 20) & 0xff; |
f5f786d0 | 609 | if (c->x86 >= 0x6) |
9d31d35b | 610 | c->x86_model += ((tfms >> 16) & 0xf) << 4; |
0f3fa48a | 611 | |
d4387bd3 | 612 | if (cap0 & (1<<19)) { |
d4387bd3 | 613 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 614 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 615 | } |
1da177e4 | 616 | } |
1da177e4 | 617 | } |
3da99c97 | 618 | |
d900329e | 619 | void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 YL |
620 | { |
621 | u32 tfms, xlvl; | |
3da99c97 | 622 | u32 ebx; |
093af8d7 | 623 | |
3da99c97 YL |
624 | /* Intel-defined flags: level 0x00000001 */ |
625 | if (c->cpuid_level >= 0x00000001) { | |
626 | u32 capability, excap; | |
0f3fa48a | 627 | |
3da99c97 YL |
628 | cpuid(0x00000001, &tfms, &ebx, &excap, &capability); |
629 | c->x86_capability[0] = capability; | |
630 | c->x86_capability[4] = excap; | |
631 | } | |
093af8d7 | 632 | |
bdc802dc PA |
633 | /* Additional Intel-defined flags: level 0x00000007 */ |
634 | if (c->cpuid_level >= 0x00000007) { | |
635 | u32 eax, ebx, ecx, edx; | |
636 | ||
637 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); | |
638 | ||
2494b030 | 639 | c->x86_capability[9] = ebx; |
bdc802dc PA |
640 | } |
641 | ||
3da99c97 YL |
642 | /* AMD-defined flags: level 0x80000001 */ |
643 | xlvl = cpuid_eax(0x80000000); | |
644 | c->extended_cpuid_level = xlvl; | |
0f3fa48a | 645 | |
3da99c97 YL |
646 | if ((xlvl & 0xffff0000) == 0x80000000) { |
647 | if (xlvl >= 0x80000001) { | |
648 | c->x86_capability[1] = cpuid_edx(0x80000001); | |
649 | c->x86_capability[6] = cpuid_ecx(0x80000001); | |
093af8d7 | 650 | } |
093af8d7 | 651 | } |
093af8d7 | 652 | |
5122c890 YL |
653 | if (c->extended_cpuid_level >= 0x80000008) { |
654 | u32 eax = cpuid_eax(0x80000008); | |
655 | ||
656 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
657 | c->x86_phys_bits = eax & 0xff; | |
093af8d7 | 658 | } |
13c6c532 JB |
659 | #ifdef CONFIG_X86_32 |
660 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
661 | c->x86_phys_bits = 36; | |
5122c890 | 662 | #endif |
e3224234 YL |
663 | |
664 | if (c->extended_cpuid_level >= 0x80000007) | |
665 | c->x86_power = cpuid_edx(0x80000007); | |
093af8d7 | 666 | |
1dedefd1 | 667 | init_scattered_cpuid_features(c); |
093af8d7 | 668 | } |
1da177e4 | 669 | |
aef93c8b YL |
670 | static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
671 | { | |
672 | #ifdef CONFIG_X86_32 | |
673 | int i; | |
674 | ||
675 | /* | |
676 | * First of all, decide if this is a 486 or higher | |
677 | * It's a 486 if we can modify the AC flag | |
678 | */ | |
679 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
680 | c->x86 = 4; | |
681 | else | |
682 | c->x86 = 3; | |
683 | ||
684 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
685 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
686 | c->x86_vendor_id[0] = 0; | |
687 | cpu_devs[i]->c_identify(c); | |
688 | if (c->x86_vendor_id[0]) { | |
689 | get_cpu_vendor(c); | |
690 | break; | |
691 | } | |
692 | } | |
693 | #endif | |
694 | } | |
695 | ||
34048c9e PC |
696 | /* |
697 | * Do minimum CPU detection early. | |
698 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
699 | * cache alignment. | |
700 | * The others are not touched to avoid unwanted side effects. | |
701 | * | |
702 | * WARNING: this function is only called on the BP. Don't add code here | |
703 | * that is supposed to run on all CPUs. | |
704 | */ | |
3da99c97 | 705 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 706 | { |
6627d242 YL |
707 | #ifdef CONFIG_X86_64 |
708 | c->x86_clflush_size = 64; | |
13c6c532 JB |
709 | c->x86_phys_bits = 36; |
710 | c->x86_virt_bits = 48; | |
6627d242 | 711 | #else |
d4387bd3 | 712 | c->x86_clflush_size = 32; |
13c6c532 JB |
713 | c->x86_phys_bits = 32; |
714 | c->x86_virt_bits = 32; | |
6627d242 | 715 | #endif |
0a488a53 | 716 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 717 | |
3da99c97 | 718 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 719 | c->extended_cpuid_level = 0; |
d7cd5611 | 720 | |
aef93c8b YL |
721 | if (!have_cpuid_p()) |
722 | identify_cpu_without_cpuid(c); | |
723 | ||
724 | /* cyrix could have cpuid enabled via c_identify()*/ | |
d7cd5611 RR |
725 | if (!have_cpuid_p()) |
726 | return; | |
727 | ||
728 | cpu_detect(c); | |
729 | ||
3da99c97 | 730 | get_cpu_vendor(c); |
2b16a235 | 731 | |
3da99c97 | 732 | get_cpu_cap(c); |
12cf105c | 733 | |
10a434fc YL |
734 | if (this_cpu->c_early_init) |
735 | this_cpu->c_early_init(c); | |
093af8d7 | 736 | |
f6e9456c | 737 | c->cpu_index = 0; |
b38b0665 | 738 | filter_cpuid_features(c, false); |
de5397ad FY |
739 | |
740 | setup_smep(c); | |
52b6179a | 741 | setup_smap(c); |
a110b5ec BP |
742 | |
743 | if (this_cpu->c_bsp_init) | |
744 | this_cpu->c_bsp_init(c); | |
d7cd5611 RR |
745 | } |
746 | ||
9d31d35b YL |
747 | void __init early_cpu_init(void) |
748 | { | |
02dde8b4 | 749 | const struct cpu_dev *const *cdev; |
10a434fc YL |
750 | int count = 0; |
751 | ||
ac23f253 | 752 | #ifdef CONFIG_PROCESSOR_SELECT |
9766cdbc | 753 | printk(KERN_INFO "KERNEL supported cpus:\n"); |
31c997ca IM |
754 | #endif |
755 | ||
10a434fc | 756 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 757 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 758 | |
10a434fc YL |
759 | if (count >= X86_VENDOR_NUM) |
760 | break; | |
761 | cpu_devs[count] = cpudev; | |
762 | count++; | |
763 | ||
ac23f253 | 764 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
765 | { |
766 | unsigned int j; | |
767 | ||
768 | for (j = 0; j < 2; j++) { | |
769 | if (!cpudev->c_ident[j]) | |
770 | continue; | |
771 | printk(KERN_INFO " %s %s\n", cpudev->c_vendor, | |
772 | cpudev->c_ident[j]); | |
773 | } | |
10a434fc | 774 | } |
0388423d | 775 | #endif |
10a434fc | 776 | } |
9d31d35b | 777 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 778 | } |
093af8d7 | 779 | |
b6734c35 | 780 | /* |
366d4a43 BP |
781 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
782 | * unfortunately, that's not true in practice because of early VIA | |
783 | * chips and (more importantly) broken virtualizers that are not easy | |
784 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
785 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 786 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 787 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 PA |
788 | */ |
789 | static void __cpuinit detect_nopl(struct cpuinfo_x86 *c) | |
790 | { | |
366d4a43 | 791 | #ifdef CONFIG_X86_32 |
b6734c35 | 792 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
793 | #else |
794 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
795 | #endif | |
d7cd5611 RR |
796 | } |
797 | ||
34048c9e | 798 | static void __cpuinit generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 799 | { |
aef93c8b | 800 | c->extended_cpuid_level = 0; |
1da177e4 | 801 | |
3da99c97 | 802 | if (!have_cpuid_p()) |
aef93c8b | 803 | identify_cpu_without_cpuid(c); |
1d67953f | 804 | |
aef93c8b | 805 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 806 | if (!have_cpuid_p()) |
aef93c8b | 807 | return; |
1da177e4 | 808 | |
3da99c97 | 809 | cpu_detect(c); |
1da177e4 | 810 | |
3da99c97 | 811 | get_cpu_vendor(c); |
1da177e4 | 812 | |
3da99c97 | 813 | get_cpu_cap(c); |
1da177e4 | 814 | |
3da99c97 YL |
815 | if (c->cpuid_level >= 0x00000001) { |
816 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e YL |
817 | #ifdef CONFIG_X86_32 |
818 | # ifdef CONFIG_X86_HT | |
cb8cc442 | 819 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 820 | # else |
3da99c97 | 821 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
822 | # endif |
823 | #endif | |
b89d3b3e | 824 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 825 | } |
1da177e4 | 826 | |
de5397ad FY |
827 | setup_smep(c); |
828 | ||
1b05d60d | 829 | get_model_name(c); /* Default name */ |
1da177e4 | 830 | |
3da99c97 | 831 | detect_nopl(c); |
1da177e4 | 832 | } |
1da177e4 LT |
833 | |
834 | /* | |
835 | * This does the hard work of actually picking apart the CPU stuff... | |
836 | */ | |
9a250347 | 837 | static void __cpuinit identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
838 | { |
839 | int i; | |
840 | ||
841 | c->loops_per_jiffy = loops_per_jiffy; | |
842 | c->x86_cache_size = -1; | |
843 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
844 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
845 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
846 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 847 | c->x86_max_cores = 1; |
102bbe3a | 848 | c->x86_coreid_bits = 0; |
11fdd252 | 849 | #ifdef CONFIG_X86_64 |
102bbe3a | 850 | c->x86_clflush_size = 64; |
13c6c532 JB |
851 | c->x86_phys_bits = 36; |
852 | c->x86_virt_bits = 48; | |
102bbe3a YL |
853 | #else |
854 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 855 | c->x86_clflush_size = 32; |
13c6c532 JB |
856 | c->x86_phys_bits = 32; |
857 | c->x86_virt_bits = 32; | |
102bbe3a YL |
858 | #endif |
859 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
860 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
861 | ||
1da177e4 LT |
862 | generic_identify(c); |
863 | ||
3898534d | 864 | if (this_cpu->c_identify) |
1da177e4 LT |
865 | this_cpu->c_identify(c); |
866 | ||
2759c328 YL |
867 | /* Clear/Set all flags overriden by options, after probe */ |
868 | for (i = 0; i < NCAPINTS; i++) { | |
869 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
870 | c->x86_capability[i] |= cpu_caps_set[i]; | |
871 | } | |
872 | ||
102bbe3a | 873 | #ifdef CONFIG_X86_64 |
cb8cc442 | 874 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
875 | #endif |
876 | ||
1da177e4 LT |
877 | /* |
878 | * Vendor-specific initialization. In this section we | |
879 | * canonicalize the feature flags, meaning if there are | |
880 | * features a certain CPU supports which CPUID doesn't | |
881 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
882 | * we handle them here. | |
883 | * | |
884 | * At the end of this section, c->x86_capability better | |
885 | * indicate the features this CPU genuinely supports! | |
886 | */ | |
887 | if (this_cpu->c_init) | |
888 | this_cpu->c_init(c); | |
889 | ||
890 | /* Disable the PN if appropriate */ | |
891 | squash_the_stupid_serial_number(c); | |
892 | ||
893 | /* | |
0f3fa48a IM |
894 | * The vendor-specific functions might have changed features. |
895 | * Now we do "generic changes." | |
1da177e4 LT |
896 | */ |
897 | ||
b38b0665 PA |
898 | /* Filter out anything that depends on CPUID levels we don't have */ |
899 | filter_cpuid_features(c, true); | |
900 | ||
1da177e4 | 901 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 902 | if (!c->x86_model_id[0]) { |
02dde8b4 | 903 | const char *p; |
1da177e4 | 904 | p = table_lookup_model(c); |
34048c9e | 905 | if (p) |
1da177e4 LT |
906 | strcpy(c->x86_model_id, p); |
907 | else | |
908 | /* Last resort... */ | |
909 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 910 | c->x86, c->x86_model); |
1da177e4 LT |
911 | } |
912 | ||
102bbe3a YL |
913 | #ifdef CONFIG_X86_64 |
914 | detect_ht(c); | |
915 | #endif | |
916 | ||
88b094fb | 917 | init_hypervisor(c); |
49d859d7 | 918 | x86_init_rdrand(c); |
3e0c3737 YL |
919 | |
920 | /* | |
921 | * Clear/Set all flags overriden by options, need do it | |
922 | * before following smp all cpus cap AND. | |
923 | */ | |
924 | for (i = 0; i < NCAPINTS; i++) { | |
925 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
926 | c->x86_capability[i] |= cpu_caps_set[i]; | |
927 | } | |
928 | ||
1da177e4 LT |
929 | /* |
930 | * On SMP, boot_cpu_data holds the common feature set between | |
931 | * all CPUs; so make sure that we indicate which features are | |
932 | * common between the CPUs. The first time this routine gets | |
933 | * executed, c == &boot_cpu_data. | |
934 | */ | |
34048c9e | 935 | if (c != &boot_cpu_data) { |
1da177e4 | 936 | /* AND the already accumulated flags with these */ |
9d31d35b | 937 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 LT |
938 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
939 | } | |
940 | ||
941 | /* Init Machine Check Exception if available. */ | |
5e09954a | 942 | mcheck_cpu_init(c); |
30d432df AK |
943 | |
944 | select_idle_routine(c); | |
102bbe3a | 945 | |
de2d9445 | 946 | #ifdef CONFIG_NUMA |
102bbe3a YL |
947 | numa_add_cpu(smp_processor_id()); |
948 | #endif | |
a6c4e076 | 949 | } |
31ab269a | 950 | |
e04d645f GC |
951 | #ifdef CONFIG_X86_64 |
952 | static void vgetcpu_set_mode(void) | |
953 | { | |
954 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | |
955 | vgetcpu_mode = VGETCPU_RDTSCP; | |
956 | else | |
957 | vgetcpu_mode = VGETCPU_LSL; | |
958 | } | |
959 | #endif | |
960 | ||
a6c4e076 JF |
961 | void __init identify_boot_cpu(void) |
962 | { | |
963 | identify_cpu(&boot_cpu_data); | |
02c68a02 | 964 | init_amd_e400_c1e_mask(); |
102bbe3a | 965 | #ifdef CONFIG_X86_32 |
a6c4e076 | 966 | sysenter_setup(); |
6fe940d6 | 967 | enable_sep_cpu(); |
e04d645f GC |
968 | #else |
969 | vgetcpu_set_mode(); | |
102bbe3a | 970 | #endif |
e0ba94f1 AS |
971 | if (boot_cpu_data.cpuid_level >= 2) |
972 | cpu_detect_tlb(&boot_cpu_data); | |
a6c4e076 | 973 | } |
3b520b23 | 974 | |
a6c4e076 JF |
975 | void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c) |
976 | { | |
977 | BUG_ON(c == &boot_cpu_data); | |
978 | identify_cpu(c); | |
102bbe3a | 979 | #ifdef CONFIG_X86_32 |
a6c4e076 | 980 | enable_sep_cpu(); |
102bbe3a | 981 | #endif |
a6c4e076 | 982 | mtrr_ap_init(); |
1da177e4 LT |
983 | } |
984 | ||
a0854a46 | 985 | struct msr_range { |
0f3fa48a IM |
986 | unsigned min; |
987 | unsigned max; | |
a0854a46 | 988 | }; |
1da177e4 | 989 | |
02dde8b4 | 990 | static const struct msr_range msr_range_array[] __cpuinitconst = { |
a0854a46 YL |
991 | { 0x00000000, 0x00000418}, |
992 | { 0xc0000000, 0xc000040b}, | |
993 | { 0xc0010000, 0xc0010142}, | |
994 | { 0xc0011000, 0xc001103b}, | |
995 | }; | |
1da177e4 | 996 | |
21c3fcf3 | 997 | static void __cpuinit __print_cpu_msr(void) |
a0854a46 | 998 | { |
0f3fa48a | 999 | unsigned index_min, index_max; |
a0854a46 YL |
1000 | unsigned index; |
1001 | u64 val; | |
1002 | int i; | |
a0854a46 YL |
1003 | |
1004 | for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) { | |
1005 | index_min = msr_range_array[i].min; | |
1006 | index_max = msr_range_array[i].max; | |
0f3fa48a | 1007 | |
a0854a46 | 1008 | for (index = index_min; index < index_max; index++) { |
ecd431d9 | 1009 | if (rdmsrl_safe(index, &val)) |
a0854a46 YL |
1010 | continue; |
1011 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | |
1da177e4 | 1012 | } |
a0854a46 YL |
1013 | } |
1014 | } | |
94605eff | 1015 | |
a0854a46 | 1016 | static int show_msr __cpuinitdata; |
0f3fa48a | 1017 | |
a0854a46 YL |
1018 | static __init int setup_show_msr(char *arg) |
1019 | { | |
1020 | int num; | |
3dd9d514 | 1021 | |
a0854a46 | 1022 | get_option(&arg, &num); |
3dd9d514 | 1023 | |
a0854a46 YL |
1024 | if (num > 0) |
1025 | show_msr = num; | |
1026 | return 1; | |
1da177e4 | 1027 | } |
a0854a46 | 1028 | __setup("show_msr=", setup_show_msr); |
1da177e4 | 1029 | |
191679fd AK |
1030 | static __init int setup_noclflush(char *arg) |
1031 | { | |
1032 | setup_clear_cpu_cap(X86_FEATURE_CLFLSH); | |
1033 | return 1; | |
1034 | } | |
1035 | __setup("noclflush", setup_noclflush); | |
1036 | ||
3bc9b76b | 1037 | void __cpuinit print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1038 | { |
02dde8b4 | 1039 | const char *vendor = NULL; |
1da177e4 | 1040 | |
0f3fa48a | 1041 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1042 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1043 | } else { |
1044 | if (c->cpuid_level >= 0) | |
1045 | vendor = c->x86_vendor_id; | |
1046 | } | |
1da177e4 | 1047 | |
bd32a8cf | 1048 | if (vendor && !strstr(c->x86_model_id, vendor)) |
9d31d35b | 1049 | printk(KERN_CONT "%s ", vendor); |
1da177e4 | 1050 | |
9d31d35b YL |
1051 | if (c->x86_model_id[0]) |
1052 | printk(KERN_CONT "%s", c->x86_model_id); | |
1da177e4 | 1053 | else |
9d31d35b | 1054 | printk(KERN_CONT "%d86", c->x86); |
1da177e4 | 1055 | |
34048c9e | 1056 | if (c->x86_mask || c->cpuid_level >= 0) |
9d31d35b | 1057 | printk(KERN_CONT " stepping %02x\n", c->x86_mask); |
1da177e4 | 1058 | else |
9d31d35b | 1059 | printk(KERN_CONT "\n"); |
a0854a46 | 1060 | |
0b8b8078 | 1061 | print_cpu_msr(c); |
21c3fcf3 YL |
1062 | } |
1063 | ||
1064 | void __cpuinit print_cpu_msr(struct cpuinfo_x86 *c) | |
1065 | { | |
a0854a46 | 1066 | if (c->cpu_index < show_msr) |
21c3fcf3 | 1067 | __print_cpu_msr(); |
1da177e4 LT |
1068 | } |
1069 | ||
ac72e788 AK |
1070 | static __init int setup_disablecpuid(char *arg) |
1071 | { | |
1072 | int bit; | |
0f3fa48a | 1073 | |
ac72e788 AK |
1074 | if (get_option(&arg, &bit) && bit < NCAPINTS*32) |
1075 | setup_clear_cpu_cap(bit); | |
1076 | else | |
1077 | return 0; | |
0f3fa48a | 1078 | |
ac72e788 AK |
1079 | return 1; |
1080 | } | |
1081 | __setup("clearcpuid=", setup_disablecpuid); | |
1082 | ||
d5494d4f | 1083 | #ifdef CONFIG_X86_64 |
9ff80942 | 1084 | struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table }; |
228bdaa9 SR |
1085 | struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1, |
1086 | (unsigned long) nmi_idt_table }; | |
d5494d4f | 1087 | |
947e76cd BG |
1088 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
1089 | irq_stack_union) __aligned(PAGE_SIZE); | |
0f3fa48a | 1090 | |
bdf977b3 TH |
1091 | /* |
1092 | * The following four percpu variables are hot. Align current_task to | |
1093 | * cacheline size such that all four fall in the same cacheline. | |
1094 | */ | |
1095 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1096 | &init_task; | |
1097 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1098 | |
9af45651 BG |
1099 | DEFINE_PER_CPU(unsigned long, kernel_stack) = |
1100 | (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE; | |
1101 | EXPORT_PER_CPU_SYMBOL(kernel_stack); | |
1102 | ||
bdf977b3 TH |
1103 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
1104 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64; | |
1105 | ||
56895530 | 1106 | DEFINE_PER_CPU(unsigned int, irq_count) = -1; |
d5494d4f | 1107 | |
7e16838d LT |
1108 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
1109 | ||
0f3fa48a IM |
1110 | /* |
1111 | * Special IST stacks which the CPU switches to when it calls | |
1112 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
1113 | * limit), all of them are 4K, except the debug stack which | |
1114 | * is 8K. | |
1115 | */ | |
1116 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
1117 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
1118 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
1119 | }; | |
1120 | ||
92d65b23 | 1121 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks |
3e352aa8 | 1122 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); |
d5494d4f | 1123 | |
d5494d4f YL |
1124 | /* May not be marked __init: used by software suspend */ |
1125 | void syscall_init(void) | |
1da177e4 | 1126 | { |
d5494d4f YL |
1127 | /* |
1128 | * LSTAR and STAR live in a bit strange symbiosis. | |
1129 | * They both write to the same internal register. STAR allows to | |
1130 | * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip. | |
1131 | */ | |
1132 | wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32); | |
1133 | wrmsrl(MSR_LSTAR, system_call); | |
1134 | wrmsrl(MSR_CSTAR, ignore_sysret); | |
03ae5768 | 1135 | |
d5494d4f YL |
1136 | #ifdef CONFIG_IA32_EMULATION |
1137 | syscall32_cpu_init(); | |
1138 | #endif | |
03ae5768 | 1139 | |
d5494d4f YL |
1140 | /* Flags to clear on syscall */ |
1141 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a PA |
1142 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
1143 | X86_EFLAGS_IOPL|X86_EFLAGS_AC); | |
1da177e4 | 1144 | } |
62111195 | 1145 | |
d5494d4f YL |
1146 | unsigned long kernel_eflags; |
1147 | ||
1148 | /* | |
1149 | * Copies of the original ist values from the tss are only accessed during | |
1150 | * debugging, no special alignment required. | |
1151 | */ | |
1152 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1153 | ||
228bdaa9 | 1154 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1155 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1156 | |
1157 | int is_debug_stack(unsigned long addr) | |
1158 | { | |
42181186 SR |
1159 | return __get_cpu_var(debug_stack_usage) || |
1160 | (addr <= __get_cpu_var(debug_stack_addr) && | |
1161 | addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 SR |
1162 | } |
1163 | ||
f8988175 SR |
1164 | static DEFINE_PER_CPU(u32, debug_stack_use_ctr); |
1165 | ||
228bdaa9 SR |
1166 | void debug_stack_set_zero(void) |
1167 | { | |
f8988175 | 1168 | this_cpu_inc(debug_stack_use_ctr); |
228bdaa9 SR |
1169 | load_idt((const struct desc_ptr *)&nmi_idt_descr); |
1170 | } | |
1171 | ||
1172 | void debug_stack_reset(void) | |
1173 | { | |
f8988175 SR |
1174 | if (WARN_ON(!this_cpu_read(debug_stack_use_ctr))) |
1175 | return; | |
1176 | if (this_cpu_dec_return(debug_stack_use_ctr) == 0) | |
1177 | load_idt((const struct desc_ptr *)&idt_descr); | |
228bdaa9 SR |
1178 | } |
1179 | ||
0f3fa48a | 1180 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1181 | |
bdf977b3 TH |
1182 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1183 | EXPORT_PER_CPU_SYMBOL(current_task); | |
27e74da9 | 1184 | DEFINE_PER_CPU(struct task_struct *, fpu_owner_task); |
bdf977b3 | 1185 | |
60a5317f | 1186 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1187 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1188 | #endif |
d5494d4f | 1189 | |
60a5317f | 1190 | /* Make sure %fs and %gs are initialized properly in idle threads */ |
6b2fb3c6 | 1191 | struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs) |
f95d47ca JF |
1192 | { |
1193 | memset(regs, 0, sizeof(struct pt_regs)); | |
65ea5b03 | 1194 | regs->fs = __KERNEL_PERCPU; |
60a5317f | 1195 | regs->gs = __KERNEL_STACK_CANARY; |
0f3fa48a | 1196 | |
f95d47ca JF |
1197 | return regs; |
1198 | } | |
0f3fa48a | 1199 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1200 | |
9766cdbc JSR |
1201 | /* |
1202 | * Clear all 6 debug registers: | |
1203 | */ | |
1204 | static void clear_all_debug_regs(void) | |
1205 | { | |
1206 | int i; | |
1207 | ||
1208 | for (i = 0; i < 8; i++) { | |
1209 | /* Ignore db4, db5 */ | |
1210 | if ((i == 4) || (i == 5)) | |
1211 | continue; | |
1212 | ||
1213 | set_debugreg(0, i); | |
1214 | } | |
1215 | } | |
c5413fbe | 1216 | |
0bb9fef9 JW |
1217 | #ifdef CONFIG_KGDB |
1218 | /* | |
1219 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1220 | * connection established. | |
1221 | */ | |
1222 | static void dbg_restore_debug_regs(void) | |
1223 | { | |
1224 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1225 | arch_kgdb_ops.correct_hw_break(); | |
1226 | } | |
1227 | #else /* ! CONFIG_KGDB */ | |
1228 | #define dbg_restore_debug_regs() | |
1229 | #endif /* ! CONFIG_KGDB */ | |
1230 | ||
d2cbcc49 RR |
1231 | /* |
1232 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1233 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1234 | * and IDT. We reload them nevertheless, this function acts as a | |
1235 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1236 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1237 | */ |
1ba76586 | 1238 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1239 | |
1ba76586 YL |
1240 | void __cpuinit cpu_init(void) |
1241 | { | |
0fe1e009 | 1242 | struct orig_ist *oist; |
1ba76586 | 1243 | struct task_struct *me; |
0f3fa48a IM |
1244 | struct tss_struct *t; |
1245 | unsigned long v; | |
1246 | int cpu; | |
1ba76586 YL |
1247 | int i; |
1248 | ||
0f3fa48a IM |
1249 | cpu = stack_smp_processor_id(); |
1250 | t = &per_cpu(init_tss, cpu); | |
0fe1e009 | 1251 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1252 | |
e7a22c1e | 1253 | #ifdef CONFIG_NUMA |
c6ae41e7 | 1254 | if (cpu != 0 && this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1255 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1256 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1257 | #endif |
1ba76586 YL |
1258 | |
1259 | me = current; | |
1260 | ||
c2d1cec1 | 1261 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) |
1ba76586 YL |
1262 | panic("CPU#%d already initialized!\n", cpu); |
1263 | ||
2eaad1fd | 1264 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 YL |
1265 | |
1266 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1267 | ||
1268 | /* | |
1269 | * Initialize the per-CPU GDT with the boot GDT, | |
1270 | * and set up the GDT descriptor: | |
1271 | */ | |
1272 | ||
552be871 | 1273 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1274 | loadsegment(fs, 0); |
1275 | ||
1ba76586 YL |
1276 | load_idt((const struct desc_ptr *)&idt_descr); |
1277 | ||
1278 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1279 | syscall_init(); | |
1280 | ||
1281 | wrmsrl(MSR_FS_BASE, 0); | |
1282 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1283 | barrier(); | |
1284 | ||
4763ed4d | 1285 | x86_configure_nx(); |
06cd9a7d | 1286 | if (cpu != 0) |
1ba76586 YL |
1287 | enable_x2apic(); |
1288 | ||
1289 | /* | |
1290 | * set up and load the per-CPU TSS | |
1291 | */ | |
0fe1e009 | 1292 | if (!oist->ist[0]) { |
92d65b23 | 1293 | char *estacks = per_cpu(exception_stacks, cpu); |
0f3fa48a | 1294 | |
1ba76586 | 1295 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1296 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1297 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1298 | (unsigned long)estacks; |
228bdaa9 SR |
1299 | if (v == DEBUG_STACK-1) |
1300 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1301 | } |
1302 | } | |
1303 | ||
1304 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); | |
0f3fa48a | 1305 | |
1ba76586 YL |
1306 | /* |
1307 | * <= is required because the CPU will access up to | |
1308 | * 8 bits beyond the end of the IO permission bitmap. | |
1309 | */ | |
1310 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1311 | t->io_bitmap[i] = ~0UL; | |
1312 | ||
1313 | atomic_inc(&init_mm.mm_count); | |
1314 | me->active_mm = &init_mm; | |
8c5dfd25 | 1315 | BUG_ON(me->mm); |
1ba76586 YL |
1316 | enter_lazy_tlb(&init_mm, me); |
1317 | ||
1318 | load_sp0(t, ¤t->thread); | |
1319 | set_tss_desc(cpu, t); | |
1320 | load_TR_desc(); | |
1321 | load_LDT(&init_mm.context); | |
1322 | ||
0bb9fef9 JW |
1323 | clear_all_debug_regs(); |
1324 | dbg_restore_debug_regs(); | |
1ba76586 YL |
1325 | |
1326 | fpu_init(); | |
1327 | ||
1328 | raw_local_save_flags(kernel_eflags); | |
1329 | ||
1330 | if (is_uv_system()) | |
1331 | uv_cpu_init(); | |
1332 | } | |
1333 | ||
1334 | #else | |
1335 | ||
d2cbcc49 | 1336 | void __cpuinit cpu_init(void) |
9ee79a3d | 1337 | { |
d2cbcc49 RR |
1338 | int cpu = smp_processor_id(); |
1339 | struct task_struct *curr = current; | |
34048c9e | 1340 | struct tss_struct *t = &per_cpu(init_tss, cpu); |
9ee79a3d | 1341 | struct thread_struct *thread = &curr->thread; |
62111195 | 1342 | |
c2d1cec1 | 1343 | if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) { |
62111195 | 1344 | printk(KERN_WARNING "CPU#%d already initialized!\n", cpu); |
9766cdbc JSR |
1345 | for (;;) |
1346 | local_irq_enable(); | |
62111195 JF |
1347 | } |
1348 | ||
1349 | printk(KERN_INFO "Initializing CPU#%d\n", cpu); | |
1350 | ||
1351 | if (cpu_has_vme || cpu_has_tsc || cpu_has_de) | |
1352 | clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
62111195 | 1353 | |
4d37e7e3 | 1354 | load_idt(&idt_descr); |
552be871 | 1355 | switch_to_new_gdt(cpu); |
1da177e4 | 1356 | |
1da177e4 LT |
1357 | /* |
1358 | * Set up and load the per-CPU TSS and LDT | |
1359 | */ | |
1360 | atomic_inc(&init_mm.mm_count); | |
62111195 | 1361 | curr->active_mm = &init_mm; |
8c5dfd25 | 1362 | BUG_ON(curr->mm); |
62111195 | 1363 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1364 | |
faca6227 | 1365 | load_sp0(t, thread); |
34048c9e | 1366 | set_tss_desc(cpu, t); |
1da177e4 LT |
1367 | load_TR_desc(); |
1368 | load_LDT(&init_mm.context); | |
1369 | ||
f9a196b8 TG |
1370 | t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap); |
1371 | ||
22c4e308 | 1372 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1373 | /* Set up doublefault TSS pointer in the GDT */ |
1374 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1375 | #endif |
1da177e4 | 1376 | |
9766cdbc | 1377 | clear_all_debug_regs(); |
0bb9fef9 | 1378 | dbg_restore_debug_regs(); |
1da177e4 | 1379 | |
0e49bf66 | 1380 | fpu_init(); |
1da177e4 | 1381 | } |
1ba76586 | 1382 | #endif |