Commit | Line | Data |
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12a67cf6 SS |
1 | #include <linux/threads.h> |
2 | #include <linux/cpumask.h> | |
3 | #include <linux/string.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/ctype.h> | |
1b9b89e7 | 6 | #include <linux/dmar.h> |
9d0fa6c5 | 7 | #include <linux/cpu.h> |
1b9b89e7 | 8 | |
12a67cf6 | 9 | #include <asm/smp.h> |
79deb8e5 | 10 | #include <asm/x2apic.h> |
12a67cf6 | 11 | |
2de1f33e | 12 | static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid); |
a39d1f3f | 13 | static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster); |
9d0fa6c5 | 14 | static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); |
12a67cf6 | 15 | |
2caa3715 | 16 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 17 | { |
ef1f87aa | 18 | return x2apic_enabled(); |
1b9b89e7 YL |
19 | } |
20 | ||
a39d1f3f CG |
21 | static inline u32 x2apic_cluster(int cpu) |
22 | { | |
23 | return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16; | |
24 | } | |
25 | ||
7b6ce46c LT |
26 | static void x2apic_send_IPI(int cpu, int vector) |
27 | { | |
28 | u32 dest = per_cpu(x86_cpu_to_logical_apicid, cpu); | |
29 | ||
30 | x2apic_wrmsr_fence(); | |
31 | __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL); | |
32 | } | |
33 | ||
a27d0b5e SS |
34 | static void |
35 | __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) | |
12a67cf6 | 36 | { |
9d0fa6c5 CG |
37 | struct cpumask *cpus_in_cluster_ptr; |
38 | struct cpumask *ipi_mask_ptr; | |
39 | unsigned int cpu, this_cpu; | |
dac5f412 | 40 | unsigned long flags; |
9d0fa6c5 | 41 | u32 dest; |
12a67cf6 | 42 | |
ce4e240c SS |
43 | x2apic_wrmsr_fence(); |
44 | ||
12a67cf6 | 45 | local_irq_save(flags); |
a27d0b5e SS |
46 | |
47 | this_cpu = smp_processor_id(); | |
9d0fa6c5 CG |
48 | |
49 | /* | |
50 | * We are to modify mask, so we need an own copy | |
51 | * and be sure it's manipulated with irq off. | |
52 | */ | |
4ba29684 | 53 | ipi_mask_ptr = this_cpu_cpumask_var_ptr(ipi_mask); |
59f6e207 | 54 | cpumask_copy(ipi_mask_ptr, mask); |
9d0fa6c5 CG |
55 | |
56 | /* | |
57 | * The idea is to send one IPI per cluster. | |
58 | */ | |
59 | for_each_cpu(cpu, ipi_mask_ptr) { | |
60 | unsigned long i; | |
61 | ||
62 | cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu); | |
63 | dest = 0; | |
64 | ||
65 | /* Collect cpus in cluster. */ | |
66 | for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) { | |
67 | if (apic_dest == APIC_DEST_ALLINC || i != this_cpu) | |
68 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); | |
69 | } | |
70 | ||
71 | if (!dest) | |
a27d0b5e | 72 | continue; |
9d0fa6c5 CG |
73 | |
74 | __x2apic_send_IPI_dest(dest, vector, apic->dest_logical); | |
75 | /* | |
76 | * Cluster sibling cpus should be discared now so | |
77 | * we would not send IPI them second time. | |
78 | */ | |
79 | cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr); | |
dac5f412 | 80 | } |
a27d0b5e | 81 | |
12a67cf6 SS |
82 | local_irq_restore(flags); |
83 | } | |
84 | ||
a27d0b5e SS |
85 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
86 | { | |
87 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); | |
88 | } | |
89 | ||
dac5f412 | 90 | static void |
49d0c7a0 | 91 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
12a67cf6 | 92 | { |
a27d0b5e | 93 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
e7986739 | 94 | } |
12a67cf6 | 95 | |
e7986739 MT |
96 | static void x2apic_send_IPI_allbutself(int vector) |
97 | { | |
a27d0b5e | 98 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT); |
12a67cf6 SS |
99 | } |
100 | ||
101 | static void x2apic_send_IPI_all(int vector) | |
102 | { | |
a27d0b5e | 103 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); |
12a67cf6 SS |
104 | } |
105 | ||
ff164324 | 106 | static int |
debccb3e | 107 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
ff164324 AG |
108 | const struct cpumask *andmask, |
109 | unsigned int *apicid) | |
95d313cf | 110 | { |
0b8255e6 SS |
111 | u32 dest = 0; |
112 | u16 cluster; | |
113 | int i; | |
95d313cf | 114 | |
0b8255e6 SS |
115 | for_each_cpu_and(i, cpumask, andmask) { |
116 | if (!cpumask_test_cpu(i, cpu_online_mask)) | |
117 | continue; | |
118 | dest = per_cpu(x86_cpu_to_logical_apicid, i); | |
119 | cluster = x2apic_cluster(i); | |
120 | break; | |
debccb3e IM |
121 | } |
122 | ||
0b8255e6 | 123 | if (!dest) |
ff164324 | 124 | return -EINVAL; |
0b8255e6 SS |
125 | |
126 | for_each_cpu_and(i, cpumask, andmask) { | |
127 | if (!cpumask_test_cpu(i, cpu_online_mask)) | |
128 | continue; | |
129 | if (cluster != x2apic_cluster(i)) | |
130 | continue; | |
131 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); | |
132 | } | |
133 | ||
ff164324 AG |
134 | *apicid = dest; |
135 | ||
136 | return 0; | |
95d313cf MT |
137 | } |
138 | ||
12a67cf6 | 139 | static void init_x2apic_ldr(void) |
a39d1f3f CG |
140 | { |
141 | unsigned int this_cpu = smp_processor_id(); | |
142 | unsigned int cpu; | |
143 | ||
144 | per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR); | |
145 | ||
d089f8e9 | 146 | cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, this_cpu)); |
a39d1f3f CG |
147 | for_each_online_cpu(cpu) { |
148 | if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) | |
149 | continue; | |
d089f8e9 RR |
150 | cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu)); |
151 | cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
a39d1f3f CG |
152 | } |
153 | } | |
154 | ||
155 | /* | |
156 | * At CPU state changes, update the x2apic cluster sibling info. | |
157 | */ | |
148f9bb8 | 158 | static int |
a39d1f3f CG |
159 | update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu) |
160 | { | |
161 | unsigned int this_cpu = (unsigned long)hcpu; | |
162 | unsigned int cpu; | |
163 | int err = 0; | |
164 | ||
165 | switch (action) { | |
166 | case CPU_UP_PREPARE: | |
167 | if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu), | |
168 | GFP_KERNEL)) { | |
169 | err = -ENOMEM; | |
9d0fa6c5 CG |
170 | } else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu), |
171 | GFP_KERNEL)) { | |
172 | free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); | |
173 | err = -ENOMEM; | |
a39d1f3f CG |
174 | } |
175 | break; | |
176 | case CPU_UP_CANCELED: | |
177 | case CPU_UP_CANCELED_FROZEN: | |
178 | case CPU_DEAD: | |
179 | for_each_online_cpu(cpu) { | |
180 | if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) | |
181 | continue; | |
fdaf3a65 RR |
182 | cpumask_clear_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu)); |
183 | cpumask_clear_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu)); | |
a39d1f3f CG |
184 | } |
185 | free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); | |
9d0fa6c5 | 186 | free_cpumask_var(per_cpu(ipi_mask, this_cpu)); |
a39d1f3f CG |
187 | break; |
188 | } | |
189 | ||
190 | return notifier_from_errno(err); | |
191 | } | |
192 | ||
4daa832d | 193 | static struct notifier_block x2apic_cpu_notifier = { |
a39d1f3f CG |
194 | .notifier_call = update_clusterinfo, |
195 | }; | |
196 | ||
197 | static int x2apic_init_cpu_notifier(void) | |
12a67cf6 SS |
198 | { |
199 | int cpu = smp_processor_id(); | |
200 | ||
a39d1f3f | 201 | zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL); |
9d0fa6c5 | 202 | zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL); |
a39d1f3f | 203 | |
9d0fa6c5 | 204 | BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu)); |
a39d1f3f | 205 | |
d089f8e9 | 206 | cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, cpu)); |
a39d1f3f CG |
207 | register_hotcpu_notifier(&x2apic_cpu_notifier); |
208 | return 1; | |
12a67cf6 SS |
209 | } |
210 | ||
9ebd680b SS |
211 | static int x2apic_cluster_probe(void) |
212 | { | |
a39d1f3f CG |
213 | if (x2apic_mode) |
214 | return x2apic_init_cpu_notifier(); | |
215 | else | |
216 | return 0; | |
9ebd680b SS |
217 | } |
218 | ||
d872818d SS |
219 | static const struct cpumask *x2apic_cluster_target_cpus(void) |
220 | { | |
221 | return cpu_all_mask; | |
222 | } | |
223 | ||
0b8255e6 SS |
224 | /* |
225 | * Each x2apic cluster is an allocation domain. | |
226 | */ | |
1ac322d0 SS |
227 | static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask, |
228 | const struct cpumask *mask) | |
0b8255e6 | 229 | { |
d872818d SS |
230 | /* |
231 | * To minimize vector pressure, default case of boot, device bringup | |
232 | * etc will use a single cpu for the interrupt destination. | |
233 | * | |
234 | * On explicit migration requests coming from irqbalance etc, | |
235 | * interrupts will be routed to the x2apic cluster (cluster-id | |
236 | * derived from the first cpu in the mask) members specified | |
237 | * in the mask. | |
238 | */ | |
239 | if (mask == x2apic_cluster_target_cpus()) | |
240 | cpumask_copy(retmask, cpumask_of(cpu)); | |
241 | else | |
242 | cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu)); | |
0b8255e6 SS |
243 | } |
244 | ||
1a8880a1 | 245 | static struct apic apic_x2apic_cluster = { |
504a3c3a IM |
246 | |
247 | .name = "cluster x2apic", | |
9ebd680b | 248 | .probe = x2apic_cluster_probe, |
504a3c3a | 249 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, |
b7157acf | 250 | .apic_id_valid = x2apic_apic_id_valid, |
504a3c3a IM |
251 | .apic_id_registered = x2apic_apic_id_registered, |
252 | ||
f8987a10 | 253 | .irq_delivery_mode = dest_LowestPrio, |
0b06e734 | 254 | .irq_dest_mode = 1, /* logical */ |
504a3c3a | 255 | |
d872818d | 256 | .target_cpus = x2apic_cluster_target_cpus, |
08125d3e | 257 | .disable_esr = 0, |
bdb1a9b6 | 258 | .dest_logical = APIC_DEST_LOGICAL, |
504a3c3a | 259 | .check_apicid_used = NULL, |
504a3c3a | 260 | |
0b8255e6 | 261 | .vector_allocation_domain = cluster_vector_allocation_domain, |
504a3c3a IM |
262 | .init_apic_ldr = init_x2apic_ldr, |
263 | ||
264 | .ioapic_phys_id_map = NULL, | |
265 | .setup_apic_routing = NULL, | |
a21769a4 | 266 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
504a3c3a | 267 | .apicid_to_cpu_present = NULL, |
a27a6210 | 268 | .check_phys_apicid_present = default_check_phys_apicid_present, |
79deb8e5 | 269 | .phys_pkg_id = x2apic_phys_pkg_id, |
504a3c3a | 270 | |
79deb8e5 CG |
271 | .get_apic_id = x2apic_get_apic_id, |
272 | .set_apic_id = x2apic_set_apic_id, | |
504a3c3a IM |
273 | .apic_id_mask = 0xFFFFFFFFu, |
274 | ||
504a3c3a IM |
275 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, |
276 | ||
7b6ce46c | 277 | .send_IPI = x2apic_send_IPI, |
504a3c3a IM |
278 | .send_IPI_mask = x2apic_send_IPI_mask, |
279 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
280 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
281 | .send_IPI_all = x2apic_send_IPI_all, | |
282 | .send_IPI_self = x2apic_send_IPI_self, | |
283 | ||
504a3c3a | 284 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
285 | |
286 | .read = native_apic_msr_read, | |
287 | .write = native_apic_msr_write, | |
0ab711ae | 288 | .eoi_write = native_apic_msr_eoi_write, |
c1eeb2de YL |
289 | .icr_read = native_x2apic_icr_read, |
290 | .icr_write = native_x2apic_icr_write, | |
291 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
292 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
12a67cf6 | 293 | }; |
107e0e0c SS |
294 | |
295 | apic_driver(apic_x2apic_cluster); |