Commit | Line | Data |
---|---|---|
12a67cf6 SS |
1 | #include <linux/threads.h> |
2 | #include <linux/cpumask.h> | |
3 | #include <linux/string.h> | |
4 | #include <linux/kernel.h> | |
5 | #include <linux/ctype.h> | |
6 | #include <linux/init.h> | |
1b9b89e7 YL |
7 | #include <linux/dmar.h> |
8 | ||
12a67cf6 | 9 | #include <asm/smp.h> |
7b6aa335 | 10 | #include <asm/apic.h> |
c1eeb2de | 11 | #include <asm/ipi.h> |
12a67cf6 | 12 | |
2de1f33e | 13 | static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid); |
12a67cf6 | 14 | |
2caa3715 | 15 | static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
1b9b89e7 | 16 | { |
ef1f87aa | 17 | return x2apic_enabled(); |
1b9b89e7 YL |
18 | } |
19 | ||
087d7e56 YL |
20 | /* |
21 | * need to use more than cpu 0, because we need more vectors when | |
22 | * MSI-X are used. | |
23 | */ | |
bcda016e | 24 | static const struct cpumask *x2apic_target_cpus(void) |
12a67cf6 | 25 | { |
087d7e56 | 26 | return cpu_online_mask; |
12a67cf6 SS |
27 | } |
28 | ||
29 | /* | |
30 | * for now each logical cpu is in its own vector allocation domain. | |
31 | */ | |
bcda016e | 32 | static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask) |
12a67cf6 | 33 | { |
bcda016e MT |
34 | cpumask_clear(retmask); |
35 | cpumask_set_cpu(cpu, retmask); | |
12a67cf6 SS |
36 | } |
37 | ||
dac5f412 IM |
38 | static void |
39 | __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) | |
12a67cf6 SS |
40 | { |
41 | unsigned long cfg; | |
42 | ||
43 | cfg = __prepare_ICR(0, vector, dest); | |
44 | ||
45 | /* | |
46 | * send the IPI. | |
47 | */ | |
c1eeb2de | 48 | native_x2apic_icr_write(cfg, apicid); |
12a67cf6 SS |
49 | } |
50 | ||
51 | /* | |
52 | * for now, we send the IPI's one by one in the cpumask. | |
53 | * TBD: Based on the cpu mask, we can send the IPI's to the cluster group | |
54 | * at once. We have 16 cpu's in a cluster. This will minimize IPI register | |
55 | * writes. | |
56 | */ | |
a27d0b5e SS |
57 | static void |
58 | __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) | |
12a67cf6 | 59 | { |
12a67cf6 | 60 | unsigned long query_cpu; |
a27d0b5e | 61 | unsigned long this_cpu; |
dac5f412 | 62 | unsigned long flags; |
12a67cf6 | 63 | |
ce4e240c SS |
64 | x2apic_wrmsr_fence(); |
65 | ||
12a67cf6 | 66 | local_irq_save(flags); |
a27d0b5e SS |
67 | |
68 | this_cpu = smp_processor_id(); | |
dac5f412 | 69 | for_each_cpu(query_cpu, mask) { |
a27d0b5e SS |
70 | if (apic_dest == APIC_DEST_ALLBUT && query_cpu == this_cpu) |
71 | continue; | |
e7986739 MT |
72 | __x2apic_send_IPI_dest( |
73 | per_cpu(x86_cpu_to_logical_apicid, query_cpu), | |
bdb1a9b6 | 74 | vector, apic->dest_logical); |
dac5f412 | 75 | } |
a27d0b5e | 76 | |
12a67cf6 SS |
77 | local_irq_restore(flags); |
78 | } | |
79 | ||
a27d0b5e SS |
80 | static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) |
81 | { | |
82 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); | |
83 | } | |
84 | ||
dac5f412 IM |
85 | static void |
86 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) | |
12a67cf6 | 87 | { |
a27d0b5e | 88 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
e7986739 | 89 | } |
12a67cf6 | 90 | |
e7986739 MT |
91 | static void x2apic_send_IPI_allbutself(int vector) |
92 | { | |
a27d0b5e | 93 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT); |
12a67cf6 SS |
94 | } |
95 | ||
96 | static void x2apic_send_IPI_all(int vector) | |
97 | { | |
a27d0b5e | 98 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); |
12a67cf6 SS |
99 | } |
100 | ||
101 | static int x2apic_apic_id_registered(void) | |
102 | { | |
103 | return 1; | |
104 | } | |
105 | ||
bcda016e | 106 | static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask) |
12a67cf6 | 107 | { |
12a67cf6 | 108 | /* |
7d87d536 | 109 | * We're using fixed IRQ delivery, can only return one logical APIC ID. |
12a67cf6 SS |
110 | * May as well be the first. |
111 | */ | |
debccb3e IM |
112 | int cpu = cpumask_first(cpumask); |
113 | ||
e7986739 | 114 | if ((unsigned)cpu < nr_cpu_ids) |
12a67cf6 SS |
115 | return per_cpu(x86_cpu_to_logical_apicid, cpu); |
116 | else | |
117 | return BAD_APICID; | |
118 | } | |
119 | ||
debccb3e IM |
120 | static unsigned int |
121 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
122 | const struct cpumask *andmask) | |
95d313cf MT |
123 | { |
124 | int cpu; | |
125 | ||
126 | /* | |
7d87d536 | 127 | * We're using fixed IRQ delivery, can only return one logical APIC ID. |
95d313cf MT |
128 | * May as well be the first. |
129 | */ | |
debccb3e | 130 | for_each_cpu_and(cpu, cpumask, andmask) { |
a775a38b MT |
131 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
132 | break; | |
debccb3e IM |
133 | } |
134 | ||
18374d89 | 135 | return per_cpu(x86_cpu_to_logical_apicid, cpu); |
95d313cf MT |
136 | } |
137 | ||
ca6c8ed4 | 138 | static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x) |
f910a9dc YL |
139 | { |
140 | unsigned int id; | |
141 | ||
142 | id = x; | |
143 | return id; | |
144 | } | |
145 | ||
146 | static unsigned long set_apic_id(unsigned int id) | |
147 | { | |
148 | unsigned long x; | |
149 | ||
150 | x = id; | |
151 | return x; | |
152 | } | |
153 | ||
d4c9a9f3 | 154 | static int x2apic_cluster_phys_pkg_id(int initial_apicid, int index_msb) |
12a67cf6 | 155 | { |
d8c7eb34 | 156 | return initial_apicid >> index_msb; |
12a67cf6 SS |
157 | } |
158 | ||
159 | static void x2apic_send_IPI_self(int vector) | |
160 | { | |
161 | apic_write(APIC_SELF_IPI, vector); | |
162 | } | |
163 | ||
164 | static void init_x2apic_ldr(void) | |
165 | { | |
166 | int cpu = smp_processor_id(); | |
167 | ||
168 | per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR); | |
12a67cf6 SS |
169 | } |
170 | ||
9ebd680b SS |
171 | static int x2apic_cluster_probe(void) |
172 | { | |
173 | return x2apic_mode; | |
174 | } | |
175 | ||
be163a15 | 176 | struct apic apic_x2apic_cluster = { |
504a3c3a IM |
177 | |
178 | .name = "cluster x2apic", | |
9ebd680b | 179 | .probe = x2apic_cluster_probe, |
504a3c3a IM |
180 | .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, |
181 | .apic_id_registered = x2apic_apic_id_registered, | |
182 | ||
f8987a10 | 183 | .irq_delivery_mode = dest_LowestPrio, |
0b06e734 | 184 | .irq_dest_mode = 1, /* logical */ |
504a3c3a IM |
185 | |
186 | .target_cpus = x2apic_target_cpus, | |
08125d3e | 187 | .disable_esr = 0, |
bdb1a9b6 | 188 | .dest_logical = APIC_DEST_LOGICAL, |
504a3c3a IM |
189 | .check_apicid_used = NULL, |
190 | .check_apicid_present = NULL, | |
191 | ||
504a3c3a IM |
192 | .vector_allocation_domain = x2apic_vector_allocation_domain, |
193 | .init_apic_ldr = init_x2apic_ldr, | |
194 | ||
195 | .ioapic_phys_id_map = NULL, | |
196 | .setup_apic_routing = NULL, | |
197 | .multi_timer_check = NULL, | |
a21769a4 | 198 | .cpu_present_to_apicid = default_cpu_present_to_apicid, |
504a3c3a IM |
199 | .apicid_to_cpu_present = NULL, |
200 | .setup_portio_remap = NULL, | |
a27a6210 | 201 | .check_phys_apicid_present = default_check_phys_apicid_present, |
504a3c3a | 202 | .enable_apic_mode = NULL, |
d4c9a9f3 | 203 | .phys_pkg_id = x2apic_cluster_phys_pkg_id, |
504a3c3a IM |
204 | .mps_oem_check = NULL, |
205 | ||
ca6c8ed4 | 206 | .get_apic_id = x2apic_cluster_phys_get_apic_id, |
504a3c3a IM |
207 | .set_apic_id = set_apic_id, |
208 | .apic_id_mask = 0xFFFFFFFFu, | |
209 | ||
210 | .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, | |
211 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, | |
212 | ||
213 | .send_IPI_mask = x2apic_send_IPI_mask, | |
214 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | |
215 | .send_IPI_allbutself = x2apic_send_IPI_allbutself, | |
216 | .send_IPI_all = x2apic_send_IPI_all, | |
217 | .send_IPI_self = x2apic_send_IPI_self, | |
218 | ||
abfa584c IM |
219 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
220 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
504a3c3a IM |
221 | .wait_for_init_deassert = NULL, |
222 | .smp_callin_clear_local_apic = NULL, | |
504a3c3a | 223 | .inquire_remote_apic = NULL, |
c1eeb2de YL |
224 | |
225 | .read = native_apic_msr_read, | |
226 | .write = native_apic_msr_write, | |
227 | .icr_read = native_x2apic_icr_read, | |
228 | .icr_write = native_x2apic_icr_write, | |
229 | .wait_icr_idle = native_x2apic_wait_icr_idle, | |
230 | .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, | |
12a67cf6 | 231 | }; |