Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
74afab7a | 32 | static DEFINE_RAW_SPINLOCK(vector_lock); |
f7fa7aee | 33 | static cpumask_var_t vector_cpumask; |
b5dc8e6c | 34 | static struct irq_chip lapic_controller; |
13315320 | 35 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 36 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 37 | #endif |
74afab7a JL |
38 | |
39 | void lock_vector_lock(void) | |
40 | { | |
41 | /* Used to the online set of cpus does not change | |
42 | * during assign_irq_vector. | |
43 | */ | |
44 | raw_spin_lock(&vector_lock); | |
45 | } | |
46 | ||
47 | void unlock_vector_lock(void) | |
48 | { | |
49 | raw_spin_unlock(&vector_lock); | |
50 | } | |
51 | ||
7f3262ed | 52 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 53 | { |
b5dc8e6c JL |
54 | if (!irq_data) |
55 | return NULL; | |
56 | ||
57 | while (irq_data->parent_data) | |
58 | irq_data = irq_data->parent_data; | |
59 | ||
74afab7a JL |
60 | return irq_data->chip_data; |
61 | } | |
62 | ||
7f3262ed JL |
63 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
64 | { | |
65 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
66 | ||
67 | return data ? &data->cfg : NULL; | |
68 | } | |
69 | ||
70 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 71 | { |
7f3262ed JL |
72 | return irqd_cfg(irq_get_irq_data(irq)); |
73 | } | |
74afab7a | 74 | |
7f3262ed JL |
75 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
76 | { | |
77 | struct apic_chip_data *data; | |
78 | ||
79 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
80 | if (!data) | |
74afab7a | 81 | return NULL; |
7f3262ed JL |
82 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
83 | goto out_data; | |
84 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 85 | goto out_domain; |
7f3262ed | 86 | return data; |
74afab7a | 87 | out_domain: |
7f3262ed JL |
88 | free_cpumask_var(data->domain); |
89 | out_data: | |
90 | kfree(data); | |
74afab7a JL |
91 | return NULL; |
92 | } | |
93 | ||
7f3262ed | 94 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 95 | { |
7f3262ed JL |
96 | if (data) { |
97 | free_cpumask_var(data->domain); | |
98 | free_cpumask_var(data->old_domain); | |
99 | kfree(data); | |
b5dc8e6c | 100 | } |
74afab7a JL |
101 | } |
102 | ||
7f3262ed JL |
103 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
104 | const struct cpumask *mask) | |
74afab7a JL |
105 | { |
106 | /* | |
107 | * NOTE! The local APIC isn't very good at handling | |
108 | * multiple interrupts at the same interrupt level. | |
109 | * As the interrupt level is determined by taking the | |
110 | * vector number and shifting that right by 4, we | |
111 | * want to spread these out a bit so that they don't | |
112 | * all fall in the same interrupt level. | |
113 | * | |
114 | * Also, we've got to be careful not to trash gate | |
115 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
116 | */ | |
117 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
118 | static int current_offset = VECTOR_OFFSET_START % 16; | |
119 | int cpu, err; | |
74afab7a | 120 | |
7f3262ed | 121 | if (d->move_in_progress) |
74afab7a JL |
122 | return -EBUSY; |
123 | ||
74afab7a JL |
124 | /* Only try and allocate irqs on cpus that are present */ |
125 | err = -ENOSPC; | |
7f3262ed | 126 | cpumask_clear(d->old_domain); |
74afab7a JL |
127 | cpu = cpumask_first_and(mask, cpu_online_mask); |
128 | while (cpu < nr_cpu_ids) { | |
129 | int new_cpu, vector, offset; | |
130 | ||
f7fa7aee | 131 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 132 | |
f7fa7aee | 133 | if (cpumask_subset(vector_cpumask, d->domain)) { |
74afab7a | 134 | err = 0; |
f7fa7aee | 135 | if (cpumask_equal(vector_cpumask, d->domain)) |
74afab7a JL |
136 | break; |
137 | /* | |
138 | * New cpumask using the vector is a proper subset of | |
139 | * the current in use mask. So cleanup the vector | |
140 | * allocation for the members that are not used anymore. | |
141 | */ | |
f7fa7aee JL |
142 | cpumask_andnot(d->old_domain, d->domain, |
143 | vector_cpumask); | |
7f3262ed JL |
144 | d->move_in_progress = |
145 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
f7fa7aee | 146 | cpumask_and(d->domain, d->domain, vector_cpumask); |
74afab7a JL |
147 | break; |
148 | } | |
149 | ||
150 | vector = current_vector; | |
151 | offset = current_offset; | |
152 | next: | |
153 | vector += 16; | |
154 | if (vector >= first_system_vector) { | |
155 | offset = (offset + 1) % 16; | |
156 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
157 | } | |
158 | ||
159 | if (unlikely(current_vector == vector)) { | |
f7fa7aee JL |
160 | cpumask_or(d->old_domain, d->old_domain, |
161 | vector_cpumask); | |
162 | cpumask_andnot(vector_cpumask, mask, d->old_domain); | |
163 | cpu = cpumask_first_and(vector_cpumask, | |
164 | cpu_online_mask); | |
74afab7a JL |
165 | continue; |
166 | } | |
167 | ||
168 | if (test_bit(vector, used_vectors)) | |
169 | goto next; | |
170 | ||
f7fa7aee | 171 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { |
7276c6a2 | 172 | if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNUSED) |
74afab7a JL |
173 | goto next; |
174 | } | |
175 | /* Found one! */ | |
176 | current_vector = vector; | |
177 | current_offset = offset; | |
7f3262ed JL |
178 | if (d->cfg.vector) { |
179 | cpumask_copy(d->old_domain, d->domain); | |
180 | d->move_in_progress = | |
181 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
74afab7a | 182 | } |
f7fa7aee | 183 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) |
74afab7a | 184 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
7f3262ed | 185 | d->cfg.vector = vector; |
f7fa7aee | 186 | cpumask_copy(d->domain, vector_cpumask); |
74afab7a JL |
187 | err = 0; |
188 | break; | |
189 | } | |
74afab7a | 190 | |
5f0052f9 JL |
191 | if (!err) { |
192 | /* cache destination APIC IDs into cfg->dest_apicid */ | |
7f3262ed JL |
193 | err = apic->cpu_mask_to_apicid_and(mask, d->domain, |
194 | &d->cfg.dest_apicid); | |
5f0052f9 JL |
195 | } |
196 | ||
74afab7a JL |
197 | return err; |
198 | } | |
199 | ||
7f3262ed | 200 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 201 | const struct cpumask *mask) |
74afab7a JL |
202 | { |
203 | int err; | |
204 | unsigned long flags; | |
205 | ||
206 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 207 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
208 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
209 | return err; | |
210 | } | |
211 | ||
486ca539 JL |
212 | static int assign_irq_vector_policy(int irq, int node, |
213 | struct apic_chip_data *data, | |
214 | struct irq_alloc_info *info) | |
215 | { | |
216 | if (info && info->mask) | |
217 | return assign_irq_vector(irq, data, info->mask); | |
218 | if (node != NUMA_NO_NODE && | |
219 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
220 | return 0; | |
221 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
222 | } | |
223 | ||
7f3262ed | 224 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a JL |
225 | { |
226 | int cpu, vector; | |
227 | unsigned long flags; | |
228 | ||
229 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 230 | BUG_ON(!data->cfg.vector); |
74afab7a | 231 | |
7f3262ed JL |
232 | vector = data->cfg.vector; |
233 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 234 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 235 | |
7f3262ed JL |
236 | data->cfg.vector = 0; |
237 | cpumask_clear(data->domain); | |
74afab7a | 238 | |
7f3262ed | 239 | if (likely(!data->move_in_progress)) { |
74afab7a JL |
240 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
241 | return; | |
242 | } | |
243 | ||
7f3262ed | 244 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
245 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
246 | vector++) { | |
247 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
248 | continue; | |
7276c6a2 | 249 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
250 | break; |
251 | } | |
252 | } | |
7f3262ed | 253 | data->move_in_progress = 0; |
74afab7a JL |
254 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
255 | } | |
256 | ||
b5dc8e6c JL |
257 | void init_irq_alloc_info(struct irq_alloc_info *info, |
258 | const struct cpumask *mask) | |
259 | { | |
260 | memset(info, 0, sizeof(*info)); | |
261 | info->mask = mask; | |
262 | } | |
263 | ||
264 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
265 | { | |
266 | if (src) | |
267 | *dst = *src; | |
268 | else | |
269 | memset(dst, 0, sizeof(*dst)); | |
270 | } | |
271 | ||
b5dc8e6c JL |
272 | static void x86_vector_free_irqs(struct irq_domain *domain, |
273 | unsigned int virq, unsigned int nr_irqs) | |
274 | { | |
275 | struct irq_data *irq_data; | |
276 | int i; | |
277 | ||
278 | for (i = 0; i < nr_irqs; i++) { | |
279 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
280 | if (irq_data && irq_data->chip_data) { | |
b5dc8e6c | 281 | clear_irq_vector(virq + i, irq_data->chip_data); |
7f3262ed | 282 | free_apic_chip_data(irq_data->chip_data); |
13315320 JL |
283 | #ifdef CONFIG_X86_IO_APIC |
284 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 285 | legacy_irq_data[virq + i] = NULL; |
13315320 | 286 | #endif |
b5dc8e6c JL |
287 | irq_domain_reset_irq_data(irq_data); |
288 | } | |
289 | } | |
290 | } | |
291 | ||
292 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
293 | unsigned int nr_irqs, void *arg) | |
294 | { | |
295 | struct irq_alloc_info *info = arg; | |
7f3262ed | 296 | struct apic_chip_data *data; |
b5dc8e6c | 297 | struct irq_data *irq_data; |
5f2dbbc5 | 298 | int i, err, node; |
b5dc8e6c JL |
299 | |
300 | if (disable_apic) | |
301 | return -ENXIO; | |
302 | ||
303 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
304 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
305 | return -ENOSYS; | |
306 | ||
b5dc8e6c JL |
307 | for (i = 0; i < nr_irqs; i++) { |
308 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
309 | BUG_ON(!irq_data); | |
5f2dbbc5 | 310 | node = irq_data_get_node(irq_data); |
13315320 | 311 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
312 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
313 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
314 | else |
315 | #endif | |
5f2dbbc5 | 316 | data = alloc_apic_chip_data(node); |
7f3262ed | 317 | if (!data) { |
b5dc8e6c JL |
318 | err = -ENOMEM; |
319 | goto error; | |
320 | } | |
321 | ||
322 | irq_data->chip = &lapic_controller; | |
7f3262ed | 323 | irq_data->chip_data = data; |
b5dc8e6c | 324 | irq_data->hwirq = virq + i; |
5f2dbbc5 | 325 | err = assign_irq_vector_policy(virq, node, data, info); |
b5dc8e6c JL |
326 | if (err) |
327 | goto error; | |
328 | } | |
329 | ||
330 | return 0; | |
331 | ||
332 | error: | |
333 | x86_vector_free_irqs(domain, virq, i + 1); | |
334 | return err; | |
335 | } | |
336 | ||
eb18cf55 TG |
337 | static const struct irq_domain_ops x86_vector_domain_ops = { |
338 | .alloc = x86_vector_alloc_irqs, | |
339 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
340 | }; |
341 | ||
11d686e9 JL |
342 | int __init arch_probe_nr_irqs(void) |
343 | { | |
344 | int nr; | |
345 | ||
346 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
347 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
348 | ||
349 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
350 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
351 | /* | |
352 | * for MSI and HT dyn irq | |
353 | */ | |
354 | if (gsi_top <= NR_IRQS_LEGACY) | |
355 | nr += 8 * nr_cpu_ids; | |
356 | else | |
357 | nr += gsi_top * 16; | |
358 | #endif | |
359 | if (nr < nr_irqs) | |
360 | nr_irqs = nr; | |
361 | ||
362 | return nr_legacy_irqs(); | |
363 | } | |
364 | ||
13315320 JL |
365 | #ifdef CONFIG_X86_IO_APIC |
366 | static void init_legacy_irqs(void) | |
367 | { | |
368 | int i, node = cpu_to_node(0); | |
7f3262ed | 369 | struct apic_chip_data *data; |
13315320 JL |
370 | |
371 | /* | |
372 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 373 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
374 | */ |
375 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
376 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
377 | BUG_ON(!data); | |
191a6635 IM |
378 | |
379 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
380 | cpumask_setall(data->domain); |
381 | irq_set_chip_data(i, data); | |
13315320 JL |
382 | } |
383 | } | |
384 | #else | |
385 | static void init_legacy_irqs(void) { } | |
386 | #endif | |
387 | ||
11d686e9 JL |
388 | int __init arch_early_irq_init(void) |
389 | { | |
13315320 JL |
390 | init_legacy_irqs(); |
391 | ||
b5dc8e6c JL |
392 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
393 | NULL); | |
394 | BUG_ON(x86_vector_domain == NULL); | |
395 | irq_set_default_host(x86_vector_domain); | |
396 | ||
52f518a3 | 397 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 398 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 399 | |
f7fa7aee JL |
400 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
401 | ||
11d686e9 JL |
402 | return arch_early_ioapic_init(); |
403 | } | |
404 | ||
74afab7a JL |
405 | static void __setup_vector_irq(int cpu) |
406 | { | |
407 | /* Initialize vector_irq on a new cpu */ | |
408 | int irq, vector; | |
7f3262ed | 409 | struct apic_chip_data *data; |
74afab7a | 410 | |
74afab7a JL |
411 | /* Mark the inuse vectors */ |
412 | for_each_active_irq(irq) { | |
7f3262ed JL |
413 | data = apic_chip_data(irq_get_irq_data(irq)); |
414 | if (!data) | |
74afab7a JL |
415 | continue; |
416 | ||
7f3262ed | 417 | if (!cpumask_test_cpu(cpu, data->domain)) |
74afab7a | 418 | continue; |
7f3262ed | 419 | vector = data->cfg.vector; |
74afab7a JL |
420 | per_cpu(vector_irq, cpu)[vector] = irq; |
421 | } | |
422 | /* Mark the free vectors */ | |
423 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
424 | irq = per_cpu(vector_irq, cpu)[vector]; | |
7276c6a2 | 425 | if (irq <= VECTOR_UNUSED) |
74afab7a JL |
426 | continue; |
427 | ||
7f3262ed JL |
428 | data = apic_chip_data(irq_get_irq_data(irq)); |
429 | if (!cpumask_test_cpu(cpu, data->domain)) | |
7276c6a2 | 430 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 431 | } |
74afab7a JL |
432 | } |
433 | ||
434 | /* | |
5a3f75e3 | 435 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
436 | */ |
437 | void setup_vector_irq(int cpu) | |
438 | { | |
439 | int irq; | |
440 | ||
5a3f75e3 | 441 | lockdep_assert_held(&vector_lock); |
74afab7a JL |
442 | /* |
443 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
444 | * boot cpu. But there are certain platforms where PIC interrupts are | |
445 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
446 | * legacy PIC, for the new cpu that is coming online, setup the static | |
447 | * legacy vector to irq mapping: | |
448 | */ | |
449 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
8b455e65 | 450 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq; |
74afab7a JL |
451 | |
452 | __setup_vector_irq(cpu); | |
453 | } | |
454 | ||
7f3262ed | 455 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 456 | { |
7f3262ed | 457 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
458 | unsigned long flags; |
459 | int cpu; | |
460 | ||
461 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
462 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
463 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
464 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
465 | ||
466 | return 1; | |
467 | } | |
468 | ||
469 | void apic_ack_edge(struct irq_data *data) | |
470 | { | |
a9786091 | 471 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
472 | irq_move_irq(data); |
473 | ack_APIC_irq(); | |
474 | } | |
475 | ||
68f9f440 JL |
476 | static int apic_set_affinity(struct irq_data *irq_data, |
477 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 478 | { |
7f3262ed | 479 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
480 | int err, irq = irq_data->irq; |
481 | ||
482 | if (!config_enabled(CONFIG_SMP)) | |
483 | return -EPERM; | |
484 | ||
485 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
486 | return -EINVAL; | |
487 | ||
7f3262ed | 488 | err = assign_irq_vector(irq, data, dest); |
b5dc8e6c JL |
489 | if (err) { |
490 | struct irq_data *top = irq_get_irq_data(irq); | |
491 | ||
c149e4cd JL |
492 | if (assign_irq_vector(irq, data, |
493 | irq_data_get_affinity_mask(top))) | |
b5dc8e6c JL |
494 | pr_err("Failed to recover vector for irq %d\n", irq); |
495 | return err; | |
496 | } | |
497 | ||
498 | return IRQ_SET_MASK_OK; | |
499 | } | |
500 | ||
501 | static struct irq_chip lapic_controller = { | |
502 | .irq_ack = apic_ack_edge, | |
68f9f440 | 503 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
504 | .irq_retrigger = apic_retrigger_irq, |
505 | }; | |
506 | ||
74afab7a | 507 | #ifdef CONFIG_SMP |
7f3262ed | 508 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a JL |
509 | { |
510 | cpumask_var_t cleanup_mask; | |
511 | ||
512 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
513 | unsigned int i; | |
514 | ||
7f3262ed | 515 | for_each_cpu_and(i, data->old_domain, cpu_online_mask) |
74afab7a JL |
516 | apic->send_IPI_mask(cpumask_of(i), |
517 | IRQ_MOVE_CLEANUP_VECTOR); | |
518 | } else { | |
7f3262ed | 519 | cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); |
74afab7a JL |
520 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
521 | free_cpumask_var(cleanup_mask); | |
522 | } | |
7f3262ed | 523 | data->move_in_progress = 0; |
74afab7a JL |
524 | } |
525 | ||
c6c2002b JL |
526 | void send_cleanup_vector(struct irq_cfg *cfg) |
527 | { | |
7f3262ed JL |
528 | struct apic_chip_data *data; |
529 | ||
530 | data = container_of(cfg, struct apic_chip_data, cfg); | |
531 | if (data->move_in_progress) | |
532 | __send_cleanup_vector(data); | |
c6c2002b JL |
533 | } |
534 | ||
74afab7a JL |
535 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
536 | { | |
537 | unsigned vector, me; | |
538 | ||
6af7faf6 | 539 | entering_ack_irq(); |
74afab7a | 540 | |
df54c493 TG |
541 | /* Prevent vectors vanishing under us */ |
542 | raw_spin_lock(&vector_lock); | |
543 | ||
74afab7a JL |
544 | me = smp_processor_id(); |
545 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
546 | int irq; | |
547 | unsigned int irr; | |
548 | struct irq_desc *desc; | |
7f3262ed | 549 | struct apic_chip_data *data; |
74afab7a | 550 | |
df54c493 | 551 | retry: |
74afab7a JL |
552 | irq = __this_cpu_read(vector_irq[vector]); |
553 | ||
7276c6a2 | 554 | if (irq <= VECTOR_UNUSED) |
74afab7a JL |
555 | continue; |
556 | ||
557 | desc = irq_to_desc(irq); | |
558 | if (!desc) | |
559 | continue; | |
560 | ||
df54c493 TG |
561 | if (!raw_spin_trylock(&desc->lock)) { |
562 | raw_spin_unlock(&vector_lock); | |
563 | cpu_relax(); | |
564 | raw_spin_lock(&vector_lock); | |
565 | goto retry; | |
566 | } | |
567 | ||
7f3262ed JL |
568 | data = apic_chip_data(&desc->irq_data); |
569 | if (!data) | |
df54c493 | 570 | goto unlock; |
74afab7a JL |
571 | /* |
572 | * Check if the irq migration is in progress. If so, we | |
573 | * haven't received the cleanup request yet for this irq. | |
574 | */ | |
7f3262ed | 575 | if (data->move_in_progress) |
74afab7a JL |
576 | goto unlock; |
577 | ||
7f3262ed JL |
578 | if (vector == data->cfg.vector && |
579 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
580 | goto unlock; |
581 | ||
582 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
583 | /* | |
584 | * Check if the vector that needs to be cleanedup is | |
585 | * registered at the cpu's IRR. If so, then this is not | |
586 | * the best time to clean it up. Lets clean it up in the | |
587 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
588 | * to myself. | |
589 | */ | |
590 | if (irr & (1 << (vector % 32))) { | |
591 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
592 | goto unlock; | |
593 | } | |
7276c6a2 | 594 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
74afab7a JL |
595 | unlock: |
596 | raw_spin_unlock(&desc->lock); | |
597 | } | |
598 | ||
df54c493 TG |
599 | raw_spin_unlock(&vector_lock); |
600 | ||
6af7faf6 | 601 | exiting_irq(); |
74afab7a JL |
602 | } |
603 | ||
604 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
605 | { | |
606 | unsigned me; | |
7f3262ed | 607 | struct apic_chip_data *data; |
74afab7a | 608 | |
7f3262ed JL |
609 | data = container_of(cfg, struct apic_chip_data, cfg); |
610 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
611 | return; |
612 | ||
613 | me = smp_processor_id(); | |
7f3262ed JL |
614 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
615 | __send_cleanup_vector(data); | |
74afab7a JL |
616 | } |
617 | ||
618 | void irq_complete_move(struct irq_cfg *cfg) | |
619 | { | |
620 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
621 | } | |
622 | ||
623 | void irq_force_complete_move(int irq) | |
624 | { | |
625 | struct irq_cfg *cfg = irq_cfg(irq); | |
626 | ||
7f3262ed JL |
627 | if (cfg) |
628 | __irq_complete_move(cfg, cfg->vector); | |
74afab7a | 629 | } |
74afab7a JL |
630 | #endif |
631 | ||
74afab7a JL |
632 | static void __init print_APIC_field(int base) |
633 | { | |
634 | int i; | |
635 | ||
636 | printk(KERN_DEBUG); | |
637 | ||
638 | for (i = 0; i < 8; i++) | |
639 | pr_cont("%08x", apic_read(base + i*0x10)); | |
640 | ||
641 | pr_cont("\n"); | |
642 | } | |
643 | ||
644 | static void __init print_local_APIC(void *dummy) | |
645 | { | |
646 | unsigned int i, v, ver, maxlvt; | |
647 | u64 icr; | |
648 | ||
849d3569 JL |
649 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
650 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 651 | v = apic_read(APIC_ID); |
849d3569 | 652 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 653 | v = apic_read(APIC_LVR); |
849d3569 | 654 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
655 | ver = GET_APIC_VERSION(v); |
656 | maxlvt = lapic_get_maxlvt(); | |
657 | ||
658 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 659 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
660 | |
661 | /* !82489DX */ | |
662 | if (APIC_INTEGRATED(ver)) { | |
663 | if (!APIC_XAPIC(ver)) { | |
664 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
665 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
666 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
667 | } |
668 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 669 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
670 | } |
671 | ||
672 | /* | |
673 | * Remote read supported only in the 82489DX and local APIC for | |
674 | * Pentium processors. | |
675 | */ | |
676 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
677 | v = apic_read(APIC_RRR); | |
849d3569 | 678 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
679 | } |
680 | ||
681 | v = apic_read(APIC_LDR); | |
849d3569 | 682 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
683 | if (!x2apic_enabled()) { |
684 | v = apic_read(APIC_DFR); | |
849d3569 | 685 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
686 | } |
687 | v = apic_read(APIC_SPIV); | |
849d3569 | 688 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 689 | |
849d3569 | 690 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 691 | print_APIC_field(APIC_ISR); |
849d3569 | 692 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 693 | print_APIC_field(APIC_TMR); |
849d3569 | 694 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
695 | print_APIC_field(APIC_IRR); |
696 | ||
697 | /* !82489DX */ | |
698 | if (APIC_INTEGRATED(ver)) { | |
699 | /* Due to the Pentium erratum 3AP. */ | |
700 | if (maxlvt > 3) | |
701 | apic_write(APIC_ESR, 0); | |
702 | ||
703 | v = apic_read(APIC_ESR); | |
849d3569 | 704 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
705 | } |
706 | ||
707 | icr = apic_icr_read(); | |
849d3569 JL |
708 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
709 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
710 | |
711 | v = apic_read(APIC_LVTT); | |
849d3569 | 712 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
713 | |
714 | if (maxlvt > 3) { | |
715 | /* PC is LVT#4. */ | |
716 | v = apic_read(APIC_LVTPC); | |
849d3569 | 717 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
718 | } |
719 | v = apic_read(APIC_LVT0); | |
849d3569 | 720 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 721 | v = apic_read(APIC_LVT1); |
849d3569 | 722 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
723 | |
724 | if (maxlvt > 2) { | |
725 | /* ERR is LVT#3. */ | |
726 | v = apic_read(APIC_LVTERR); | |
849d3569 | 727 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
728 | } |
729 | ||
730 | v = apic_read(APIC_TMICT); | |
849d3569 | 731 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 732 | v = apic_read(APIC_TMCCT); |
849d3569 | 733 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 734 | v = apic_read(APIC_TDCR); |
849d3569 | 735 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
736 | |
737 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
738 | v = apic_read(APIC_EFEAT); | |
739 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 740 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 741 | v = apic_read(APIC_ECTRL); |
849d3569 | 742 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
743 | for (i = 0; i < maxlvt; i++) { |
744 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 745 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
746 | } |
747 | } | |
748 | pr_cont("\n"); | |
749 | } | |
750 | ||
751 | static void __init print_local_APICs(int maxcpu) | |
752 | { | |
753 | int cpu; | |
754 | ||
755 | if (!maxcpu) | |
756 | return; | |
757 | ||
758 | preempt_disable(); | |
759 | for_each_online_cpu(cpu) { | |
760 | if (cpu >= maxcpu) | |
761 | break; | |
762 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
763 | } | |
764 | preempt_enable(); | |
765 | } | |
766 | ||
767 | static void __init print_PIC(void) | |
768 | { | |
769 | unsigned int v; | |
770 | unsigned long flags; | |
771 | ||
772 | if (!nr_legacy_irqs()) | |
773 | return; | |
774 | ||
849d3569 | 775 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
776 | |
777 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
778 | ||
779 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 780 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
781 | |
782 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 783 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
784 | |
785 | outb(0x0b, 0xa0); | |
786 | outb(0x0b, 0x20); | |
787 | v = inb(0xa0) << 8 | inb(0x20); | |
788 | outb(0x0a, 0xa0); | |
789 | outb(0x0a, 0x20); | |
790 | ||
791 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
792 | ||
849d3569 | 793 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
794 | |
795 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 796 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
797 | } |
798 | ||
799 | static int show_lapic __initdata = 1; | |
800 | static __init int setup_show_lapic(char *arg) | |
801 | { | |
802 | int num = -1; | |
803 | ||
804 | if (strcmp(arg, "all") == 0) { | |
805 | show_lapic = CONFIG_NR_CPUS; | |
806 | } else { | |
807 | get_option(&arg, &num); | |
808 | if (num >= 0) | |
809 | show_lapic = num; | |
810 | } | |
811 | ||
812 | return 1; | |
813 | } | |
814 | __setup("show_lapic=", setup_show_lapic); | |
815 | ||
816 | static int __init print_ICs(void) | |
817 | { | |
818 | if (apic_verbosity == APIC_QUIET) | |
819 | return 0; | |
820 | ||
821 | print_PIC(); | |
822 | ||
823 | /* don't print out if apic is not there */ | |
824 | if (!cpu_has_apic && !apic_from_smp_config()) | |
825 | return 0; | |
826 | ||
827 | print_local_APICs(show_lapic); | |
828 | print_IO_APICs(); | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
833 | late_initcall(print_ICs); |