Commit | Line | Data |
---|---|---|
74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 32 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 33 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 34 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 35 | static struct irq_chip lapic_controller; |
13315320 | 36 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 37 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 38 | #endif |
74afab7a JL |
39 | |
40 | void lock_vector_lock(void) | |
41 | { | |
42 | /* Used to the online set of cpus does not change | |
43 | * during assign_irq_vector. | |
44 | */ | |
45 | raw_spin_lock(&vector_lock); | |
46 | } | |
47 | ||
48 | void unlock_vector_lock(void) | |
49 | { | |
50 | raw_spin_unlock(&vector_lock); | |
51 | } | |
52 | ||
7f3262ed | 53 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 54 | { |
b5dc8e6c JL |
55 | if (!irq_data) |
56 | return NULL; | |
57 | ||
58 | while (irq_data->parent_data) | |
59 | irq_data = irq_data->parent_data; | |
60 | ||
74afab7a JL |
61 | return irq_data->chip_data; |
62 | } | |
63 | ||
7f3262ed JL |
64 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
65 | { | |
66 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
67 | ||
68 | return data ? &data->cfg : NULL; | |
69 | } | |
c8f3e518 | 70 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
71 | |
72 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 73 | { |
7f3262ed JL |
74 | return irqd_cfg(irq_get_irq_data(irq)); |
75 | } | |
74afab7a | 76 | |
7f3262ed JL |
77 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
78 | { | |
79 | struct apic_chip_data *data; | |
80 | ||
81 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
82 | if (!data) | |
74afab7a | 83 | return NULL; |
7f3262ed JL |
84 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
85 | goto out_data; | |
86 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 87 | goto out_domain; |
7f3262ed | 88 | return data; |
74afab7a | 89 | out_domain: |
7f3262ed JL |
90 | free_cpumask_var(data->domain); |
91 | out_data: | |
92 | kfree(data); | |
74afab7a JL |
93 | return NULL; |
94 | } | |
95 | ||
7f3262ed | 96 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 97 | { |
7f3262ed JL |
98 | if (data) { |
99 | free_cpumask_var(data->domain); | |
100 | free_cpumask_var(data->old_domain); | |
101 | kfree(data); | |
b5dc8e6c | 102 | } |
74afab7a JL |
103 | } |
104 | ||
7f3262ed JL |
105 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
106 | const struct cpumask *mask) | |
74afab7a JL |
107 | { |
108 | /* | |
109 | * NOTE! The local APIC isn't very good at handling | |
110 | * multiple interrupts at the same interrupt level. | |
111 | * As the interrupt level is determined by taking the | |
112 | * vector number and shifting that right by 4, we | |
113 | * want to spread these out a bit so that they don't | |
114 | * all fall in the same interrupt level. | |
115 | * | |
116 | * Also, we've got to be careful not to trash gate | |
117 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
118 | */ | |
119 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
120 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 121 | int cpu, vector; |
74afab7a | 122 | |
7f3262ed | 123 | if (d->move_in_progress) |
74afab7a JL |
124 | return -EBUSY; |
125 | ||
74afab7a | 126 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 127 | cpumask_clear(d->old_domain); |
8a580f70 | 128 | cpumask_clear(searched_cpumask); |
74afab7a JL |
129 | cpu = cpumask_first_and(mask, cpu_online_mask); |
130 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 131 | int new_cpu, offset; |
74afab7a | 132 | |
3716fd27 | 133 | /* Get the possible target cpus for @mask/@cpu from the apic */ |
f7fa7aee | 134 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 135 | |
3716fd27 TG |
136 | /* |
137 | * Clear the offline cpus from @vector_cpumask for searching | |
138 | * and verify whether the result overlaps with @mask. If true, | |
139 | * then the call to apic->cpu_mask_to_apicid_and() will | |
140 | * succeed as well. If not, no point in trying to find a | |
141 | * vector in this mask. | |
142 | */ | |
143 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
144 | if (!cpumask_intersects(vector_searchmask, mask)) | |
145 | goto next_cpu; | |
146 | ||
f7fa7aee | 147 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 148 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 149 | goto success; |
74afab7a | 150 | /* |
ab25ac02 TG |
151 | * Mark the cpus which are not longer in the mask for |
152 | * cleanup. | |
74afab7a | 153 | */ |
ab25ac02 TG |
154 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
155 | vector = d->cfg.vector; | |
156 | goto update; | |
74afab7a JL |
157 | } |
158 | ||
159 | vector = current_vector; | |
160 | offset = current_offset; | |
161 | next: | |
162 | vector += 16; | |
163 | if (vector >= first_system_vector) { | |
164 | offset = (offset + 1) % 16; | |
165 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
166 | } | |
167 | ||
95ffeb4b TG |
168 | /* If the search wrapped around, try the next cpu */ |
169 | if (unlikely(current_vector == vector)) | |
170 | goto next_cpu; | |
74afab7a JL |
171 | |
172 | if (test_bit(vector, used_vectors)) | |
173 | goto next; | |
174 | ||
3716fd27 | 175 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 176 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
177 | goto next; |
178 | } | |
179 | /* Found one! */ | |
180 | current_vector = vector; | |
181 | current_offset = offset; | |
ab25ac02 TG |
182 | /* Schedule the old vector for cleanup on all cpus */ |
183 | if (d->cfg.vector) | |
7f3262ed | 184 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 185 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 186 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 187 | goto update; |
95ffeb4b TG |
188 | |
189 | next_cpu: | |
190 | /* | |
191 | * We exclude the current @vector_cpumask from the requested | |
192 | * @mask and try again with the next online cpu in the | |
193 | * result. We cannot modify @mask, so we use @vector_cpumask | |
194 | * as a temporary buffer here as it will be reassigned when | |
195 | * calling apic->vector_allocation_domain() above. | |
196 | */ | |
197 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
198 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
199 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
200 | continue; | |
74afab7a | 201 | } |
433cbd57 | 202 | return -ENOSPC; |
74afab7a | 203 | |
ab25ac02 TG |
204 | update: |
205 | /* Cleanup required ? */ | |
206 | d->move_in_progress = cpumask_intersects(d->old_domain, cpu_online_mask); | |
207 | d->cfg.vector = vector; | |
208 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 209 | success: |
3716fd27 TG |
210 | /* |
211 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
212 | * as we already established, that mask & d->domain & cpu_online_mask | |
213 | * is not empty. | |
214 | */ | |
215 | BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain, | |
216 | &d->cfg.dest_apicid)); | |
217 | return 0; | |
74afab7a JL |
218 | } |
219 | ||
7f3262ed | 220 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 221 | const struct cpumask *mask) |
74afab7a JL |
222 | { |
223 | int err; | |
224 | unsigned long flags; | |
225 | ||
226 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 227 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
228 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
229 | return err; | |
230 | } | |
231 | ||
486ca539 JL |
232 | static int assign_irq_vector_policy(int irq, int node, |
233 | struct apic_chip_data *data, | |
234 | struct irq_alloc_info *info) | |
235 | { | |
236 | if (info && info->mask) | |
237 | return assign_irq_vector(irq, data, info->mask); | |
238 | if (node != NUMA_NO_NODE && | |
239 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
240 | return 0; | |
241 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
242 | } | |
243 | ||
7f3262ed | 244 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a | 245 | { |
a782a7e4 | 246 | struct irq_desc *desc; |
a782a7e4 | 247 | int cpu, vector; |
74afab7a | 248 | |
7f3262ed | 249 | BUG_ON(!data->cfg.vector); |
74afab7a | 250 | |
7f3262ed JL |
251 | vector = data->cfg.vector; |
252 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 253 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 254 | |
7f3262ed JL |
255 | data->cfg.vector = 0; |
256 | cpumask_clear(data->domain); | |
74afab7a | 257 | |
111abeba | 258 | if (likely(!data->move_in_progress)) |
74afab7a | 259 | return; |
74afab7a | 260 | |
a782a7e4 | 261 | desc = irq_to_desc(irq); |
7f3262ed | 262 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
263 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
264 | vector++) { | |
a782a7e4 | 265 | if (per_cpu(vector_irq, cpu)[vector] != desc) |
74afab7a | 266 | continue; |
7276c6a2 | 267 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
268 | break; |
269 | } | |
270 | } | |
7f3262ed | 271 | data->move_in_progress = 0; |
74afab7a JL |
272 | } |
273 | ||
b5dc8e6c JL |
274 | void init_irq_alloc_info(struct irq_alloc_info *info, |
275 | const struct cpumask *mask) | |
276 | { | |
277 | memset(info, 0, sizeof(*info)); | |
278 | info->mask = mask; | |
279 | } | |
280 | ||
281 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
282 | { | |
283 | if (src) | |
284 | *dst = *src; | |
285 | else | |
286 | memset(dst, 0, sizeof(*dst)); | |
287 | } | |
288 | ||
b5dc8e6c JL |
289 | static void x86_vector_free_irqs(struct irq_domain *domain, |
290 | unsigned int virq, unsigned int nr_irqs) | |
291 | { | |
111abeba | 292 | struct apic_chip_data *apic_data; |
b5dc8e6c | 293 | struct irq_data *irq_data; |
111abeba | 294 | unsigned long flags; |
b5dc8e6c JL |
295 | int i; |
296 | ||
297 | for (i = 0; i < nr_irqs; i++) { | |
298 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
299 | if (irq_data && irq_data->chip_data) { | |
111abeba | 300 | raw_spin_lock_irqsave(&vector_lock, flags); |
b5dc8e6c | 301 | clear_irq_vector(virq + i, irq_data->chip_data); |
111abeba JL |
302 | apic_data = irq_data->chip_data; |
303 | irq_domain_reset_irq_data(irq_data); | |
304 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
305 | free_apic_chip_data(apic_data); | |
13315320 JL |
306 | #ifdef CONFIG_X86_IO_APIC |
307 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 308 | legacy_irq_data[virq + i] = NULL; |
13315320 | 309 | #endif |
b5dc8e6c JL |
310 | } |
311 | } | |
312 | } | |
313 | ||
314 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
315 | unsigned int nr_irqs, void *arg) | |
316 | { | |
317 | struct irq_alloc_info *info = arg; | |
7f3262ed | 318 | struct apic_chip_data *data; |
b5dc8e6c | 319 | struct irq_data *irq_data; |
5f2dbbc5 | 320 | int i, err, node; |
b5dc8e6c JL |
321 | |
322 | if (disable_apic) | |
323 | return -ENXIO; | |
324 | ||
325 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
326 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
327 | return -ENOSYS; | |
328 | ||
b5dc8e6c JL |
329 | for (i = 0; i < nr_irqs; i++) { |
330 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
331 | BUG_ON(!irq_data); | |
5f2dbbc5 | 332 | node = irq_data_get_node(irq_data); |
13315320 | 333 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
334 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
335 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
336 | else |
337 | #endif | |
5f2dbbc5 | 338 | data = alloc_apic_chip_data(node); |
7f3262ed | 339 | if (!data) { |
b5dc8e6c JL |
340 | err = -ENOMEM; |
341 | goto error; | |
342 | } | |
343 | ||
344 | irq_data->chip = &lapic_controller; | |
7f3262ed | 345 | irq_data->chip_data = data; |
b5dc8e6c | 346 | irq_data->hwirq = virq + i; |
43af9872 | 347 | err = assign_irq_vector_policy(virq + i, node, data, info); |
b5dc8e6c JL |
348 | if (err) |
349 | goto error; | |
350 | } | |
351 | ||
352 | return 0; | |
353 | ||
354 | error: | |
355 | x86_vector_free_irqs(domain, virq, i + 1); | |
356 | return err; | |
357 | } | |
358 | ||
eb18cf55 TG |
359 | static const struct irq_domain_ops x86_vector_domain_ops = { |
360 | .alloc = x86_vector_alloc_irqs, | |
361 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
362 | }; |
363 | ||
11d686e9 JL |
364 | int __init arch_probe_nr_irqs(void) |
365 | { | |
366 | int nr; | |
367 | ||
368 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
369 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
370 | ||
371 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
372 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
373 | /* | |
374 | * for MSI and HT dyn irq | |
375 | */ | |
376 | if (gsi_top <= NR_IRQS_LEGACY) | |
377 | nr += 8 * nr_cpu_ids; | |
378 | else | |
379 | nr += gsi_top * 16; | |
380 | #endif | |
381 | if (nr < nr_irqs) | |
382 | nr_irqs = nr; | |
383 | ||
8c058b0b VK |
384 | /* |
385 | * We don't know if PIC is present at this point so we need to do | |
386 | * probe() to get the right number of legacy IRQs. | |
387 | */ | |
388 | return legacy_pic->probe(); | |
11d686e9 JL |
389 | } |
390 | ||
13315320 JL |
391 | #ifdef CONFIG_X86_IO_APIC |
392 | static void init_legacy_irqs(void) | |
393 | { | |
394 | int i, node = cpu_to_node(0); | |
7f3262ed | 395 | struct apic_chip_data *data; |
13315320 JL |
396 | |
397 | /* | |
398 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 399 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
400 | */ |
401 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
402 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
403 | BUG_ON(!data); | |
191a6635 IM |
404 | |
405 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
406 | cpumask_setall(data->domain); |
407 | irq_set_chip_data(i, data); | |
13315320 JL |
408 | } |
409 | } | |
410 | #else | |
411 | static void init_legacy_irqs(void) { } | |
412 | #endif | |
413 | ||
11d686e9 JL |
414 | int __init arch_early_irq_init(void) |
415 | { | |
13315320 JL |
416 | init_legacy_irqs(); |
417 | ||
b5dc8e6c JL |
418 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
419 | NULL); | |
420 | BUG_ON(x86_vector_domain == NULL); | |
421 | irq_set_default_host(x86_vector_domain); | |
422 | ||
52f518a3 | 423 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 424 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 425 | |
f7fa7aee | 426 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 427 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 428 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 429 | |
11d686e9 JL |
430 | return arch_early_ioapic_init(); |
431 | } | |
432 | ||
a782a7e4 | 433 | /* Initialize vector_irq on a new cpu */ |
74afab7a JL |
434 | static void __setup_vector_irq(int cpu) |
435 | { | |
7f3262ed | 436 | struct apic_chip_data *data; |
a782a7e4 TG |
437 | struct irq_desc *desc; |
438 | int irq, vector; | |
74afab7a | 439 | |
74afab7a | 440 | /* Mark the inuse vectors */ |
a782a7e4 TG |
441 | for_each_irq_desc(irq, desc) { |
442 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
74afab7a | 443 | |
a782a7e4 TG |
444 | data = apic_chip_data(idata); |
445 | if (!data || !cpumask_test_cpu(cpu, data->domain)) | |
74afab7a | 446 | continue; |
7f3262ed | 447 | vector = data->cfg.vector; |
a782a7e4 | 448 | per_cpu(vector_irq, cpu)[vector] = desc; |
74afab7a JL |
449 | } |
450 | /* Mark the free vectors */ | |
451 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
a782a7e4 TG |
452 | desc = per_cpu(vector_irq, cpu)[vector]; |
453 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
454 | continue; |
455 | ||
a782a7e4 | 456 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 457 | if (!cpumask_test_cpu(cpu, data->domain)) |
7276c6a2 | 458 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 459 | } |
74afab7a JL |
460 | } |
461 | ||
462 | /* | |
5a3f75e3 | 463 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
464 | */ |
465 | void setup_vector_irq(int cpu) | |
466 | { | |
467 | int irq; | |
468 | ||
5a3f75e3 | 469 | lockdep_assert_held(&vector_lock); |
74afab7a JL |
470 | /* |
471 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
472 | * boot cpu. But there are certain platforms where PIC interrupts are | |
473 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
474 | * legacy PIC, for the new cpu that is coming online, setup the static | |
475 | * legacy vector to irq mapping: | |
476 | */ | |
477 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
a782a7e4 | 478 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); |
74afab7a JL |
479 | |
480 | __setup_vector_irq(cpu); | |
481 | } | |
482 | ||
7f3262ed | 483 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 484 | { |
7f3262ed | 485 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
486 | unsigned long flags; |
487 | int cpu; | |
488 | ||
489 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
490 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
491 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
492 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
493 | ||
494 | return 1; | |
495 | } | |
496 | ||
497 | void apic_ack_edge(struct irq_data *data) | |
498 | { | |
a9786091 | 499 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
500 | irq_move_irq(data); |
501 | ack_APIC_irq(); | |
502 | } | |
503 | ||
68f9f440 JL |
504 | static int apic_set_affinity(struct irq_data *irq_data, |
505 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 506 | { |
7f3262ed | 507 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
508 | int err, irq = irq_data->irq; |
509 | ||
510 | if (!config_enabled(CONFIG_SMP)) | |
511 | return -EPERM; | |
512 | ||
513 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
514 | return -EINVAL; | |
515 | ||
7f3262ed | 516 | err = assign_irq_vector(irq, data, dest); |
3716fd27 | 517 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
518 | } |
519 | ||
520 | static struct irq_chip lapic_controller = { | |
521 | .irq_ack = apic_ack_edge, | |
68f9f440 | 522 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
523 | .irq_retrigger = apic_retrigger_irq, |
524 | }; | |
525 | ||
74afab7a | 526 | #ifdef CONFIG_SMP |
7f3262ed | 527 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a JL |
528 | { |
529 | cpumask_var_t cleanup_mask; | |
530 | ||
531 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
532 | unsigned int i; | |
533 | ||
7f3262ed | 534 | for_each_cpu_and(i, data->old_domain, cpu_online_mask) |
74afab7a JL |
535 | apic->send_IPI_mask(cpumask_of(i), |
536 | IRQ_MOVE_CLEANUP_VECTOR); | |
537 | } else { | |
7f3262ed | 538 | cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); |
74afab7a JL |
539 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
540 | free_cpumask_var(cleanup_mask); | |
541 | } | |
7f3262ed | 542 | data->move_in_progress = 0; |
74afab7a JL |
543 | } |
544 | ||
c6c2002b JL |
545 | void send_cleanup_vector(struct irq_cfg *cfg) |
546 | { | |
7f3262ed JL |
547 | struct apic_chip_data *data; |
548 | ||
549 | data = container_of(cfg, struct apic_chip_data, cfg); | |
550 | if (data->move_in_progress) | |
551 | __send_cleanup_vector(data); | |
c6c2002b JL |
552 | } |
553 | ||
74afab7a JL |
554 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
555 | { | |
556 | unsigned vector, me; | |
557 | ||
6af7faf6 | 558 | entering_ack_irq(); |
74afab7a | 559 | |
df54c493 TG |
560 | /* Prevent vectors vanishing under us */ |
561 | raw_spin_lock(&vector_lock); | |
562 | ||
74afab7a JL |
563 | me = smp_processor_id(); |
564 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
7f3262ed | 565 | struct apic_chip_data *data; |
a782a7e4 TG |
566 | struct irq_desc *desc; |
567 | unsigned int irr; | |
74afab7a | 568 | |
df54c493 | 569 | retry: |
a782a7e4 TG |
570 | desc = __this_cpu_read(vector_irq[vector]); |
571 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
572 | continue; |
573 | ||
df54c493 TG |
574 | if (!raw_spin_trylock(&desc->lock)) { |
575 | raw_spin_unlock(&vector_lock); | |
576 | cpu_relax(); | |
577 | raw_spin_lock(&vector_lock); | |
578 | goto retry; | |
579 | } | |
74afab7a | 580 | |
a782a7e4 | 581 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 582 | if (!data) |
df54c493 | 583 | goto unlock; |
74afab7a JL |
584 | |
585 | /* | |
586 | * Check if the irq migration is in progress. If so, we | |
587 | * haven't received the cleanup request yet for this irq. | |
588 | */ | |
7f3262ed | 589 | if (data->move_in_progress) |
74afab7a JL |
590 | goto unlock; |
591 | ||
7f3262ed JL |
592 | if (vector == data->cfg.vector && |
593 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
594 | goto unlock; |
595 | ||
596 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
597 | /* | |
598 | * Check if the vector that needs to be cleanedup is | |
599 | * registered at the cpu's IRR. If so, then this is not | |
600 | * the best time to clean it up. Lets clean it up in the | |
601 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
602 | * to myself. | |
603 | */ | |
604 | if (irr & (1 << (vector % 32))) { | |
605 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
606 | goto unlock; | |
607 | } | |
7276c6a2 | 608 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
74afab7a JL |
609 | unlock: |
610 | raw_spin_unlock(&desc->lock); | |
611 | } | |
612 | ||
df54c493 TG |
613 | raw_spin_unlock(&vector_lock); |
614 | ||
6af7faf6 | 615 | exiting_irq(); |
74afab7a JL |
616 | } |
617 | ||
618 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
619 | { | |
620 | unsigned me; | |
7f3262ed | 621 | struct apic_chip_data *data; |
74afab7a | 622 | |
7f3262ed JL |
623 | data = container_of(cfg, struct apic_chip_data, cfg); |
624 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
625 | return; |
626 | ||
627 | me = smp_processor_id(); | |
7f3262ed JL |
628 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
629 | __send_cleanup_vector(data); | |
74afab7a JL |
630 | } |
631 | ||
632 | void irq_complete_move(struct irq_cfg *cfg) | |
633 | { | |
634 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
635 | } | |
636 | ||
637 | void irq_force_complete_move(int irq) | |
638 | { | |
639 | struct irq_cfg *cfg = irq_cfg(irq); | |
640 | ||
7f3262ed JL |
641 | if (cfg) |
642 | __irq_complete_move(cfg, cfg->vector); | |
74afab7a | 643 | } |
74afab7a JL |
644 | #endif |
645 | ||
74afab7a JL |
646 | static void __init print_APIC_field(int base) |
647 | { | |
648 | int i; | |
649 | ||
650 | printk(KERN_DEBUG); | |
651 | ||
652 | for (i = 0; i < 8; i++) | |
653 | pr_cont("%08x", apic_read(base + i*0x10)); | |
654 | ||
655 | pr_cont("\n"); | |
656 | } | |
657 | ||
658 | static void __init print_local_APIC(void *dummy) | |
659 | { | |
660 | unsigned int i, v, ver, maxlvt; | |
661 | u64 icr; | |
662 | ||
849d3569 JL |
663 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
664 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 665 | v = apic_read(APIC_ID); |
849d3569 | 666 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 667 | v = apic_read(APIC_LVR); |
849d3569 | 668 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
669 | ver = GET_APIC_VERSION(v); |
670 | maxlvt = lapic_get_maxlvt(); | |
671 | ||
672 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 673 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
674 | |
675 | /* !82489DX */ | |
676 | if (APIC_INTEGRATED(ver)) { | |
677 | if (!APIC_XAPIC(ver)) { | |
678 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
679 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
680 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
681 | } |
682 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 683 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
684 | } |
685 | ||
686 | /* | |
687 | * Remote read supported only in the 82489DX and local APIC for | |
688 | * Pentium processors. | |
689 | */ | |
690 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
691 | v = apic_read(APIC_RRR); | |
849d3569 | 692 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
693 | } |
694 | ||
695 | v = apic_read(APIC_LDR); | |
849d3569 | 696 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
697 | if (!x2apic_enabled()) { |
698 | v = apic_read(APIC_DFR); | |
849d3569 | 699 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
700 | } |
701 | v = apic_read(APIC_SPIV); | |
849d3569 | 702 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 703 | |
849d3569 | 704 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 705 | print_APIC_field(APIC_ISR); |
849d3569 | 706 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 707 | print_APIC_field(APIC_TMR); |
849d3569 | 708 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
709 | print_APIC_field(APIC_IRR); |
710 | ||
711 | /* !82489DX */ | |
712 | if (APIC_INTEGRATED(ver)) { | |
713 | /* Due to the Pentium erratum 3AP. */ | |
714 | if (maxlvt > 3) | |
715 | apic_write(APIC_ESR, 0); | |
716 | ||
717 | v = apic_read(APIC_ESR); | |
849d3569 | 718 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
719 | } |
720 | ||
721 | icr = apic_icr_read(); | |
849d3569 JL |
722 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
723 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
724 | |
725 | v = apic_read(APIC_LVTT); | |
849d3569 | 726 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
727 | |
728 | if (maxlvt > 3) { | |
729 | /* PC is LVT#4. */ | |
730 | v = apic_read(APIC_LVTPC); | |
849d3569 | 731 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
732 | } |
733 | v = apic_read(APIC_LVT0); | |
849d3569 | 734 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 735 | v = apic_read(APIC_LVT1); |
849d3569 | 736 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
737 | |
738 | if (maxlvt > 2) { | |
739 | /* ERR is LVT#3. */ | |
740 | v = apic_read(APIC_LVTERR); | |
849d3569 | 741 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
742 | } |
743 | ||
744 | v = apic_read(APIC_TMICT); | |
849d3569 | 745 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 746 | v = apic_read(APIC_TMCCT); |
849d3569 | 747 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 748 | v = apic_read(APIC_TDCR); |
849d3569 | 749 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
750 | |
751 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
752 | v = apic_read(APIC_EFEAT); | |
753 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 754 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 755 | v = apic_read(APIC_ECTRL); |
849d3569 | 756 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
757 | for (i = 0; i < maxlvt; i++) { |
758 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 759 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
760 | } |
761 | } | |
762 | pr_cont("\n"); | |
763 | } | |
764 | ||
765 | static void __init print_local_APICs(int maxcpu) | |
766 | { | |
767 | int cpu; | |
768 | ||
769 | if (!maxcpu) | |
770 | return; | |
771 | ||
772 | preempt_disable(); | |
773 | for_each_online_cpu(cpu) { | |
774 | if (cpu >= maxcpu) | |
775 | break; | |
776 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
777 | } | |
778 | preempt_enable(); | |
779 | } | |
780 | ||
781 | static void __init print_PIC(void) | |
782 | { | |
783 | unsigned int v; | |
784 | unsigned long flags; | |
785 | ||
786 | if (!nr_legacy_irqs()) | |
787 | return; | |
788 | ||
849d3569 | 789 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
790 | |
791 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
792 | ||
793 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 794 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
795 | |
796 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 797 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
798 | |
799 | outb(0x0b, 0xa0); | |
800 | outb(0x0b, 0x20); | |
801 | v = inb(0xa0) << 8 | inb(0x20); | |
802 | outb(0x0a, 0xa0); | |
803 | outb(0x0a, 0x20); | |
804 | ||
805 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
806 | ||
849d3569 | 807 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
808 | |
809 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 810 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
811 | } |
812 | ||
813 | static int show_lapic __initdata = 1; | |
814 | static __init int setup_show_lapic(char *arg) | |
815 | { | |
816 | int num = -1; | |
817 | ||
818 | if (strcmp(arg, "all") == 0) { | |
819 | show_lapic = CONFIG_NR_CPUS; | |
820 | } else { | |
821 | get_option(&arg, &num); | |
822 | if (num >= 0) | |
823 | show_lapic = num; | |
824 | } | |
825 | ||
826 | return 1; | |
827 | } | |
828 | __setup("show_lapic=", setup_show_lapic); | |
829 | ||
830 | static int __init print_ICs(void) | |
831 | { | |
832 | if (apic_verbosity == APIC_QUIET) | |
833 | return 0; | |
834 | ||
835 | print_PIC(); | |
836 | ||
837 | /* don't print out if apic is not there */ | |
838 | if (!cpu_has_apic && !apic_from_smp_config()) | |
839 | return 0; | |
840 | ||
841 | print_local_APICs(show_lapic); | |
842 | print_IO_APICs(); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | late_initcall(print_ICs); |