Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 32 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 33 | static DEFINE_RAW_SPINLOCK(vector_lock); |
3716fd27 | 34 | static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask; |
b5dc8e6c | 35 | static struct irq_chip lapic_controller; |
13315320 | 36 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 37 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 38 | #endif |
74afab7a JL |
39 | |
40 | void lock_vector_lock(void) | |
41 | { | |
42 | /* Used to the online set of cpus does not change | |
43 | * during assign_irq_vector. | |
44 | */ | |
45 | raw_spin_lock(&vector_lock); | |
46 | } | |
47 | ||
48 | void unlock_vector_lock(void) | |
49 | { | |
50 | raw_spin_unlock(&vector_lock); | |
51 | } | |
52 | ||
7f3262ed | 53 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 54 | { |
b5dc8e6c JL |
55 | if (!irq_data) |
56 | return NULL; | |
57 | ||
58 | while (irq_data->parent_data) | |
59 | irq_data = irq_data->parent_data; | |
60 | ||
74afab7a JL |
61 | return irq_data->chip_data; |
62 | } | |
63 | ||
7f3262ed JL |
64 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
65 | { | |
66 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
67 | ||
68 | return data ? &data->cfg : NULL; | |
69 | } | |
c8f3e518 | 70 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
71 | |
72 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 73 | { |
7f3262ed JL |
74 | return irqd_cfg(irq_get_irq_data(irq)); |
75 | } | |
74afab7a | 76 | |
7f3262ed JL |
77 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
78 | { | |
79 | struct apic_chip_data *data; | |
80 | ||
81 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
82 | if (!data) | |
74afab7a | 83 | return NULL; |
7f3262ed JL |
84 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
85 | goto out_data; | |
86 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 87 | goto out_domain; |
7f3262ed | 88 | return data; |
74afab7a | 89 | out_domain: |
7f3262ed JL |
90 | free_cpumask_var(data->domain); |
91 | out_data: | |
92 | kfree(data); | |
74afab7a JL |
93 | return NULL; |
94 | } | |
95 | ||
7f3262ed | 96 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 97 | { |
7f3262ed JL |
98 | if (data) { |
99 | free_cpumask_var(data->domain); | |
100 | free_cpumask_var(data->old_domain); | |
101 | kfree(data); | |
b5dc8e6c | 102 | } |
74afab7a JL |
103 | } |
104 | ||
7f3262ed JL |
105 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
106 | const struct cpumask *mask) | |
74afab7a JL |
107 | { |
108 | /* | |
109 | * NOTE! The local APIC isn't very good at handling | |
110 | * multiple interrupts at the same interrupt level. | |
111 | * As the interrupt level is determined by taking the | |
112 | * vector number and shifting that right by 4, we | |
113 | * want to spread these out a bit so that they don't | |
114 | * all fall in the same interrupt level. | |
115 | * | |
116 | * Also, we've got to be careful not to trash gate | |
117 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
118 | */ | |
119 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
120 | static int current_offset = VECTOR_OFFSET_START % 16; | |
ab25ac02 | 121 | int cpu, vector; |
74afab7a | 122 | |
7f3262ed | 123 | if (d->move_in_progress) |
74afab7a JL |
124 | return -EBUSY; |
125 | ||
74afab7a | 126 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 127 | cpumask_clear(d->old_domain); |
8a580f70 | 128 | cpumask_clear(searched_cpumask); |
74afab7a JL |
129 | cpu = cpumask_first_and(mask, cpu_online_mask); |
130 | while (cpu < nr_cpu_ids) { | |
ab25ac02 | 131 | int new_cpu, offset; |
74afab7a | 132 | |
3716fd27 | 133 | /* Get the possible target cpus for @mask/@cpu from the apic */ |
f7fa7aee | 134 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 135 | |
3716fd27 TG |
136 | /* |
137 | * Clear the offline cpus from @vector_cpumask for searching | |
138 | * and verify whether the result overlaps with @mask. If true, | |
139 | * then the call to apic->cpu_mask_to_apicid_and() will | |
140 | * succeed as well. If not, no point in trying to find a | |
141 | * vector in this mask. | |
142 | */ | |
143 | cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask); | |
144 | if (!cpumask_intersects(vector_searchmask, mask)) | |
145 | goto next_cpu; | |
146 | ||
f7fa7aee | 147 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 148 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 149 | goto success; |
74afab7a | 150 | /* |
ab25ac02 TG |
151 | * Mark the cpus which are not longer in the mask for |
152 | * cleanup. | |
74afab7a | 153 | */ |
ab25ac02 TG |
154 | cpumask_andnot(d->old_domain, d->domain, vector_cpumask); |
155 | vector = d->cfg.vector; | |
156 | goto update; | |
74afab7a JL |
157 | } |
158 | ||
159 | vector = current_vector; | |
160 | offset = current_offset; | |
161 | next: | |
162 | vector += 16; | |
163 | if (vector >= first_system_vector) { | |
164 | offset = (offset + 1) % 16; | |
165 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
166 | } | |
167 | ||
95ffeb4b TG |
168 | /* If the search wrapped around, try the next cpu */ |
169 | if (unlikely(current_vector == vector)) | |
170 | goto next_cpu; | |
74afab7a JL |
171 | |
172 | if (test_bit(vector, used_vectors)) | |
173 | goto next; | |
174 | ||
3716fd27 | 175 | for_each_cpu(new_cpu, vector_searchmask) { |
a782a7e4 | 176 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
177 | goto next; |
178 | } | |
179 | /* Found one! */ | |
180 | current_vector = vector; | |
181 | current_offset = offset; | |
ab25ac02 TG |
182 | /* Schedule the old vector for cleanup on all cpus */ |
183 | if (d->cfg.vector) | |
7f3262ed | 184 | cpumask_copy(d->old_domain, d->domain); |
3716fd27 | 185 | for_each_cpu(new_cpu, vector_searchmask) |
a782a7e4 | 186 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
ab25ac02 | 187 | goto update; |
95ffeb4b TG |
188 | |
189 | next_cpu: | |
190 | /* | |
191 | * We exclude the current @vector_cpumask from the requested | |
192 | * @mask and try again with the next online cpu in the | |
193 | * result. We cannot modify @mask, so we use @vector_cpumask | |
194 | * as a temporary buffer here as it will be reassigned when | |
195 | * calling apic->vector_allocation_domain() above. | |
196 | */ | |
197 | cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask); | |
198 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); | |
199 | cpu = cpumask_first_and(vector_cpumask, cpu_online_mask); | |
200 | continue; | |
74afab7a | 201 | } |
433cbd57 | 202 | return -ENOSPC; |
74afab7a | 203 | |
ab25ac02 | 204 | update: |
847667ef TG |
205 | /* |
206 | * Exclude offline cpus from the cleanup mask and set the | |
207 | * move_in_progress flag when the result is not empty. | |
208 | */ | |
209 | cpumask_and(d->old_domain, d->old_domain, cpu_online_mask); | |
210 | d->move_in_progress = !cpumask_empty(d->old_domain); | |
ab25ac02 TG |
211 | d->cfg.vector = vector; |
212 | cpumask_copy(d->domain, vector_cpumask); | |
433cbd57 | 213 | success: |
3716fd27 TG |
214 | /* |
215 | * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail | |
216 | * as we already established, that mask & d->domain & cpu_online_mask | |
217 | * is not empty. | |
218 | */ | |
219 | BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain, | |
220 | &d->cfg.dest_apicid)); | |
221 | return 0; | |
74afab7a JL |
222 | } |
223 | ||
7f3262ed | 224 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 225 | const struct cpumask *mask) |
74afab7a JL |
226 | { |
227 | int err; | |
228 | unsigned long flags; | |
229 | ||
230 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 231 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
232 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
233 | return err; | |
234 | } | |
235 | ||
486ca539 JL |
236 | static int assign_irq_vector_policy(int irq, int node, |
237 | struct apic_chip_data *data, | |
238 | struct irq_alloc_info *info) | |
239 | { | |
240 | if (info && info->mask) | |
241 | return assign_irq_vector(irq, data, info->mask); | |
242 | if (node != NUMA_NO_NODE && | |
243 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
244 | return 0; | |
245 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
246 | } | |
247 | ||
7f3262ed | 248 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a | 249 | { |
a782a7e4 | 250 | struct irq_desc *desc; |
a782a7e4 | 251 | int cpu, vector; |
74afab7a | 252 | |
7f3262ed | 253 | BUG_ON(!data->cfg.vector); |
74afab7a | 254 | |
7f3262ed JL |
255 | vector = data->cfg.vector; |
256 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 257 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 258 | |
7f3262ed JL |
259 | data->cfg.vector = 0; |
260 | cpumask_clear(data->domain); | |
74afab7a | 261 | |
111abeba | 262 | if (likely(!data->move_in_progress)) |
74afab7a | 263 | return; |
74afab7a | 264 | |
a782a7e4 | 265 | desc = irq_to_desc(irq); |
7f3262ed | 266 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
267 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
268 | vector++) { | |
a782a7e4 | 269 | if (per_cpu(vector_irq, cpu)[vector] != desc) |
74afab7a | 270 | continue; |
7276c6a2 | 271 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
272 | break; |
273 | } | |
274 | } | |
7f3262ed | 275 | data->move_in_progress = 0; |
74afab7a JL |
276 | } |
277 | ||
b5dc8e6c JL |
278 | void init_irq_alloc_info(struct irq_alloc_info *info, |
279 | const struct cpumask *mask) | |
280 | { | |
281 | memset(info, 0, sizeof(*info)); | |
282 | info->mask = mask; | |
283 | } | |
284 | ||
285 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
286 | { | |
287 | if (src) | |
288 | *dst = *src; | |
289 | else | |
290 | memset(dst, 0, sizeof(*dst)); | |
291 | } | |
292 | ||
b5dc8e6c JL |
293 | static void x86_vector_free_irqs(struct irq_domain *domain, |
294 | unsigned int virq, unsigned int nr_irqs) | |
295 | { | |
111abeba | 296 | struct apic_chip_data *apic_data; |
b5dc8e6c | 297 | struct irq_data *irq_data; |
111abeba | 298 | unsigned long flags; |
b5dc8e6c JL |
299 | int i; |
300 | ||
301 | for (i = 0; i < nr_irqs; i++) { | |
302 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
303 | if (irq_data && irq_data->chip_data) { | |
111abeba | 304 | raw_spin_lock_irqsave(&vector_lock, flags); |
b5dc8e6c | 305 | clear_irq_vector(virq + i, irq_data->chip_data); |
111abeba JL |
306 | apic_data = irq_data->chip_data; |
307 | irq_domain_reset_irq_data(irq_data); | |
308 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
309 | free_apic_chip_data(apic_data); | |
13315320 JL |
310 | #ifdef CONFIG_X86_IO_APIC |
311 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 312 | legacy_irq_data[virq + i] = NULL; |
13315320 | 313 | #endif |
b5dc8e6c JL |
314 | } |
315 | } | |
316 | } | |
317 | ||
318 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
319 | unsigned int nr_irqs, void *arg) | |
320 | { | |
321 | struct irq_alloc_info *info = arg; | |
7f3262ed | 322 | struct apic_chip_data *data; |
b5dc8e6c | 323 | struct irq_data *irq_data; |
5f2dbbc5 | 324 | int i, err, node; |
b5dc8e6c JL |
325 | |
326 | if (disable_apic) | |
327 | return -ENXIO; | |
328 | ||
329 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
330 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
331 | return -ENOSYS; | |
332 | ||
b5dc8e6c JL |
333 | for (i = 0; i < nr_irqs; i++) { |
334 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
335 | BUG_ON(!irq_data); | |
5f2dbbc5 | 336 | node = irq_data_get_node(irq_data); |
13315320 | 337 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
338 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
339 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
340 | else |
341 | #endif | |
5f2dbbc5 | 342 | data = alloc_apic_chip_data(node); |
7f3262ed | 343 | if (!data) { |
b5dc8e6c JL |
344 | err = -ENOMEM; |
345 | goto error; | |
346 | } | |
347 | ||
348 | irq_data->chip = &lapic_controller; | |
7f3262ed | 349 | irq_data->chip_data = data; |
b5dc8e6c | 350 | irq_data->hwirq = virq + i; |
43af9872 | 351 | err = assign_irq_vector_policy(virq + i, node, data, info); |
b5dc8e6c JL |
352 | if (err) |
353 | goto error; | |
354 | } | |
355 | ||
356 | return 0; | |
357 | ||
358 | error: | |
359 | x86_vector_free_irqs(domain, virq, i + 1); | |
360 | return err; | |
361 | } | |
362 | ||
eb18cf55 TG |
363 | static const struct irq_domain_ops x86_vector_domain_ops = { |
364 | .alloc = x86_vector_alloc_irqs, | |
365 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
366 | }; |
367 | ||
11d686e9 JL |
368 | int __init arch_probe_nr_irqs(void) |
369 | { | |
370 | int nr; | |
371 | ||
372 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
373 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
374 | ||
375 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
376 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
377 | /* | |
378 | * for MSI and HT dyn irq | |
379 | */ | |
380 | if (gsi_top <= NR_IRQS_LEGACY) | |
381 | nr += 8 * nr_cpu_ids; | |
382 | else | |
383 | nr += gsi_top * 16; | |
384 | #endif | |
385 | if (nr < nr_irqs) | |
386 | nr_irqs = nr; | |
387 | ||
8c058b0b VK |
388 | /* |
389 | * We don't know if PIC is present at this point so we need to do | |
390 | * probe() to get the right number of legacy IRQs. | |
391 | */ | |
392 | return legacy_pic->probe(); | |
11d686e9 JL |
393 | } |
394 | ||
13315320 JL |
395 | #ifdef CONFIG_X86_IO_APIC |
396 | static void init_legacy_irqs(void) | |
397 | { | |
398 | int i, node = cpu_to_node(0); | |
7f3262ed | 399 | struct apic_chip_data *data; |
13315320 JL |
400 | |
401 | /* | |
402 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 403 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
404 | */ |
405 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
406 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
407 | BUG_ON(!data); | |
191a6635 IM |
408 | |
409 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
410 | cpumask_setall(data->domain); |
411 | irq_set_chip_data(i, data); | |
13315320 JL |
412 | } |
413 | } | |
414 | #else | |
415 | static void init_legacy_irqs(void) { } | |
416 | #endif | |
417 | ||
11d686e9 JL |
418 | int __init arch_early_irq_init(void) |
419 | { | |
13315320 JL |
420 | init_legacy_irqs(); |
421 | ||
b5dc8e6c JL |
422 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
423 | NULL); | |
424 | BUG_ON(x86_vector_domain == NULL); | |
425 | irq_set_default_host(x86_vector_domain); | |
426 | ||
52f518a3 | 427 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 428 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 429 | |
f7fa7aee | 430 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
3716fd27 | 431 | BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); |
8a580f70 | 432 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 433 | |
11d686e9 JL |
434 | return arch_early_ioapic_init(); |
435 | } | |
436 | ||
a782a7e4 | 437 | /* Initialize vector_irq on a new cpu */ |
74afab7a JL |
438 | static void __setup_vector_irq(int cpu) |
439 | { | |
7f3262ed | 440 | struct apic_chip_data *data; |
a782a7e4 TG |
441 | struct irq_desc *desc; |
442 | int irq, vector; | |
74afab7a | 443 | |
74afab7a | 444 | /* Mark the inuse vectors */ |
a782a7e4 TG |
445 | for_each_irq_desc(irq, desc) { |
446 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
74afab7a | 447 | |
a782a7e4 TG |
448 | data = apic_chip_data(idata); |
449 | if (!data || !cpumask_test_cpu(cpu, data->domain)) | |
74afab7a | 450 | continue; |
7f3262ed | 451 | vector = data->cfg.vector; |
a782a7e4 | 452 | per_cpu(vector_irq, cpu)[vector] = desc; |
74afab7a JL |
453 | } |
454 | /* Mark the free vectors */ | |
455 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
a782a7e4 TG |
456 | desc = per_cpu(vector_irq, cpu)[vector]; |
457 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
458 | continue; |
459 | ||
a782a7e4 | 460 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 461 | if (!cpumask_test_cpu(cpu, data->domain)) |
7276c6a2 | 462 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 463 | } |
74afab7a JL |
464 | } |
465 | ||
466 | /* | |
5a3f75e3 | 467 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
468 | */ |
469 | void setup_vector_irq(int cpu) | |
470 | { | |
471 | int irq; | |
472 | ||
5a3f75e3 | 473 | lockdep_assert_held(&vector_lock); |
74afab7a JL |
474 | /* |
475 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
476 | * boot cpu. But there are certain platforms where PIC interrupts are | |
477 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
478 | * legacy PIC, for the new cpu that is coming online, setup the static | |
479 | * legacy vector to irq mapping: | |
480 | */ | |
481 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
a782a7e4 | 482 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); |
74afab7a JL |
483 | |
484 | __setup_vector_irq(cpu); | |
485 | } | |
486 | ||
7f3262ed | 487 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 488 | { |
7f3262ed | 489 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
490 | unsigned long flags; |
491 | int cpu; | |
492 | ||
493 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
494 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
495 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
496 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
497 | ||
498 | return 1; | |
499 | } | |
500 | ||
501 | void apic_ack_edge(struct irq_data *data) | |
502 | { | |
a9786091 | 503 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
504 | irq_move_irq(data); |
505 | ack_APIC_irq(); | |
506 | } | |
507 | ||
68f9f440 JL |
508 | static int apic_set_affinity(struct irq_data *irq_data, |
509 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 510 | { |
7f3262ed | 511 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
512 | int err, irq = irq_data->irq; |
513 | ||
514 | if (!config_enabled(CONFIG_SMP)) | |
515 | return -EPERM; | |
516 | ||
517 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
518 | return -EINVAL; | |
519 | ||
7f3262ed | 520 | err = assign_irq_vector(irq, data, dest); |
3716fd27 | 521 | return err ? err : IRQ_SET_MASK_OK; |
b5dc8e6c JL |
522 | } |
523 | ||
524 | static struct irq_chip lapic_controller = { | |
525 | .irq_ack = apic_ack_edge, | |
68f9f440 | 526 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
527 | .irq_retrigger = apic_retrigger_irq, |
528 | }; | |
529 | ||
74afab7a | 530 | #ifdef CONFIG_SMP |
7f3262ed | 531 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a | 532 | { |
c1684f50 | 533 | raw_spin_lock(&vector_lock); |
5da0c121 | 534 | cpumask_and(data->old_domain, data->old_domain, cpu_online_mask); |
c1684f50 | 535 | data->move_in_progress = 0; |
5da0c121 TG |
536 | if (!cpumask_empty(data->old_domain)) |
537 | apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR); | |
c1684f50 | 538 | raw_spin_unlock(&vector_lock); |
74afab7a JL |
539 | } |
540 | ||
c6c2002b JL |
541 | void send_cleanup_vector(struct irq_cfg *cfg) |
542 | { | |
7f3262ed JL |
543 | struct apic_chip_data *data; |
544 | ||
545 | data = container_of(cfg, struct apic_chip_data, cfg); | |
546 | if (data->move_in_progress) | |
547 | __send_cleanup_vector(data); | |
c6c2002b JL |
548 | } |
549 | ||
74afab7a JL |
550 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
551 | { | |
552 | unsigned vector, me; | |
553 | ||
6af7faf6 | 554 | entering_ack_irq(); |
74afab7a | 555 | |
df54c493 TG |
556 | /* Prevent vectors vanishing under us */ |
557 | raw_spin_lock(&vector_lock); | |
558 | ||
74afab7a JL |
559 | me = smp_processor_id(); |
560 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
7f3262ed | 561 | struct apic_chip_data *data; |
a782a7e4 TG |
562 | struct irq_desc *desc; |
563 | unsigned int irr; | |
74afab7a | 564 | |
df54c493 | 565 | retry: |
a782a7e4 TG |
566 | desc = __this_cpu_read(vector_irq[vector]); |
567 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
568 | continue; |
569 | ||
df54c493 TG |
570 | if (!raw_spin_trylock(&desc->lock)) { |
571 | raw_spin_unlock(&vector_lock); | |
572 | cpu_relax(); | |
573 | raw_spin_lock(&vector_lock); | |
574 | goto retry; | |
575 | } | |
74afab7a | 576 | |
a782a7e4 | 577 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 578 | if (!data) |
df54c493 | 579 | goto unlock; |
74afab7a JL |
580 | |
581 | /* | |
582 | * Check if the irq migration is in progress. If so, we | |
583 | * haven't received the cleanup request yet for this irq. | |
584 | */ | |
7f3262ed | 585 | if (data->move_in_progress) |
74afab7a JL |
586 | goto unlock; |
587 | ||
7f3262ed JL |
588 | if (vector == data->cfg.vector && |
589 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
590 | goto unlock; |
591 | ||
592 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
593 | /* | |
594 | * Check if the vector that needs to be cleanedup is | |
595 | * registered at the cpu's IRR. If so, then this is not | |
596 | * the best time to clean it up. Lets clean it up in the | |
597 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
598 | * to myself. | |
599 | */ | |
600 | if (irr & (1 << (vector % 32))) { | |
601 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
602 | goto unlock; | |
603 | } | |
7276c6a2 | 604 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
74afab7a JL |
605 | unlock: |
606 | raw_spin_unlock(&desc->lock); | |
607 | } | |
608 | ||
df54c493 TG |
609 | raw_spin_unlock(&vector_lock); |
610 | ||
6af7faf6 | 611 | exiting_irq(); |
74afab7a JL |
612 | } |
613 | ||
614 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
615 | { | |
616 | unsigned me; | |
7f3262ed | 617 | struct apic_chip_data *data; |
74afab7a | 618 | |
7f3262ed JL |
619 | data = container_of(cfg, struct apic_chip_data, cfg); |
620 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
621 | return; |
622 | ||
623 | me = smp_processor_id(); | |
7f3262ed JL |
624 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
625 | __send_cleanup_vector(data); | |
74afab7a JL |
626 | } |
627 | ||
628 | void irq_complete_move(struct irq_cfg *cfg) | |
629 | { | |
630 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
631 | } | |
632 | ||
90a2282e TG |
633 | /* |
634 | * Called with @desc->lock held and interrupts disabled. | |
635 | */ | |
636 | void irq_force_complete_move(struct irq_desc *desc) | |
74afab7a | 637 | { |
90a2282e TG |
638 | struct irq_data *irqdata = irq_desc_get_irq_data(desc); |
639 | struct apic_chip_data *data = apic_chip_data(irqdata); | |
640 | struct irq_cfg *cfg = data ? &data->cfg : NULL; | |
56d7d2f4 TG |
641 | |
642 | if (!cfg) | |
643 | return; | |
74afab7a | 644 | |
56d7d2f4 TG |
645 | __irq_complete_move(cfg, cfg->vector); |
646 | ||
647 | /* | |
648 | * Remove this cpu from the cleanup mask. The IPI might have been sent | |
649 | * just before the cpu was removed from the offline mask, but has not | |
650 | * been processed because the CPU has interrupts disabled and is on | |
651 | * the way out. | |
652 | */ | |
653 | raw_spin_lock(&vector_lock); | |
56d7d2f4 TG |
654 | cpumask_clear_cpu(smp_processor_id(), data->old_domain); |
655 | raw_spin_unlock(&vector_lock); | |
74afab7a | 656 | } |
74afab7a JL |
657 | #endif |
658 | ||
74afab7a JL |
659 | static void __init print_APIC_field(int base) |
660 | { | |
661 | int i; | |
662 | ||
663 | printk(KERN_DEBUG); | |
664 | ||
665 | for (i = 0; i < 8; i++) | |
666 | pr_cont("%08x", apic_read(base + i*0x10)); | |
667 | ||
668 | pr_cont("\n"); | |
669 | } | |
670 | ||
671 | static void __init print_local_APIC(void *dummy) | |
672 | { | |
673 | unsigned int i, v, ver, maxlvt; | |
674 | u64 icr; | |
675 | ||
849d3569 JL |
676 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
677 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 678 | v = apic_read(APIC_ID); |
849d3569 | 679 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 680 | v = apic_read(APIC_LVR); |
849d3569 | 681 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
682 | ver = GET_APIC_VERSION(v); |
683 | maxlvt = lapic_get_maxlvt(); | |
684 | ||
685 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 686 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
687 | |
688 | /* !82489DX */ | |
689 | if (APIC_INTEGRATED(ver)) { | |
690 | if (!APIC_XAPIC(ver)) { | |
691 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
692 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
693 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
694 | } |
695 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 696 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
697 | } |
698 | ||
699 | /* | |
700 | * Remote read supported only in the 82489DX and local APIC for | |
701 | * Pentium processors. | |
702 | */ | |
703 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
704 | v = apic_read(APIC_RRR); | |
849d3569 | 705 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
706 | } |
707 | ||
708 | v = apic_read(APIC_LDR); | |
849d3569 | 709 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
710 | if (!x2apic_enabled()) { |
711 | v = apic_read(APIC_DFR); | |
849d3569 | 712 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
713 | } |
714 | v = apic_read(APIC_SPIV); | |
849d3569 | 715 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 716 | |
849d3569 | 717 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 718 | print_APIC_field(APIC_ISR); |
849d3569 | 719 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 720 | print_APIC_field(APIC_TMR); |
849d3569 | 721 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
722 | print_APIC_field(APIC_IRR); |
723 | ||
724 | /* !82489DX */ | |
725 | if (APIC_INTEGRATED(ver)) { | |
726 | /* Due to the Pentium erratum 3AP. */ | |
727 | if (maxlvt > 3) | |
728 | apic_write(APIC_ESR, 0); | |
729 | ||
730 | v = apic_read(APIC_ESR); | |
849d3569 | 731 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
732 | } |
733 | ||
734 | icr = apic_icr_read(); | |
849d3569 JL |
735 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
736 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
737 | |
738 | v = apic_read(APIC_LVTT); | |
849d3569 | 739 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
740 | |
741 | if (maxlvt > 3) { | |
742 | /* PC is LVT#4. */ | |
743 | v = apic_read(APIC_LVTPC); | |
849d3569 | 744 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
745 | } |
746 | v = apic_read(APIC_LVT0); | |
849d3569 | 747 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 748 | v = apic_read(APIC_LVT1); |
849d3569 | 749 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
750 | |
751 | if (maxlvt > 2) { | |
752 | /* ERR is LVT#3. */ | |
753 | v = apic_read(APIC_LVTERR); | |
849d3569 | 754 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
755 | } |
756 | ||
757 | v = apic_read(APIC_TMICT); | |
849d3569 | 758 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 759 | v = apic_read(APIC_TMCCT); |
849d3569 | 760 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 761 | v = apic_read(APIC_TDCR); |
849d3569 | 762 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
763 | |
764 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
765 | v = apic_read(APIC_EFEAT); | |
766 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 767 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 768 | v = apic_read(APIC_ECTRL); |
849d3569 | 769 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
770 | for (i = 0; i < maxlvt; i++) { |
771 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 772 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
773 | } |
774 | } | |
775 | pr_cont("\n"); | |
776 | } | |
777 | ||
778 | static void __init print_local_APICs(int maxcpu) | |
779 | { | |
780 | int cpu; | |
781 | ||
782 | if (!maxcpu) | |
783 | return; | |
784 | ||
785 | preempt_disable(); | |
786 | for_each_online_cpu(cpu) { | |
787 | if (cpu >= maxcpu) | |
788 | break; | |
789 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
790 | } | |
791 | preempt_enable(); | |
792 | } | |
793 | ||
794 | static void __init print_PIC(void) | |
795 | { | |
796 | unsigned int v; | |
797 | unsigned long flags; | |
798 | ||
799 | if (!nr_legacy_irqs()) | |
800 | return; | |
801 | ||
849d3569 | 802 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
803 | |
804 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
805 | ||
806 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 807 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
808 | |
809 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 810 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
811 | |
812 | outb(0x0b, 0xa0); | |
813 | outb(0x0b, 0x20); | |
814 | v = inb(0xa0) << 8 | inb(0x20); | |
815 | outb(0x0a, 0xa0); | |
816 | outb(0x0a, 0x20); | |
817 | ||
818 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
819 | ||
849d3569 | 820 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
821 | |
822 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 823 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
824 | } |
825 | ||
826 | static int show_lapic __initdata = 1; | |
827 | static __init int setup_show_lapic(char *arg) | |
828 | { | |
829 | int num = -1; | |
830 | ||
831 | if (strcmp(arg, "all") == 0) { | |
832 | show_lapic = CONFIG_NR_CPUS; | |
833 | } else { | |
834 | get_option(&arg, &num); | |
835 | if (num >= 0) | |
836 | show_lapic = num; | |
837 | } | |
838 | ||
839 | return 1; | |
840 | } | |
841 | __setup("show_lapic=", setup_show_lapic); | |
842 | ||
843 | static int __init print_ICs(void) | |
844 | { | |
845 | if (apic_verbosity == APIC_QUIET) | |
846 | return 0; | |
847 | ||
848 | print_PIC(); | |
849 | ||
850 | /* don't print out if apic is not there */ | |
851 | if (!cpu_has_apic && !apic_from_smp_config()) | |
852 | return 0; | |
853 | ||
854 | print_local_APICs(show_lapic); | |
855 | print_IO_APICs(); | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | late_initcall(print_ICs); |