Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/compiler.h> | |
14 | #include <linux/irqdomain.h> | |
15 | #include <linux/slab.h> | |
16 | #include <asm/hw_irq.h> | |
17 | #include <asm/apic.h> | |
18 | #include <asm/i8259.h> | |
19 | #include <asm/desc.h> | |
20 | #include <asm/irq_remapping.h> | |
21 | ||
22 | static DEFINE_RAW_SPINLOCK(vector_lock); | |
23 | ||
24 | void lock_vector_lock(void) | |
25 | { | |
26 | /* Used to the online set of cpus does not change | |
27 | * during assign_irq_vector. | |
28 | */ | |
29 | raw_spin_lock(&vector_lock); | |
30 | } | |
31 | ||
32 | void unlock_vector_lock(void) | |
33 | { | |
34 | raw_spin_unlock(&vector_lock); | |
35 | } | |
36 | ||
37 | struct irq_cfg *irq_cfg(unsigned int irq) | |
38 | { | |
39 | return irq_get_chip_data(irq); | |
40 | } | |
41 | ||
42 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) | |
43 | { | |
44 | return irq_data->chip_data; | |
45 | } | |
46 | ||
47 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) | |
48 | { | |
49 | struct irq_cfg *cfg; | |
50 | ||
51 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); | |
52 | if (!cfg) | |
53 | return NULL; | |
54 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) | |
55 | goto out_cfg; | |
56 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) | |
57 | goto out_domain; | |
58 | #ifdef CONFIG_X86_IO_APIC | |
59 | INIT_LIST_HEAD(&cfg->irq_2_pin); | |
60 | #endif | |
61 | return cfg; | |
62 | out_domain: | |
63 | free_cpumask_var(cfg->domain); | |
64 | out_cfg: | |
65 | kfree(cfg); | |
66 | return NULL; | |
67 | } | |
68 | ||
69 | struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) | |
70 | { | |
71 | int res = irq_alloc_desc_at(at, node); | |
72 | struct irq_cfg *cfg; | |
73 | ||
74 | if (res < 0) { | |
75 | if (res != -EEXIST) | |
76 | return NULL; | |
77 | cfg = irq_cfg(at); | |
78 | if (cfg) | |
79 | return cfg; | |
80 | } | |
81 | ||
82 | cfg = alloc_irq_cfg(at, node); | |
83 | if (cfg) | |
84 | irq_set_chip_data(at, cfg); | |
85 | else | |
86 | irq_free_desc(at); | |
87 | return cfg; | |
88 | } | |
89 | ||
90 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) | |
91 | { | |
92 | if (!cfg) | |
93 | return; | |
94 | irq_set_chip_data(at, NULL); | |
95 | free_cpumask_var(cfg->domain); | |
96 | free_cpumask_var(cfg->old_domain); | |
97 | kfree(cfg); | |
98 | } | |
99 | ||
100 | static int | |
101 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
102 | { | |
103 | /* | |
104 | * NOTE! The local APIC isn't very good at handling | |
105 | * multiple interrupts at the same interrupt level. | |
106 | * As the interrupt level is determined by taking the | |
107 | * vector number and shifting that right by 4, we | |
108 | * want to spread these out a bit so that they don't | |
109 | * all fall in the same interrupt level. | |
110 | * | |
111 | * Also, we've got to be careful not to trash gate | |
112 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
113 | */ | |
114 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
115 | static int current_offset = VECTOR_OFFSET_START % 16; | |
116 | int cpu, err; | |
117 | cpumask_var_t tmp_mask; | |
118 | ||
119 | if (cfg->move_in_progress) | |
120 | return -EBUSY; | |
121 | ||
122 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) | |
123 | return -ENOMEM; | |
124 | ||
125 | /* Only try and allocate irqs on cpus that are present */ | |
126 | err = -ENOSPC; | |
127 | cpumask_clear(cfg->old_domain); | |
128 | cpu = cpumask_first_and(mask, cpu_online_mask); | |
129 | while (cpu < nr_cpu_ids) { | |
130 | int new_cpu, vector, offset; | |
131 | ||
132 | apic->vector_allocation_domain(cpu, tmp_mask, mask); | |
133 | ||
134 | if (cpumask_subset(tmp_mask, cfg->domain)) { | |
135 | err = 0; | |
136 | if (cpumask_equal(tmp_mask, cfg->domain)) | |
137 | break; | |
138 | /* | |
139 | * New cpumask using the vector is a proper subset of | |
140 | * the current in use mask. So cleanup the vector | |
141 | * allocation for the members that are not used anymore. | |
142 | */ | |
143 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | |
144 | cfg->move_in_progress = | |
145 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
146 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); | |
147 | break; | |
148 | } | |
149 | ||
150 | vector = current_vector; | |
151 | offset = current_offset; | |
152 | next: | |
153 | vector += 16; | |
154 | if (vector >= first_system_vector) { | |
155 | offset = (offset + 1) % 16; | |
156 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
157 | } | |
158 | ||
159 | if (unlikely(current_vector == vector)) { | |
160 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); | |
161 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | |
162 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | |
163 | continue; | |
164 | } | |
165 | ||
166 | if (test_bit(vector, used_vectors)) | |
167 | goto next; | |
168 | ||
169 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { | |
170 | if (per_cpu(vector_irq, new_cpu)[vector] > | |
171 | VECTOR_UNDEFINED) | |
172 | goto next; | |
173 | } | |
174 | /* Found one! */ | |
175 | current_vector = vector; | |
176 | current_offset = offset; | |
177 | if (cfg->vector) { | |
178 | cpumask_copy(cfg->old_domain, cfg->domain); | |
179 | cfg->move_in_progress = | |
180 | cpumask_intersects(cfg->old_domain, cpu_online_mask); | |
181 | } | |
182 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) | |
183 | per_cpu(vector_irq, new_cpu)[vector] = irq; | |
184 | cfg->vector = vector; | |
185 | cpumask_copy(cfg->domain, tmp_mask); | |
186 | err = 0; | |
187 | break; | |
188 | } | |
189 | free_cpumask_var(tmp_mask); | |
190 | ||
5f0052f9 JL |
191 | if (!err) { |
192 | /* cache destination APIC IDs into cfg->dest_apicid */ | |
193 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, | |
194 | &cfg->dest_apicid); | |
195 | } | |
196 | ||
74afab7a JL |
197 | return err; |
198 | } | |
199 | ||
200 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |
201 | { | |
202 | int err; | |
203 | unsigned long flags; | |
204 | ||
205 | raw_spin_lock_irqsave(&vector_lock, flags); | |
206 | err = __assign_irq_vector(irq, cfg, mask); | |
207 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
208 | return err; | |
209 | } | |
210 | ||
211 | void clear_irq_vector(int irq, struct irq_cfg *cfg) | |
212 | { | |
213 | int cpu, vector; | |
214 | unsigned long flags; | |
215 | ||
216 | raw_spin_lock_irqsave(&vector_lock, flags); | |
217 | BUG_ON(!cfg->vector); | |
218 | ||
219 | vector = cfg->vector; | |
220 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) | |
221 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; | |
222 | ||
223 | cfg->vector = 0; | |
224 | cpumask_clear(cfg->domain); | |
225 | ||
226 | if (likely(!cfg->move_in_progress)) { | |
227 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
228 | return; | |
229 | } | |
230 | ||
231 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { | |
232 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; | |
233 | vector++) { | |
234 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
235 | continue; | |
236 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; | |
237 | break; | |
238 | } | |
239 | } | |
240 | cfg->move_in_progress = 0; | |
241 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
242 | } | |
243 | ||
11d686e9 JL |
244 | int __init arch_probe_nr_irqs(void) |
245 | { | |
246 | int nr; | |
247 | ||
248 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
249 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
250 | ||
251 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
252 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
253 | /* | |
254 | * for MSI and HT dyn irq | |
255 | */ | |
256 | if (gsi_top <= NR_IRQS_LEGACY) | |
257 | nr += 8 * nr_cpu_ids; | |
258 | else | |
259 | nr += gsi_top * 16; | |
260 | #endif | |
261 | if (nr < nr_irqs) | |
262 | nr_irqs = nr; | |
263 | ||
264 | return nr_legacy_irqs(); | |
265 | } | |
266 | ||
267 | int __init arch_early_irq_init(void) | |
268 | { | |
269 | return arch_early_ioapic_init(); | |
270 | } | |
271 | ||
74afab7a JL |
272 | static void __setup_vector_irq(int cpu) |
273 | { | |
274 | /* Initialize vector_irq on a new cpu */ | |
275 | int irq, vector; | |
276 | struct irq_cfg *cfg; | |
277 | ||
278 | /* | |
279 | * vector_lock will make sure that we don't run into irq vector | |
280 | * assignments that might be happening on another cpu in parallel, | |
281 | * while we setup our initial vector to irq mappings. | |
282 | */ | |
283 | raw_spin_lock(&vector_lock); | |
284 | /* Mark the inuse vectors */ | |
285 | for_each_active_irq(irq) { | |
286 | cfg = irq_cfg(irq); | |
287 | if (!cfg) | |
288 | continue; | |
289 | ||
290 | if (!cpumask_test_cpu(cpu, cfg->domain)) | |
291 | continue; | |
292 | vector = cfg->vector; | |
293 | per_cpu(vector_irq, cpu)[vector] = irq; | |
294 | } | |
295 | /* Mark the free vectors */ | |
296 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
297 | irq = per_cpu(vector_irq, cpu)[vector]; | |
298 | if (irq <= VECTOR_UNDEFINED) | |
299 | continue; | |
300 | ||
301 | cfg = irq_cfg(irq); | |
302 | if (!cpumask_test_cpu(cpu, cfg->domain)) | |
303 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; | |
304 | } | |
305 | raw_spin_unlock(&vector_lock); | |
306 | } | |
307 | ||
308 | /* | |
309 | * Setup the vector to irq mappings. | |
310 | */ | |
311 | void setup_vector_irq(int cpu) | |
312 | { | |
313 | int irq; | |
314 | ||
315 | /* | |
316 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
317 | * boot cpu. But there are certain platforms where PIC interrupts are | |
318 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
319 | * legacy PIC, for the new cpu that is coming online, setup the static | |
320 | * legacy vector to irq mapping: | |
321 | */ | |
322 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
323 | per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq; | |
324 | ||
325 | __setup_vector_irq(cpu); | |
326 | } | |
327 | ||
328 | int apic_retrigger_irq(struct irq_data *data) | |
329 | { | |
a9786091 | 330 | struct irq_cfg *cfg = irqd_cfg(data); |
74afab7a JL |
331 | unsigned long flags; |
332 | int cpu; | |
333 | ||
334 | raw_spin_lock_irqsave(&vector_lock, flags); | |
335 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); | |
336 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); | |
337 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
338 | ||
339 | return 1; | |
340 | } | |
341 | ||
342 | void apic_ack_edge(struct irq_data *data) | |
343 | { | |
a9786091 | 344 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
345 | irq_move_irq(data); |
346 | ack_APIC_irq(); | |
347 | } | |
348 | ||
349 | /* | |
350 | * Either sets data->affinity to a valid value, and returns | |
351 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | |
352 | * leaves data->affinity untouched. | |
353 | */ | |
354 | int apic_set_affinity(struct irq_data *data, const struct cpumask *mask, | |
355 | unsigned int *dest_id) | |
356 | { | |
a9786091 | 357 | struct irq_cfg *cfg = irqd_cfg(data); |
74afab7a JL |
358 | unsigned int irq = data->irq; |
359 | int err; | |
360 | ||
361 | if (!config_enabled(CONFIG_SMP)) | |
362 | return -EPERM; | |
363 | ||
364 | if (!cpumask_intersects(mask, cpu_online_mask)) | |
365 | return -EINVAL; | |
366 | ||
367 | err = assign_irq_vector(irq, cfg, mask); | |
368 | if (err) | |
369 | return err; | |
370 | ||
371 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | |
372 | if (err) { | |
373 | if (assign_irq_vector(irq, cfg, data->affinity)) | |
374 | pr_err("Failed to recover vector for irq %d\n", irq); | |
375 | return err; | |
376 | } | |
377 | ||
378 | cpumask_copy(data->affinity, mask); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | #ifdef CONFIG_SMP | |
384 | void send_cleanup_vector(struct irq_cfg *cfg) | |
385 | { | |
386 | cpumask_var_t cleanup_mask; | |
387 | ||
388 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
389 | unsigned int i; | |
390 | ||
391 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) | |
392 | apic->send_IPI_mask(cpumask_of(i), | |
393 | IRQ_MOVE_CLEANUP_VECTOR); | |
394 | } else { | |
395 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); | |
396 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); | |
397 | free_cpumask_var(cleanup_mask); | |
398 | } | |
399 | cfg->move_in_progress = 0; | |
400 | } | |
401 | ||
402 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) | |
403 | { | |
404 | unsigned vector, me; | |
405 | ||
406 | ack_APIC_irq(); | |
407 | irq_enter(); | |
408 | exit_idle(); | |
409 | ||
410 | me = smp_processor_id(); | |
411 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
412 | int irq; | |
413 | unsigned int irr; | |
414 | struct irq_desc *desc; | |
415 | struct irq_cfg *cfg; | |
416 | ||
417 | irq = __this_cpu_read(vector_irq[vector]); | |
418 | ||
419 | if (irq <= VECTOR_UNDEFINED) | |
420 | continue; | |
421 | ||
422 | desc = irq_to_desc(irq); | |
423 | if (!desc) | |
424 | continue; | |
425 | ||
426 | cfg = irq_cfg(irq); | |
427 | if (!cfg) | |
428 | continue; | |
429 | ||
430 | raw_spin_lock(&desc->lock); | |
431 | ||
432 | /* | |
433 | * Check if the irq migration is in progress. If so, we | |
434 | * haven't received the cleanup request yet for this irq. | |
435 | */ | |
436 | if (cfg->move_in_progress) | |
437 | goto unlock; | |
438 | ||
439 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) | |
440 | goto unlock; | |
441 | ||
442 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
443 | /* | |
444 | * Check if the vector that needs to be cleanedup is | |
445 | * registered at the cpu's IRR. If so, then this is not | |
446 | * the best time to clean it up. Lets clean it up in the | |
447 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
448 | * to myself. | |
449 | */ | |
450 | if (irr & (1 << (vector % 32))) { | |
451 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
452 | goto unlock; | |
453 | } | |
454 | __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); | |
455 | unlock: | |
456 | raw_spin_unlock(&desc->lock); | |
457 | } | |
458 | ||
459 | irq_exit(); | |
460 | } | |
461 | ||
462 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
463 | { | |
464 | unsigned me; | |
465 | ||
466 | if (likely(!cfg->move_in_progress)) | |
467 | return; | |
468 | ||
469 | me = smp_processor_id(); | |
470 | ||
471 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) | |
472 | send_cleanup_vector(cfg); | |
473 | } | |
474 | ||
475 | void irq_complete_move(struct irq_cfg *cfg) | |
476 | { | |
477 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
478 | } | |
479 | ||
480 | void irq_force_complete_move(int irq) | |
481 | { | |
482 | struct irq_cfg *cfg = irq_cfg(irq); | |
483 | ||
484 | if (!cfg) | |
485 | return; | |
486 | ||
487 | __irq_complete_move(cfg, cfg->vector); | |
488 | } | |
74afab7a JL |
489 | #endif |
490 | ||
491 | /* | |
492 | * Dynamic irq allocate and deallocation. Should be replaced by irq domains! | |
493 | */ | |
494 | int arch_setup_hwirq(unsigned int irq, int node) | |
495 | { | |
496 | struct irq_cfg *cfg; | |
497 | unsigned long flags; | |
498 | int ret; | |
499 | ||
500 | cfg = alloc_irq_cfg(irq, node); | |
501 | if (!cfg) | |
502 | return -ENOMEM; | |
503 | ||
504 | raw_spin_lock_irqsave(&vector_lock, flags); | |
505 | ret = __assign_irq_vector(irq, cfg, apic->target_cpus()); | |
506 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
507 | ||
508 | if (!ret) | |
509 | irq_set_chip_data(irq, cfg); | |
510 | else | |
511 | free_irq_cfg(irq, cfg); | |
512 | return ret; | |
513 | } | |
514 | ||
515 | void arch_teardown_hwirq(unsigned int irq) | |
516 | { | |
517 | struct irq_cfg *cfg = irq_cfg(irq); | |
518 | ||
519 | free_remapped_irq(irq); | |
520 | clear_irq_vector(irq, cfg); | |
521 | free_irq_cfg(irq, cfg); | |
522 | } | |
523 | ||
524 | static void __init print_APIC_field(int base) | |
525 | { | |
526 | int i; | |
527 | ||
528 | printk(KERN_DEBUG); | |
529 | ||
530 | for (i = 0; i < 8; i++) | |
531 | pr_cont("%08x", apic_read(base + i*0x10)); | |
532 | ||
533 | pr_cont("\n"); | |
534 | } | |
535 | ||
536 | static void __init print_local_APIC(void *dummy) | |
537 | { | |
538 | unsigned int i, v, ver, maxlvt; | |
539 | u64 icr; | |
540 | ||
849d3569 JL |
541 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
542 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 543 | v = apic_read(APIC_ID); |
849d3569 | 544 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 545 | v = apic_read(APIC_LVR); |
849d3569 | 546 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
547 | ver = GET_APIC_VERSION(v); |
548 | maxlvt = lapic_get_maxlvt(); | |
549 | ||
550 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 551 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
552 | |
553 | /* !82489DX */ | |
554 | if (APIC_INTEGRATED(ver)) { | |
555 | if (!APIC_XAPIC(ver)) { | |
556 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
557 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
558 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
559 | } |
560 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 561 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
562 | } |
563 | ||
564 | /* | |
565 | * Remote read supported only in the 82489DX and local APIC for | |
566 | * Pentium processors. | |
567 | */ | |
568 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
569 | v = apic_read(APIC_RRR); | |
849d3569 | 570 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
571 | } |
572 | ||
573 | v = apic_read(APIC_LDR); | |
849d3569 | 574 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
575 | if (!x2apic_enabled()) { |
576 | v = apic_read(APIC_DFR); | |
849d3569 | 577 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
578 | } |
579 | v = apic_read(APIC_SPIV); | |
849d3569 | 580 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 581 | |
849d3569 | 582 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 583 | print_APIC_field(APIC_ISR); |
849d3569 | 584 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 585 | print_APIC_field(APIC_TMR); |
849d3569 | 586 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
587 | print_APIC_field(APIC_IRR); |
588 | ||
589 | /* !82489DX */ | |
590 | if (APIC_INTEGRATED(ver)) { | |
591 | /* Due to the Pentium erratum 3AP. */ | |
592 | if (maxlvt > 3) | |
593 | apic_write(APIC_ESR, 0); | |
594 | ||
595 | v = apic_read(APIC_ESR); | |
849d3569 | 596 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
597 | } |
598 | ||
599 | icr = apic_icr_read(); | |
849d3569 JL |
600 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
601 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
602 | |
603 | v = apic_read(APIC_LVTT); | |
849d3569 | 604 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
605 | |
606 | if (maxlvt > 3) { | |
607 | /* PC is LVT#4. */ | |
608 | v = apic_read(APIC_LVTPC); | |
849d3569 | 609 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
610 | } |
611 | v = apic_read(APIC_LVT0); | |
849d3569 | 612 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 613 | v = apic_read(APIC_LVT1); |
849d3569 | 614 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
615 | |
616 | if (maxlvt > 2) { | |
617 | /* ERR is LVT#3. */ | |
618 | v = apic_read(APIC_LVTERR); | |
849d3569 | 619 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
620 | } |
621 | ||
622 | v = apic_read(APIC_TMICT); | |
849d3569 | 623 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 624 | v = apic_read(APIC_TMCCT); |
849d3569 | 625 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 626 | v = apic_read(APIC_TDCR); |
849d3569 | 627 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
628 | |
629 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
630 | v = apic_read(APIC_EFEAT); | |
631 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 632 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 633 | v = apic_read(APIC_ECTRL); |
849d3569 | 634 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
635 | for (i = 0; i < maxlvt; i++) { |
636 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 637 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
638 | } |
639 | } | |
640 | pr_cont("\n"); | |
641 | } | |
642 | ||
643 | static void __init print_local_APICs(int maxcpu) | |
644 | { | |
645 | int cpu; | |
646 | ||
647 | if (!maxcpu) | |
648 | return; | |
649 | ||
650 | preempt_disable(); | |
651 | for_each_online_cpu(cpu) { | |
652 | if (cpu >= maxcpu) | |
653 | break; | |
654 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
655 | } | |
656 | preempt_enable(); | |
657 | } | |
658 | ||
659 | static void __init print_PIC(void) | |
660 | { | |
661 | unsigned int v; | |
662 | unsigned long flags; | |
663 | ||
664 | if (!nr_legacy_irqs()) | |
665 | return; | |
666 | ||
849d3569 | 667 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
668 | |
669 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
670 | ||
671 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 672 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
673 | |
674 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 675 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
676 | |
677 | outb(0x0b, 0xa0); | |
678 | outb(0x0b, 0x20); | |
679 | v = inb(0xa0) << 8 | inb(0x20); | |
680 | outb(0x0a, 0xa0); | |
681 | outb(0x0a, 0x20); | |
682 | ||
683 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
684 | ||
849d3569 | 685 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
686 | |
687 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 688 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
689 | } |
690 | ||
691 | static int show_lapic __initdata = 1; | |
692 | static __init int setup_show_lapic(char *arg) | |
693 | { | |
694 | int num = -1; | |
695 | ||
696 | if (strcmp(arg, "all") == 0) { | |
697 | show_lapic = CONFIG_NR_CPUS; | |
698 | } else { | |
699 | get_option(&arg, &num); | |
700 | if (num >= 0) | |
701 | show_lapic = num; | |
702 | } | |
703 | ||
704 | return 1; | |
705 | } | |
706 | __setup("show_lapic=", setup_show_lapic); | |
707 | ||
708 | static int __init print_ICs(void) | |
709 | { | |
710 | if (apic_verbosity == APIC_QUIET) | |
711 | return 0; | |
712 | ||
713 | print_PIC(); | |
714 | ||
715 | /* don't print out if apic is not there */ | |
716 | if (!cpu_has_apic && !apic_from_smp_config()) | |
717 | return 0; | |
718 | ||
719 | print_local_APICs(show_lapic); | |
720 | print_IO_APICs(); | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | late_initcall(print_ICs); |