Commit | Line | Data |
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74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
74afab7a | 32 | static DEFINE_RAW_SPINLOCK(vector_lock); |
f7fa7aee | 33 | static cpumask_var_t vector_cpumask; |
b5dc8e6c | 34 | static struct irq_chip lapic_controller; |
13315320 | 35 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 36 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 37 | #endif |
74afab7a JL |
38 | |
39 | void lock_vector_lock(void) | |
40 | { | |
41 | /* Used to the online set of cpus does not change | |
42 | * during assign_irq_vector. | |
43 | */ | |
44 | raw_spin_lock(&vector_lock); | |
45 | } | |
46 | ||
47 | void unlock_vector_lock(void) | |
48 | { | |
49 | raw_spin_unlock(&vector_lock); | |
50 | } | |
51 | ||
7f3262ed | 52 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 53 | { |
b5dc8e6c JL |
54 | if (!irq_data) |
55 | return NULL; | |
56 | ||
57 | while (irq_data->parent_data) | |
58 | irq_data = irq_data->parent_data; | |
59 | ||
74afab7a JL |
60 | return irq_data->chip_data; |
61 | } | |
62 | ||
7f3262ed JL |
63 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
64 | { | |
65 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
66 | ||
67 | return data ? &data->cfg : NULL; | |
68 | } | |
69 | ||
70 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 71 | { |
7f3262ed JL |
72 | return irqd_cfg(irq_get_irq_data(irq)); |
73 | } | |
74afab7a | 74 | |
7f3262ed JL |
75 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
76 | { | |
77 | struct apic_chip_data *data; | |
78 | ||
79 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
80 | if (!data) | |
74afab7a | 81 | return NULL; |
7f3262ed JL |
82 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
83 | goto out_data; | |
84 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 85 | goto out_domain; |
7f3262ed | 86 | return data; |
74afab7a | 87 | out_domain: |
7f3262ed JL |
88 | free_cpumask_var(data->domain); |
89 | out_data: | |
90 | kfree(data); | |
74afab7a JL |
91 | return NULL; |
92 | } | |
93 | ||
7f3262ed | 94 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 95 | { |
7f3262ed JL |
96 | if (data) { |
97 | free_cpumask_var(data->domain); | |
98 | free_cpumask_var(data->old_domain); | |
99 | kfree(data); | |
b5dc8e6c | 100 | } |
74afab7a JL |
101 | } |
102 | ||
7f3262ed JL |
103 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
104 | const struct cpumask *mask) | |
74afab7a JL |
105 | { |
106 | /* | |
107 | * NOTE! The local APIC isn't very good at handling | |
108 | * multiple interrupts at the same interrupt level. | |
109 | * As the interrupt level is determined by taking the | |
110 | * vector number and shifting that right by 4, we | |
111 | * want to spread these out a bit so that they don't | |
112 | * all fall in the same interrupt level. | |
113 | * | |
114 | * Also, we've got to be careful not to trash gate | |
115 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
116 | */ | |
117 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
118 | static int current_offset = VECTOR_OFFSET_START % 16; | |
119 | int cpu, err; | |
74afab7a | 120 | |
7f3262ed | 121 | if (d->move_in_progress) |
74afab7a JL |
122 | return -EBUSY; |
123 | ||
74afab7a JL |
124 | /* Only try and allocate irqs on cpus that are present */ |
125 | err = -ENOSPC; | |
7f3262ed | 126 | cpumask_clear(d->old_domain); |
74afab7a JL |
127 | cpu = cpumask_first_and(mask, cpu_online_mask); |
128 | while (cpu < nr_cpu_ids) { | |
129 | int new_cpu, vector, offset; | |
130 | ||
f7fa7aee | 131 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 132 | |
f7fa7aee | 133 | if (cpumask_subset(vector_cpumask, d->domain)) { |
74afab7a | 134 | err = 0; |
f7fa7aee | 135 | if (cpumask_equal(vector_cpumask, d->domain)) |
74afab7a JL |
136 | break; |
137 | /* | |
138 | * New cpumask using the vector is a proper subset of | |
139 | * the current in use mask. So cleanup the vector | |
140 | * allocation for the members that are not used anymore. | |
141 | */ | |
f7fa7aee JL |
142 | cpumask_andnot(d->old_domain, d->domain, |
143 | vector_cpumask); | |
7f3262ed JL |
144 | d->move_in_progress = |
145 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
f7fa7aee | 146 | cpumask_and(d->domain, d->domain, vector_cpumask); |
74afab7a JL |
147 | break; |
148 | } | |
149 | ||
150 | vector = current_vector; | |
151 | offset = current_offset; | |
152 | next: | |
153 | vector += 16; | |
154 | if (vector >= first_system_vector) { | |
155 | offset = (offset + 1) % 16; | |
156 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
157 | } | |
158 | ||
159 | if (unlikely(current_vector == vector)) { | |
f7fa7aee JL |
160 | cpumask_or(d->old_domain, d->old_domain, |
161 | vector_cpumask); | |
162 | cpumask_andnot(vector_cpumask, mask, d->old_domain); | |
163 | cpu = cpumask_first_and(vector_cpumask, | |
164 | cpu_online_mask); | |
74afab7a JL |
165 | continue; |
166 | } | |
167 | ||
168 | if (test_bit(vector, used_vectors)) | |
169 | goto next; | |
170 | ||
f7fa7aee | 171 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { |
74afab7a JL |
172 | if (per_cpu(vector_irq, new_cpu)[vector] > |
173 | VECTOR_UNDEFINED) | |
174 | goto next; | |
175 | } | |
176 | /* Found one! */ | |
177 | current_vector = vector; | |
178 | current_offset = offset; | |
7f3262ed JL |
179 | if (d->cfg.vector) { |
180 | cpumask_copy(d->old_domain, d->domain); | |
181 | d->move_in_progress = | |
182 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
74afab7a | 183 | } |
f7fa7aee | 184 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) |
74afab7a | 185 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
7f3262ed | 186 | d->cfg.vector = vector; |
f7fa7aee | 187 | cpumask_copy(d->domain, vector_cpumask); |
74afab7a JL |
188 | err = 0; |
189 | break; | |
190 | } | |
74afab7a | 191 | |
5f0052f9 JL |
192 | if (!err) { |
193 | /* cache destination APIC IDs into cfg->dest_apicid */ | |
7f3262ed JL |
194 | err = apic->cpu_mask_to_apicid_and(mask, d->domain, |
195 | &d->cfg.dest_apicid); | |
5f0052f9 JL |
196 | } |
197 | ||
74afab7a JL |
198 | return err; |
199 | } | |
200 | ||
7f3262ed | 201 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 202 | const struct cpumask *mask) |
74afab7a JL |
203 | { |
204 | int err; | |
205 | unsigned long flags; | |
206 | ||
207 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 208 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
209 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
210 | return err; | |
211 | } | |
212 | ||
7f3262ed | 213 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a JL |
214 | { |
215 | int cpu, vector; | |
216 | unsigned long flags; | |
217 | ||
218 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 219 | BUG_ON(!data->cfg.vector); |
74afab7a | 220 | |
7f3262ed JL |
221 | vector = data->cfg.vector; |
222 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
74afab7a JL |
223 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
224 | ||
7f3262ed JL |
225 | data->cfg.vector = 0; |
226 | cpumask_clear(data->domain); | |
74afab7a | 227 | |
7f3262ed | 228 | if (likely(!data->move_in_progress)) { |
74afab7a JL |
229 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
230 | return; | |
231 | } | |
232 | ||
7f3262ed | 233 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
234 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
235 | vector++) { | |
236 | if (per_cpu(vector_irq, cpu)[vector] != irq) | |
237 | continue; | |
238 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; | |
239 | break; | |
240 | } | |
241 | } | |
7f3262ed | 242 | data->move_in_progress = 0; |
74afab7a JL |
243 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
244 | } | |
245 | ||
b5dc8e6c JL |
246 | void init_irq_alloc_info(struct irq_alloc_info *info, |
247 | const struct cpumask *mask) | |
248 | { | |
249 | memset(info, 0, sizeof(*info)); | |
250 | info->mask = mask; | |
251 | } | |
252 | ||
253 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
254 | { | |
255 | if (src) | |
256 | *dst = *src; | |
257 | else | |
258 | memset(dst, 0, sizeof(*dst)); | |
259 | } | |
260 | ||
261 | static inline const struct cpumask * | |
262 | irq_alloc_info_get_mask(struct irq_alloc_info *info) | |
263 | { | |
264 | return (!info || !info->mask) ? apic->target_cpus() : info->mask; | |
265 | } | |
266 | ||
267 | static void x86_vector_free_irqs(struct irq_domain *domain, | |
268 | unsigned int virq, unsigned int nr_irqs) | |
269 | { | |
270 | struct irq_data *irq_data; | |
271 | int i; | |
272 | ||
273 | for (i = 0; i < nr_irqs; i++) { | |
274 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
275 | if (irq_data && irq_data->chip_data) { | |
b5dc8e6c | 276 | clear_irq_vector(virq + i, irq_data->chip_data); |
7f3262ed | 277 | free_apic_chip_data(irq_data->chip_data); |
13315320 JL |
278 | #ifdef CONFIG_X86_IO_APIC |
279 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 280 | legacy_irq_data[virq + i] = NULL; |
13315320 | 281 | #endif |
b5dc8e6c JL |
282 | irq_domain_reset_irq_data(irq_data); |
283 | } | |
284 | } | |
285 | } | |
286 | ||
287 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
288 | unsigned int nr_irqs, void *arg) | |
289 | { | |
290 | struct irq_alloc_info *info = arg; | |
7f3262ed | 291 | struct apic_chip_data *data; |
b5dc8e6c JL |
292 | const struct cpumask *mask; |
293 | struct irq_data *irq_data; | |
b5dc8e6c JL |
294 | int i, err; |
295 | ||
296 | if (disable_apic) | |
297 | return -ENXIO; | |
298 | ||
299 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
300 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
301 | return -ENOSYS; | |
302 | ||
303 | mask = irq_alloc_info_get_mask(info); | |
304 | for (i = 0; i < nr_irqs; i++) { | |
305 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
306 | BUG_ON(!irq_data); | |
13315320 | 307 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
308 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
309 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
310 | else |
311 | #endif | |
7f3262ed JL |
312 | data = alloc_apic_chip_data(irq_data->node); |
313 | if (!data) { | |
b5dc8e6c JL |
314 | err = -ENOMEM; |
315 | goto error; | |
316 | } | |
317 | ||
318 | irq_data->chip = &lapic_controller; | |
7f3262ed | 319 | irq_data->chip_data = data; |
b5dc8e6c | 320 | irq_data->hwirq = virq + i; |
7f3262ed | 321 | err = assign_irq_vector(virq, data, mask); |
b5dc8e6c JL |
322 | if (err) |
323 | goto error; | |
324 | } | |
325 | ||
326 | return 0; | |
327 | ||
328 | error: | |
329 | x86_vector_free_irqs(domain, virq, i + 1); | |
330 | return err; | |
331 | } | |
332 | ||
eb18cf55 TG |
333 | static const struct irq_domain_ops x86_vector_domain_ops = { |
334 | .alloc = x86_vector_alloc_irqs, | |
335 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
336 | }; |
337 | ||
11d686e9 JL |
338 | int __init arch_probe_nr_irqs(void) |
339 | { | |
340 | int nr; | |
341 | ||
342 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
343 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
344 | ||
345 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
346 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
347 | /* | |
348 | * for MSI and HT dyn irq | |
349 | */ | |
350 | if (gsi_top <= NR_IRQS_LEGACY) | |
351 | nr += 8 * nr_cpu_ids; | |
352 | else | |
353 | nr += gsi_top * 16; | |
354 | #endif | |
355 | if (nr < nr_irqs) | |
356 | nr_irqs = nr; | |
357 | ||
358 | return nr_legacy_irqs(); | |
359 | } | |
360 | ||
13315320 JL |
361 | #ifdef CONFIG_X86_IO_APIC |
362 | static void init_legacy_irqs(void) | |
363 | { | |
364 | int i, node = cpu_to_node(0); | |
7f3262ed | 365 | struct apic_chip_data *data; |
13315320 JL |
366 | |
367 | /* | |
368 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 369 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
370 | */ |
371 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
372 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
373 | BUG_ON(!data); | |
191a6635 IM |
374 | |
375 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
376 | cpumask_setall(data->domain); |
377 | irq_set_chip_data(i, data); | |
13315320 JL |
378 | } |
379 | } | |
380 | #else | |
381 | static void init_legacy_irqs(void) { } | |
382 | #endif | |
383 | ||
11d686e9 JL |
384 | int __init arch_early_irq_init(void) |
385 | { | |
13315320 JL |
386 | init_legacy_irqs(); |
387 | ||
b5dc8e6c JL |
388 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
389 | NULL); | |
390 | BUG_ON(x86_vector_domain == NULL); | |
391 | irq_set_default_host(x86_vector_domain); | |
392 | ||
52f518a3 | 393 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 394 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 395 | |
f7fa7aee JL |
396 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
397 | ||
11d686e9 JL |
398 | return arch_early_ioapic_init(); |
399 | } | |
400 | ||
74afab7a JL |
401 | static void __setup_vector_irq(int cpu) |
402 | { | |
403 | /* Initialize vector_irq on a new cpu */ | |
404 | int irq, vector; | |
7f3262ed | 405 | struct apic_chip_data *data; |
74afab7a JL |
406 | |
407 | /* | |
408 | * vector_lock will make sure that we don't run into irq vector | |
409 | * assignments that might be happening on another cpu in parallel, | |
410 | * while we setup our initial vector to irq mappings. | |
411 | */ | |
412 | raw_spin_lock(&vector_lock); | |
413 | /* Mark the inuse vectors */ | |
414 | for_each_active_irq(irq) { | |
7f3262ed JL |
415 | data = apic_chip_data(irq_get_irq_data(irq)); |
416 | if (!data) | |
74afab7a JL |
417 | continue; |
418 | ||
7f3262ed | 419 | if (!cpumask_test_cpu(cpu, data->domain)) |
74afab7a | 420 | continue; |
7f3262ed | 421 | vector = data->cfg.vector; |
74afab7a JL |
422 | per_cpu(vector_irq, cpu)[vector] = irq; |
423 | } | |
424 | /* Mark the free vectors */ | |
425 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
426 | irq = per_cpu(vector_irq, cpu)[vector]; | |
427 | if (irq <= VECTOR_UNDEFINED) | |
428 | continue; | |
429 | ||
7f3262ed JL |
430 | data = apic_chip_data(irq_get_irq_data(irq)); |
431 | if (!cpumask_test_cpu(cpu, data->domain)) | |
74afab7a JL |
432 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
433 | } | |
434 | raw_spin_unlock(&vector_lock); | |
435 | } | |
436 | ||
437 | /* | |
438 | * Setup the vector to irq mappings. | |
439 | */ | |
440 | void setup_vector_irq(int cpu) | |
441 | { | |
442 | int irq; | |
443 | ||
444 | /* | |
445 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
446 | * boot cpu. But there are certain platforms where PIC interrupts are | |
447 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
448 | * legacy PIC, for the new cpu that is coming online, setup the static | |
449 | * legacy vector to irq mapping: | |
450 | */ | |
451 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
8b455e65 | 452 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq; |
74afab7a JL |
453 | |
454 | __setup_vector_irq(cpu); | |
455 | } | |
456 | ||
7f3262ed | 457 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 458 | { |
7f3262ed | 459 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
460 | unsigned long flags; |
461 | int cpu; | |
462 | ||
463 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
464 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
465 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
466 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
467 | ||
468 | return 1; | |
469 | } | |
470 | ||
471 | void apic_ack_edge(struct irq_data *data) | |
472 | { | |
a9786091 | 473 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
474 | irq_move_irq(data); |
475 | ack_APIC_irq(); | |
476 | } | |
477 | ||
68f9f440 JL |
478 | static int apic_set_affinity(struct irq_data *irq_data, |
479 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 480 | { |
7f3262ed | 481 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
482 | int err, irq = irq_data->irq; |
483 | ||
484 | if (!config_enabled(CONFIG_SMP)) | |
485 | return -EPERM; | |
486 | ||
487 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
488 | return -EINVAL; | |
489 | ||
7f3262ed | 490 | err = assign_irq_vector(irq, data, dest); |
b5dc8e6c JL |
491 | if (err) { |
492 | struct irq_data *top = irq_get_irq_data(irq); | |
493 | ||
7f3262ed | 494 | if (assign_irq_vector(irq, data, top->affinity)) |
b5dc8e6c JL |
495 | pr_err("Failed to recover vector for irq %d\n", irq); |
496 | return err; | |
497 | } | |
498 | ||
499 | return IRQ_SET_MASK_OK; | |
500 | } | |
501 | ||
502 | static struct irq_chip lapic_controller = { | |
503 | .irq_ack = apic_ack_edge, | |
68f9f440 | 504 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
505 | .irq_retrigger = apic_retrigger_irq, |
506 | }; | |
507 | ||
74afab7a | 508 | #ifdef CONFIG_SMP |
7f3262ed | 509 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a JL |
510 | { |
511 | cpumask_var_t cleanup_mask; | |
512 | ||
513 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
514 | unsigned int i; | |
515 | ||
7f3262ed | 516 | for_each_cpu_and(i, data->old_domain, cpu_online_mask) |
74afab7a JL |
517 | apic->send_IPI_mask(cpumask_of(i), |
518 | IRQ_MOVE_CLEANUP_VECTOR); | |
519 | } else { | |
7f3262ed | 520 | cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); |
74afab7a JL |
521 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
522 | free_cpumask_var(cleanup_mask); | |
523 | } | |
7f3262ed | 524 | data->move_in_progress = 0; |
74afab7a JL |
525 | } |
526 | ||
c6c2002b JL |
527 | void send_cleanup_vector(struct irq_cfg *cfg) |
528 | { | |
7f3262ed JL |
529 | struct apic_chip_data *data; |
530 | ||
531 | data = container_of(cfg, struct apic_chip_data, cfg); | |
532 | if (data->move_in_progress) | |
533 | __send_cleanup_vector(data); | |
c6c2002b JL |
534 | } |
535 | ||
74afab7a JL |
536 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
537 | { | |
538 | unsigned vector, me; | |
539 | ||
540 | ack_APIC_irq(); | |
541 | irq_enter(); | |
542 | exit_idle(); | |
543 | ||
544 | me = smp_processor_id(); | |
545 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
546 | int irq; | |
547 | unsigned int irr; | |
548 | struct irq_desc *desc; | |
7f3262ed | 549 | struct apic_chip_data *data; |
74afab7a JL |
550 | |
551 | irq = __this_cpu_read(vector_irq[vector]); | |
552 | ||
553 | if (irq <= VECTOR_UNDEFINED) | |
554 | continue; | |
555 | ||
556 | desc = irq_to_desc(irq); | |
557 | if (!desc) | |
558 | continue; | |
559 | ||
7f3262ed JL |
560 | data = apic_chip_data(&desc->irq_data); |
561 | if (!data) | |
74afab7a JL |
562 | continue; |
563 | ||
564 | raw_spin_lock(&desc->lock); | |
565 | ||
566 | /* | |
567 | * Check if the irq migration is in progress. If so, we | |
568 | * haven't received the cleanup request yet for this irq. | |
569 | */ | |
7f3262ed | 570 | if (data->move_in_progress) |
74afab7a JL |
571 | goto unlock; |
572 | ||
7f3262ed JL |
573 | if (vector == data->cfg.vector && |
574 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
575 | goto unlock; |
576 | ||
577 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
578 | /* | |
579 | * Check if the vector that needs to be cleanedup is | |
580 | * registered at the cpu's IRR. If so, then this is not | |
581 | * the best time to clean it up. Lets clean it up in the | |
582 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
583 | * to myself. | |
584 | */ | |
585 | if (irr & (1 << (vector % 32))) { | |
586 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
587 | goto unlock; | |
588 | } | |
589 | __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED); | |
590 | unlock: | |
591 | raw_spin_unlock(&desc->lock); | |
592 | } | |
593 | ||
594 | irq_exit(); | |
595 | } | |
596 | ||
597 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
598 | { | |
599 | unsigned me; | |
7f3262ed | 600 | struct apic_chip_data *data; |
74afab7a | 601 | |
7f3262ed JL |
602 | data = container_of(cfg, struct apic_chip_data, cfg); |
603 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
604 | return; |
605 | ||
606 | me = smp_processor_id(); | |
7f3262ed JL |
607 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
608 | __send_cleanup_vector(data); | |
74afab7a JL |
609 | } |
610 | ||
611 | void irq_complete_move(struct irq_cfg *cfg) | |
612 | { | |
613 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
614 | } | |
615 | ||
616 | void irq_force_complete_move(int irq) | |
617 | { | |
618 | struct irq_cfg *cfg = irq_cfg(irq); | |
619 | ||
7f3262ed JL |
620 | if (cfg) |
621 | __irq_complete_move(cfg, cfg->vector); | |
74afab7a | 622 | } |
74afab7a JL |
623 | #endif |
624 | ||
74afab7a JL |
625 | static void __init print_APIC_field(int base) |
626 | { | |
627 | int i; | |
628 | ||
629 | printk(KERN_DEBUG); | |
630 | ||
631 | for (i = 0; i < 8; i++) | |
632 | pr_cont("%08x", apic_read(base + i*0x10)); | |
633 | ||
634 | pr_cont("\n"); | |
635 | } | |
636 | ||
637 | static void __init print_local_APIC(void *dummy) | |
638 | { | |
639 | unsigned int i, v, ver, maxlvt; | |
640 | u64 icr; | |
641 | ||
849d3569 JL |
642 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
643 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 644 | v = apic_read(APIC_ID); |
849d3569 | 645 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 646 | v = apic_read(APIC_LVR); |
849d3569 | 647 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
648 | ver = GET_APIC_VERSION(v); |
649 | maxlvt = lapic_get_maxlvt(); | |
650 | ||
651 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 652 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
653 | |
654 | /* !82489DX */ | |
655 | if (APIC_INTEGRATED(ver)) { | |
656 | if (!APIC_XAPIC(ver)) { | |
657 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
658 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
659 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
660 | } |
661 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 662 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
663 | } |
664 | ||
665 | /* | |
666 | * Remote read supported only in the 82489DX and local APIC for | |
667 | * Pentium processors. | |
668 | */ | |
669 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
670 | v = apic_read(APIC_RRR); | |
849d3569 | 671 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
672 | } |
673 | ||
674 | v = apic_read(APIC_LDR); | |
849d3569 | 675 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
676 | if (!x2apic_enabled()) { |
677 | v = apic_read(APIC_DFR); | |
849d3569 | 678 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
679 | } |
680 | v = apic_read(APIC_SPIV); | |
849d3569 | 681 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 682 | |
849d3569 | 683 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 684 | print_APIC_field(APIC_ISR); |
849d3569 | 685 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 686 | print_APIC_field(APIC_TMR); |
849d3569 | 687 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
688 | print_APIC_field(APIC_IRR); |
689 | ||
690 | /* !82489DX */ | |
691 | if (APIC_INTEGRATED(ver)) { | |
692 | /* Due to the Pentium erratum 3AP. */ | |
693 | if (maxlvt > 3) | |
694 | apic_write(APIC_ESR, 0); | |
695 | ||
696 | v = apic_read(APIC_ESR); | |
849d3569 | 697 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
698 | } |
699 | ||
700 | icr = apic_icr_read(); | |
849d3569 JL |
701 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
702 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
703 | |
704 | v = apic_read(APIC_LVTT); | |
849d3569 | 705 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
706 | |
707 | if (maxlvt > 3) { | |
708 | /* PC is LVT#4. */ | |
709 | v = apic_read(APIC_LVTPC); | |
849d3569 | 710 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
711 | } |
712 | v = apic_read(APIC_LVT0); | |
849d3569 | 713 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 714 | v = apic_read(APIC_LVT1); |
849d3569 | 715 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
716 | |
717 | if (maxlvt > 2) { | |
718 | /* ERR is LVT#3. */ | |
719 | v = apic_read(APIC_LVTERR); | |
849d3569 | 720 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
721 | } |
722 | ||
723 | v = apic_read(APIC_TMICT); | |
849d3569 | 724 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 725 | v = apic_read(APIC_TMCCT); |
849d3569 | 726 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 727 | v = apic_read(APIC_TDCR); |
849d3569 | 728 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
729 | |
730 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
731 | v = apic_read(APIC_EFEAT); | |
732 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 733 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 734 | v = apic_read(APIC_ECTRL); |
849d3569 | 735 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
736 | for (i = 0; i < maxlvt; i++) { |
737 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 738 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
739 | } |
740 | } | |
741 | pr_cont("\n"); | |
742 | } | |
743 | ||
744 | static void __init print_local_APICs(int maxcpu) | |
745 | { | |
746 | int cpu; | |
747 | ||
748 | if (!maxcpu) | |
749 | return; | |
750 | ||
751 | preempt_disable(); | |
752 | for_each_online_cpu(cpu) { | |
753 | if (cpu >= maxcpu) | |
754 | break; | |
755 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
756 | } | |
757 | preempt_enable(); | |
758 | } | |
759 | ||
760 | static void __init print_PIC(void) | |
761 | { | |
762 | unsigned int v; | |
763 | unsigned long flags; | |
764 | ||
765 | if (!nr_legacy_irqs()) | |
766 | return; | |
767 | ||
849d3569 | 768 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
769 | |
770 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
771 | ||
772 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 773 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
774 | |
775 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 776 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
777 | |
778 | outb(0x0b, 0xa0); | |
779 | outb(0x0b, 0x20); | |
780 | v = inb(0xa0) << 8 | inb(0x20); | |
781 | outb(0x0a, 0xa0); | |
782 | outb(0x0a, 0x20); | |
783 | ||
784 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
785 | ||
849d3569 | 786 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
787 | |
788 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 789 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
790 | } |
791 | ||
792 | static int show_lapic __initdata = 1; | |
793 | static __init int setup_show_lapic(char *arg) | |
794 | { | |
795 | int num = -1; | |
796 | ||
797 | if (strcmp(arg, "all") == 0) { | |
798 | show_lapic = CONFIG_NR_CPUS; | |
799 | } else { | |
800 | get_option(&arg, &num); | |
801 | if (num >= 0) | |
802 | show_lapic = num; | |
803 | } | |
804 | ||
805 | return 1; | |
806 | } | |
807 | __setup("show_lapic=", setup_show_lapic); | |
808 | ||
809 | static int __init print_ICs(void) | |
810 | { | |
811 | if (apic_verbosity == APIC_QUIET) | |
812 | return 0; | |
813 | ||
814 | print_PIC(); | |
815 | ||
816 | /* don't print out if apic is not there */ | |
817 | if (!cpu_has_apic && !apic_from_smp_config()) | |
818 | return 0; | |
819 | ||
820 | print_local_APICs(show_lapic); | |
821 | print_IO_APICs(); | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
826 | late_initcall(print_ICs); |