Commit | Line | Data |
---|---|---|
74afab7a JL |
1 | /* |
2 | * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
b5dc8e6c JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Enable support of hierarchical irqdomains | |
74afab7a JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/compiler.h> | |
74afab7a | 16 | #include <linux/slab.h> |
d746d1eb | 17 | #include <asm/irqdomain.h> |
74afab7a JL |
18 | #include <asm/hw_irq.h> |
19 | #include <asm/apic.h> | |
20 | #include <asm/i8259.h> | |
21 | #include <asm/desc.h> | |
22 | #include <asm/irq_remapping.h> | |
23 | ||
7f3262ed JL |
24 | struct apic_chip_data { |
25 | struct irq_cfg cfg; | |
26 | cpumask_var_t domain; | |
27 | cpumask_var_t old_domain; | |
28 | u8 move_in_progress : 1; | |
29 | }; | |
30 | ||
b5dc8e6c | 31 | struct irq_domain *x86_vector_domain; |
c8f3e518 | 32 | EXPORT_SYMBOL_GPL(x86_vector_domain); |
74afab7a | 33 | static DEFINE_RAW_SPINLOCK(vector_lock); |
8a580f70 | 34 | static cpumask_var_t vector_cpumask, searched_cpumask; |
b5dc8e6c | 35 | static struct irq_chip lapic_controller; |
13315320 | 36 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed | 37 | static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; |
13315320 | 38 | #endif |
74afab7a JL |
39 | |
40 | void lock_vector_lock(void) | |
41 | { | |
42 | /* Used to the online set of cpus does not change | |
43 | * during assign_irq_vector. | |
44 | */ | |
45 | raw_spin_lock(&vector_lock); | |
46 | } | |
47 | ||
48 | void unlock_vector_lock(void) | |
49 | { | |
50 | raw_spin_unlock(&vector_lock); | |
51 | } | |
52 | ||
7f3262ed | 53 | static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) |
74afab7a | 54 | { |
b5dc8e6c JL |
55 | if (!irq_data) |
56 | return NULL; | |
57 | ||
58 | while (irq_data->parent_data) | |
59 | irq_data = irq_data->parent_data; | |
60 | ||
74afab7a JL |
61 | return irq_data->chip_data; |
62 | } | |
63 | ||
7f3262ed JL |
64 | struct irq_cfg *irqd_cfg(struct irq_data *irq_data) |
65 | { | |
66 | struct apic_chip_data *data = apic_chip_data(irq_data); | |
67 | ||
68 | return data ? &data->cfg : NULL; | |
69 | } | |
c8f3e518 | 70 | EXPORT_SYMBOL_GPL(irqd_cfg); |
7f3262ed JL |
71 | |
72 | struct irq_cfg *irq_cfg(unsigned int irq) | |
74afab7a | 73 | { |
7f3262ed JL |
74 | return irqd_cfg(irq_get_irq_data(irq)); |
75 | } | |
74afab7a | 76 | |
7f3262ed JL |
77 | static struct apic_chip_data *alloc_apic_chip_data(int node) |
78 | { | |
79 | struct apic_chip_data *data; | |
80 | ||
81 | data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); | |
82 | if (!data) | |
74afab7a | 83 | return NULL; |
7f3262ed JL |
84 | if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) |
85 | goto out_data; | |
86 | if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) | |
74afab7a | 87 | goto out_domain; |
7f3262ed | 88 | return data; |
74afab7a | 89 | out_domain: |
7f3262ed JL |
90 | free_cpumask_var(data->domain); |
91 | out_data: | |
92 | kfree(data); | |
74afab7a JL |
93 | return NULL; |
94 | } | |
95 | ||
7f3262ed | 96 | static void free_apic_chip_data(struct apic_chip_data *data) |
74afab7a | 97 | { |
7f3262ed JL |
98 | if (data) { |
99 | free_cpumask_var(data->domain); | |
100 | free_cpumask_var(data->old_domain); | |
101 | kfree(data); | |
b5dc8e6c | 102 | } |
74afab7a JL |
103 | } |
104 | ||
7f3262ed JL |
105 | static int __assign_irq_vector(int irq, struct apic_chip_data *d, |
106 | const struct cpumask *mask) | |
74afab7a JL |
107 | { |
108 | /* | |
109 | * NOTE! The local APIC isn't very good at handling | |
110 | * multiple interrupts at the same interrupt level. | |
111 | * As the interrupt level is determined by taking the | |
112 | * vector number and shifting that right by 4, we | |
113 | * want to spread these out a bit so that they don't | |
114 | * all fall in the same interrupt level. | |
115 | * | |
116 | * Also, we've got to be careful not to trash gate | |
117 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | |
118 | */ | |
119 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | |
120 | static int current_offset = VECTOR_OFFSET_START % 16; | |
433cbd57 | 121 | int cpu; |
74afab7a | 122 | |
7f3262ed | 123 | if (d->move_in_progress) |
74afab7a JL |
124 | return -EBUSY; |
125 | ||
74afab7a | 126 | /* Only try and allocate irqs on cpus that are present */ |
7f3262ed | 127 | cpumask_clear(d->old_domain); |
8a580f70 | 128 | cpumask_clear(searched_cpumask); |
74afab7a JL |
129 | cpu = cpumask_first_and(mask, cpu_online_mask); |
130 | while (cpu < nr_cpu_ids) { | |
131 | int new_cpu, vector, offset; | |
132 | ||
f7fa7aee | 133 | apic->vector_allocation_domain(cpu, vector_cpumask, mask); |
74afab7a | 134 | |
f7fa7aee | 135 | if (cpumask_subset(vector_cpumask, d->domain)) { |
f7fa7aee | 136 | if (cpumask_equal(vector_cpumask, d->domain)) |
433cbd57 | 137 | goto success; |
74afab7a JL |
138 | /* |
139 | * New cpumask using the vector is a proper subset of | |
140 | * the current in use mask. So cleanup the vector | |
141 | * allocation for the members that are not used anymore. | |
142 | */ | |
f7fa7aee JL |
143 | cpumask_andnot(d->old_domain, d->domain, |
144 | vector_cpumask); | |
7f3262ed JL |
145 | d->move_in_progress = |
146 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
f7fa7aee | 147 | cpumask_and(d->domain, d->domain, vector_cpumask); |
433cbd57 | 148 | goto success; |
74afab7a JL |
149 | } |
150 | ||
151 | vector = current_vector; | |
152 | offset = current_offset; | |
153 | next: | |
154 | vector += 16; | |
155 | if (vector >= first_system_vector) { | |
156 | offset = (offset + 1) % 16; | |
157 | vector = FIRST_EXTERNAL_VECTOR + offset; | |
158 | } | |
159 | ||
160 | if (unlikely(current_vector == vector)) { | |
8a580f70 | 161 | cpumask_or(searched_cpumask, searched_cpumask, |
f7fa7aee | 162 | vector_cpumask); |
8a580f70 | 163 | cpumask_andnot(vector_cpumask, mask, searched_cpumask); |
f7fa7aee JL |
164 | cpu = cpumask_first_and(vector_cpumask, |
165 | cpu_online_mask); | |
74afab7a JL |
166 | continue; |
167 | } | |
168 | ||
169 | if (test_bit(vector, used_vectors)) | |
170 | goto next; | |
171 | ||
f7fa7aee | 172 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { |
a782a7e4 | 173 | if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) |
74afab7a JL |
174 | goto next; |
175 | } | |
176 | /* Found one! */ | |
177 | current_vector = vector; | |
178 | current_offset = offset; | |
7f3262ed JL |
179 | if (d->cfg.vector) { |
180 | cpumask_copy(d->old_domain, d->domain); | |
181 | d->move_in_progress = | |
182 | cpumask_intersects(d->old_domain, cpu_online_mask); | |
74afab7a | 183 | } |
f7fa7aee | 184 | for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) |
a782a7e4 | 185 | per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); |
7f3262ed | 186 | d->cfg.vector = vector; |
f7fa7aee | 187 | cpumask_copy(d->domain, vector_cpumask); |
433cbd57 | 188 | goto success; |
74afab7a | 189 | } |
433cbd57 | 190 | return -ENOSPC; |
74afab7a | 191 | |
433cbd57 TG |
192 | success: |
193 | /* cache destination APIC IDs into cfg->dest_apicid */ | |
194 | return apic->cpu_mask_to_apicid_and(mask, d->domain, &d->cfg.dest_apicid); | |
74afab7a JL |
195 | } |
196 | ||
7f3262ed | 197 | static int assign_irq_vector(int irq, struct apic_chip_data *data, |
f970510c | 198 | const struct cpumask *mask) |
74afab7a JL |
199 | { |
200 | int err; | |
201 | unsigned long flags; | |
202 | ||
203 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed | 204 | err = __assign_irq_vector(irq, data, mask); |
74afab7a JL |
205 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
206 | return err; | |
207 | } | |
208 | ||
486ca539 JL |
209 | static int assign_irq_vector_policy(int irq, int node, |
210 | struct apic_chip_data *data, | |
211 | struct irq_alloc_info *info) | |
212 | { | |
213 | if (info && info->mask) | |
214 | return assign_irq_vector(irq, data, info->mask); | |
215 | if (node != NUMA_NO_NODE && | |
216 | assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) | |
217 | return 0; | |
218 | return assign_irq_vector(irq, data, apic->target_cpus()); | |
219 | } | |
220 | ||
7f3262ed | 221 | static void clear_irq_vector(int irq, struct apic_chip_data *data) |
74afab7a | 222 | { |
a782a7e4 | 223 | struct irq_desc *desc; |
a782a7e4 | 224 | int cpu, vector; |
74afab7a | 225 | |
7f3262ed | 226 | BUG_ON(!data->cfg.vector); |
74afab7a | 227 | |
7f3262ed JL |
228 | vector = data->cfg.vector; |
229 | for_each_cpu_and(cpu, data->domain, cpu_online_mask) | |
7276c6a2 | 230 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 231 | |
7f3262ed JL |
232 | data->cfg.vector = 0; |
233 | cpumask_clear(data->domain); | |
74afab7a | 234 | |
111abeba | 235 | if (likely(!data->move_in_progress)) |
74afab7a | 236 | return; |
74afab7a | 237 | |
a782a7e4 | 238 | desc = irq_to_desc(irq); |
7f3262ed | 239 | for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { |
74afab7a JL |
240 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; |
241 | vector++) { | |
a782a7e4 | 242 | if (per_cpu(vector_irq, cpu)[vector] != desc) |
74afab7a | 243 | continue; |
7276c6a2 | 244 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a JL |
245 | break; |
246 | } | |
247 | } | |
7f3262ed | 248 | data->move_in_progress = 0; |
74afab7a JL |
249 | } |
250 | ||
b5dc8e6c JL |
251 | void init_irq_alloc_info(struct irq_alloc_info *info, |
252 | const struct cpumask *mask) | |
253 | { | |
254 | memset(info, 0, sizeof(*info)); | |
255 | info->mask = mask; | |
256 | } | |
257 | ||
258 | void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) | |
259 | { | |
260 | if (src) | |
261 | *dst = *src; | |
262 | else | |
263 | memset(dst, 0, sizeof(*dst)); | |
264 | } | |
265 | ||
b5dc8e6c JL |
266 | static void x86_vector_free_irqs(struct irq_domain *domain, |
267 | unsigned int virq, unsigned int nr_irqs) | |
268 | { | |
111abeba | 269 | struct apic_chip_data *apic_data; |
b5dc8e6c | 270 | struct irq_data *irq_data; |
111abeba | 271 | unsigned long flags; |
b5dc8e6c JL |
272 | int i; |
273 | ||
274 | for (i = 0; i < nr_irqs; i++) { | |
275 | irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); | |
276 | if (irq_data && irq_data->chip_data) { | |
111abeba | 277 | raw_spin_lock_irqsave(&vector_lock, flags); |
b5dc8e6c | 278 | clear_irq_vector(virq + i, irq_data->chip_data); |
111abeba JL |
279 | apic_data = irq_data->chip_data; |
280 | irq_domain_reset_irq_data(irq_data); | |
281 | raw_spin_unlock_irqrestore(&vector_lock, flags); | |
282 | free_apic_chip_data(apic_data); | |
13315320 JL |
283 | #ifdef CONFIG_X86_IO_APIC |
284 | if (virq + i < nr_legacy_irqs()) | |
7f3262ed | 285 | legacy_irq_data[virq + i] = NULL; |
13315320 | 286 | #endif |
b5dc8e6c JL |
287 | } |
288 | } | |
289 | } | |
290 | ||
291 | static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, | |
292 | unsigned int nr_irqs, void *arg) | |
293 | { | |
294 | struct irq_alloc_info *info = arg; | |
7f3262ed | 295 | struct apic_chip_data *data; |
b5dc8e6c | 296 | struct irq_data *irq_data; |
5f2dbbc5 | 297 | int i, err, node; |
b5dc8e6c JL |
298 | |
299 | if (disable_apic) | |
300 | return -ENXIO; | |
301 | ||
302 | /* Currently vector allocator can't guarantee contiguous allocations */ | |
303 | if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) | |
304 | return -ENOSYS; | |
305 | ||
b5dc8e6c JL |
306 | for (i = 0; i < nr_irqs; i++) { |
307 | irq_data = irq_domain_get_irq_data(domain, virq + i); | |
308 | BUG_ON(!irq_data); | |
5f2dbbc5 | 309 | node = irq_data_get_node(irq_data); |
13315320 | 310 | #ifdef CONFIG_X86_IO_APIC |
7f3262ed JL |
311 | if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) |
312 | data = legacy_irq_data[virq + i]; | |
13315320 JL |
313 | else |
314 | #endif | |
5f2dbbc5 | 315 | data = alloc_apic_chip_data(node); |
7f3262ed | 316 | if (!data) { |
b5dc8e6c JL |
317 | err = -ENOMEM; |
318 | goto error; | |
319 | } | |
320 | ||
321 | irq_data->chip = &lapic_controller; | |
7f3262ed | 322 | irq_data->chip_data = data; |
b5dc8e6c | 323 | irq_data->hwirq = virq + i; |
43af9872 | 324 | err = assign_irq_vector_policy(virq + i, node, data, info); |
b5dc8e6c JL |
325 | if (err) |
326 | goto error; | |
327 | } | |
328 | ||
329 | return 0; | |
330 | ||
331 | error: | |
332 | x86_vector_free_irqs(domain, virq, i + 1); | |
333 | return err; | |
334 | } | |
335 | ||
eb18cf55 TG |
336 | static const struct irq_domain_ops x86_vector_domain_ops = { |
337 | .alloc = x86_vector_alloc_irqs, | |
338 | .free = x86_vector_free_irqs, | |
b5dc8e6c JL |
339 | }; |
340 | ||
11d686e9 JL |
341 | int __init arch_probe_nr_irqs(void) |
342 | { | |
343 | int nr; | |
344 | ||
345 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) | |
346 | nr_irqs = NR_VECTORS * nr_cpu_ids; | |
347 | ||
348 | nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; | |
349 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) | |
350 | /* | |
351 | * for MSI and HT dyn irq | |
352 | */ | |
353 | if (gsi_top <= NR_IRQS_LEGACY) | |
354 | nr += 8 * nr_cpu_ids; | |
355 | else | |
356 | nr += gsi_top * 16; | |
357 | #endif | |
358 | if (nr < nr_irqs) | |
359 | nr_irqs = nr; | |
360 | ||
8c058b0b VK |
361 | /* |
362 | * We don't know if PIC is present at this point so we need to do | |
363 | * probe() to get the right number of legacy IRQs. | |
364 | */ | |
365 | return legacy_pic->probe(); | |
11d686e9 JL |
366 | } |
367 | ||
13315320 JL |
368 | #ifdef CONFIG_X86_IO_APIC |
369 | static void init_legacy_irqs(void) | |
370 | { | |
371 | int i, node = cpu_to_node(0); | |
7f3262ed | 372 | struct apic_chip_data *data; |
13315320 JL |
373 | |
374 | /* | |
375 | * For legacy IRQ's, start with assigning irq0 to irq15 to | |
191a6635 | 376 | * ISA_IRQ_VECTOR(i) for all cpu's. |
13315320 JL |
377 | */ |
378 | for (i = 0; i < nr_legacy_irqs(); i++) { | |
7f3262ed JL |
379 | data = legacy_irq_data[i] = alloc_apic_chip_data(node); |
380 | BUG_ON(!data); | |
191a6635 IM |
381 | |
382 | data->cfg.vector = ISA_IRQ_VECTOR(i); | |
7f3262ed JL |
383 | cpumask_setall(data->domain); |
384 | irq_set_chip_data(i, data); | |
13315320 JL |
385 | } |
386 | } | |
387 | #else | |
388 | static void init_legacy_irqs(void) { } | |
389 | #endif | |
390 | ||
11d686e9 JL |
391 | int __init arch_early_irq_init(void) |
392 | { | |
13315320 JL |
393 | init_legacy_irqs(); |
394 | ||
b5dc8e6c JL |
395 | x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, |
396 | NULL); | |
397 | BUG_ON(x86_vector_domain == NULL); | |
398 | irq_set_default_host(x86_vector_domain); | |
399 | ||
52f518a3 | 400 | arch_init_msi_domain(x86_vector_domain); |
49e07d8f | 401 | arch_init_htirq_domain(x86_vector_domain); |
52f518a3 | 402 | |
f7fa7aee | 403 | BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); |
8a580f70 | 404 | BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL)); |
f7fa7aee | 405 | |
11d686e9 JL |
406 | return arch_early_ioapic_init(); |
407 | } | |
408 | ||
a782a7e4 | 409 | /* Initialize vector_irq on a new cpu */ |
74afab7a JL |
410 | static void __setup_vector_irq(int cpu) |
411 | { | |
7f3262ed | 412 | struct apic_chip_data *data; |
a782a7e4 TG |
413 | struct irq_desc *desc; |
414 | int irq, vector; | |
74afab7a | 415 | |
74afab7a | 416 | /* Mark the inuse vectors */ |
a782a7e4 TG |
417 | for_each_irq_desc(irq, desc) { |
418 | struct irq_data *idata = irq_desc_get_irq_data(desc); | |
74afab7a | 419 | |
a782a7e4 TG |
420 | data = apic_chip_data(idata); |
421 | if (!data || !cpumask_test_cpu(cpu, data->domain)) | |
74afab7a | 422 | continue; |
7f3262ed | 423 | vector = data->cfg.vector; |
a782a7e4 | 424 | per_cpu(vector_irq, cpu)[vector] = desc; |
74afab7a JL |
425 | } |
426 | /* Mark the free vectors */ | |
427 | for (vector = 0; vector < NR_VECTORS; ++vector) { | |
a782a7e4 TG |
428 | desc = per_cpu(vector_irq, cpu)[vector]; |
429 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
430 | continue; |
431 | ||
a782a7e4 | 432 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 433 | if (!cpumask_test_cpu(cpu, data->domain)) |
7276c6a2 | 434 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; |
74afab7a | 435 | } |
74afab7a JL |
436 | } |
437 | ||
438 | /* | |
5a3f75e3 | 439 | * Setup the vector to irq mappings. Must be called with vector_lock held. |
74afab7a JL |
440 | */ |
441 | void setup_vector_irq(int cpu) | |
442 | { | |
443 | int irq; | |
444 | ||
5a3f75e3 | 445 | lockdep_assert_held(&vector_lock); |
74afab7a JL |
446 | /* |
447 | * On most of the platforms, legacy PIC delivers the interrupts on the | |
448 | * boot cpu. But there are certain platforms where PIC interrupts are | |
449 | * delivered to multiple cpu's. If the legacy IRQ is handled by the | |
450 | * legacy PIC, for the new cpu that is coming online, setup the static | |
451 | * legacy vector to irq mapping: | |
452 | */ | |
453 | for (irq = 0; irq < nr_legacy_irqs(); irq++) | |
a782a7e4 | 454 | per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); |
74afab7a JL |
455 | |
456 | __setup_vector_irq(cpu); | |
457 | } | |
458 | ||
7f3262ed | 459 | static int apic_retrigger_irq(struct irq_data *irq_data) |
74afab7a | 460 | { |
7f3262ed | 461 | struct apic_chip_data *data = apic_chip_data(irq_data); |
74afab7a JL |
462 | unsigned long flags; |
463 | int cpu; | |
464 | ||
465 | raw_spin_lock_irqsave(&vector_lock, flags); | |
7f3262ed JL |
466 | cpu = cpumask_first_and(data->domain, cpu_online_mask); |
467 | apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); | |
74afab7a JL |
468 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
469 | ||
470 | return 1; | |
471 | } | |
472 | ||
473 | void apic_ack_edge(struct irq_data *data) | |
474 | { | |
a9786091 | 475 | irq_complete_move(irqd_cfg(data)); |
74afab7a JL |
476 | irq_move_irq(data); |
477 | ack_APIC_irq(); | |
478 | } | |
479 | ||
68f9f440 JL |
480 | static int apic_set_affinity(struct irq_data *irq_data, |
481 | const struct cpumask *dest, bool force) | |
b5dc8e6c | 482 | { |
7f3262ed | 483 | struct apic_chip_data *data = irq_data->chip_data; |
b5dc8e6c JL |
484 | int err, irq = irq_data->irq; |
485 | ||
486 | if (!config_enabled(CONFIG_SMP)) | |
487 | return -EPERM; | |
488 | ||
489 | if (!cpumask_intersects(dest, cpu_online_mask)) | |
490 | return -EINVAL; | |
491 | ||
7f3262ed | 492 | err = assign_irq_vector(irq, data, dest); |
b5dc8e6c | 493 | if (err) { |
c149e4cd | 494 | if (assign_irq_vector(irq, data, |
9df872fa | 495 | irq_data_get_affinity_mask(irq_data))) |
b5dc8e6c JL |
496 | pr_err("Failed to recover vector for irq %d\n", irq); |
497 | return err; | |
498 | } | |
499 | ||
500 | return IRQ_SET_MASK_OK; | |
501 | } | |
502 | ||
503 | static struct irq_chip lapic_controller = { | |
504 | .irq_ack = apic_ack_edge, | |
68f9f440 | 505 | .irq_set_affinity = apic_set_affinity, |
b5dc8e6c JL |
506 | .irq_retrigger = apic_retrigger_irq, |
507 | }; | |
508 | ||
74afab7a | 509 | #ifdef CONFIG_SMP |
7f3262ed | 510 | static void __send_cleanup_vector(struct apic_chip_data *data) |
74afab7a JL |
511 | { |
512 | cpumask_var_t cleanup_mask; | |
513 | ||
514 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { | |
515 | unsigned int i; | |
516 | ||
7f3262ed | 517 | for_each_cpu_and(i, data->old_domain, cpu_online_mask) |
74afab7a JL |
518 | apic->send_IPI_mask(cpumask_of(i), |
519 | IRQ_MOVE_CLEANUP_VECTOR); | |
520 | } else { | |
7f3262ed | 521 | cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); |
74afab7a JL |
522 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
523 | free_cpumask_var(cleanup_mask); | |
524 | } | |
7f3262ed | 525 | data->move_in_progress = 0; |
74afab7a JL |
526 | } |
527 | ||
c6c2002b JL |
528 | void send_cleanup_vector(struct irq_cfg *cfg) |
529 | { | |
7f3262ed JL |
530 | struct apic_chip_data *data; |
531 | ||
532 | data = container_of(cfg, struct apic_chip_data, cfg); | |
533 | if (data->move_in_progress) | |
534 | __send_cleanup_vector(data); | |
c6c2002b JL |
535 | } |
536 | ||
74afab7a JL |
537 | asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) |
538 | { | |
539 | unsigned vector, me; | |
540 | ||
6af7faf6 | 541 | entering_ack_irq(); |
74afab7a | 542 | |
df54c493 TG |
543 | /* Prevent vectors vanishing under us */ |
544 | raw_spin_lock(&vector_lock); | |
545 | ||
74afab7a JL |
546 | me = smp_processor_id(); |
547 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { | |
7f3262ed | 548 | struct apic_chip_data *data; |
a782a7e4 TG |
549 | struct irq_desc *desc; |
550 | unsigned int irr; | |
74afab7a | 551 | |
df54c493 | 552 | retry: |
a782a7e4 TG |
553 | desc = __this_cpu_read(vector_irq[vector]); |
554 | if (IS_ERR_OR_NULL(desc)) | |
74afab7a JL |
555 | continue; |
556 | ||
df54c493 TG |
557 | if (!raw_spin_trylock(&desc->lock)) { |
558 | raw_spin_unlock(&vector_lock); | |
559 | cpu_relax(); | |
560 | raw_spin_lock(&vector_lock); | |
561 | goto retry; | |
562 | } | |
74afab7a | 563 | |
a782a7e4 | 564 | data = apic_chip_data(irq_desc_get_irq_data(desc)); |
7f3262ed | 565 | if (!data) |
df54c493 | 566 | goto unlock; |
74afab7a JL |
567 | |
568 | /* | |
569 | * Check if the irq migration is in progress. If so, we | |
570 | * haven't received the cleanup request yet for this irq. | |
571 | */ | |
7f3262ed | 572 | if (data->move_in_progress) |
74afab7a JL |
573 | goto unlock; |
574 | ||
7f3262ed JL |
575 | if (vector == data->cfg.vector && |
576 | cpumask_test_cpu(me, data->domain)) | |
74afab7a JL |
577 | goto unlock; |
578 | ||
579 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); | |
580 | /* | |
581 | * Check if the vector that needs to be cleanedup is | |
582 | * registered at the cpu's IRR. If so, then this is not | |
583 | * the best time to clean it up. Lets clean it up in the | |
584 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR | |
585 | * to myself. | |
586 | */ | |
587 | if (irr & (1 << (vector % 32))) { | |
588 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); | |
589 | goto unlock; | |
590 | } | |
7276c6a2 | 591 | __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); |
74afab7a JL |
592 | unlock: |
593 | raw_spin_unlock(&desc->lock); | |
594 | } | |
595 | ||
df54c493 TG |
596 | raw_spin_unlock(&vector_lock); |
597 | ||
6af7faf6 | 598 | exiting_irq(); |
74afab7a JL |
599 | } |
600 | ||
601 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) | |
602 | { | |
603 | unsigned me; | |
7f3262ed | 604 | struct apic_chip_data *data; |
74afab7a | 605 | |
7f3262ed JL |
606 | data = container_of(cfg, struct apic_chip_data, cfg); |
607 | if (likely(!data->move_in_progress)) | |
74afab7a JL |
608 | return; |
609 | ||
610 | me = smp_processor_id(); | |
7f3262ed JL |
611 | if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) |
612 | __send_cleanup_vector(data); | |
74afab7a JL |
613 | } |
614 | ||
615 | void irq_complete_move(struct irq_cfg *cfg) | |
616 | { | |
617 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); | |
618 | } | |
619 | ||
620 | void irq_force_complete_move(int irq) | |
621 | { | |
622 | struct irq_cfg *cfg = irq_cfg(irq); | |
623 | ||
7f3262ed JL |
624 | if (cfg) |
625 | __irq_complete_move(cfg, cfg->vector); | |
74afab7a | 626 | } |
74afab7a JL |
627 | #endif |
628 | ||
74afab7a JL |
629 | static void __init print_APIC_field(int base) |
630 | { | |
631 | int i; | |
632 | ||
633 | printk(KERN_DEBUG); | |
634 | ||
635 | for (i = 0; i < 8; i++) | |
636 | pr_cont("%08x", apic_read(base + i*0x10)); | |
637 | ||
638 | pr_cont("\n"); | |
639 | } | |
640 | ||
641 | static void __init print_local_APIC(void *dummy) | |
642 | { | |
643 | unsigned int i, v, ver, maxlvt; | |
644 | u64 icr; | |
645 | ||
849d3569 JL |
646 | pr_debug("printing local APIC contents on CPU#%d/%d:\n", |
647 | smp_processor_id(), hard_smp_processor_id()); | |
74afab7a | 648 | v = apic_read(APIC_ID); |
849d3569 | 649 | pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
74afab7a | 650 | v = apic_read(APIC_LVR); |
849d3569 | 651 | pr_info("... APIC VERSION: %08x\n", v); |
74afab7a JL |
652 | ver = GET_APIC_VERSION(v); |
653 | maxlvt = lapic_get_maxlvt(); | |
654 | ||
655 | v = apic_read(APIC_TASKPRI); | |
849d3569 | 656 | pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
74afab7a JL |
657 | |
658 | /* !82489DX */ | |
659 | if (APIC_INTEGRATED(ver)) { | |
660 | if (!APIC_XAPIC(ver)) { | |
661 | v = apic_read(APIC_ARBPRI); | |
849d3569 JL |
662 | pr_debug("... APIC ARBPRI: %08x (%02x)\n", |
663 | v, v & APIC_ARBPRI_MASK); | |
74afab7a JL |
664 | } |
665 | v = apic_read(APIC_PROCPRI); | |
849d3569 | 666 | pr_debug("... APIC PROCPRI: %08x\n", v); |
74afab7a JL |
667 | } |
668 | ||
669 | /* | |
670 | * Remote read supported only in the 82489DX and local APIC for | |
671 | * Pentium processors. | |
672 | */ | |
673 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { | |
674 | v = apic_read(APIC_RRR); | |
849d3569 | 675 | pr_debug("... APIC RRR: %08x\n", v); |
74afab7a JL |
676 | } |
677 | ||
678 | v = apic_read(APIC_LDR); | |
849d3569 | 679 | pr_debug("... APIC LDR: %08x\n", v); |
74afab7a JL |
680 | if (!x2apic_enabled()) { |
681 | v = apic_read(APIC_DFR); | |
849d3569 | 682 | pr_debug("... APIC DFR: %08x\n", v); |
74afab7a JL |
683 | } |
684 | v = apic_read(APIC_SPIV); | |
849d3569 | 685 | pr_debug("... APIC SPIV: %08x\n", v); |
74afab7a | 686 | |
849d3569 | 687 | pr_debug("... APIC ISR field:\n"); |
74afab7a | 688 | print_APIC_field(APIC_ISR); |
849d3569 | 689 | pr_debug("... APIC TMR field:\n"); |
74afab7a | 690 | print_APIC_field(APIC_TMR); |
849d3569 | 691 | pr_debug("... APIC IRR field:\n"); |
74afab7a JL |
692 | print_APIC_field(APIC_IRR); |
693 | ||
694 | /* !82489DX */ | |
695 | if (APIC_INTEGRATED(ver)) { | |
696 | /* Due to the Pentium erratum 3AP. */ | |
697 | if (maxlvt > 3) | |
698 | apic_write(APIC_ESR, 0); | |
699 | ||
700 | v = apic_read(APIC_ESR); | |
849d3569 | 701 | pr_debug("... APIC ESR: %08x\n", v); |
74afab7a JL |
702 | } |
703 | ||
704 | icr = apic_icr_read(); | |
849d3569 JL |
705 | pr_debug("... APIC ICR: %08x\n", (u32)icr); |
706 | pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); | |
74afab7a JL |
707 | |
708 | v = apic_read(APIC_LVTT); | |
849d3569 | 709 | pr_debug("... APIC LVTT: %08x\n", v); |
74afab7a JL |
710 | |
711 | if (maxlvt > 3) { | |
712 | /* PC is LVT#4. */ | |
713 | v = apic_read(APIC_LVTPC); | |
849d3569 | 714 | pr_debug("... APIC LVTPC: %08x\n", v); |
74afab7a JL |
715 | } |
716 | v = apic_read(APIC_LVT0); | |
849d3569 | 717 | pr_debug("... APIC LVT0: %08x\n", v); |
74afab7a | 718 | v = apic_read(APIC_LVT1); |
849d3569 | 719 | pr_debug("... APIC LVT1: %08x\n", v); |
74afab7a JL |
720 | |
721 | if (maxlvt > 2) { | |
722 | /* ERR is LVT#3. */ | |
723 | v = apic_read(APIC_LVTERR); | |
849d3569 | 724 | pr_debug("... APIC LVTERR: %08x\n", v); |
74afab7a JL |
725 | } |
726 | ||
727 | v = apic_read(APIC_TMICT); | |
849d3569 | 728 | pr_debug("... APIC TMICT: %08x\n", v); |
74afab7a | 729 | v = apic_read(APIC_TMCCT); |
849d3569 | 730 | pr_debug("... APIC TMCCT: %08x\n", v); |
74afab7a | 731 | v = apic_read(APIC_TDCR); |
849d3569 | 732 | pr_debug("... APIC TDCR: %08x\n", v); |
74afab7a JL |
733 | |
734 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { | |
735 | v = apic_read(APIC_EFEAT); | |
736 | maxlvt = (v >> 16) & 0xff; | |
849d3569 | 737 | pr_debug("... APIC EFEAT: %08x\n", v); |
74afab7a | 738 | v = apic_read(APIC_ECTRL); |
849d3569 | 739 | pr_debug("... APIC ECTRL: %08x\n", v); |
74afab7a JL |
740 | for (i = 0; i < maxlvt; i++) { |
741 | v = apic_read(APIC_EILVTn(i)); | |
849d3569 | 742 | pr_debug("... APIC EILVT%d: %08x\n", i, v); |
74afab7a JL |
743 | } |
744 | } | |
745 | pr_cont("\n"); | |
746 | } | |
747 | ||
748 | static void __init print_local_APICs(int maxcpu) | |
749 | { | |
750 | int cpu; | |
751 | ||
752 | if (!maxcpu) | |
753 | return; | |
754 | ||
755 | preempt_disable(); | |
756 | for_each_online_cpu(cpu) { | |
757 | if (cpu >= maxcpu) | |
758 | break; | |
759 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); | |
760 | } | |
761 | preempt_enable(); | |
762 | } | |
763 | ||
764 | static void __init print_PIC(void) | |
765 | { | |
766 | unsigned int v; | |
767 | unsigned long flags; | |
768 | ||
769 | if (!nr_legacy_irqs()) | |
770 | return; | |
771 | ||
849d3569 | 772 | pr_debug("\nprinting PIC contents\n"); |
74afab7a JL |
773 | |
774 | raw_spin_lock_irqsave(&i8259A_lock, flags); | |
775 | ||
776 | v = inb(0xa1) << 8 | inb(0x21); | |
849d3569 | 777 | pr_debug("... PIC IMR: %04x\n", v); |
74afab7a JL |
778 | |
779 | v = inb(0xa0) << 8 | inb(0x20); | |
849d3569 | 780 | pr_debug("... PIC IRR: %04x\n", v); |
74afab7a JL |
781 | |
782 | outb(0x0b, 0xa0); | |
783 | outb(0x0b, 0x20); | |
784 | v = inb(0xa0) << 8 | inb(0x20); | |
785 | outb(0x0a, 0xa0); | |
786 | outb(0x0a, 0x20); | |
787 | ||
788 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); | |
789 | ||
849d3569 | 790 | pr_debug("... PIC ISR: %04x\n", v); |
74afab7a JL |
791 | |
792 | v = inb(0x4d1) << 8 | inb(0x4d0); | |
849d3569 | 793 | pr_debug("... PIC ELCR: %04x\n", v); |
74afab7a JL |
794 | } |
795 | ||
796 | static int show_lapic __initdata = 1; | |
797 | static __init int setup_show_lapic(char *arg) | |
798 | { | |
799 | int num = -1; | |
800 | ||
801 | if (strcmp(arg, "all") == 0) { | |
802 | show_lapic = CONFIG_NR_CPUS; | |
803 | } else { | |
804 | get_option(&arg, &num); | |
805 | if (num >= 0) | |
806 | show_lapic = num; | |
807 | } | |
808 | ||
809 | return 1; | |
810 | } | |
811 | __setup("show_lapic=", setup_show_lapic); | |
812 | ||
813 | static int __init print_ICs(void) | |
814 | { | |
815 | if (apic_verbosity == APIC_QUIET) | |
816 | return 0; | |
817 | ||
818 | print_PIC(); | |
819 | ||
820 | /* don't print out if apic is not there */ | |
821 | if (!cpu_has_apic && !apic_from_smp_config()) | |
822 | return 0; | |
823 | ||
824 | print_local_APICs(show_lapic); | |
825 | print_IO_APICs(); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
830 | late_initcall(print_ICs); |