Commit | Line | Data |
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1da177e4 | 1 | /* |
835c34a1 | 2 | * IBM Summit-Specific Code |
1da177e4 LT |
3 | * |
4 | * Written By: Matthew Dobson, IBM Corporation | |
5 | * | |
6 | * Copyright (c) 2003 IBM Corp. | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or (at | |
13 | * your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
18 | * NON INFRINGEMENT. See the GNU General Public License for more | |
19 | * details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * Send feedback to <colpatch@us.ibm.com> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/mm.h> | |
30 | #include <linux/init.h> | |
31 | #include <asm/io.h> | |
356fa0c6 | 32 | #include <asm/bios_ebda.h> |
b11b867f IM |
33 | |
34 | /* | |
35 | * APIC driver for the IBM "Summit" chipset. | |
36 | */ | |
b11b867f IM |
37 | #include <linux/threads.h> |
38 | #include <linux/cpumask.h> | |
39 | #include <asm/mpspec.h> | |
40 | #include <asm/apic.h> | |
41 | #include <asm/smp.h> | |
b11b867f IM |
42 | #include <asm/fixmap.h> |
43 | #include <asm/apicdef.h> | |
43f39890 | 44 | #include <asm/ipi.h> |
b11b867f IM |
45 | #include <linux/kernel.h> |
46 | #include <linux/string.h> | |
47 | #include <linux/init.h> | |
48 | #include <linux/gfp.h> | |
49 | #include <linux/smp.h> | |
50 | ||
b5f26d05 | 51 | static unsigned summit_get_apic_id(unsigned long x) |
b11b867f IM |
52 | { |
53 | return (x >> 24) & 0xFF; | |
54 | } | |
55 | ||
b11b867f IM |
56 | static inline void summit_send_IPI_mask(const cpumask_t *mask, int vector) |
57 | { | |
43f39890 | 58 | default_send_IPI_mask_sequence_logical(mask, vector); |
b11b867f IM |
59 | } |
60 | ||
b5f26d05 | 61 | static void summit_send_IPI_allbutself(int vector) |
b11b867f IM |
62 | { |
63 | cpumask_t mask = cpu_online_map; | |
64 | cpu_clear(smp_processor_id(), mask); | |
65 | ||
66 | if (!cpus_empty(mask)) | |
67 | summit_send_IPI_mask(&mask, vector); | |
68 | } | |
69 | ||
b5f26d05 | 70 | static void summit_send_IPI_all(int vector) |
b11b867f IM |
71 | { |
72 | summit_send_IPI_mask(&cpu_online_map, vector); | |
73 | } | |
74 | ||
75 | #include <asm/tsc.h> | |
76 | ||
77 | extern int use_cyclone; | |
78 | ||
79 | #ifdef CONFIG_X86_SUMMIT_NUMA | |
2fcb1f1f | 80 | static void setup_summit(void); |
b11b867f | 81 | #else |
2fcb1f1f | 82 | static inline void setup_summit(void) {} |
b11b867f IM |
83 | #endif |
84 | ||
b5f26d05 JS |
85 | static int summit_mps_oem_check(struct mpc_table *mpc, char *oem, |
86 | char *productid) | |
b11b867f IM |
87 | { |
88 | if (!strncmp(oem, "IBM ENSW", 8) && | |
89 | (!strncmp(productid, "VIGIL SMP", 9) | |
90 | || !strncmp(productid, "EXA", 3) | |
91 | || !strncmp(productid, "RUTHLESS SMP", 12))){ | |
92 | mark_tsc_unstable("Summit based system"); | |
93 | use_cyclone = 1; /*enable cyclone-timer*/ | |
94 | setup_summit(); | |
95 | return 1; | |
96 | } | |
97 | return 0; | |
98 | } | |
99 | ||
100 | /* Hook from generic ACPI tables.c */ | |
b5f26d05 | 101 | static int summit_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
b11b867f IM |
102 | { |
103 | if (!strncmp(oem_id, "IBM", 3) && | |
104 | (!strncmp(oem_table_id, "SERVIGIL", 8) | |
105 | || !strncmp(oem_table_id, "EXA", 3))){ | |
106 | mark_tsc_unstable("Summit based system"); | |
107 | use_cyclone = 1; /*enable cyclone-timer*/ | |
108 | setup_summit(); | |
109 | return 1; | |
110 | } | |
111 | return 0; | |
112 | } | |
113 | ||
114 | struct rio_table_hdr { | |
115 | unsigned char version; /* Version number of this data structure */ | |
116 | /* Version 3 adds chassis_num & WP_index */ | |
117 | unsigned char num_scal_dev; /* # of Scalability devices (Twisters for Vigil) */ | |
118 | unsigned char num_rio_dev; /* # of RIO I/O devices (Cyclones and Winnipegs) */ | |
119 | } __attribute__((packed)); | |
120 | ||
121 | struct scal_detail { | |
122 | unsigned char node_id; /* Scalability Node ID */ | |
123 | unsigned long CBAR; /* Address of 1MB register space */ | |
124 | unsigned char port0node; /* Node ID port connected to: 0xFF=None */ | |
125 | unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
126 | unsigned char port1node; /* Node ID port connected to: 0xFF = None */ | |
127 | unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
128 | unsigned char port2node; /* Node ID port connected to: 0xFF = None */ | |
129 | unsigned char port2port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
130 | unsigned char chassis_num; /* 1 based Chassis number (1 = boot node) */ | |
131 | } __attribute__((packed)); | |
132 | ||
133 | struct rio_detail { | |
134 | unsigned char node_id; /* RIO Node ID */ | |
135 | unsigned long BBAR; /* Address of 1MB register space */ | |
136 | unsigned char type; /* Type of device */ | |
137 | unsigned char owner_id; /* For WPEG: Node ID of Cyclone that owns this WPEG*/ | |
138 | /* For CYC: Node ID of Twister that owns this CYC */ | |
139 | unsigned char port0node; /* Node ID port connected to: 0xFF=None */ | |
140 | unsigned char port0port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
141 | unsigned char port1node; /* Node ID port connected to: 0xFF=None */ | |
142 | unsigned char port1port; /* Port num port connected to: 0,1,2, or 0xFF=None */ | |
143 | unsigned char first_slot; /* For WPEG: Lowest slot number below this WPEG */ | |
144 | /* For CYC: 0 */ | |
145 | unsigned char status; /* For WPEG: Bit 0 = 1 : the XAPIC is used */ | |
146 | /* = 0 : the XAPIC is not used, ie:*/ | |
147 | /* ints fwded to another XAPIC */ | |
148 | /* Bits1:7 Reserved */ | |
149 | /* For CYC: Bits0:7 Reserved */ | |
150 | unsigned char WP_index; /* For WPEG: WPEG instance index - lower ones have */ | |
151 | /* lower slot numbers/PCI bus numbers */ | |
152 | /* For CYC: No meaning */ | |
153 | unsigned char chassis_num; /* 1 based Chassis number */ | |
154 | /* For LookOut WPEGs this field indicates the */ | |
155 | /* Expansion Chassis #, enumerated from Boot */ | |
156 | /* Node WPEG external port, then Boot Node CYC */ | |
157 | /* external port, then Next Vigil chassis WPEG */ | |
158 | /* external port, etc. */ | |
159 | /* Shared Lookouts have only 1 chassis number (the */ | |
160 | /* first one assigned) */ | |
161 | } __attribute__((packed)); | |
162 | ||
163 | ||
164 | typedef enum { | |
165 | CompatTwister = 0, /* Compatibility Twister */ | |
166 | AltTwister = 1, /* Alternate Twister of internal 8-way */ | |
167 | CompatCyclone = 2, /* Compatibility Cyclone */ | |
168 | AltCyclone = 3, /* Alternate Cyclone of internal 8-way */ | |
169 | CompatWPEG = 4, /* Compatibility WPEG */ | |
170 | AltWPEG = 5, /* Second Planar WPEG */ | |
171 | LookOutAWPEG = 6, /* LookOut WPEG */ | |
172 | LookOutBWPEG = 7, /* LookOut WPEG */ | |
173 | } node_type; | |
174 | ||
175 | static inline int is_WPEG(struct rio_detail *rio){ | |
176 | return (rio->type == CompatWPEG || rio->type == AltWPEG || | |
177 | rio->type == LookOutAWPEG || rio->type == LookOutBWPEG); | |
178 | } | |
179 | ||
180 | ||
181 | /* In clustered mode, the high nibble of APIC ID is a cluster number. | |
182 | * The low nibble is a 4-bit bitmap. */ | |
183 | #define XAPIC_DEST_CPUS_SHIFT 4 | |
184 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) | |
185 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) | |
186 | ||
187 | #define SUMMIT_APIC_DFR_VALUE (APIC_DFR_CLUSTER) | |
188 | ||
b5f26d05 | 189 | static const cpumask_t *summit_target_cpus(void) |
b11b867f IM |
190 | { |
191 | /* CPU_MASK_ALL (0xff) has undefined behaviour with | |
192 | * dest_LowestPrio mode logical clustered apic interrupt routing | |
193 | * Just start on cpu 0. IRQ balancing will spread load | |
194 | */ | |
4f062896 | 195 | return cpumask_of(0); |
b11b867f IM |
196 | } |
197 | ||
b5f26d05 | 198 | static unsigned long summit_check_apicid_used(physid_mask_t bitmap, int apicid) |
b11b867f IM |
199 | { |
200 | return 0; | |
201 | } | |
202 | ||
203 | /* we don't use the phys_cpu_present_map to indicate apicid presence */ | |
b5f26d05 | 204 | static unsigned long summit_check_apicid_present(int bit) |
b11b867f IM |
205 | { |
206 | return 1; | |
207 | } | |
208 | ||
b5f26d05 | 209 | static void summit_init_apic_ldr(void) |
b11b867f IM |
210 | { |
211 | unsigned long val, id; | |
212 | int count = 0; | |
213 | u8 my_id = (u8)hard_smp_processor_id(); | |
b9e0d1aa | 214 | u8 my_cluster = APIC_CLUSTER(my_id); |
b11b867f IM |
215 | #ifdef CONFIG_SMP |
216 | u8 lid; | |
217 | int i; | |
218 | ||
219 | /* Create logical APIC IDs by counting CPUs already in cluster. */ | |
220 | for (count = 0, i = nr_cpu_ids; --i >= 0; ) { | |
221 | lid = cpu_2_logical_apicid[i]; | |
b9e0d1aa | 222 | if (lid != BAD_APICID && APIC_CLUSTER(lid) == my_cluster) |
b11b867f IM |
223 | ++count; |
224 | } | |
225 | #endif | |
226 | /* We only have a 4 wide bitmap in cluster mode. If a deranged | |
227 | * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */ | |
228 | BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT); | |
229 | id = my_cluster | (1UL << count); | |
230 | apic_write(APIC_DFR, SUMMIT_APIC_DFR_VALUE); | |
231 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; | |
232 | val |= SET_APIC_LOGICAL_ID(id); | |
233 | apic_write(APIC_LDR, val); | |
234 | } | |
235 | ||
b5f26d05 | 236 | static int summit_apic_id_registered(void) |
b11b867f IM |
237 | { |
238 | return 1; | |
239 | } | |
240 | ||
b5f26d05 | 241 | static void summit_setup_apic_routing(void) |
b11b867f IM |
242 | { |
243 | printk("Enabling APIC mode: Summit. Using %d I/O APICs\n", | |
244 | nr_ioapics); | |
245 | } | |
246 | ||
b5f26d05 | 247 | static int summit_apicid_to_node(int logical_apicid) |
b11b867f IM |
248 | { |
249 | #ifdef CONFIG_SMP | |
250 | return apicid_2_node[hard_smp_processor_id()]; | |
251 | #else | |
252 | return 0; | |
253 | #endif | |
254 | } | |
255 | ||
256 | /* Mapping from cpu number to logical apicid */ | |
257 | static inline int summit_cpu_to_logical_apicid(int cpu) | |
258 | { | |
259 | #ifdef CONFIG_SMP | |
260 | if (cpu >= nr_cpu_ids) | |
261 | return BAD_APICID; | |
2f205bc4 | 262 | return cpu_2_logical_apicid[cpu]; |
b11b867f IM |
263 | #else |
264 | return logical_smp_processor_id(); | |
265 | #endif | |
266 | } | |
267 | ||
b5f26d05 | 268 | static int summit_cpu_present_to_apicid(int mps_cpu) |
b11b867f IM |
269 | { |
270 | if (mps_cpu < nr_cpu_ids) | |
271 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
272 | else | |
273 | return BAD_APICID; | |
274 | } | |
275 | ||
b5f26d05 | 276 | static physid_mask_t summit_ioapic_phys_id_map(physid_mask_t phys_id_map) |
b11b867f IM |
277 | { |
278 | /* For clustered we don't have a good way to do this yet - hack */ | |
279 | return physids_promote(0x0F); | |
280 | } | |
281 | ||
b5f26d05 | 282 | static physid_mask_t summit_apicid_to_cpu_present(int apicid) |
b11b867f IM |
283 | { |
284 | return physid_mask_of_physid(0); | |
285 | } | |
286 | ||
b5f26d05 | 287 | static int summit_check_phys_apicid_present(int boot_cpu_physical_apicid) |
b11b867f IM |
288 | { |
289 | return 1; | |
290 | } | |
291 | ||
b5f26d05 | 292 | static unsigned int summit_cpu_mask_to_apicid(const cpumask_t *cpumask) |
b11b867f | 293 | { |
fae176d6 JS |
294 | unsigned int round = 0; |
295 | int cpu, apicid = 0; | |
b11b867f | 296 | |
b11b867f | 297 | /* |
10b614ea | 298 | * The cpus in the mask must all be on the apic cluster. |
b11b867f | 299 | */ |
fae176d6 JS |
300 | for_each_cpu(cpu, cpumask) { |
301 | int new_apicid = summit_cpu_to_logical_apicid(cpu); | |
b11b867f | 302 | |
fae176d6 JS |
303 | if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { |
304 | printk("%s: Not a valid mask!\n", __func__); | |
305 | return BAD_APICID; | |
b11b867f | 306 | } |
fae176d6 JS |
307 | apicid |= new_apicid; |
308 | round++; | |
b11b867f IM |
309 | } |
310 | return apicid; | |
311 | } | |
312 | ||
b5f26d05 | 313 | static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, |
b11b867f IM |
314 | const struct cpumask *andmask) |
315 | { | |
316 | int apicid = summit_cpu_to_logical_apicid(0); | |
317 | cpumask_var_t cpumask; | |
318 | ||
319 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) | |
320 | return apicid; | |
321 | ||
322 | cpumask_and(cpumask, inmask, andmask); | |
323 | cpumask_and(cpumask, cpumask, cpu_online_mask); | |
324 | apicid = summit_cpu_mask_to_apicid(cpumask); | |
325 | ||
326 | free_cpumask_var(cpumask); | |
327 | ||
328 | return apicid; | |
329 | } | |
330 | ||
331 | /* | |
332 | * cpuid returns the value latched in the HW at reset, not the APIC ID | |
333 | * register's value. For any box whose BIOS changes APIC IDs, like | |
334 | * clustered APIC systems, we must use hard_smp_processor_id. | |
335 | * | |
336 | * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID. | |
337 | */ | |
b5f26d05 | 338 | static int summit_phys_pkg_id(int cpuid_apic, int index_msb) |
b11b867f IM |
339 | { |
340 | return hard_smp_processor_id() >> index_msb; | |
341 | } | |
342 | ||
343 | static int probe_summit(void) | |
344 | { | |
345 | /* probed later in mptable/ACPI hooks */ | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static void summit_vector_allocation_domain(int cpu, cpumask_t *retmask) | |
350 | { | |
351 | /* Careful. Some cpus do not strictly honor the set of cpus | |
352 | * specified in the interrupt destination when using lowest | |
353 | * priority interrupt delivery mode. | |
354 | * | |
355 | * In particular there was a hyperthreading cpu observed to | |
356 | * deliver interrupts to the wrong hyperthread when only one | |
357 | * hyperthread was specified in the interrupt desitination. | |
358 | */ | |
359 | *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } }; | |
360 | } | |
1da177e4 | 361 | |
7c20dcc5 | 362 | #ifdef CONFIG_X86_SUMMIT_NUMA |
2fcb1f1f JS |
363 | static struct rio_table_hdr *rio_table_hdr; |
364 | static struct scal_detail *scal_devs[MAX_NUMNODES]; | |
365 | static struct rio_detail *rio_devs[MAX_NUMNODES*4]; | |
1da177e4 | 366 | |
d49c4288 | 367 | #ifndef CONFIG_X86_NUMAQ |
2fcb1f1f | 368 | static int mp_bus_id_to_node[MAX_MP_BUSSES]; |
d49c4288 | 369 | #endif |
037cab07 | 370 | |
2fcb1f1f | 371 | static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) |
1da177e4 LT |
372 | { |
373 | int twister = 0, node = 0; | |
374 | int i, bus, num_buses; | |
375 | ||
60e11746 PC |
376 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { |
377 | if (rio_devs[i]->node_id == rio_devs[wpeg_num]->owner_id) { | |
1da177e4 LT |
378 | twister = rio_devs[i]->owner_id; |
379 | break; | |
380 | } | |
381 | } | |
60e11746 | 382 | if (i == rio_table_hdr->num_rio_dev) { |
77bf90ed | 383 | printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__); |
1da177e4 LT |
384 | return last_bus; |
385 | } | |
386 | ||
60e11746 PC |
387 | for (i = 0; i < rio_table_hdr->num_scal_dev; i++) { |
388 | if (scal_devs[i]->node_id == twister) { | |
1da177e4 LT |
389 | node = scal_devs[i]->node_id; |
390 | break; | |
391 | } | |
392 | } | |
60e11746 | 393 | if (i == rio_table_hdr->num_scal_dev) { |
77bf90ed | 394 | printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__); |
1da177e4 LT |
395 | return last_bus; |
396 | } | |
397 | ||
60e11746 | 398 | switch (rio_devs[wpeg_num]->type) { |
1da177e4 | 399 | case CompatWPEG: |
60e11746 PC |
400 | /* |
401 | * The Compatibility Winnipeg controls the 2 legacy buses, | |
1da177e4 LT |
402 | * the 66MHz PCI bus [2 slots] and the 2 "extra" buses in case |
403 | * a PCI-PCI bridge card is used in either slot: total 5 buses. | |
404 | */ | |
405 | num_buses = 5; | |
406 | break; | |
407 | case AltWPEG: | |
60e11746 PC |
408 | /* |
409 | * The Alternate Winnipeg controls the 2 133MHz buses [1 slot | |
1da177e4 LT |
410 | * each], their 2 "extra" buses, the 100MHz bus [2 slots] and |
411 | * the "extra" buses for each of those slots: total 7 buses. | |
412 | */ | |
413 | num_buses = 7; | |
414 | break; | |
415 | case LookOutAWPEG: | |
416 | case LookOutBWPEG: | |
60e11746 PC |
417 | /* |
418 | * A Lookout Winnipeg controls 3 100MHz buses [2 slots each] | |
1da177e4 LT |
419 | * & the "extra" buses for each of those slots: total 9 buses. |
420 | */ | |
421 | num_buses = 9; | |
422 | break; | |
423 | default: | |
77bf90ed | 424 | printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__); |
1da177e4 LT |
425 | return last_bus; |
426 | } | |
427 | ||
60e11746 | 428 | for (bus = last_bus; bus < last_bus + num_buses; bus++) |
1da177e4 LT |
429 | mp_bus_id_to_node[bus] = node; |
430 | return bus; | |
431 | } | |
432 | ||
2fcb1f1f | 433 | static int build_detail_arrays(void) |
1da177e4 LT |
434 | { |
435 | unsigned long ptr; | |
436 | int i, scal_detail_size, rio_detail_size; | |
437 | ||
60e11746 | 438 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) { |
77bf90ed | 439 | printk(KERN_WARNING "%s: MAX_NUMNODES too low! Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev); |
1da177e4 LT |
440 | return 0; |
441 | } | |
442 | ||
60e11746 | 443 | switch (rio_table_hdr->version) { |
1da177e4 | 444 | default: |
77bf90ed | 445 | printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version); |
1da177e4 LT |
446 | return 0; |
447 | case 2: | |
448 | scal_detail_size = 11; | |
449 | rio_detail_size = 13; | |
450 | break; | |
451 | case 3: | |
452 | scal_detail_size = 12; | |
453 | rio_detail_size = 15; | |
454 | break; | |
455 | } | |
456 | ||
457 | ptr = (unsigned long)rio_table_hdr + 3; | |
60e11746 | 458 | for (i = 0; i < rio_table_hdr->num_scal_dev; i++, ptr += scal_detail_size) |
1da177e4 LT |
459 | scal_devs[i] = (struct scal_detail *)ptr; |
460 | ||
60e11746 | 461 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++, ptr += rio_detail_size) |
1da177e4 LT |
462 | rio_devs[i] = (struct rio_detail *)ptr; |
463 | ||
464 | return 1; | |
465 | } | |
466 | ||
2fcb1f1f | 467 | void setup_summit(void) |
1da177e4 LT |
468 | { |
469 | unsigned long ptr; | |
470 | unsigned short offset; | |
471 | int i, next_wpeg, next_bus = 0; | |
472 | ||
473 | /* The pointer to the EBDA is stored in the word @ phys 0x40E(40:0E) */ | |
356fa0c6 AM |
474 | ptr = get_bios_ebda(); |
475 | ptr = (unsigned long)phys_to_virt(ptr); | |
1da177e4 LT |
476 | |
477 | rio_table_hdr = NULL; | |
478 | offset = 0x180; | |
60e11746 | 479 | while (offset) { |
1da177e4 | 480 | /* The block id is stored in the 2nd word */ |
60e11746 | 481 | if (*((unsigned short *)(ptr + offset + 2)) == 0x4752) { |
1da177e4 LT |
482 | /* set the pointer past the offset & block id */ |
483 | rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4); | |
484 | break; | |
485 | } | |
486 | /* The next offset is stored in the 1st word. 0 means no more */ | |
487 | offset = *((unsigned short *)(ptr + offset)); | |
488 | } | |
60e11746 | 489 | if (!rio_table_hdr) { |
77bf90ed | 490 | printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__); |
1da177e4 LT |
491 | return; |
492 | } | |
493 | ||
494 | if (!build_detail_arrays()) | |
495 | return; | |
496 | ||
497 | /* The first Winnipeg we're looking for has an index of 0 */ | |
498 | next_wpeg = 0; | |
499 | do { | |
60e11746 PC |
500 | for (i = 0; i < rio_table_hdr->num_rio_dev; i++) { |
501 | if (is_WPEG(rio_devs[i]) && rio_devs[i]->WP_index == next_wpeg) { | |
1da177e4 LT |
502 | /* It's the Winnipeg we're looking for! */ |
503 | next_bus = setup_pci_node_map_for_wpeg(i, next_bus); | |
504 | next_wpeg++; | |
505 | break; | |
506 | } | |
507 | } | |
508 | /* | |
509 | * If we go through all Rio devices and don't find one with | |
510 | * the next index, it means we've found all the Winnipegs, | |
511 | * and thus all the PCI buses. | |
512 | */ | |
513 | if (i == rio_table_hdr->num_rio_dev) | |
514 | next_wpeg = 0; | |
515 | } while (next_wpeg != 0); | |
516 | } | |
7c20dcc5 | 517 | #endif |
b11b867f | 518 | |
be163a15 | 519 | struct apic apic_summit = { |
b11b867f IM |
520 | |
521 | .name = "summit", | |
522 | .probe = probe_summit, | |
523 | .acpi_madt_oem_check = summit_acpi_madt_oem_check, | |
524 | .apic_id_registered = summit_apic_id_registered, | |
525 | ||
526 | .irq_delivery_mode = dest_LowestPrio, | |
527 | /* logical delivery broadcast to all CPUs: */ | |
528 | .irq_dest_mode = 1, | |
529 | ||
530 | .target_cpus = summit_target_cpus, | |
531 | .disable_esr = 1, | |
532 | .dest_logical = APIC_DEST_LOGICAL, | |
533 | .check_apicid_used = summit_check_apicid_used, | |
534 | .check_apicid_present = summit_check_apicid_present, | |
535 | ||
536 | .vector_allocation_domain = summit_vector_allocation_domain, | |
537 | .init_apic_ldr = summit_init_apic_ldr, | |
538 | ||
539 | .ioapic_phys_id_map = summit_ioapic_phys_id_map, | |
540 | .setup_apic_routing = summit_setup_apic_routing, | |
541 | .multi_timer_check = NULL, | |
542 | .apicid_to_node = summit_apicid_to_node, | |
543 | .cpu_to_logical_apicid = summit_cpu_to_logical_apicid, | |
544 | .cpu_present_to_apicid = summit_cpu_present_to_apicid, | |
545 | .apicid_to_cpu_present = summit_apicid_to_cpu_present, | |
546 | .setup_portio_remap = NULL, | |
547 | .check_phys_apicid_present = summit_check_phys_apicid_present, | |
548 | .enable_apic_mode = NULL, | |
549 | .phys_pkg_id = summit_phys_pkg_id, | |
550 | .mps_oem_check = summit_mps_oem_check, | |
551 | ||
552 | .get_apic_id = summit_get_apic_id, | |
553 | .set_apic_id = NULL, | |
554 | .apic_id_mask = 0xFF << 24, | |
555 | ||
556 | .cpu_mask_to_apicid = summit_cpu_mask_to_apicid, | |
557 | .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and, | |
558 | ||
559 | .send_IPI_mask = summit_send_IPI_mask, | |
560 | .send_IPI_mask_allbutself = NULL, | |
561 | .send_IPI_allbutself = summit_send_IPI_allbutself, | |
562 | .send_IPI_all = summit_send_IPI_all, | |
6b64ee02 | 563 | .send_IPI_self = default_send_IPI_self, |
b11b867f | 564 | |
b11b867f IM |
565 | .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, |
566 | .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, | |
567 | ||
568 | .wait_for_init_deassert = default_wait_for_init_deassert, | |
569 | ||
570 | .smp_callin_clear_local_apic = NULL, | |
b11b867f | 571 | .inquire_remote_apic = default_inquire_remote_apic, |
c1eeb2de YL |
572 | |
573 | .read = native_apic_mem_read, | |
574 | .write = native_apic_mem_write, | |
575 | .icr_read = native_apic_icr_read, | |
576 | .icr_write = native_apic_icr_write, | |
577 | .wait_icr_idle = native_apic_wait_icr_idle, | |
578 | .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, | |
b11b867f | 579 | }; |