[linux-2.6-block.git] / arch / x86 / include / asm / uv / uv_hub.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * SGI UV architectural definitions
 *
 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
 */

#ifndef _ASM_X86_UV_UV_HUB_H
#define _ASM_X86_UV_UV_HUB_H

#include <linux/numa.h>
#include <linux/percpu.h>
#include <linux/timer.h>
#include <asm/types.h>
#include <asm/percpu.h>


/*
 * Addressing Terminology
 *
 *	M       - The low M bits of a physical address represent the offset
 *		  into the blade local memory. RAM memory on a blade is physically
 *		  contiguous (although various IO spaces may punch holes in
 *		  it)..
 *
 * 	N	- Number of bits in the node portion of a socket physical
 * 		  address.
 *
 * 	NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
 * 	 	  routers always have low bit of 1, C/MBricks have low bit
 * 		  equal to 0. Most addressing macros that target UV hub chips
 * 		  right shift the NASID by 1 to exclude the always-zero bit.
 * 		  NASIDs contain up to 15 bits.
 *
 *	GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
 *		  of nasids.
 *
 * 	PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
 * 		  of the nasid for socket usage.
 *
 *
 *  NumaLink Global Physical Address Format:
 *  +--------------------------------+---------------------+
 *  |00..000|      GNODE             |      NodeOffset     |
 *  +--------------------------------+---------------------+
 *          |<-------53 - M bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *
 *
 *  Memory/UV-HUB Processor Socket Address Format:
 *  +----------------+---------------+---------------------+
 *  |00..000000000000|   PNODE       |      NodeOffset     |
 *  +----------------+---------------+---------------------+
 *                   <--- N bits --->|<--------M bits ----->
 *
 *	M - number of node offset bits (35 .. 40)
 *	N - number of PNODE bits (0 .. 10)
 *
 *		Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
 *		The actual values are configuration dependent and are set at
 *		boot time. M & N values are set by the hardware/BIOS at boot.
 *
 *
 * APICID format
 * 	NOTE!!!!!! This is the current format of the APICID. However, code
 * 	should assume that this will change in the future. Use functions
 * 	in this file for all APICID bit manipulations and conversion.
 *
 * 		1111110000000000
 * 		5432109876543210
 *		pppppppppplc0cch
 *		sssssssssss
 *
 *			p  = pnode bits
 *			l =  socket number on board
 *			c  = core
 *			h  = hyperthread
 *			s  = bits that are in the SOCKET_ID CSR
 *
 *	Note: Processor only supports 12 bits in the APICID register. The ACPI
 *	      tables hold all 16 bits. Software needs to be aware of this.
 *
 * 	      Unless otherwise specified, all references to APICID refer to
 * 	      the FULL value contained in ACPI tables, not the subset in the
 * 	      processor APICID register.
 */


/*
 * Maximum number of bricks in all partitions and in all coherency domains.
 * This is the total number of bricks accessible in the numalink fabric. It
 * includes all C & M bricks. Routers are NOT included.
 *
 * This value is also the value of the maximum number of non-router NASIDs
 * in the numalink fabric.
 *
 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
 */
#define UV_MAX_NUMALINK_BLADES	16384

/*
 * Maximum number of C/Mbricks within a software SSI (hardware may support
 * more).
 */
#define UV_MAX_SSI_BLADES	256

/*
 * The largest possible NASID of a C or M brick (+ 2)
 */
#define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_NODES * 2)

struct uv_scir_s {
	struct timer_list timer;
	unsigned long	offset;
	unsigned long	last;
	unsigned long	idle_on;
	unsigned long	idle_off;
	unsigned char	state;
	unsigned char	enabled;
};

/*
 * The following defines attributes of the HUB chip. These attributes are
 * frequently referenced and are kept in the per-cpu data areas of each cpu.
 * They are kept together in a struct to minimize cache misses.
 */
struct uv_hub_info_s {
	unsigned long		global_mmr_base;
	unsigned long		gpa_mask;
	unsigned long		gnode_upper;
	unsigned long		lowmem_remap_top;
	unsigned long		lowmem_remap_base;
	unsigned short		pnode;
	unsigned short		pnode_mask;
	unsigned short		coherency_domain_number;
	unsigned short		numa_blade_id;
	unsigned char		blade_processor_id;
	unsigned char		m_val;
	unsigned char		n_val;
	struct uv_scir_s	scir;
};

DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
#define uv_hub_info 		(&__get_cpu_var(__uv_hub_info))
#define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))

/*
 * Local & Global MMR space macros.
 * 	Note: macros are intended to be used ONLY by inline functions
 * 	in this file - not by other kernel code.
 * 		n -  NASID (full 15-bit global nasid)
 * 		g -  GNODE (full 15-bit global nasid, right shifted 1)
 * 		p -  PNODE (local part of nsids, right shifted 1)
 */
#define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
#define UV_PNODE_TO_NASID(p)		(((p) << 1) | uv_hub_info->gnode_upper)

#define UV_LOCAL_MMR_BASE		0xf4000000UL
#define UV_GLOBAL_MMR32_BASE		0xf8000000UL
#define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
#define UV_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
#define UV_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)

#define UV_GLOBAL_MMR32_PNODE_SHIFT	15
#define UV_GLOBAL_MMR64_PNODE_SHIFT	26

#define UV_GLOBAL_MMR32_PNODE_BITS(p)	((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))

#define UV_GLOBAL_MMR64_PNODE_BITS(p)					\
	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)

#define UV_APIC_PNODE_SHIFT	6

/* Local Bus from cpu's perspective */
#define LOCAL_BUS_BASE		0x1c00000
#define LOCAL_BUS_SIZE		(4 * 1024 * 1024)

/*
 * System Controller Interface Reg
 *
 * Note there are NO leds on a UV system.  This register is only
 * used by the system controller to monitor system-wide operation.
 * There are 64 regs per node.  With Nahelem cpus (2 cores per node,
 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
 * a node.
 *
 * The window is located at top of ACPI MMR space
 */
#define SCIR_WINDOW_COUNT	64
#define SCIR_LOCAL_MMR_BASE	(LOCAL_BUS_BASE + \
				 LOCAL_BUS_SIZE - \
				 SCIR_WINDOW_COUNT)

#define SCIR_CPU_HEARTBEAT	0x01	/* timer interrupt */
#define SCIR_CPU_ACTIVITY	0x02	/* not idle */
#define SCIR_CPU_HB_INTERVAL	(HZ)	/* once per second */

/*
 * Macros for converting between kernel virtual addresses, socket local physical
 * addresses, and UV global physical addresses.
 * 	Note: use the standard __pa() & __va() macros for converting
 * 	      between socket virtual and socket physical addresses.
 */

/* socket phys RAM --> UV global physical address */
static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
{
	if (paddr < uv_hub_info->lowmem_remap_top)
		paddr |= uv_hub_info->lowmem_remap_base;
	return paddr | uv_hub_info->gnode_upper;
}


/* socket virtual --> UV global physical address */
static inline unsigned long uv_gpa(void *v)
{
	return uv_soc_phys_ram_to_gpa(__pa(v));
}

/* pnode, offset --> socket virtual */
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
{
	return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
}


/*
 * Extract a PNODE from an APICID (full apicid, not processor subset)
 */
static inline int uv_apicid_to_pnode(int apicid)
{
	return (apicid >> UV_APIC_PNODE_SHIFT);
}

/*
 * Access global MMRs using the low memory MMR32 space. This region supports
 * faster MMR access but not all MMRs are accessible in this space.
 */
static inline unsigned long *uv_global_mmr32_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR32_BASE |
		       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
				 unsigned long val)
{
	*uv_global_mmr32_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr32(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr32_address(pnode, offset);
}

/*
 * Access Global MMR space using the MMR space located at the top of physical
 * memory.
 */
static inline unsigned long *uv_global_mmr64_address(int pnode,
				unsigned long offset)
{
	return __va(UV_GLOBAL_MMR64_BASE |
		    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
}

static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
				unsigned long val)
{
	*uv_global_mmr64_address(pnode, offset) = val;
}

static inline unsigned long uv_read_global_mmr64(int pnode,
						 unsigned long offset)
{
	return *uv_global_mmr64_address(pnode, offset);
}

/*
 * Access hub local MMRs. Faster than using global space but only local MMRs
 * are accessible.
 */
static inline unsigned long *uv_local_mmr_address(unsigned long offset)
{
	return __va(UV_LOCAL_MMR_BASE | offset);
}

static inline unsigned long uv_read_local_mmr(unsigned long offset)
{
	return *uv_local_mmr_address(offset);
}

static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
{
	*uv_local_mmr_address(offset) = val;
}

static inline unsigned char uv_read_local_mmr8(unsigned long offset)
{
	return *((unsigned char *)uv_local_mmr_address(offset));
}

static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
{
	*((unsigned char *)uv_local_mmr_address(offset)) = val;
}

/*
 * Structures and definitions for converting between cpu, node, pnode, and blade
 * numbers.
 */
struct uv_blade_info {
	unsigned short	nr_possible_cpus;
	unsigned short	nr_online_cpus;
	unsigned short	pnode;
};
extern struct uv_blade_info *uv_blade_info;
extern short *uv_node_to_blade;
extern short *uv_cpu_to_blade;
extern short uv_possible_blades;

/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
static inline int uv_blade_processor_id(void)
{
	return uv_hub_info->blade_processor_id;
}

/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
static inline int uv_numa_blade_id(void)
{
	return uv_hub_info->numa_blade_id;
}

/* Convert a cpu number to the the UV blade number */
static inline int uv_cpu_to_blade_id(int cpu)
{
	return uv_cpu_to_blade[cpu];
}

/* Convert linux node number to the UV blade number */
static inline int uv_node_to_blade_id(int nid)
{
	return uv_node_to_blade[nid];
}

/* Convert a blade id to the PNODE of the blade */
static inline int uv_blade_to_pnode(int bid)
{
	return uv_blade_info[bid].pnode;
}

/* Determine the number of possible cpus on a blade */
static inline int uv_blade_nr_possible_cpus(int bid)
{
	return uv_blade_info[bid].nr_possible_cpus;
}

/* Determine the number of online cpus on a blade */
static inline int uv_blade_nr_online_cpus(int bid)
{
	return uv_blade_info[bid].nr_online_cpus;
}

/* Convert a cpu id to the PNODE of the blade containing the cpu */
static inline int uv_cpu_to_pnode(int cpu)
{
	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
}

/* Convert a linux node number to the PNODE of the blade */
static inline int uv_node_to_pnode(int nid)
{
	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
}

/* Maximum possible number of blades */
static inline int uv_num_possible_blades(void)
{
	return uv_possible_blades;
}

/* Update SCIR state */
static inline void uv_set_scir_bits(unsigned char value)
{
	if (uv_hub_info->scir.state != value) {
		uv_hub_info->scir.state = value;
		uv_write_local_mmr8(uv_hub_info->scir.offset, value);
	}
}
static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
{
	if (uv_cpu_hub_info(cpu)->scir.state != value) {
		uv_cpu_hub_info(cpu)->scir.state = value;
		uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
	}
}

#endif /* _ASM_X86_UV_UV_HUB_H */
Commit	Line	Data
952cf6d7 JS	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* SGI UV architectural definitions
	7	*
9f5314fb	8	* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
952cf6d7 JS	9	*/
952cf6d7 JS	10
05e4d316 PA	11	#ifndef _ASM_X86_UV_UV_HUB_H
05e4d316 PA	12	#define _ASM_X86_UV_UV_HUB_H
952cf6d7 JS	13
	14	#include <linux/numa.h>
	15	#include <linux/percpu.h>
c08b6acc	16	#include <linux/timer.h>
952cf6d7 JS	17	#include <asm/types.h>
	18	#include <asm/percpu.h>
	19
	20
	21	/*
	22	* Addressing Terminology
	23	*
9f5314fb JS	24	* M - The low M bits of a physical address represent the offset
	25	* into the blade local memory. RAM memory on a blade is physically
	26	* contiguous (although various IO spaces may punch holes in
	27	* it)..
952cf6d7	28	*
9f5314fb JS	29	* N - Number of bits in the node portion of a socket physical
	30	* address.
	31	*
	32	* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
	33	* routers always have low bit of 1, C/MBricks have low bit
	34	* equal to 0. Most addressing macros that target UV hub chips
	35	* right shift the NASID by 1 to exclude the always-zero bit.
	36	* NASIDs contain up to 15 bits.
	37	*
	38	* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
	39	* of nasids.
	40	*
	41	* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
	42	* of the nasid for socket usage.
	43	*
	44	*
	45	* NumaLink Global Physical Address Format:
	46	* +--------------------------------+---------------------+
	47	* \|00..000\| GNODE \| NodeOffset \|
	48	* +--------------------------------+---------------------+
	49	* \|<-------53 - M bits --->\|<--------M bits ----->
	50	*
	51	* M - number of node offset bits (35 .. 40)
952cf6d7 JS	52	*
	53	*
	54	* Memory/UV-HUB Processor Socket Address Format:
9f5314fb JS	55	* +----------------+---------------+---------------------+
	56	* \|00..000000000000\| PNODE \| NodeOffset \|
	57	* +----------------+---------------+---------------------+
	58	* <--- N bits --->\|<--------M bits ----->
952cf6d7	59	*
9f5314fb JS	60	* M - number of node offset bits (35 .. 40)
9f5314fb JS	61	* N - number of PNODE bits (0 .. 10)
952cf6d7 JS	62	*
	63	* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
	64	* The actual values are configuration dependent and are set at
9f5314fb JS	65	* boot time. M & N values are set by the hardware/BIOS at boot.
9f5314fb JS	66	*
952cf6d7 JS	67	*
	68	* APICID format
	69	* NOTE!!!!!! This is the current format of the APICID. However, code
	70	* should assume that this will change in the future. Use functions
	71	* in this file for all APICID bit manipulations and conversion.
	72	*
	73	* 1111110000000000
	74	* 5432109876543210
9f5314fb	75	* pppppppppplc0cch
952cf6d7 JS	76	* sssssssssss
952cf6d7 JS	77	*
9f5314fb	78	* p = pnode bits
952cf6d7 JS	79	* l = socket number on board
	80	* c = core
	81	* h = hyperthread
9f5314fb	82	* s = bits that are in the SOCKET_ID CSR
952cf6d7 JS	83	*
	84	* Note: Processor only supports 12 bits in the APICID register. The ACPI
	85	* tables hold all 16 bits. Software needs to be aware of this.
	86	*
	87	* Unless otherwise specified, all references to APICID refer to
	88	* the FULL value contained in ACPI tables, not the subset in the
	89	* processor APICID register.
	90	*/
	91
	92
	93	/*
	94	* Maximum number of bricks in all partitions and in all coherency domains.
	95	* This is the total number of bricks accessible in the numalink fabric. It
	96	* includes all C & M bricks. Routers are NOT included.
	97	*
	98	* This value is also the value of the maximum number of non-router NASIDs
	99	* in the numalink fabric.
	100	*
9f5314fb	101	* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
952cf6d7 JS	102	*/
	103	#define UV_MAX_NUMALINK_BLADES 16384
	104
	105	/*
	106	* Maximum number of C/Mbricks within a software SSI (hardware may support
	107	* more).
	108	*/
	109	#define UV_MAX_SSI_BLADES 256
	110
	111	/*
	112	* The largest possible NASID of a C or M brick (+ 2)
	113	*/
	114	#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2)
	115
7f1baa06 MT	116	struct uv_scir_s {
	117	struct timer_list timer;
	118	unsigned long offset;
	119	unsigned long last;
	120	unsigned long idle_on;
	121	unsigned long idle_off;
	122	unsigned char state;
	123	unsigned char enabled;
	124	};
	125
952cf6d7 JS	126	/*
	127	* The following defines attributes of the HUB chip. These attributes are
	128	* frequently referenced and are kept in the per-cpu data areas of each cpu.
	129	* They are kept together in a struct to minimize cache misses.
	130	*/
	131	struct uv_hub_info_s {
69a72a0e MT	132	unsigned long global_mmr_base;
	133	unsigned long gpa_mask;
	134	unsigned long gnode_upper;
	135	unsigned long lowmem_remap_top;
	136	unsigned long lowmem_remap_base;
	137	unsigned short pnode;
	138	unsigned short pnode_mask;
	139	unsigned short coherency_domain_number;
	140	unsigned short numa_blade_id;
	141	unsigned char blade_processor_id;
	142	unsigned char m_val;
	143	unsigned char n_val;
	144	struct uv_scir_s scir;
952cf6d7	145	};
7f1baa06	146
952cf6d7 JS	147	DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
	148	#define uv_hub_info (&__get_cpu_var(__uv_hub_info))
	149	#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu))
	150
	151	/*
	152	* Local & Global MMR space macros.
	153	* Note: macros are intended to be used ONLY by inline functions
	154	* in this file - not by other kernel code.
9f5314fb JS	155	* n - NASID (full 15-bit global nasid)
	156	* g - GNODE (full 15-bit global nasid, right shifted 1)
	157	* p - PNODE (local part of nsids, right shifted 1)
952cf6d7	158	*/
9f5314fb JS	159	#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
9f5314fb JS	160	#define UV_PNODE_TO_NASID(p) (((p) << 1) \| uv_hub_info->gnode_upper)
952cf6d7 JS	161
	162	#define UV_LOCAL_MMR_BASE 0xf4000000UL
	163	#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
	164	#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
83f5d894 JS	165	#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
83f5d894 JS	166	#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
952cf6d7	167
9f5314fb JS	168	#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
9f5314fb JS	169	#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
952cf6d7	170
9f5314fb	171	#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
952cf6d7	172
9f5314fb JS	173	#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
	174	((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
	175
	176	#define UV_APIC_PNODE_SHIFT 6
	177
7f1baa06 MT	178	/* Local Bus from cpu's perspective */
	179	#define LOCAL_BUS_BASE 0x1c00000
	180	#define LOCAL_BUS_SIZE (4 * 1024 * 1024)
	181
	182	/*
	183	* System Controller Interface Reg
	184	*
	185	* Note there are NO leds on a UV system. This register is only
	186	* used by the system controller to monitor system-wide operation.
	187	* There are 64 regs per node. With Nahelem cpus (2 cores per node,
	188	* 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
	189	* a node.
	190	*
	191	* The window is located at top of ACPI MMR space
	192	*/
	193	#define SCIR_WINDOW_COUNT 64
	194	#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
	195	LOCAL_BUS_SIZE - \
	196	SCIR_WINDOW_COUNT)
	197
	198	#define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */
	199	#define SCIR_CPU_ACTIVITY 0x02 /* not idle */
	200	#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */
	201
9f5314fb JS	202	/*
	203	* Macros for converting between kernel virtual addresses, socket local physical
	204	* addresses, and UV global physical addresses.
	205	* Note: use the standard __pa() & __va() macros for converting
	206	* between socket virtual and socket physical addresses.
	207	*/
	208
	209	/* socket phys RAM --> UV global physical address */
	210	static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
	211	{
	212	if (paddr < uv_hub_info->lowmem_remap_top)
189f67c4	213	paddr \|= uv_hub_info->lowmem_remap_base;
9f5314fb JS	214	return paddr \| uv_hub_info->gnode_upper;
	215	}
	216
	217
	218	/* socket virtual --> UV global physical address */
	219	static inline unsigned long uv_gpa(void *v)
	220	{
189f67c4	221	return uv_soc_phys_ram_to_gpa(__pa(v));
9f5314fb JS	222	}
	223
	224	/* pnode, offset --> socket virtual */
	225	static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
	226	{
	227	return __va(((unsigned long)pnode << uv_hub_info->m_val) \| offset);
	228	}
952cf6d7	229
952cf6d7 JS	230
952cf6d7 JS	231	/*
9f5314fb	232	* Extract a PNODE from an APICID (full apicid, not processor subset)
952cf6d7	233	*/
9f5314fb	234	static inline int uv_apicid_to_pnode(int apicid)
952cf6d7	235	{
9f5314fb	236	return (apicid >> UV_APIC_PNODE_SHIFT);
952cf6d7 JS	237	}
	238
	239	/*
	240	* Access global MMRs using the low memory MMR32 space. This region supports
	241	* faster MMR access but not all MMRs are accessible in this space.
	242	*/
9f5314fb	243	static inline unsigned long *uv_global_mmr32_address(int pnode,
952cf6d7 JS	244	unsigned long offset)
	245	{
	246	return __va(UV_GLOBAL_MMR32_BASE \|
9f5314fb	247	UV_GLOBAL_MMR32_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	248	}
952cf6d7 JS	249
9f5314fb	250	static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
952cf6d7 JS	251	unsigned long val)
952cf6d7 JS	252	{
9f5314fb	253	*uv_global_mmr32_address(pnode, offset) = val;
952cf6d7 JS	254	}
952cf6d7 JS	255
9f5314fb	256	static inline unsigned long uv_read_global_mmr32(int pnode,
952cf6d7 JS	257	unsigned long offset)
952cf6d7 JS	258	{
9f5314fb	259	return *uv_global_mmr32_address(pnode, offset);
952cf6d7 JS	260	}
	261
	262	/*
	263	* Access Global MMR space using the MMR space located at the top of physical
	264	* memory.
	265	*/
9f5314fb	266	static inline unsigned long *uv_global_mmr64_address(int pnode,
952cf6d7 JS	267	unsigned long offset)
	268	{
	269	return __va(UV_GLOBAL_MMR64_BASE \|
9f5314fb	270	UV_GLOBAL_MMR64_PNODE_BITS(pnode) \| offset);
952cf6d7 JS	271	}
952cf6d7 JS	272
9f5314fb	273	static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
952cf6d7 JS	274	unsigned long val)
952cf6d7 JS	275	{
9f5314fb	276	*uv_global_mmr64_address(pnode, offset) = val;
952cf6d7 JS	277	}
952cf6d7 JS	278
9f5314fb	279	static inline unsigned long uv_read_global_mmr64(int pnode,
952cf6d7 JS	280	unsigned long offset)
952cf6d7 JS	281	{
9f5314fb	282	return *uv_global_mmr64_address(pnode, offset);
952cf6d7 JS	283	}
	284
	285	/*
9f5314fb	286	* Access hub local MMRs. Faster than using global space but only local MMRs
952cf6d7 JS	287	* are accessible.
	288	*/
	289	static inline unsigned long *uv_local_mmr_address(unsigned long offset)
	290	{
	291	return __va(UV_LOCAL_MMR_BASE \| offset);
	292	}
	293
	294	static inline unsigned long uv_read_local_mmr(unsigned long offset)
	295	{
	296	return *uv_local_mmr_address(offset);
	297	}
	298
	299	static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
	300	{
	301	*uv_local_mmr_address(offset) = val;
	302	}
	303
7f1baa06 MT	304	static inline unsigned char uv_read_local_mmr8(unsigned long offset)
	305	{
	306	return ((unsigned char )uv_local_mmr_address(offset));
	307	}
	308
	309	static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
	310	{
	311	((unsigned char )uv_local_mmr_address(offset)) = val;
	312	}
	313
8400def8	314	/*
9f5314fb	315	* Structures and definitions for converting between cpu, node, pnode, and blade
8400def8 JS	316	* numbers.
	317	*/
	318	struct uv_blade_info {
9f5314fb	319	unsigned short nr_possible_cpus;
8400def8	320	unsigned short nr_online_cpus;
9f5314fb	321	unsigned short pnode;
8400def8	322	};
9f5314fb	323	extern struct uv_blade_info *uv_blade_info;
8400def8 JS	324	extern short *uv_node_to_blade;
	325	extern short *uv_cpu_to_blade;
	326	extern short uv_possible_blades;
	327
	328	/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
	329	static inline int uv_blade_processor_id(void)
	330	{
	331	return uv_hub_info->blade_processor_id;
	332	}
	333
	334	/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
	335	static inline int uv_numa_blade_id(void)
	336	{
	337	return uv_hub_info->numa_blade_id;
	338	}
	339
	340	/* Convert a cpu number to the the UV blade number */
	341	static inline int uv_cpu_to_blade_id(int cpu)
	342	{
	343	return uv_cpu_to_blade[cpu];
	344	}
	345
	346	/* Convert linux node number to the UV blade number */
	347	static inline int uv_node_to_blade_id(int nid)
	348	{
	349	return uv_node_to_blade[nid];
	350	}
	351
9f5314fb JS	352	/* Convert a blade id to the PNODE of the blade */
9f5314fb JS	353	static inline int uv_blade_to_pnode(int bid)
8400def8	354	{
9f5314fb	355	return uv_blade_info[bid].pnode;
8400def8 JS	356	}
	357
	358	/* Determine the number of possible cpus on a blade */
	359	static inline int uv_blade_nr_possible_cpus(int bid)
	360	{
9f5314fb	361	return uv_blade_info[bid].nr_possible_cpus;
8400def8 JS	362	}
	363
	364	/* Determine the number of online cpus on a blade */
	365	static inline int uv_blade_nr_online_cpus(int bid)
	366	{
	367	return uv_blade_info[bid].nr_online_cpus;
	368	}
	369
9f5314fb JS	370	/* Convert a cpu id to the PNODE of the blade containing the cpu */
9f5314fb JS	371	static inline int uv_cpu_to_pnode(int cpu)
8400def8	372	{
9f5314fb	373	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
8400def8 JS	374	}
8400def8 JS	375
9f5314fb JS	376	/* Convert a linux node number to the PNODE of the blade */
9f5314fb JS	377	static inline int uv_node_to_pnode(int nid)
8400def8	378	{
9f5314fb	379	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
8400def8 JS	380	}
	381
	382	/* Maximum possible number of blades */
	383	static inline int uv_num_possible_blades(void)
	384	{
	385	return uv_possible_blades;
	386	}
	387
7f1baa06 MT	388	/* Update SCIR state */
	389	static inline void uv_set_scir_bits(unsigned char value)
	390	{
	391	if (uv_hub_info->scir.state != value) {
	392	uv_hub_info->scir.state = value;
	393	uv_write_local_mmr8(uv_hub_info->scir.offset, value);
	394	}
	395	}
	396	static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
	397	{
	398	if (uv_cpu_hub_info(cpu)->scir.state != value) {
	399	uv_cpu_hub_info(cpu)->scir.state = value;
	400	uv_write_local_mmr8(uv_cpu_hub_info(cpu)->scir.offset, value);
	401	}
	402	}
952cf6d7	403
7f1baa06	404	#endif /* _ASM_X86_UV_UV_HUB_H */