Commit | Line | Data |
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952cf6d7 JS |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * SGI UV architectural definitions | |
7 | * | |
5f40f7d9 | 8 | * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
952cf6d7 JS |
9 | */ |
10 | ||
05e4d316 PA |
11 | #ifndef _ASM_X86_UV_UV_HUB_H |
12 | #define _ASM_X86_UV_UV_HUB_H | |
952cf6d7 | 13 | |
bc5d9940 | 14 | #ifdef CONFIG_X86_64 |
952cf6d7 JS |
15 | #include <linux/numa.h> |
16 | #include <linux/percpu.h> | |
c08b6acc | 17 | #include <linux/timer.h> |
8dc579e8 | 18 | #include <linux/io.h> |
952cf6d7 JS |
19 | #include <asm/types.h> |
20 | #include <asm/percpu.h> | |
66666e50 | 21 | #include <asm/uv/uv_mmrs.h> |
02dd0a06 RH |
22 | #include <asm/irq_vectors.h> |
23 | #include <asm/io_apic.h> | |
952cf6d7 JS |
24 | |
25 | ||
26 | /* | |
27 | * Addressing Terminology | |
28 | * | |
9f5314fb JS |
29 | * M - The low M bits of a physical address represent the offset |
30 | * into the blade local memory. RAM memory on a blade is physically | |
31 | * contiguous (although various IO spaces may punch holes in | |
32 | * it).. | |
952cf6d7 | 33 | * |
39d30770 MT |
34 | * N - Number of bits in the node portion of a socket physical |
35 | * address. | |
9f5314fb | 36 | * |
39d30770 MT |
37 | * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of |
38 | * routers always have low bit of 1, C/MBricks have low bit | |
39 | * equal to 0. Most addressing macros that target UV hub chips | |
40 | * right shift the NASID by 1 to exclude the always-zero bit. | |
41 | * NASIDs contain up to 15 bits. | |
9f5314fb JS |
42 | * |
43 | * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead | |
44 | * of nasids. | |
45 | * | |
39d30770 MT |
46 | * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant |
47 | * of the nasid for socket usage. | |
9f5314fb | 48 | * |
6a469e46 JS |
49 | * GPA - (global physical address) a socket physical address converted |
50 | * so that it can be used by the GRU as a global address. Socket | |
51 | * physical addresses 1) need additional NASID (node) bits added | |
52 | * to the high end of the address, and 2) unaliased if the | |
53 | * partition does not have a physical address 0. In addition, on | |
54 | * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. | |
55 | * | |
9f5314fb JS |
56 | * |
57 | * NumaLink Global Physical Address Format: | |
58 | * +--------------------------------+---------------------+ | |
59 | * |00..000| GNODE | NodeOffset | | |
60 | * +--------------------------------+---------------------+ | |
61 | * |<-------53 - M bits --->|<--------M bits -----> | |
62 | * | |
63 | * M - number of node offset bits (35 .. 40) | |
952cf6d7 JS |
64 | * |
65 | * | |
66 | * Memory/UV-HUB Processor Socket Address Format: | |
9f5314fb JS |
67 | * +----------------+---------------+---------------------+ |
68 | * |00..000000000000| PNODE | NodeOffset | | |
69 | * +----------------+---------------+---------------------+ | |
70 | * <--- N bits --->|<--------M bits -----> | |
952cf6d7 | 71 | * |
9f5314fb JS |
72 | * M - number of node offset bits (35 .. 40) |
73 | * N - number of PNODE bits (0 .. 10) | |
952cf6d7 JS |
74 | * |
75 | * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). | |
76 | * The actual values are configuration dependent and are set at | |
9f5314fb JS |
77 | * boot time. M & N values are set by the hardware/BIOS at boot. |
78 | * | |
952cf6d7 JS |
79 | * |
80 | * APICID format | |
39d30770 MT |
81 | * NOTE!!!!!! This is the current format of the APICID. However, code |
82 | * should assume that this will change in the future. Use functions | |
83 | * in this file for all APICID bit manipulations and conversion. | |
952cf6d7 | 84 | * |
39d30770 MT |
85 | * 1111110000000000 |
86 | * 5432109876543210 | |
2a919596 JS |
87 | * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) |
88 | * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) | |
89 | * pppppppppppcccch SandyBridge (15 bits in hdw reg) | |
952cf6d7 JS |
90 | * sssssssssss |
91 | * | |
9f5314fb | 92 | * p = pnode bits |
952cf6d7 JS |
93 | * l = socket number on board |
94 | * c = core | |
95 | * h = hyperthread | |
9f5314fb | 96 | * s = bits that are in the SOCKET_ID CSR |
952cf6d7 | 97 | * |
2a919596 | 98 | * Note: Processor may support fewer bits in the APICID register. The ACPI |
952cf6d7 JS |
99 | * tables hold all 16 bits. Software needs to be aware of this. |
100 | * | |
39d30770 MT |
101 | * Unless otherwise specified, all references to APICID refer to |
102 | * the FULL value contained in ACPI tables, not the subset in the | |
103 | * processor APICID register. | |
952cf6d7 JS |
104 | */ |
105 | ||
106 | ||
107 | /* | |
108 | * Maximum number of bricks in all partitions and in all coherency domains. | |
109 | * This is the total number of bricks accessible in the numalink fabric. It | |
110 | * includes all C & M bricks. Routers are NOT included. | |
111 | * | |
112 | * This value is also the value of the maximum number of non-router NASIDs | |
113 | * in the numalink fabric. | |
114 | * | |
9f5314fb | 115 | * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. |
952cf6d7 JS |
116 | */ |
117 | #define UV_MAX_NUMALINK_BLADES 16384 | |
118 | ||
119 | /* | |
120 | * Maximum number of C/Mbricks within a software SSI (hardware may support | |
121 | * more). | |
122 | */ | |
123 | #define UV_MAX_SSI_BLADES 256 | |
124 | ||
125 | /* | |
126 | * The largest possible NASID of a C or M brick (+ 2) | |
127 | */ | |
1d21e6e3 | 128 | #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) |
952cf6d7 | 129 | |
d38bb135 | 130 | /* System Controller Interface Reg info */ |
7f1baa06 MT |
131 | struct uv_scir_s { |
132 | struct timer_list timer; | |
133 | unsigned long offset; | |
134 | unsigned long last; | |
135 | unsigned long idle_on; | |
136 | unsigned long idle_off; | |
137 | unsigned char state; | |
138 | unsigned char enabled; | |
139 | }; | |
140 | ||
952cf6d7 JS |
141 | /* |
142 | * The following defines attributes of the HUB chip. These attributes are | |
0045ddd2 MT |
143 | * frequently referenced and are kept in a common per hub struct. |
144 | * After setup, the struct is read only, so it should be readily | |
145 | * available in the L3 cache on the cpu socket for the node. | |
952cf6d7 JS |
146 | */ |
147 | struct uv_hub_info_s { | |
69a72a0e MT |
148 | unsigned long global_mmr_base; |
149 | unsigned long gpa_mask; | |
c4ed3f04 | 150 | unsigned int gnode_extra; |
2a919596 JS |
151 | unsigned char hub_revision; |
152 | unsigned char apic_pnode_shift; | |
6a469e46 JS |
153 | unsigned char m_shift; |
154 | unsigned char n_lshift; | |
69a72a0e MT |
155 | unsigned long gnode_upper; |
156 | unsigned long lowmem_remap_top; | |
157 | unsigned long lowmem_remap_base; | |
158 | unsigned short pnode; | |
159 | unsigned short pnode_mask; | |
160 | unsigned short coherency_domain_number; | |
161 | unsigned short numa_blade_id; | |
69a72a0e MT |
162 | unsigned char m_val; |
163 | unsigned char n_val; | |
952cf6d7 | 164 | }; |
7f1baa06 | 165 | |
0045ddd2 MT |
166 | /* CPU specific info with a pointer to the hub common info struct */ |
167 | struct uv_cpu_info_s { | |
168 | void *p_uv_hub_info; | |
169 | unsigned char blade_cpu_id; | |
170 | struct uv_scir_s scir; | |
171 | }; | |
172 | DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); | |
173 | ||
174 | #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) | |
175 | #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) | |
176 | ||
d38bb135 MT |
177 | #define uv_scir_info (&uv_cpu_info->scir) |
178 | #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) | |
179 | ||
3edcf2ff MT |
180 | /* Node specific hub common info struct */ |
181 | extern void **__uv_hub_info_list; | |
182 | static inline struct uv_hub_info_s *uv_hub_info_list(int node) | |
183 | { | |
184 | return (struct uv_hub_info_s *)__uv_hub_info_list[node]; | |
185 | } | |
186 | ||
187 | static inline struct uv_hub_info_s *_uv_hub_info(void) | |
188 | { | |
189 | return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; | |
190 | } | |
191 | #define uv_hub_info _uv_hub_info() | |
192 | ||
193 | static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) | |
194 | { | |
195 | return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; | |
196 | } | |
197 | ||
198 | #define UV_HUB_INFO_VERSION 0x7150 | |
199 | extern int uv_hub_info_version(void); | |
200 | static inline int uv_hub_info_check(int version) | |
201 | { | |
202 | if (uv_hub_info_version() == version) | |
203 | return 0; | |
204 | ||
205 | pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n", | |
206 | uv_hub_info_version(), version); | |
207 | ||
208 | BUG(); /* Catastrophic - cannot continue on unknown UV system */ | |
209 | } | |
210 | #define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION) | |
211 | ||
2a919596 | 212 | /* |
0045ddd2 | 213 | * HUB revision ranges for each UV HUB architecture. |
2a919596 JS |
214 | * This is a software convention - NOT the hardware revision numbers in |
215 | * the hub chip. | |
216 | */ | |
217 | #define UV1_HUB_REVISION_BASE 1 | |
218 | #define UV2_HUB_REVISION_BASE 3 | |
6edbd471 | 219 | #define UV3_HUB_REVISION_BASE 5 |
eb1e3461 | 220 | #define UV4_HUB_REVISION_BASE 7 |
2a919596 | 221 | |
e0ee1c97 | 222 | #ifdef UV1_HUB_IS_SUPPORTED |
2a919596 JS |
223 | static inline int is_uv1_hub(void) |
224 | { | |
225 | return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; | |
226 | } | |
e0ee1c97 MT |
227 | #else |
228 | static inline int is_uv1_hub(void) | |
229 | { | |
230 | return 0; | |
231 | } | |
232 | #endif | |
2a919596 | 233 | |
e0ee1c97 | 234 | #ifdef UV2_HUB_IS_SUPPORTED |
2a919596 | 235 | static inline int is_uv2_hub(void) |
6edbd471 MT |
236 | { |
237 | return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && | |
238 | (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); | |
239 | } | |
e0ee1c97 MT |
240 | #else |
241 | static inline int is_uv2_hub(void) | |
242 | { | |
243 | return 0; | |
244 | } | |
245 | #endif | |
6edbd471 | 246 | |
e0ee1c97 | 247 | #ifdef UV3_HUB_IS_SUPPORTED |
6edbd471 MT |
248 | static inline int is_uv3_hub(void) |
249 | { | |
eb1e3461 MT |
250 | return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) && |
251 | (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE)); | |
6edbd471 | 252 | } |
e0ee1c97 MT |
253 | #else |
254 | static inline int is_uv3_hub(void) | |
255 | { | |
256 | return 0; | |
257 | } | |
258 | #endif | |
6edbd471 | 259 | |
eb1e3461 MT |
260 | #ifdef UV4_HUB_IS_SUPPORTED |
261 | static inline int is_uv4_hub(void) | |
262 | { | |
263 | return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE; | |
264 | } | |
265 | #else | |
266 | static inline int is_uv4_hub(void) | |
267 | { | |
268 | return 0; | |
269 | } | |
270 | #endif | |
271 | ||
e0ee1c97 | 272 | static inline int is_uvx_hub(void) |
6edbd471 | 273 | { |
e0ee1c97 MT |
274 | if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) |
275 | return uv_hub_info->hub_revision; | |
276 | ||
277 | return 0; | |
6edbd471 MT |
278 | } |
279 | ||
e0ee1c97 | 280 | static inline int is_uv_hub(void) |
2a919596 | 281 | { |
e0ee1c97 MT |
282 | #ifdef UV1_HUB_IS_SUPPORTED |
283 | return uv_hub_info->hub_revision; | |
284 | #endif | |
285 | return is_uvx_hub(); | |
2a919596 JS |
286 | } |
287 | ||
c8f730b1 RA |
288 | union uvh_apicid { |
289 | unsigned long v; | |
290 | struct uvh_apicid_s { | |
291 | unsigned long local_apic_mask : 24; | |
292 | unsigned long local_apic_shift : 5; | |
293 | unsigned long unused1 : 3; | |
294 | unsigned long pnode_mask : 24; | |
295 | unsigned long pnode_shift : 5; | |
296 | unsigned long unused2 : 3; | |
297 | } s; | |
298 | }; | |
299 | ||
952cf6d7 JS |
300 | /* |
301 | * Local & Global MMR space macros. | |
39d30770 MT |
302 | * Note: macros are intended to be used ONLY by inline functions |
303 | * in this file - not by other kernel code. | |
304 | * n - NASID (full 15-bit global nasid) | |
305 | * g - GNODE (full 15-bit global nasid, right shifted 1) | |
306 | * p - PNODE (local part of nsids, right shifted 1) | |
952cf6d7 | 307 | */ |
9f5314fb | 308 | #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) |
c4ed3f04 JS |
309 | #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) |
310 | #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) | |
952cf6d7 | 311 | |
2a919596 JS |
312 | #define UV1_LOCAL_MMR_BASE 0xf4000000UL |
313 | #define UV1_GLOBAL_MMR32_BASE 0xf8000000UL | |
314 | #define UV1_LOCAL_MMR_SIZE (64UL * 1024 * 1024) | |
315 | #define UV1_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024) | |
316 | ||
317 | #define UV2_LOCAL_MMR_BASE 0xfa000000UL | |
318 | #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL | |
319 | #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) | |
320 | #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) | |
321 | ||
6edbd471 MT |
322 | #define UV3_LOCAL_MMR_BASE 0xfa000000UL |
323 | #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL | |
324 | #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) | |
325 | #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) | |
326 | ||
eb1e3461 MT |
327 | #define UV4_LOCAL_MMR_BASE 0xfa000000UL |
328 | #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL | |
329 | #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) | |
330 | #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) | |
331 | ||
332 | #define UV_LOCAL_MMR_BASE ( \ | |
333 | is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ | |
334 | is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ | |
335 | is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ | |
336 | /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) | |
337 | ||
338 | #define UV_GLOBAL_MMR32_BASE ( \ | |
339 | is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \ | |
340 | is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ | |
341 | is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ | |
342 | /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) | |
343 | ||
344 | #define UV_LOCAL_MMR_SIZE ( \ | |
345 | is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ | |
346 | is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ | |
347 | is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ | |
348 | /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) | |
349 | ||
350 | #define UV_GLOBAL_MMR32_SIZE ( \ | |
351 | is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \ | |
352 | is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ | |
353 | is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ | |
354 | /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) | |
355 | ||
952cf6d7 JS |
356 | #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) |
357 | ||
56abcf24 JS |
358 | #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 |
359 | ||
9f5314fb JS |
360 | #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 |
361 | #define UV_GLOBAL_MMR64_PNODE_SHIFT 26 | |
952cf6d7 | 362 | |
9f5314fb | 363 | #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) |
952cf6d7 | 364 | |
9f5314fb | 365 | #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
67e83f30 | 366 | (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
9f5314fb | 367 | |
c8f730b1 | 368 | #define UVH_APICID 0x002D0E00L |
9f5314fb JS |
369 | #define UV_APIC_PNODE_SHIFT 6 |
370 | ||
8191c9f6 DS |
371 | #define UV_APICID_HIBIT_MASK 0xffff0000 |
372 | ||
7f1baa06 MT |
373 | /* Local Bus from cpu's perspective */ |
374 | #define LOCAL_BUS_BASE 0x1c00000 | |
375 | #define LOCAL_BUS_SIZE (4 * 1024 * 1024) | |
376 | ||
377 | /* | |
378 | * System Controller Interface Reg | |
379 | * | |
380 | * Note there are NO leds on a UV system. This register is only | |
381 | * used by the system controller to monitor system-wide operation. | |
382 | * There are 64 regs per node. With Nahelem cpus (2 cores per node, | |
383 | * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on | |
384 | * a node. | |
385 | * | |
386 | * The window is located at top of ACPI MMR space | |
387 | */ | |
388 | #define SCIR_WINDOW_COUNT 64 | |
389 | #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ | |
390 | LOCAL_BUS_SIZE - \ | |
391 | SCIR_WINDOW_COUNT) | |
392 | ||
393 | #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ | |
394 | #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ | |
395 | #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ | |
396 | ||
8661984f DS |
397 | /* Loop through all installed blades */ |
398 | #define for_each_possible_blade(bid) \ | |
399 | for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) | |
400 | ||
9f5314fb JS |
401 | /* |
402 | * Macros for converting between kernel virtual addresses, socket local physical | |
403 | * addresses, and UV global physical addresses. | |
39d30770 MT |
404 | * Note: use the standard __pa() & __va() macros for converting |
405 | * between socket virtual and socket physical addresses. | |
9f5314fb JS |
406 | */ |
407 | ||
408 | /* socket phys RAM --> UV global physical address */ | |
409 | static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) | |
410 | { | |
411 | if (paddr < uv_hub_info->lowmem_remap_top) | |
189f67c4 | 412 | paddr |= uv_hub_info->lowmem_remap_base; |
6a469e46 JS |
413 | paddr |= uv_hub_info->gnode_upper; |
414 | paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | | |
415 | ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); | |
416 | return paddr; | |
9f5314fb JS |
417 | } |
418 | ||
419 | ||
420 | /* socket virtual --> UV global physical address */ | |
421 | static inline unsigned long uv_gpa(void *v) | |
422 | { | |
189f67c4 | 423 | return uv_soc_phys_ram_to_gpa(__pa(v)); |
9f5314fb | 424 | } |
1d21e6e3 | 425 | |
fae419f2 RH |
426 | /* Top two bits indicate the requested address is in MMR space. */ |
427 | static inline int | |
428 | uv_gpa_in_mmr_space(unsigned long gpa) | |
429 | { | |
430 | return (gpa >> 62) == 0x3UL; | |
431 | } | |
432 | ||
729d69e6 RH |
433 | /* UV global physical address --> socket phys RAM */ |
434 | static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) | |
435 | { | |
5a51467b | 436 | unsigned long paddr; |
729d69e6 RH |
437 | unsigned long remap_base = uv_hub_info->lowmem_remap_base; |
438 | unsigned long remap_top = uv_hub_info->lowmem_remap_top; | |
439 | ||
6a469e46 JS |
440 | gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | |
441 | ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); | |
5a51467b | 442 | paddr = gpa & uv_hub_info->gpa_mask; |
729d69e6 RH |
443 | if (paddr >= remap_base && paddr < remap_base + remap_top) |
444 | paddr -= remap_base; | |
445 | return paddr; | |
446 | } | |
447 | ||
448 | ||
6a469e46 | 449 | /* gpa -> pnode */ |
1d21e6e3 RH |
450 | static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) |
451 | { | |
6a469e46 | 452 | return gpa >> uv_hub_info->n_lshift; |
1d21e6e3 RH |
453 | } |
454 | ||
455 | /* gpa -> pnode */ | |
456 | static inline int uv_gpa_to_pnode(unsigned long gpa) | |
457 | { | |
458 | unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; | |
459 | ||
460 | return uv_gpa_to_gnode(gpa) & n_mask; | |
461 | } | |
9f5314fb | 462 | |
6a469e46 JS |
463 | /* gpa -> node offset*/ |
464 | static inline unsigned long uv_gpa_to_offset(unsigned long gpa) | |
465 | { | |
466 | return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; | |
467 | } | |
468 | ||
9f5314fb JS |
469 | /* pnode, offset --> socket virtual */ |
470 | static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) | |
471 | { | |
472 | return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); | |
473 | } | |
952cf6d7 | 474 | |
952cf6d7 JS |
475 | |
476 | /* | |
9f5314fb | 477 | * Extract a PNODE from an APICID (full apicid, not processor subset) |
952cf6d7 | 478 | */ |
9f5314fb | 479 | static inline int uv_apicid_to_pnode(int apicid) |
952cf6d7 | 480 | { |
c8f730b1 | 481 | return (apicid >> uv_hub_info->apic_pnode_shift); |
952cf6d7 JS |
482 | } |
483 | ||
2a919596 JS |
484 | /* |
485 | * Convert an apicid to the socket number on the blade | |
486 | */ | |
487 | static inline int uv_apicid_to_socket(int apicid) | |
488 | { | |
489 | if (is_uv1_hub()) | |
490 | return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1; | |
491 | else | |
492 | return 0; | |
493 | } | |
494 | ||
952cf6d7 JS |
495 | /* |
496 | * Access global MMRs using the low memory MMR32 space. This region supports | |
497 | * faster MMR access but not all MMRs are accessible in this space. | |
498 | */ | |
39d30770 | 499 | static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) |
952cf6d7 JS |
500 | { |
501 | return __va(UV_GLOBAL_MMR32_BASE | | |
9f5314fb | 502 | UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
503 | } |
504 | ||
39d30770 | 505 | static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) |
952cf6d7 | 506 | { |
8dc579e8 | 507 | writeq(val, uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
508 | } |
509 | ||
39d30770 | 510 | static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) |
952cf6d7 | 511 | { |
8dc579e8 | 512 | return readq(uv_global_mmr32_address(pnode, offset)); |
952cf6d7 JS |
513 | } |
514 | ||
515 | /* | |
516 | * Access Global MMR space using the MMR space located at the top of physical | |
517 | * memory. | |
518 | */ | |
a289cc7c | 519 | static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) |
952cf6d7 JS |
520 | { |
521 | return __va(UV_GLOBAL_MMR64_BASE | | |
9f5314fb | 522 | UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); |
952cf6d7 JS |
523 | } |
524 | ||
39d30770 | 525 | static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) |
952cf6d7 | 526 | { |
8dc579e8 | 527 | writeq(val, uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
528 | } |
529 | ||
39d30770 | 530 | static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) |
952cf6d7 | 531 | { |
8dc579e8 | 532 | return readq(uv_global_mmr64_address(pnode, offset)); |
952cf6d7 JS |
533 | } |
534 | ||
56abcf24 JS |
535 | /* |
536 | * Global MMR space addresses when referenced by the GRU. (GRU does | |
537 | * NOT use socket addressing). | |
538 | */ | |
539 | static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset) | |
540 | { | |
e1e0138d JS |
541 | return UV_GLOBAL_GRU_MMR_BASE | offset | |
542 | ((unsigned long)pnode << uv_hub_info->m_val); | |
56abcf24 JS |
543 | } |
544 | ||
39d30770 MT |
545 | static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) |
546 | { | |
547 | writeb(val, uv_global_mmr64_address(pnode, offset)); | |
548 | } | |
549 | ||
550 | static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) | |
551 | { | |
552 | return readb(uv_global_mmr64_address(pnode, offset)); | |
553 | } | |
554 | ||
952cf6d7 | 555 | /* |
9f5314fb | 556 | * Access hub local MMRs. Faster than using global space but only local MMRs |
952cf6d7 JS |
557 | * are accessible. |
558 | */ | |
559 | static inline unsigned long *uv_local_mmr_address(unsigned long offset) | |
560 | { | |
561 | return __va(UV_LOCAL_MMR_BASE | offset); | |
562 | } | |
563 | ||
564 | static inline unsigned long uv_read_local_mmr(unsigned long offset) | |
565 | { | |
8dc579e8 | 566 | return readq(uv_local_mmr_address(offset)); |
952cf6d7 JS |
567 | } |
568 | ||
569 | static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) | |
570 | { | |
8dc579e8 | 571 | writeq(val, uv_local_mmr_address(offset)); |
952cf6d7 JS |
572 | } |
573 | ||
7f1baa06 MT |
574 | static inline unsigned char uv_read_local_mmr8(unsigned long offset) |
575 | { | |
8dc579e8 | 576 | return readb(uv_local_mmr_address(offset)); |
7f1baa06 MT |
577 | } |
578 | ||
579 | static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) | |
580 | { | |
8dc579e8 | 581 | writeb(val, uv_local_mmr_address(offset)); |
7f1baa06 MT |
582 | } |
583 | ||
8400def8 | 584 | /* |
9f5314fb | 585 | * Structures and definitions for converting between cpu, node, pnode, and blade |
8400def8 JS |
586 | * numbers. |
587 | */ | |
588 | struct uv_blade_info { | |
9f5314fb | 589 | unsigned short nr_possible_cpus; |
8400def8 | 590 | unsigned short nr_online_cpus; |
9f5314fb | 591 | unsigned short pnode; |
6c7184b7 | 592 | short memory_nid; |
8400def8 | 593 | }; |
9f5314fb | 594 | extern struct uv_blade_info *uv_blade_info; |
8400def8 JS |
595 | extern short *uv_node_to_blade; |
596 | extern short *uv_cpu_to_blade; | |
597 | extern short uv_possible_blades; | |
598 | ||
599 | /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ | |
600 | static inline int uv_blade_processor_id(void) | |
601 | { | |
5627a825 | 602 | return uv_cpu_info->blade_cpu_id; |
8400def8 JS |
603 | } |
604 | ||
5627a825 MT |
605 | /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ |
606 | static inline int uv_cpu_blade_processor_id(int cpu) | |
607 | { | |
608 | return uv_cpu_info_per(cpu)->blade_cpu_id; | |
609 | } | |
610 | #define _uv_cpu_blade_processor_id 1 /* indicate function available */ | |
611 | ||
8400def8 JS |
612 | /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ |
613 | static inline int uv_numa_blade_id(void) | |
614 | { | |
615 | return uv_hub_info->numa_blade_id; | |
616 | } | |
617 | ||
618 | /* Convert a cpu number to the the UV blade number */ | |
619 | static inline int uv_cpu_to_blade_id(int cpu) | |
620 | { | |
621 | return uv_cpu_to_blade[cpu]; | |
622 | } | |
623 | ||
624 | /* Convert linux node number to the UV blade number */ | |
625 | static inline int uv_node_to_blade_id(int nid) | |
626 | { | |
627 | return uv_node_to_blade[nid]; | |
628 | } | |
629 | ||
9f5314fb JS |
630 | /* Convert a blade id to the PNODE of the blade */ |
631 | static inline int uv_blade_to_pnode(int bid) | |
8400def8 | 632 | { |
9f5314fb | 633 | return uv_blade_info[bid].pnode; |
8400def8 JS |
634 | } |
635 | ||
6c7184b7 JS |
636 | /* Nid of memory node on blade. -1 if no blade-local memory */ |
637 | static inline int uv_blade_to_memory_nid(int bid) | |
638 | { | |
639 | return uv_blade_info[bid].memory_nid; | |
640 | } | |
641 | ||
8400def8 JS |
642 | /* Determine the number of possible cpus on a blade */ |
643 | static inline int uv_blade_nr_possible_cpus(int bid) | |
644 | { | |
9f5314fb | 645 | return uv_blade_info[bid].nr_possible_cpus; |
8400def8 JS |
646 | } |
647 | ||
648 | /* Determine the number of online cpus on a blade */ | |
649 | static inline int uv_blade_nr_online_cpus(int bid) | |
650 | { | |
651 | return uv_blade_info[bid].nr_online_cpus; | |
652 | } | |
653 | ||
9f5314fb JS |
654 | /* Convert a cpu id to the PNODE of the blade containing the cpu */ |
655 | static inline int uv_cpu_to_pnode(int cpu) | |
8400def8 | 656 | { |
9f5314fb | 657 | return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; |
8400def8 JS |
658 | } |
659 | ||
9f5314fb JS |
660 | /* Convert a linux node number to the PNODE of the blade */ |
661 | static inline int uv_node_to_pnode(int nid) | |
8400def8 | 662 | { |
9f5314fb | 663 | return uv_blade_info[uv_node_to_blade_id(nid)].pnode; |
8400def8 JS |
664 | } |
665 | ||
666 | /* Maximum possible number of blades */ | |
667 | static inline int uv_num_possible_blades(void) | |
668 | { | |
669 | return uv_possible_blades; | |
670 | } | |
671 | ||
0d12ef0c MT |
672 | /* Per Hub NMI support */ |
673 | extern void uv_nmi_setup(void); | |
674 | ||
675 | /* BMC sets a bit this MMR non-zero before sending an NMI */ | |
676 | #define UVH_NMI_MMR UVH_SCRATCH5 | |
677 | #define UVH_NMI_MMR_CLEAR UVH_SCRATCH5_ALIAS | |
678 | #define UVH_NMI_MMR_SHIFT 63 | |
679 | #define UVH_NMI_MMR_TYPE "SCRATCH5" | |
680 | ||
681 | /* Newer SMM NMI handler, not present in all systems */ | |
682 | #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 | |
683 | #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS | |
c443c03d | 684 | #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT |
0d12ef0c MT |
685 | #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" |
686 | ||
687 | /* Non-zero indicates newer SMM NMI handler present */ | |
688 | #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST | |
689 | ||
690 | /* Indicates to BIOS that we want to use the newer SMM NMI handler */ | |
691 | #define UVH_NMI_MMRX_REQ UVH_SCRATCH5_ALIAS_2 | |
692 | #define UVH_NMI_MMRX_REQ_SHIFT 62 | |
693 | ||
694 | struct uv_hub_nmi_s { | |
695 | raw_spinlock_t nmi_lock; | |
696 | atomic_t in_nmi; /* flag this node in UV NMI IRQ */ | |
697 | atomic_t cpu_owner; /* last locker of this struct */ | |
698 | atomic_t read_mmr_count; /* count of MMR reads */ | |
699 | atomic_t nmi_count; /* count of true UV NMIs */ | |
700 | unsigned long nmi_value; /* last value read from NMI MMR */ | |
701 | }; | |
702 | ||
703 | struct uv_cpu_nmi_s { | |
704 | struct uv_hub_nmi_s *hub; | |
e1632170 CL |
705 | int state; |
706 | int pinging; | |
0d12ef0c MT |
707 | int queries; |
708 | int pings; | |
709 | }; | |
710 | ||
e1632170 CL |
711 | DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); |
712 | ||
7c52198b | 713 | #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) |
e1632170 | 714 | #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) |
0d12ef0c MT |
715 | #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) |
716 | ||
717 | /* uv_cpu_nmi_states */ | |
718 | #define UV_NMI_STATE_OUT 0 | |
719 | #define UV_NMI_STATE_IN 1 | |
720 | #define UV_NMI_STATE_DUMP 2 | |
721 | #define UV_NMI_STATE_DUMP_DONE 3 | |
722 | ||
7f1baa06 MT |
723 | /* Update SCIR state */ |
724 | static inline void uv_set_scir_bits(unsigned char value) | |
725 | { | |
d38bb135 MT |
726 | if (uv_scir_info->state != value) { |
727 | uv_scir_info->state = value; | |
728 | uv_write_local_mmr8(uv_scir_info->offset, value); | |
7f1baa06 MT |
729 | } |
730 | } | |
66666e50 | 731 | |
39d30770 MT |
732 | static inline unsigned long uv_scir_offset(int apicid) |
733 | { | |
734 | return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); | |
735 | } | |
736 | ||
7f1baa06 MT |
737 | static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) |
738 | { | |
d38bb135 | 739 | if (uv_cpu_scir_info(cpu)->state != value) { |
39d30770 | 740 | uv_write_global_mmr8(uv_cpu_to_pnode(cpu), |
d38bb135 MT |
741 | uv_cpu_scir_info(cpu)->offset, value); |
742 | uv_cpu_scir_info(cpu)->state = value; | |
7f1baa06 MT |
743 | } |
744 | } | |
952cf6d7 | 745 | |
8191c9f6 | 746 | extern unsigned int uv_apicid_hibits; |
56abcf24 JS |
747 | static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode) |
748 | { | |
8191c9f6 | 749 | apicid |= uv_apicid_hibits; |
56abcf24 JS |
750 | return (1UL << UVH_IPI_INT_SEND_SHFT) | |
751 | ((apicid) << UVH_IPI_INT_APIC_ID_SHFT) | | |
752 | (mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | | |
753 | (vector << UVH_IPI_INT_VECTOR_SHFT); | |
754 | } | |
755 | ||
66666e50 JS |
756 | static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) |
757 | { | |
758 | unsigned long val; | |
02dd0a06 RH |
759 | unsigned long dmode = dest_Fixed; |
760 | ||
761 | if (vector == NMI_VECTOR) | |
762 | dmode = dest_NMI; | |
66666e50 | 763 | |
56abcf24 | 764 | val = uv_hub_ipi_value(apicid, vector, dmode); |
66666e50 JS |
765 | uv_write_global_mmr64(pnode, UVH_IPI_INT, val); |
766 | } | |
767 | ||
7a1110e8 JS |
768 | /* |
769 | * Get the minimum revision number of the hub chips within the partition. | |
eb1e3461 | 770 | * (See UVx_HUB_REVISION_BASE above for specific values.) |
7a1110e8 JS |
771 | */ |
772 | static inline int uv_get_min_hub_revision_id(void) | |
773 | { | |
2a919596 | 774 | return uv_hub_info->hub_revision; |
7a1110e8 JS |
775 | } |
776 | ||
bc5d9940 | 777 | #endif /* CONFIG_X86_64 */ |
7f1baa06 | 778 | #endif /* _ASM_X86_UV_UV_HUB_H */ |